hdmi_controller

2024.03.04.17:42:33 Datasheet
Overview
  clk_50  hdmi_controller
Processor
   nios2_gen2_0 Nios II 19.1.0
All Components
   I2C_SCL altera_avalon_pio 19.2.0
   I2C_SDA altera_avalon_pio 19.2.0
   RX0_EDID_I2C_SCL altera_avalon_pio 19.2.0
   RX0_EDID_I2C_SDA altera_avalon_pio 19.2.0
   RX1_EDID_I2C_SCL altera_avalon_pio 19.2.0
   RX1_EDID_I2C_SDA altera_avalon_pio 19.2.0
   adv7619_int altera_avalon_pio 19.2.0
   adv7619_rst altera_avalon_pio 19.2.0
   button altera_avalon_pio 19.2.0
   hdmi_tx_fmc_i2c_scl altera_avalon_pio 19.2.0
   hdmi_tx_fmc_i2c_sda altera_avalon_pio 19.2.0
   jtag_uart altera_avalon_jtag_uart 19.2.0
   led altera_avalon_pio 19.2.0
   nios2_gen2_0 altera_nios2_gen2 19.1.0
   onchip_memory2 altera_avalon_onchip_memory2 19.3.8
   sii9136_int altera_avalon_pio 19.2.0
   sii9136_rst_n altera_avalon_pio 19.2.0
   sii9678_int altera_avalon_pio 19.2.0
   sw altera_avalon_pio 19.2.0
   sysid_qsys_0 altera_avalon_sysid_qsys 19.1.2
   timer altera_avalon_timer 19.3.0
Memory Map
nios2_gen2_0
 data_master  instruction_master
  I2C_SCL
s1  0x00081090
  I2C_SDA
s1  0x00081080
  RX0_EDID_I2C_SCL
s1  0x00081060
  RX0_EDID_I2C_SDA
s1  0x00081050
  RX1_EDID_I2C_SCL
s1  0x00081030
  RX1_EDID_I2C_SDA
s1  0x00081020
  adv7619_int
s1  0x00081040
  adv7619_rst
s1  0x00081070
  button
s1  0x000810f0
  hdmi_tx_fmc_i2c_scl
s1  0x000810d0
  hdmi_tx_fmc_i2c_sda
s1  0x000810e0
  jtag_uart
avalon_jtag_slave  0x00081128
  led
s1  0x00081110
  nios2_gen2_0
debug_mem_slave  0x00080800 0x00080800
  onchip_memory2
s1  0x00040000 0x00040000
  sii9136_int
s1  0x000810c0
  sii9136_rst_n
s1  0x000810b0
  sii9678_int
s1  0x000810a0
  sw
s1  0x00081100
  sysid_qsys_0
control_slave  0x00081120
  timer
s1  0x00081000

I2C_SCL

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   I2C_SCL
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 0
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

I2C_SDA

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   I2C_SDA
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 0
HAS_IN 0
HAS_OUT 0
HAS_TRI 1
IRQ_TYPE NONE
RESET_VALUE 0

RX0_EDID_I2C_SCL

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   RX0_EDID_I2C_SCL
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 0
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

RX0_EDID_I2C_SDA

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   RX0_EDID_I2C_SDA
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 0
HAS_TRI 1
IRQ_TYPE NONE
RESET_VALUE 0

RX1_EDID_I2C_SCL

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   RX1_EDID_I2C_SCL
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 0
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

RX1_EDID_I2C_SDA

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   RX1_EDID_I2C_SDA
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 0
HAS_IN 0
HAS_OUT 0
HAS_TRI 1
IRQ_TYPE NONE
RESET_VALUE 0

adv7619_int

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   adv7619_int
  s1
irq  
  irq
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 0
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

adv7619_rst

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   adv7619_rst
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 0
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

button

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   button
  s1
irq  
  irq
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 0
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

clk_50

clock_source vnull


Parameters

generateLegacySim false
  

Software Assignments

(none)

hdmi_tx_fmc_i2c_scl

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   hdmi_tx_fmc_i2c_scl
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

hdmi_tx_fmc_i2c_sda

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   hdmi_tx_fmc_i2c_sda
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 0
HAS_TRI 1
IRQ_TYPE NONE
RESET_VALUE 0

jtag_uart

altera_avalon_jtag_uart v19.2.0
nios2_gen2_0 data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

led

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   led
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

nios2_gen2_0

altera_nios2_gen2 v19.1.0
clk_50 clk   nios2_gen2_0
  clk
clk_reset  
  reset
data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
data_master   sysid_qsys_0
  control_slave
data_master   timer
  s1
irq  
  irq
data_master   led
  s1
data_master   sw
  s1
irq  
  irq
data_master   button
  s1
irq  
  irq
data_master   onchip_memory2
  s1
instruction_master  
  s1
data_master   hdmi_tx_fmc_i2c_sda
  s1
data_master   hdmi_tx_fmc_i2c_scl
  s1
data_master   sii9136_int
  s1
irq  
  irq
data_master   sii9136_rst_n
  s1
data_master   sii9678_int
  s1
irq  
  irq
data_master   I2C_SCL
  s1
data_master   I2C_SDA
  s1
data_master   adv7619_rst
  s1
data_master   RX0_EDID_I2C_SCL
  s1
data_master   RX0_EDID_I2C_SDA
  s1
data_master   adv7619_int
  s1
irq  
  irq
data_master   RX1_EDID_I2C_SCL
  s1
data_master   RX1_EDID_I2C_SDA
  s1


Parameters

generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x00080820
CPU_ARCH_NIOS2_R1
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 20
DCACHE_BYPASS_MASK 0x80000000
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
EXCEPTION_ADDR 0x00040020
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INITDA_SUPPORTED
INST_ADDR_WIDTH 20
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x00040000

onchip_memory2

altera_avalon_onchip_memory2 v19.3.8
nios2_gen2_0 data_master   onchip_memory2
  s1
instruction_master  
  s1
clk_50 clk  
  clk1
clk_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 1
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE hdmi_controller_onchip_memory2_onchip_memory2
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 256000
WRITABLE 1

sii9136_int

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   sii9136_int
  s1
irq  
  irq
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

sii9136_rst_n

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   sii9136_rst_n
  s1
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

sii9678_int

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   sii9678_int
  s1
irq  
  irq
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE RISING
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

sw

altera_avalon_pio v19.2.0
nios2_gen2_0 data_master   sw
  s1
irq  
  irq
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

sysid_qsys_0

altera_avalon_sysid_qsys v19.1.2
nios2_gen2_0 data_master   sysid_qsys_0
  control_slave
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

timer

altera_avalon_timer v19.3.0
nios2_gen2_0 data_master   timer
  s1
irq  
  irq
clk_50 clk  
  clk
clk_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1
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