| syspll_mod_0 |
PCIE_FREQ_700 |
| syspll_mod_1 |
Disabled |
| syspll_mod_2 |
Disabled |
| syspll_refclk_src_0 |
RefClk #1 |
| syspll_refclk_src_1 |
RefClk #0 |
| syspll_refclk_src_2 |
RefClk #0 |
| syspll_freq_mhz_default_0 |
700 |
| syspll_freq_mhz_default_1 |
805.6640625 |
| syspll_freq_mhz_default_2 |
805.6640625 |
| cmnpll_enable_0 |
false |
| cmnpll_enable_1 |
false |
| cmnpll_refclk_src_0 |
FHT RefClk #0 |
| cmnpll_refclk_src_1 |
FHT RefClk #0 |
| cmnpll_xtensa_src |
Auto |
| refclk_fgt_output_enable_0 |
true |
| refclk_fgt_freq_mhz_txt_0 |
100 |
| refclk_fgt_output_enable_1 |
false |
| refclk_fgt_usedby_1 |
PLL#0 |
| refclk_fgt_freq_mhz_1 |
100.000000 |
| refclk_fgt_output_enable_2 |
false |
| refclk_fgt_freq_mhz_txt_2 |
100 |
| refclk_fgt_output_enable_3 |
false |
| refclk_fgt_freq_mhz_txt_3 |
100 |
| refclk_fgt_output_enable_4 |
false |
| refclk_fgt_freq_mhz_txt_4 |
100 |
| refclk_fgt_output_enable_5 |
false |
| refclk_fgt_freq_mhz_txt_5 |
100 |
| refclk_fgt_output_enable_6 |
false |
| refclk_fgt_freq_mhz_txt_6 |
100 |
| refclk_fgt_output_enable_7 |
false |
| refclk_fgt_freq_mhz_txt_7 |
100 |
| refclk_fgt_output_enable_8 |
false |
| refclk_fgt_freq_mhz_txt_8 |
100 |
| refclk_fgt_output_enable_9 |
false |
| refclk_fgt_freq_mhz_txt_9 |
100 |
| refclk_cdrclk_output_enable_0 |
false |
| refclk_cdrclk_output_enable_1 |
false |
| refclk_fht_freq_mhz_txt_0 |
|
| refclk_fht_freq_mhz_txt_1 |
|
| refclk_fgt_always_active_0 |
true |
| refclk_fgt_always_active_1 |
true |
| refclk_fgt_coreclk_enable_0 |
false |
| refclk_fgt_coreclk_enable_1 |
false |
| bk_cfg_kvcc_vreg_offset_en_val |
CFG_KVCC_VREG_OFFSET_EN_VAL_DISABLE |
| rx_onchip_termination |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable |
ENABLE |
| ux_txeq_post_tap_1 |
0 |
| ux_txeq_main_tap |
35 |
| ux_txeq_pre_tap_1 |
5 |
| ux_txeq_pre_tap_2 |
0 |
| vsr_mode |
VSR_MODE_DISABLE |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |