| xcvr_type |
0 |
| rcfg_group |
25G-1 |
| duplex_mode |
rx |
| fec_en |
0 |
| syspll_outclk_freq_mhz |
900.0 |
| num_sec_profiles |
3 |
| avmm1_enable |
1 |
| soft_csr_enable |
1 |
| soft_dr_csr_enable |
1 |
| avmm1_ready_enable |
0 |
| avmm1_jtag_enable |
0 |
| avmm2_enable |
0 |
| avmm2_ready_enable |
0 |
| avmm2_jtag_enable |
0 |
| prof0_num_xcvr |
1 |
| prof0_fgt_protocol_mode |
SDI |
| prof0_pma_modulation |
NRZ |
| prof0_pma_data_rate |
11880 |
| prof0_pma_width |
20 |
| prof0_fgt_tx_serdes_gray_coding_enable |
0 |
| prof0_fgt_tx_serdes_pre_coding_enable |
0 |
| prof0_enable_port_fgt_tx_beacon |
0 |
| prof0_fgt_tx_pll_txuserclk1_enable |
0 |
| prof0_fgt_tx_pll_txuserclk2_enable |
0 |
| prof0_fgt_tx_pll_txuserclk_div |
32 |
| prof0_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof0_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof0_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof0_bk_tx_precode_en |
0 |
| prof0_bk_tx_predivider_en |
0 |
| prof0_bk_tx_user_clk1_en |
0 |
| prof0_bk_tx_user_clk1_sel |
0 |
| prof0_bk_tx_user_clk2_en |
0 |
| prof0_bk_tx_user_clk2_sel |
0 |
| prof0_fgt_rx_serdes_gray_coding_enable |
0 |
| prof0_fgt_rx_serdes_pre_coding_enable |
0 |
| prof0_fgt_rx_sata_squelch_det_enable |
0 |
| prof0_enable_port_fgt_rx_signal_detect |
0 |
| prof0_enable_port_fgt_rx_signal_detect_lfps |
0 |
| prof0_fgt_rx_serdes_adapt_mode |
auto |
| prof0_fgt_rx_cdr_rxuserclk_enable |
1 |
| prof0_fgt_rx_cdr_rxuserclk_div |
40 |
| prof0_bk_alt_pam4_grey_code |
0 |
| prof0_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof0_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof0_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof0_bk_rx_precode_en |
0 |
| prof0_bk_rx_user_clk1_en |
0 |
| prof0_bk_rx_user_clk1_sel |
0 |
| prof0_bk_rx_user_clk2_en |
0 |
| prof0_bk_rx_user_clk2_sel |
0 |
| prof0_enable_port_rx_pmaif_fifo_empty |
0 |
| prof0_enable_port_rx_pmaif_fifo_pempty |
0 |
| prof0_enable_port_rx_pmaif_fifo_pfull |
0 |
| prof0_fec_en |
0 |
| prof0_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof0_fec_802p3ck |
0 |
| prof0_fgt_tx_pll_fout_hz |
|
| prof0_fgt_tx_pll_vco_MHz |
|
| prof0_fgt_tx_pll_cascade_enable |
0 |
| prof0_fgt_tx_pll_frac_mode_enable |
0 |
| prof0_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof0_fgt_rx_pll_fout_hz |
5940.000000 |
| prof0_fgt_rx_pll_vco_MHz |
11880.000000 |
| prof0_fgt_rx_pll_refclk_freq_mhz |
148.500000 |
| prof0_enable_port_fgt_rx_set_locktoref |
1 |
| prof0_enable_port_fgt_rx_set_locktodata |
1 |
| prof0_enable_port_fgt_rx_cdr_set_locktoref |
0 |
| prof0_enable_port_fgt_rx_cdr_freeze |
0 |
| prof0_fgt_rx_cdr_lock_mode |
manual |
| prof1_num_xcvr |
1 |
| prof1_fgt_protocol_mode |
SDI |
| prof1_pma_modulation |
NRZ |
| prof1_pma_data_rate |
5940 |
| prof1_pma_width |
20 |
| prof1_pma_secondary_profile_refclk_en |
0 |
| prof1_fgt_tx_serdes_gray_coding_enable |
0 |
| prof1_fgt_tx_serdes_pre_coding_enable |
0 |
| prof1_fgt_tx_pll_txuserclk1_enable |
0 |
| prof1_fgt_tx_pll_txuserclk2_enable |
0 |
| prof1_fgt_tx_pll_txuserclk_div |
32 |
| prof1_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof1_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof1_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof1_bk_tx_precode_en |
0 |
| prof1_bk_tx_predivider_en |
0 |
| prof1_bk_tx_user_clk1_en |
0 |
| prof1_bk_tx_user_clk1_sel |
0 |
| prof1_bk_tx_user_clk2_en |
0 |
| prof1_bk_tx_user_clk2_sel |
0 |
| prof1_fgt_rx_serdes_gray_coding_enable |
0 |
| prof1_fgt_rx_serdes_pre_coding_enable |
0 |
| prof1_fgt_rx_sata_squelch_det_enable |
0 |
| prof1_fgt_rx_serdes_adapt_mode |
auto |
| prof1_fgt_rx_cdr_lock_mode |
manual |
| prof1_fgt_rx_cdr_rxuserclk_enable |
1 |
| prof1_fgt_rx_cdr_rxuserclk_div |
40 |
| prof1_bk_alt_pam4_grey_code |
0 |
| prof1_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof1_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof1_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof1_bk_rx_precode_en |
0 |
| prof1_bk_rx_user_clk1_en |
0 |
| prof1_bk_rx_user_clk1_sel |
0 |
| prof1_bk_rx_user_clk2_en |
0 |
| prof1_bk_rx_user_clk2_sel |
0 |
| prof1_fec_en |
0 |
| prof1_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof1_fec_802p3ck |
0 |
| prof1_fgt_tx_pll_fout_hz |
|
| prof1_fgt_tx_pll_vco_MHz |
|
| prof1_fgt_tx_pll_cascade_enable |
0 |
| prof1_fgt_tx_pll_frac_mode_enable |
0 |
| prof1_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof1_fgt_rx_pll_fout_hz |
2970.000000 |
| prof1_fgt_rx_pll_vco_MHz |
11880.000000 |
| prof1_fgt_rx_pll_refclk_freq_mhz |
148.500000 |
| prof2_num_xcvr |
1 |
| prof2_fgt_protocol_mode |
SDI |
| prof2_pma_modulation |
NRZ |
| prof2_pma_data_rate |
2970 |
| prof2_pma_width |
20 |
| prof2_pma_secondary_profile_refclk_en |
0 |
| prof2_fgt_tx_serdes_gray_coding_enable |
0 |
| prof2_fgt_tx_serdes_pre_coding_enable |
0 |
| prof2_fgt_tx_pll_txuserclk1_enable |
0 |
| prof2_fgt_tx_pll_txuserclk2_enable |
0 |
| prof2_fgt_tx_pll_txuserclk_div |
32 |
| prof2_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof2_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof2_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof2_bk_tx_precode_en |
0 |
| prof2_bk_tx_predivider_en |
0 |
| prof2_bk_tx_user_clk1_en |
0 |
| prof2_bk_tx_user_clk1_sel |
0 |
| prof2_bk_tx_user_clk2_en |
0 |
| prof2_bk_tx_user_clk2_sel |
0 |
| prof2_fgt_rx_serdes_gray_coding_enable |
0 |
| prof2_fgt_rx_serdes_pre_coding_enable |
0 |
| prof2_fgt_rx_sata_squelch_det_enable |
0 |
| prof2_fgt_rx_serdes_adapt_mode |
auto |
| prof2_fgt_rx_cdr_lock_mode |
manual |
| prof2_fgt_rx_cdr_rxuserclk_enable |
1 |
| prof2_fgt_rx_cdr_rxuserclk_div |
40 |
| prof2_bk_alt_pam4_grey_code |
0 |
| prof2_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof2_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof2_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof2_bk_rx_precode_en |
0 |
| prof2_bk_rx_user_clk1_en |
0 |
| prof2_bk_rx_user_clk1_sel |
0 |
| prof2_bk_rx_user_clk2_en |
0 |
| prof2_bk_rx_user_clk2_sel |
0 |
| prof2_fec_en |
0 |
| prof2_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof2_fec_802p3ck |
0 |
| prof2_fgt_tx_pll_fout_hz |
|
| prof2_fgt_tx_pll_vco_MHz |
|
| prof2_fgt_tx_pll_cascade_enable |
0 |
| prof2_fgt_tx_pll_frac_mode_enable |
0 |
| prof2_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof2_fgt_rx_pll_fout_hz |
1485.000000 |
| prof2_fgt_rx_pll_vco_MHz |
11880.000000 |
| prof2_fgt_rx_pll_refclk_freq_mhz |
148.500000 |
| prof3_num_xcvr |
1 |
| prof3_fgt_protocol_mode |
SDI |
| prof3_pma_modulation |
NRZ |
| prof3_pma_data_rate |
1485 |
| prof3_pma_width |
20 |
| prof3_pma_secondary_profile_refclk_en |
0 |
| prof3_fgt_tx_serdes_gray_coding_enable |
0 |
| prof3_fgt_tx_serdes_pre_coding_enable |
0 |
| prof3_fgt_tx_pll_txuserclk1_enable |
0 |
| prof3_fgt_tx_pll_txuserclk2_enable |
0 |
| prof3_fgt_tx_pll_txuserclk_div |
32 |
| prof3_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof3_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof3_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof3_bk_tx_precode_en |
0 |
| prof3_bk_tx_predivider_en |
0 |
| prof3_bk_tx_user_clk1_en |
0 |
| prof3_bk_tx_user_clk1_sel |
0 |
| prof3_bk_tx_user_clk2_en |
0 |
| prof3_bk_tx_user_clk2_sel |
0 |
| prof3_fgt_rx_serdes_gray_coding_enable |
0 |
| prof3_fgt_rx_serdes_pre_coding_enable |
0 |
| prof3_fgt_rx_sata_squelch_det_enable |
0 |
| prof3_fgt_rx_serdes_adapt_mode |
auto |
| prof3_fgt_rx_cdr_lock_mode |
manual |
| prof3_fgt_rx_cdr_rxuserclk_enable |
1 |
| prof3_fgt_rx_cdr_rxuserclk_div |
80 |
| prof3_bk_alt_pam4_grey_code |
0 |
| prof3_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof3_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof3_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof3_bk_rx_precode_en |
0 |
| prof3_bk_rx_user_clk1_en |
0 |
| prof3_bk_rx_user_clk1_sel |
0 |
| prof3_bk_rx_user_clk2_en |
0 |
| prof3_bk_rx_user_clk2_sel |
0 |
| prof3_fec_en |
0 |
| prof3_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof3_fec_802p3ck |
0 |
| prof3_fgt_tx_pll_fout_hz |
|
| prof3_fgt_tx_pll_vco_MHz |
|
| prof3_fgt_tx_pll_cascade_enable |
0 |
| prof3_fgt_tx_pll_frac_mode_enable |
0 |
| prof3_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof3_fgt_rx_pll_fout_hz |
742.500000 |
| prof3_fgt_rx_pll_vco_MHz |
11880.000000 |
| prof3_fgt_rx_pll_refclk_freq_mhz |
148.500000 |
| prof4_num_xcvr |
1 |
| prof4_fgt_protocol_mode |
DISABLED |
| prof4_pma_modulation |
PAM4 |
| prof4_pma_data_rate |
26562.5 |
| prof4_pma_width |
32 |
| prof4_pma_secondary_profile_refclk_en |
0 |
| prof4_fgt_tx_serdes_gray_coding_enable |
0 |
| prof4_fgt_tx_serdes_pre_coding_enable |
0 |
| prof4_fgt_tx_pll_txuserclk1_enable |
0 |
| prof4_fgt_tx_pll_txuserclk2_enable |
0 |
| prof4_fgt_tx_pll_txuserclk_div |
32 |
| prof4_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof4_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof4_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof4_bk_tx_precode_en |
0 |
| prof4_bk_tx_predivider_en |
0 |
| prof4_bk_tx_user_clk1_en |
0 |
| prof4_bk_tx_user_clk1_sel |
0 |
| prof4_bk_tx_user_clk2_en |
0 |
| prof4_bk_tx_user_clk2_sel |
0 |
| prof4_fgt_rx_serdes_gray_coding_enable |
0 |
| prof4_fgt_rx_serdes_pre_coding_enable |
0 |
| prof4_fgt_rx_sata_squelch_det_enable |
0 |
| prof4_fgt_rx_serdes_adapt_mode |
auto |
| prof4_fgt_rx_cdr_lock_mode |
auto |
| prof4_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof4_fgt_rx_cdr_rxuserclk_div |
32 |
| prof4_bk_alt_pam4_grey_code |
0 |
| prof4_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof4_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof4_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof4_bk_rx_precode_en |
0 |
| prof4_bk_rx_user_clk1_en |
0 |
| prof4_bk_rx_user_clk1_sel |
0 |
| prof4_bk_rx_user_clk2_en |
0 |
| prof4_bk_rx_user_clk2_sel |
0 |
| prof4_fec_en |
0 |
| prof4_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof4_fec_802p3ck |
0 |
| prof4_fgt_tx_pll_fout_hz |
|
| prof4_fgt_tx_pll_vco_MHz |
|
| prof4_fgt_tx_pll_cascade_enable |
0 |
| prof4_fgt_tx_pll_frac_mode_enable |
0 |
| prof4_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof4_fgt_rx_pll_fout_hz |
0 |
| prof4_fgt_rx_pll_vco_MHz |
|
| prof4_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof5_num_xcvr |
1 |
| prof5_fgt_protocol_mode |
DISABLED |
| prof5_pma_modulation |
PAM4 |
| prof5_pma_data_rate |
26562.5 |
| prof5_pma_width |
32 |
| prof5_pma_secondary_profile_refclk_en |
0 |
| prof5_fgt_tx_serdes_gray_coding_enable |
0 |
| prof5_fgt_tx_serdes_pre_coding_enable |
0 |
| prof5_fgt_tx_pll_txuserclk1_enable |
0 |
| prof5_fgt_tx_pll_txuserclk2_enable |
0 |
| prof5_fgt_tx_pll_txuserclk_div |
32 |
| prof5_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof5_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof5_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof5_bk_tx_precode_en |
0 |
| prof5_bk_tx_predivider_en |
0 |
| prof5_bk_tx_user_clk1_en |
0 |
| prof5_bk_tx_user_clk1_sel |
0 |
| prof5_bk_tx_user_clk2_en |
0 |
| prof5_bk_tx_user_clk2_sel |
0 |
| prof5_fgt_rx_serdes_gray_coding_enable |
0 |
| prof5_fgt_rx_serdes_pre_coding_enable |
0 |
| prof5_fgt_rx_sata_squelch_det_enable |
0 |
| prof5_fgt_rx_serdes_adapt_mode |
auto |
| prof5_fgt_rx_cdr_lock_mode |
auto |
| prof5_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof5_fgt_rx_cdr_rxuserclk_div |
32 |
| prof5_bk_alt_pam4_grey_code |
0 |
| prof5_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof5_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof5_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof5_bk_rx_precode_en |
0 |
| prof5_bk_rx_user_clk1_en |
0 |
| prof5_bk_rx_user_clk1_sel |
0 |
| prof5_bk_rx_user_clk2_en |
0 |
| prof5_bk_rx_user_clk2_sel |
0 |
| prof5_fec_en |
0 |
| prof5_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof5_fec_802p3ck |
0 |
| prof5_fgt_tx_pll_fout_hz |
|
| prof5_fgt_tx_pll_vco_MHz |
|
| prof5_fgt_tx_pll_cascade_enable |
0 |
| prof5_fgt_tx_pll_frac_mode_enable |
0 |
| prof5_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof5_fgt_rx_pll_fout_hz |
0 |
| prof5_fgt_rx_pll_vco_MHz |
|
| prof5_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof6_num_xcvr |
1 |
| prof6_fgt_protocol_mode |
DISABLED |
| prof6_pma_modulation |
PAM4 |
| prof6_pma_data_rate |
26562.5 |
| prof6_pma_width |
32 |
| prof6_pma_secondary_profile_refclk_en |
0 |
| prof6_fgt_tx_serdes_gray_coding_enable |
0 |
| prof6_fgt_tx_serdes_pre_coding_enable |
0 |
| prof6_fgt_tx_pll_txuserclk1_enable |
0 |
| prof6_fgt_tx_pll_txuserclk2_enable |
0 |
| prof6_fgt_tx_pll_txuserclk_div |
32 |
| prof6_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof6_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof6_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof6_bk_tx_precode_en |
0 |
| prof6_bk_tx_predivider_en |
0 |
| prof6_bk_tx_user_clk1_en |
0 |
| prof6_bk_tx_user_clk1_sel |
0 |
| prof6_bk_tx_user_clk2_en |
0 |
| prof6_bk_tx_user_clk2_sel |
0 |
| prof6_fgt_rx_serdes_gray_coding_enable |
0 |
| prof6_fgt_rx_serdes_pre_coding_enable |
0 |
| prof6_fgt_rx_sata_squelch_det_enable |
0 |
| prof6_fgt_rx_serdes_adapt_mode |
auto |
| prof6_fgt_rx_cdr_lock_mode |
auto |
| prof6_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof6_fgt_rx_cdr_rxuserclk_div |
32 |
| prof6_bk_alt_pam4_grey_code |
0 |
| prof6_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof6_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof6_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof6_bk_rx_precode_en |
0 |
| prof6_bk_rx_user_clk1_en |
0 |
| prof6_bk_rx_user_clk1_sel |
0 |
| prof6_bk_rx_user_clk2_en |
0 |
| prof6_bk_rx_user_clk2_sel |
0 |
| prof6_fec_en |
0 |
| prof6_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof6_fec_802p3ck |
0 |
| prof6_fgt_tx_pll_fout_hz |
|
| prof6_fgt_tx_pll_vco_MHz |
|
| prof6_fgt_tx_pll_cascade_enable |
0 |
| prof6_fgt_tx_pll_frac_mode_enable |
0 |
| prof6_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof6_fgt_rx_pll_fout_hz |
0 |
| prof6_fgt_rx_pll_vco_MHz |
|
| prof6_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof7_num_xcvr |
1 |
| prof7_fgt_protocol_mode |
DISABLED |
| prof7_pma_modulation |
PAM4 |
| prof7_pma_data_rate |
26562.5 |
| prof7_pma_width |
32 |
| prof7_pma_secondary_profile_refclk_en |
0 |
| prof7_fgt_tx_serdes_gray_coding_enable |
0 |
| prof7_fgt_tx_serdes_pre_coding_enable |
0 |
| prof7_fgt_tx_pll_txuserclk1_enable |
0 |
| prof7_fgt_tx_pll_txuserclk2_enable |
0 |
| prof7_fgt_tx_pll_txuserclk_div |
32 |
| prof7_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof7_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof7_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof7_bk_tx_precode_en |
0 |
| prof7_bk_tx_predivider_en |
0 |
| prof7_bk_tx_user_clk1_en |
0 |
| prof7_bk_tx_user_clk1_sel |
0 |
| prof7_bk_tx_user_clk2_en |
0 |
| prof7_bk_tx_user_clk2_sel |
0 |
| prof7_fgt_rx_serdes_gray_coding_enable |
0 |
| prof7_fgt_rx_serdes_pre_coding_enable |
0 |
| prof7_fgt_rx_sata_squelch_det_enable |
0 |
| prof7_fgt_rx_serdes_adapt_mode |
auto |
| prof7_fgt_rx_cdr_lock_mode |
auto |
| prof7_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof7_fgt_rx_cdr_rxuserclk_div |
32 |
| prof7_bk_alt_pam4_grey_code |
0 |
| prof7_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof7_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof7_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof7_bk_rx_precode_en |
0 |
| prof7_bk_rx_user_clk1_en |
0 |
| prof7_bk_rx_user_clk1_sel |
0 |
| prof7_bk_rx_user_clk2_en |
0 |
| prof7_bk_rx_user_clk2_sel |
0 |
| prof7_fec_en |
0 |
| prof7_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof7_fec_802p3ck |
0 |
| prof7_fgt_tx_pll_fout_hz |
|
| prof7_fgt_tx_pll_vco_MHz |
|
| prof7_fgt_tx_pll_cascade_enable |
0 |
| prof7_fgt_tx_pll_frac_mode_enable |
0 |
| prof7_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof7_fgt_rx_pll_fout_hz |
0 |
| prof7_fgt_rx_pll_vco_MHz |
|
| prof7_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof8_num_xcvr |
1 |
| prof8_fgt_protocol_mode |
DISABLED |
| prof8_pma_modulation |
PAM4 |
| prof8_pma_data_rate |
26562.5 |
| prof8_pma_width |
32 |
| prof8_pma_secondary_profile_refclk_en |
0 |
| prof8_fgt_tx_serdes_gray_coding_enable |
0 |
| prof8_fgt_tx_serdes_pre_coding_enable |
0 |
| prof8_fgt_tx_pll_txuserclk1_enable |
0 |
| prof8_fgt_tx_pll_txuserclk2_enable |
0 |
| prof8_fgt_tx_pll_txuserclk_div |
32 |
| prof8_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof8_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof8_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof8_bk_tx_precode_en |
0 |
| prof8_bk_tx_predivider_en |
0 |
| prof8_bk_tx_user_clk1_en |
0 |
| prof8_bk_tx_user_clk1_sel |
0 |
| prof8_bk_tx_user_clk2_en |
0 |
| prof8_bk_tx_user_clk2_sel |
0 |
| prof8_fgt_rx_serdes_gray_coding_enable |
0 |
| prof8_fgt_rx_serdes_pre_coding_enable |
0 |
| prof8_fgt_rx_sata_squelch_det_enable |
0 |
| prof8_fgt_rx_serdes_adapt_mode |
auto |
| prof8_fgt_rx_cdr_lock_mode |
auto |
| prof8_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof8_fgt_rx_cdr_rxuserclk_div |
32 |
| prof8_bk_alt_pam4_grey_code |
0 |
| prof8_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof8_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof8_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof8_bk_rx_precode_en |
0 |
| prof8_bk_rx_user_clk1_en |
0 |
| prof8_bk_rx_user_clk1_sel |
0 |
| prof8_bk_rx_user_clk2_en |
0 |
| prof8_bk_rx_user_clk2_sel |
0 |
| prof8_fec_en |
0 |
| prof8_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof8_fec_802p3ck |
0 |
| prof8_fgt_tx_pll_fout_hz |
|
| prof8_fgt_tx_pll_vco_MHz |
|
| prof8_fgt_tx_pll_cascade_enable |
0 |
| prof8_fgt_tx_pll_frac_mode_enable |
0 |
| prof8_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof8_fgt_rx_pll_fout_hz |
0 |
| prof8_fgt_rx_pll_vco_MHz |
|
| prof8_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof9_num_xcvr |
1 |
| prof9_fgt_protocol_mode |
DISABLED |
| prof9_pma_modulation |
PAM4 |
| prof9_pma_data_rate |
26562.5 |
| prof9_pma_width |
32 |
| prof9_pma_secondary_profile_refclk_en |
0 |
| prof9_fgt_tx_serdes_gray_coding_enable |
0 |
| prof9_fgt_tx_serdes_pre_coding_enable |
0 |
| prof9_fgt_tx_pll_txuserclk1_enable |
0 |
| prof9_fgt_tx_pll_txuserclk2_enable |
0 |
| prof9_fgt_tx_pll_txuserclk_div |
32 |
| prof9_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof9_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof9_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof9_bk_tx_precode_en |
0 |
| prof9_bk_tx_predivider_en |
0 |
| prof9_bk_tx_user_clk1_en |
0 |
| prof9_bk_tx_user_clk1_sel |
0 |
| prof9_bk_tx_user_clk2_en |
0 |
| prof9_bk_tx_user_clk2_sel |
0 |
| prof9_fgt_rx_serdes_gray_coding_enable |
0 |
| prof9_fgt_rx_serdes_pre_coding_enable |
0 |
| prof9_fgt_rx_sata_squelch_det_enable |
0 |
| prof9_fgt_rx_serdes_adapt_mode |
auto |
| prof9_fgt_rx_cdr_lock_mode |
auto |
| prof9_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof9_fgt_rx_cdr_rxuserclk_div |
32 |
| prof9_bk_alt_pam4_grey_code |
0 |
| prof9_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof9_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof9_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof9_bk_rx_precode_en |
0 |
| prof9_bk_rx_user_clk1_en |
0 |
| prof9_bk_rx_user_clk1_sel |
0 |
| prof9_bk_rx_user_clk2_en |
0 |
| prof9_bk_rx_user_clk2_sel |
0 |
| prof9_fec_en |
0 |
| prof9_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof9_fec_802p3ck |
0 |
| prof9_fgt_tx_pll_fout_hz |
|
| prof9_fgt_tx_pll_vco_MHz |
|
| prof9_fgt_tx_pll_cascade_enable |
0 |
| prof9_fgt_tx_pll_frac_mode_enable |
0 |
| prof9_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof9_fgt_rx_pll_fout_hz |
0 |
| prof9_fgt_rx_pll_vco_MHz |
|
| prof9_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof10_num_xcvr |
1 |
| prof10_fgt_protocol_mode |
DISABLED |
| prof10_pma_modulation |
PAM4 |
| prof10_pma_data_rate |
26562.5 |
| prof10_pma_width |
32 |
| prof10_pma_secondary_profile_refclk_en |
0 |
| prof10_fgt_tx_serdes_gray_coding_enable |
0 |
| prof10_fgt_tx_serdes_pre_coding_enable |
0 |
| prof10_fgt_tx_pll_txuserclk1_enable |
0 |
| prof10_fgt_tx_pll_txuserclk2_enable |
0 |
| prof10_fgt_tx_pll_txuserclk_div |
32 |
| prof10_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof10_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof10_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof10_bk_tx_precode_en |
0 |
| prof10_bk_tx_predivider_en |
0 |
| prof10_bk_tx_user_clk1_en |
0 |
| prof10_bk_tx_user_clk1_sel |
0 |
| prof10_bk_tx_user_clk2_en |
0 |
| prof10_bk_tx_user_clk2_sel |
0 |
| prof10_fgt_rx_serdes_gray_coding_enable |
0 |
| prof10_fgt_rx_serdes_pre_coding_enable |
0 |
| prof10_fgt_rx_sata_squelch_det_enable |
0 |
| prof10_fgt_rx_serdes_adapt_mode |
auto |
| prof10_fgt_rx_cdr_lock_mode |
auto |
| prof10_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof10_fgt_rx_cdr_rxuserclk_div |
32 |
| prof10_bk_alt_pam4_grey_code |
0 |
| prof10_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof10_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof10_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof10_bk_rx_precode_en |
0 |
| prof10_bk_rx_user_clk1_en |
0 |
| prof10_bk_rx_user_clk1_sel |
0 |
| prof10_bk_rx_user_clk2_en |
0 |
| prof10_bk_rx_user_clk2_sel |
0 |
| prof10_fec_en |
0 |
| prof10_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof10_fec_802p3ck |
0 |
| prof10_fgt_tx_pll_fout_hz |
|
| prof10_fgt_tx_pll_vco_MHz |
|
| prof10_fgt_tx_pll_cascade_enable |
0 |
| prof10_fgt_tx_pll_frac_mode_enable |
0 |
| prof10_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof10_fgt_rx_pll_fout_hz |
0 |
| prof10_fgt_rx_pll_vco_MHz |
|
| prof10_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof11_num_xcvr |
1 |
| prof11_fgt_protocol_mode |
DISABLED |
| prof11_pma_modulation |
PAM4 |
| prof11_pma_data_rate |
26562.5 |
| prof11_pma_width |
32 |
| prof11_pma_secondary_profile_refclk_en |
0 |
| prof11_fgt_tx_serdes_gray_coding_enable |
0 |
| prof11_fgt_tx_serdes_pre_coding_enable |
0 |
| prof11_fgt_tx_pll_txuserclk1_enable |
0 |
| prof11_fgt_tx_pll_txuserclk2_enable |
0 |
| prof11_fgt_tx_pll_txuserclk_div |
32 |
| prof11_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof11_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof11_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof11_bk_tx_precode_en |
0 |
| prof11_bk_tx_predivider_en |
0 |
| prof11_bk_tx_user_clk1_en |
0 |
| prof11_bk_tx_user_clk1_sel |
0 |
| prof11_bk_tx_user_clk2_en |
0 |
| prof11_bk_tx_user_clk2_sel |
0 |
| prof11_fgt_rx_serdes_gray_coding_enable |
0 |
| prof11_fgt_rx_serdes_pre_coding_enable |
0 |
| prof11_fgt_rx_sata_squelch_det_enable |
0 |
| prof11_fgt_rx_serdes_adapt_mode |
auto |
| prof11_fgt_rx_cdr_lock_mode |
auto |
| prof11_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof11_fgt_rx_cdr_rxuserclk_div |
32 |
| prof11_bk_alt_pam4_grey_code |
0 |
| prof11_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof11_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof11_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof11_bk_rx_precode_en |
0 |
| prof11_bk_rx_user_clk1_en |
0 |
| prof11_bk_rx_user_clk1_sel |
0 |
| prof11_bk_rx_user_clk2_en |
0 |
| prof11_bk_rx_user_clk2_sel |
0 |
| prof11_fec_en |
0 |
| prof11_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof11_fec_802p3ck |
0 |
| prof11_fgt_tx_pll_fout_hz |
|
| prof11_fgt_tx_pll_vco_MHz |
|
| prof11_fgt_tx_pll_cascade_enable |
0 |
| prof11_fgt_tx_pll_frac_mode_enable |
0 |
| prof11_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof11_fgt_rx_pll_fout_hz |
0 |
| prof11_fgt_rx_pll_vco_MHz |
|
| prof11_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof12_num_xcvr |
1 |
| prof12_fgt_protocol_mode |
DISABLED |
| prof12_pma_modulation |
PAM4 |
| prof12_pma_data_rate |
26562.5 |
| prof12_pma_width |
32 |
| prof12_pma_secondary_profile_refclk_en |
0 |
| prof12_fgt_tx_serdes_gray_coding_enable |
0 |
| prof12_fgt_tx_serdes_pre_coding_enable |
0 |
| prof12_fgt_tx_pll_txuserclk1_enable |
0 |
| prof12_fgt_tx_pll_txuserclk2_enable |
0 |
| prof12_fgt_tx_pll_txuserclk_div |
32 |
| prof12_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof12_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof12_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof12_bk_tx_precode_en |
0 |
| prof12_bk_tx_predivider_en |
0 |
| prof12_bk_tx_user_clk1_en |
0 |
| prof12_bk_tx_user_clk1_sel |
0 |
| prof12_bk_tx_user_clk2_en |
0 |
| prof12_bk_tx_user_clk2_sel |
0 |
| prof12_fgt_rx_serdes_gray_coding_enable |
0 |
| prof12_fgt_rx_serdes_pre_coding_enable |
0 |
| prof12_fgt_rx_sata_squelch_det_enable |
0 |
| prof12_fgt_rx_serdes_adapt_mode |
auto |
| prof12_fgt_rx_cdr_lock_mode |
auto |
| prof12_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof12_fgt_rx_cdr_rxuserclk_div |
32 |
| prof12_bk_alt_pam4_grey_code |
0 |
| prof12_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof12_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof12_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof12_bk_rx_precode_en |
0 |
| prof12_bk_rx_user_clk1_en |
0 |
| prof12_bk_rx_user_clk1_sel |
0 |
| prof12_bk_rx_user_clk2_en |
0 |
| prof12_bk_rx_user_clk2_sel |
0 |
| prof12_fec_en |
0 |
| prof12_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof12_fec_802p3ck |
0 |
| prof12_fgt_tx_pll_fout_hz |
|
| prof12_fgt_tx_pll_vco_MHz |
|
| prof12_fgt_tx_pll_cascade_enable |
0 |
| prof12_fgt_tx_pll_frac_mode_enable |
0 |
| prof12_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof12_fgt_rx_pll_fout_hz |
0 |
| prof12_fgt_rx_pll_vco_MHz |
|
| prof12_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof13_num_xcvr |
1 |
| prof13_fgt_protocol_mode |
DISABLED |
| prof13_pma_modulation |
PAM4 |
| prof13_pma_data_rate |
26562.5 |
| prof13_pma_width |
32 |
| prof13_pma_secondary_profile_refclk_en |
0 |
| prof13_fgt_tx_serdes_gray_coding_enable |
0 |
| prof13_fgt_tx_serdes_pre_coding_enable |
0 |
| prof13_fgt_tx_pll_txuserclk1_enable |
0 |
| prof13_fgt_tx_pll_txuserclk2_enable |
0 |
| prof13_fgt_tx_pll_txuserclk_div |
32 |
| prof13_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof13_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof13_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof13_bk_tx_precode_en |
0 |
| prof13_bk_tx_predivider_en |
0 |
| prof13_bk_tx_user_clk1_en |
0 |
| prof13_bk_tx_user_clk1_sel |
0 |
| prof13_bk_tx_user_clk2_en |
0 |
| prof13_bk_tx_user_clk2_sel |
0 |
| prof13_fgt_rx_serdes_gray_coding_enable |
0 |
| prof13_fgt_rx_serdes_pre_coding_enable |
0 |
| prof13_fgt_rx_sata_squelch_det_enable |
0 |
| prof13_fgt_rx_serdes_adapt_mode |
auto |
| prof13_fgt_rx_cdr_lock_mode |
auto |
| prof13_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof13_fgt_rx_cdr_rxuserclk_div |
32 |
| prof13_bk_alt_pam4_grey_code |
0 |
| prof13_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof13_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof13_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof13_bk_rx_precode_en |
0 |
| prof13_bk_rx_user_clk1_en |
0 |
| prof13_bk_rx_user_clk1_sel |
0 |
| prof13_bk_rx_user_clk2_en |
0 |
| prof13_bk_rx_user_clk2_sel |
0 |
| prof13_fec_en |
0 |
| prof13_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof13_fec_802p3ck |
0 |
| prof13_fgt_tx_pll_fout_hz |
|
| prof13_fgt_tx_pll_vco_MHz |
|
| prof13_fgt_tx_pll_cascade_enable |
0 |
| prof13_fgt_tx_pll_frac_mode_enable |
0 |
| prof13_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof13_fgt_rx_pll_fout_hz |
0 |
| prof13_fgt_rx_pll_vco_MHz |
|
| prof13_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof14_num_xcvr |
1 |
| prof14_fgt_protocol_mode |
DISABLED |
| prof14_pma_modulation |
PAM4 |
| prof14_pma_data_rate |
26562.5 |
| prof14_pma_width |
32 |
| prof14_pma_secondary_profile_refclk_en |
0 |
| prof14_fgt_tx_serdes_gray_coding_enable |
0 |
| prof14_fgt_tx_serdes_pre_coding_enable |
0 |
| prof14_fgt_tx_pll_txuserclk1_enable |
0 |
| prof14_fgt_tx_pll_txuserclk2_enable |
0 |
| prof14_fgt_tx_pll_txuserclk_div |
32 |
| prof14_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof14_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof14_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof14_bk_tx_precode_en |
0 |
| prof14_bk_tx_predivider_en |
0 |
| prof14_bk_tx_user_clk1_en |
0 |
| prof14_bk_tx_user_clk1_sel |
0 |
| prof14_bk_tx_user_clk2_en |
0 |
| prof14_bk_tx_user_clk2_sel |
0 |
| prof14_fgt_rx_serdes_gray_coding_enable |
0 |
| prof14_fgt_rx_serdes_pre_coding_enable |
0 |
| prof14_fgt_rx_sata_squelch_det_enable |
0 |
| prof14_fgt_rx_serdes_adapt_mode |
auto |
| prof14_fgt_rx_cdr_lock_mode |
auto |
| prof14_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof14_fgt_rx_cdr_rxuserclk_div |
32 |
| prof14_bk_alt_pam4_grey_code |
0 |
| prof14_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof14_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof14_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof14_bk_rx_precode_en |
0 |
| prof14_bk_rx_user_clk1_en |
0 |
| prof14_bk_rx_user_clk1_sel |
0 |
| prof14_bk_rx_user_clk2_en |
0 |
| prof14_bk_rx_user_clk2_sel |
0 |
| prof14_fec_en |
0 |
| prof14_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof14_fec_802p3ck |
0 |
| prof14_fgt_tx_pll_fout_hz |
|
| prof14_fgt_tx_pll_vco_MHz |
|
| prof14_fgt_tx_pll_cascade_enable |
0 |
| prof14_fgt_tx_pll_frac_mode_enable |
0 |
| prof14_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof14_fgt_rx_pll_fout_hz |
0 |
| prof14_fgt_rx_pll_vco_MHz |
|
| prof14_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof15_num_xcvr |
1 |
| prof15_fgt_protocol_mode |
DISABLED |
| prof15_pma_modulation |
PAM4 |
| prof15_pma_data_rate |
26562.5 |
| prof15_pma_width |
32 |
| prof15_pma_secondary_profile_refclk_en |
0 |
| prof15_fgt_tx_serdes_gray_coding_enable |
0 |
| prof15_fgt_tx_serdes_pre_coding_enable |
0 |
| prof15_fgt_tx_pll_txuserclk1_enable |
0 |
| prof15_fgt_tx_pll_txuserclk2_enable |
0 |
| prof15_fgt_tx_pll_txuserclk_div |
32 |
| prof15_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof15_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof15_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof15_bk_tx_precode_en |
0 |
| prof15_bk_tx_predivider_en |
0 |
| prof15_bk_tx_user_clk1_en |
0 |
| prof15_bk_tx_user_clk1_sel |
0 |
| prof15_bk_tx_user_clk2_en |
0 |
| prof15_bk_tx_user_clk2_sel |
0 |
| prof15_fgt_rx_serdes_gray_coding_enable |
0 |
| prof15_fgt_rx_serdes_pre_coding_enable |
0 |
| prof15_fgt_rx_sata_squelch_det_enable |
0 |
| prof15_fgt_rx_serdes_adapt_mode |
auto |
| prof15_fgt_rx_cdr_lock_mode |
auto |
| prof15_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof15_fgt_rx_cdr_rxuserclk_div |
32 |
| prof15_bk_alt_pam4_grey_code |
0 |
| prof15_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof15_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof15_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof15_bk_rx_precode_en |
0 |
| prof15_bk_rx_user_clk1_en |
0 |
| prof15_bk_rx_user_clk1_sel |
0 |
| prof15_bk_rx_user_clk2_en |
0 |
| prof15_bk_rx_user_clk2_sel |
0 |
| prof15_fec_en |
0 |
| prof15_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof15_fec_802p3ck |
0 |
| prof15_fgt_tx_pll_fout_hz |
|
| prof15_fgt_tx_pll_vco_MHz |
|
| prof15_fgt_tx_pll_cascade_enable |
0 |
| prof15_fgt_tx_pll_frac_mode_enable |
0 |
| prof15_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof15_fgt_rx_pll_fout_hz |
0 |
| prof15_fgt_rx_pll_vco_MHz |
|
| prof15_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof16_num_xcvr |
1 |
| prof16_fgt_protocol_mode |
DISABLED |
| prof16_pma_modulation |
PAM4 |
| prof16_pma_data_rate |
26562.5 |
| prof16_pma_width |
32 |
| prof16_pma_secondary_profile_refclk_en |
0 |
| prof16_fgt_tx_serdes_gray_coding_enable |
0 |
| prof16_fgt_tx_serdes_pre_coding_enable |
0 |
| prof16_fgt_tx_pll_txuserclk1_enable |
0 |
| prof16_fgt_tx_pll_txuserclk2_enable |
0 |
| prof16_fgt_tx_pll_txuserclk_div |
32 |
| prof16_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof16_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof16_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof16_bk_tx_precode_en |
0 |
| prof16_bk_tx_predivider_en |
0 |
| prof16_bk_tx_user_clk1_en |
0 |
| prof16_bk_tx_user_clk1_sel |
0 |
| prof16_bk_tx_user_clk2_en |
0 |
| prof16_bk_tx_user_clk2_sel |
0 |
| prof16_fgt_rx_serdes_gray_coding_enable |
0 |
| prof16_fgt_rx_serdes_pre_coding_enable |
0 |
| prof16_fgt_rx_sata_squelch_det_enable |
0 |
| prof16_fgt_rx_serdes_adapt_mode |
auto |
| prof16_fgt_rx_cdr_lock_mode |
auto |
| prof16_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof16_fgt_rx_cdr_rxuserclk_div |
32 |
| prof16_bk_alt_pam4_grey_code |
0 |
| prof16_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof16_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof16_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof16_bk_rx_precode_en |
0 |
| prof16_bk_rx_user_clk1_en |
0 |
| prof16_bk_rx_user_clk1_sel |
0 |
| prof16_bk_rx_user_clk2_en |
0 |
| prof16_bk_rx_user_clk2_sel |
0 |
| prof16_fec_en |
0 |
| prof16_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof16_fec_802p3ck |
0 |
| prof16_fgt_tx_pll_fout_hz |
|
| prof16_fgt_tx_pll_vco_MHz |
|
| prof16_fgt_tx_pll_cascade_enable |
0 |
| prof16_fgt_tx_pll_frac_mode_enable |
0 |
| prof16_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof16_fgt_rx_pll_fout_hz |
0 |
| prof16_fgt_rx_pll_vco_MHz |
|
| prof16_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof17_num_xcvr |
1 |
| prof17_fgt_protocol_mode |
DISABLED |
| prof17_pma_modulation |
PAM4 |
| prof17_pma_data_rate |
26562.5 |
| prof17_pma_width |
32 |
| prof17_pma_secondary_profile_refclk_en |
0 |
| prof17_fgt_tx_serdes_gray_coding_enable |
0 |
| prof17_fgt_tx_serdes_pre_coding_enable |
0 |
| prof17_fgt_tx_pll_txuserclk1_enable |
0 |
| prof17_fgt_tx_pll_txuserclk2_enable |
0 |
| prof17_fgt_tx_pll_txuserclk_div |
32 |
| prof17_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof17_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof17_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof17_bk_tx_precode_en |
0 |
| prof17_bk_tx_predivider_en |
0 |
| prof17_bk_tx_user_clk1_en |
0 |
| prof17_bk_tx_user_clk1_sel |
0 |
| prof17_bk_tx_user_clk2_en |
0 |
| prof17_bk_tx_user_clk2_sel |
0 |
| prof17_fgt_rx_serdes_gray_coding_enable |
0 |
| prof17_fgt_rx_serdes_pre_coding_enable |
0 |
| prof17_fgt_rx_sata_squelch_det_enable |
0 |
| prof17_fgt_rx_serdes_adapt_mode |
auto |
| prof17_fgt_rx_cdr_lock_mode |
auto |
| prof17_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof17_fgt_rx_cdr_rxuserclk_div |
32 |
| prof17_bk_alt_pam4_grey_code |
0 |
| prof17_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof17_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof17_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof17_bk_rx_precode_en |
0 |
| prof17_bk_rx_user_clk1_en |
0 |
| prof17_bk_rx_user_clk1_sel |
0 |
| prof17_bk_rx_user_clk2_en |
0 |
| prof17_bk_rx_user_clk2_sel |
0 |
| prof17_fec_en |
0 |
| prof17_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof17_fec_802p3ck |
0 |
| prof17_fgt_tx_pll_fout_hz |
|
| prof17_fgt_tx_pll_vco_MHz |
|
| prof17_fgt_tx_pll_cascade_enable |
0 |
| prof17_fgt_tx_pll_frac_mode_enable |
0 |
| prof17_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof17_fgt_rx_pll_fout_hz |
0 |
| prof17_fgt_rx_pll_vco_MHz |
|
| prof17_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof18_num_xcvr |
1 |
| prof18_fgt_protocol_mode |
DISABLED |
| prof18_pma_modulation |
PAM4 |
| prof18_pma_data_rate |
26562.5 |
| prof18_pma_width |
32 |
| prof18_pma_secondary_profile_refclk_en |
0 |
| prof18_fgt_tx_serdes_gray_coding_enable |
0 |
| prof18_fgt_tx_serdes_pre_coding_enable |
0 |
| prof18_fgt_tx_pll_txuserclk1_enable |
0 |
| prof18_fgt_tx_pll_txuserclk2_enable |
0 |
| prof18_fgt_tx_pll_txuserclk_div |
32 |
| prof18_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof18_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof18_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof18_bk_tx_precode_en |
0 |
| prof18_bk_tx_predivider_en |
0 |
| prof18_bk_tx_user_clk1_en |
0 |
| prof18_bk_tx_user_clk1_sel |
0 |
| prof18_bk_tx_user_clk2_en |
0 |
| prof18_bk_tx_user_clk2_sel |
0 |
| prof18_fgt_rx_serdes_gray_coding_enable |
0 |
| prof18_fgt_rx_serdes_pre_coding_enable |
0 |
| prof18_fgt_rx_sata_squelch_det_enable |
0 |
| prof18_fgt_rx_serdes_adapt_mode |
auto |
| prof18_fgt_rx_cdr_lock_mode |
auto |
| prof18_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof18_fgt_rx_cdr_rxuserclk_div |
32 |
| prof18_bk_alt_pam4_grey_code |
0 |
| prof18_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof18_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof18_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof18_bk_rx_precode_en |
0 |
| prof18_bk_rx_user_clk1_en |
0 |
| prof18_bk_rx_user_clk1_sel |
0 |
| prof18_bk_rx_user_clk2_en |
0 |
| prof18_bk_rx_user_clk2_sel |
0 |
| prof18_fec_en |
0 |
| prof18_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof18_fec_802p3ck |
0 |
| prof18_fgt_tx_pll_fout_hz |
|
| prof18_fgt_tx_pll_vco_MHz |
|
| prof18_fgt_tx_pll_cascade_enable |
0 |
| prof18_fgt_tx_pll_frac_mode_enable |
0 |
| prof18_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof18_fgt_rx_pll_fout_hz |
0 |
| prof18_fgt_rx_pll_vco_MHz |
|
| prof18_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof19_num_xcvr |
1 |
| prof19_fgt_protocol_mode |
DISABLED |
| prof19_pma_modulation |
PAM4 |
| prof19_pma_data_rate |
26562.5 |
| prof19_pma_width |
32 |
| prof19_pma_secondary_profile_refclk_en |
0 |
| prof19_fgt_tx_serdes_gray_coding_enable |
0 |
| prof19_fgt_tx_serdes_pre_coding_enable |
0 |
| prof19_fgt_tx_pll_txuserclk1_enable |
0 |
| prof19_fgt_tx_pll_txuserclk2_enable |
0 |
| prof19_fgt_tx_pll_txuserclk_div |
32 |
| prof19_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof19_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof19_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof19_bk_tx_precode_en |
0 |
| prof19_bk_tx_predivider_en |
0 |
| prof19_bk_tx_user_clk1_en |
0 |
| prof19_bk_tx_user_clk1_sel |
0 |
| prof19_bk_tx_user_clk2_en |
0 |
| prof19_bk_tx_user_clk2_sel |
0 |
| prof19_fgt_rx_serdes_gray_coding_enable |
0 |
| prof19_fgt_rx_serdes_pre_coding_enable |
0 |
| prof19_fgt_rx_sata_squelch_det_enable |
0 |
| prof19_fgt_rx_serdes_adapt_mode |
auto |
| prof19_fgt_rx_cdr_lock_mode |
auto |
| prof19_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof19_fgt_rx_cdr_rxuserclk_div |
32 |
| prof19_bk_alt_pam4_grey_code |
0 |
| prof19_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof19_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof19_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof19_bk_rx_precode_en |
0 |
| prof19_bk_rx_user_clk1_en |
0 |
| prof19_bk_rx_user_clk1_sel |
0 |
| prof19_bk_rx_user_clk2_en |
0 |
| prof19_bk_rx_user_clk2_sel |
0 |
| prof19_fec_en |
0 |
| prof19_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof19_fec_802p3ck |
0 |
| prof19_fgt_tx_pll_fout_hz |
|
| prof19_fgt_tx_pll_vco_MHz |
|
| prof19_fgt_tx_pll_cascade_enable |
0 |
| prof19_fgt_tx_pll_frac_mode_enable |
0 |
| prof19_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof19_fgt_rx_pll_fout_hz |
0 |
| prof19_fgt_rx_pll_vco_MHz |
|
| prof19_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof20_num_xcvr |
1 |
| prof20_fgt_protocol_mode |
DISABLED |
| prof20_pma_modulation |
PAM4 |
| prof20_pma_data_rate |
26562.5 |
| prof20_pma_width |
32 |
| prof20_pma_secondary_profile_refclk_en |
0 |
| prof20_fgt_tx_serdes_gray_coding_enable |
0 |
| prof20_fgt_tx_serdes_pre_coding_enable |
0 |
| prof20_fgt_tx_pll_txuserclk1_enable |
0 |
| prof20_fgt_tx_pll_txuserclk2_enable |
0 |
| prof20_fgt_tx_pll_txuserclk_div |
32 |
| prof20_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof20_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof20_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof20_bk_tx_precode_en |
0 |
| prof20_bk_tx_predivider_en |
0 |
| prof20_bk_tx_user_clk1_en |
0 |
| prof20_bk_tx_user_clk1_sel |
0 |
| prof20_bk_tx_user_clk2_en |
0 |
| prof20_bk_tx_user_clk2_sel |
0 |
| prof20_fgt_rx_serdes_gray_coding_enable |
0 |
| prof20_fgt_rx_serdes_pre_coding_enable |
0 |
| prof20_fgt_rx_sata_squelch_det_enable |
0 |
| prof20_fgt_rx_serdes_adapt_mode |
auto |
| prof20_fgt_rx_cdr_lock_mode |
auto |
| prof20_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof20_fgt_rx_cdr_rxuserclk_div |
32 |
| prof20_bk_alt_pam4_grey_code |
0 |
| prof20_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof20_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof20_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof20_bk_rx_precode_en |
0 |
| prof20_bk_rx_user_clk1_en |
0 |
| prof20_bk_rx_user_clk1_sel |
0 |
| prof20_bk_rx_user_clk2_en |
0 |
| prof20_bk_rx_user_clk2_sel |
0 |
| prof20_fec_en |
0 |
| prof20_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof20_fec_802p3ck |
0 |
| prof20_fgt_tx_pll_fout_hz |
|
| prof20_fgt_tx_pll_vco_MHz |
|
| prof20_fgt_tx_pll_cascade_enable |
0 |
| prof20_fgt_tx_pll_frac_mode_enable |
0 |
| prof20_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof20_fgt_rx_pll_fout_hz |
0 |
| prof20_fgt_rx_pll_vco_MHz |
|
| prof20_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof21_num_xcvr |
1 |
| prof21_fgt_protocol_mode |
DISABLED |
| prof21_pma_modulation |
PAM4 |
| prof21_pma_data_rate |
26562.5 |
| prof21_pma_width |
32 |
| prof21_pma_secondary_profile_refclk_en |
0 |
| prof21_fgt_tx_serdes_gray_coding_enable |
0 |
| prof21_fgt_tx_serdes_pre_coding_enable |
0 |
| prof21_fgt_tx_pll_txuserclk1_enable |
0 |
| prof21_fgt_tx_pll_txuserclk2_enable |
0 |
| prof21_fgt_tx_pll_txuserclk_div |
32 |
| prof21_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof21_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof21_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof21_bk_tx_precode_en |
0 |
| prof21_bk_tx_predivider_en |
0 |
| prof21_bk_tx_user_clk1_en |
0 |
| prof21_bk_tx_user_clk1_sel |
0 |
| prof21_bk_tx_user_clk2_en |
0 |
| prof21_bk_tx_user_clk2_sel |
0 |
| prof21_fgt_rx_serdes_gray_coding_enable |
0 |
| prof21_fgt_rx_serdes_pre_coding_enable |
0 |
| prof21_fgt_rx_sata_squelch_det_enable |
0 |
| prof21_fgt_rx_serdes_adapt_mode |
auto |
| prof21_fgt_rx_cdr_lock_mode |
auto |
| prof21_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof21_fgt_rx_cdr_rxuserclk_div |
32 |
| prof21_bk_alt_pam4_grey_code |
0 |
| prof21_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof21_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof21_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof21_bk_rx_precode_en |
0 |
| prof21_bk_rx_user_clk1_en |
0 |
| prof21_bk_rx_user_clk1_sel |
0 |
| prof21_bk_rx_user_clk2_en |
0 |
| prof21_bk_rx_user_clk2_sel |
0 |
| prof21_fec_en |
0 |
| prof21_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof21_fec_802p3ck |
0 |
| prof21_fgt_tx_pll_fout_hz |
|
| prof21_fgt_tx_pll_vco_MHz |
|
| prof21_fgt_tx_pll_cascade_enable |
0 |
| prof21_fgt_tx_pll_frac_mode_enable |
0 |
| prof21_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof21_fgt_rx_pll_fout_hz |
0 |
| prof21_fgt_rx_pll_vco_MHz |
|
| prof21_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof22_num_xcvr |
1 |
| prof22_fgt_protocol_mode |
DISABLED |
| prof22_pma_modulation |
PAM4 |
| prof22_pma_data_rate |
26562.5 |
| prof22_pma_width |
32 |
| prof22_pma_secondary_profile_refclk_en |
0 |
| prof22_fgt_tx_serdes_gray_coding_enable |
0 |
| prof22_fgt_tx_serdes_pre_coding_enable |
0 |
| prof22_fgt_tx_pll_txuserclk1_enable |
0 |
| prof22_fgt_tx_pll_txuserclk2_enable |
0 |
| prof22_fgt_tx_pll_txuserclk_div |
32 |
| prof22_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof22_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof22_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof22_bk_tx_precode_en |
0 |
| prof22_bk_tx_predivider_en |
0 |
| prof22_bk_tx_user_clk1_en |
0 |
| prof22_bk_tx_user_clk1_sel |
0 |
| prof22_bk_tx_user_clk2_en |
0 |
| prof22_bk_tx_user_clk2_sel |
0 |
| prof22_fgt_rx_serdes_gray_coding_enable |
0 |
| prof22_fgt_rx_serdes_pre_coding_enable |
0 |
| prof22_fgt_rx_sata_squelch_det_enable |
0 |
| prof22_fgt_rx_serdes_adapt_mode |
auto |
| prof22_fgt_rx_cdr_lock_mode |
auto |
| prof22_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof22_fgt_rx_cdr_rxuserclk_div |
32 |
| prof22_bk_alt_pam4_grey_code |
0 |
| prof22_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof22_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof22_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof22_bk_rx_precode_en |
0 |
| prof22_bk_rx_user_clk1_en |
0 |
| prof22_bk_rx_user_clk1_sel |
0 |
| prof22_bk_rx_user_clk2_en |
0 |
| prof22_bk_rx_user_clk2_sel |
0 |
| prof22_fec_en |
0 |
| prof22_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof22_fec_802p3ck |
0 |
| prof22_fgt_tx_pll_fout_hz |
|
| prof22_fgt_tx_pll_vco_MHz |
|
| prof22_fgt_tx_pll_cascade_enable |
0 |
| prof22_fgt_tx_pll_frac_mode_enable |
0 |
| prof22_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof22_fgt_rx_pll_fout_hz |
0 |
| prof22_fgt_rx_pll_vco_MHz |
|
| prof22_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof23_num_xcvr |
1 |
| prof23_fgt_protocol_mode |
DISABLED |
| prof23_pma_modulation |
PAM4 |
| prof23_pma_data_rate |
26562.5 |
| prof23_pma_width |
32 |
| prof23_pma_secondary_profile_refclk_en |
0 |
| prof23_fgt_tx_serdes_gray_coding_enable |
0 |
| prof23_fgt_tx_serdes_pre_coding_enable |
0 |
| prof23_fgt_tx_pll_txuserclk1_enable |
0 |
| prof23_fgt_tx_pll_txuserclk2_enable |
0 |
| prof23_fgt_tx_pll_txuserclk_div |
32 |
| prof23_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof23_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof23_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof23_bk_tx_precode_en |
0 |
| prof23_bk_tx_predivider_en |
0 |
| prof23_bk_tx_user_clk1_en |
0 |
| prof23_bk_tx_user_clk1_sel |
0 |
| prof23_bk_tx_user_clk2_en |
0 |
| prof23_bk_tx_user_clk2_sel |
0 |
| prof23_fgt_rx_serdes_gray_coding_enable |
0 |
| prof23_fgt_rx_serdes_pre_coding_enable |
0 |
| prof23_fgt_rx_sata_squelch_det_enable |
0 |
| prof23_fgt_rx_serdes_adapt_mode |
auto |
| prof23_fgt_rx_cdr_lock_mode |
auto |
| prof23_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof23_fgt_rx_cdr_rxuserclk_div |
32 |
| prof23_bk_alt_pam4_grey_code |
0 |
| prof23_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof23_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof23_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof23_bk_rx_precode_en |
0 |
| prof23_bk_rx_user_clk1_en |
0 |
| prof23_bk_rx_user_clk1_sel |
0 |
| prof23_bk_rx_user_clk2_en |
0 |
| prof23_bk_rx_user_clk2_sel |
0 |
| prof23_fec_en |
0 |
| prof23_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof23_fec_802p3ck |
0 |
| prof23_fgt_tx_pll_fout_hz |
|
| prof23_fgt_tx_pll_vco_MHz |
|
| prof23_fgt_tx_pll_cascade_enable |
0 |
| prof23_fgt_tx_pll_frac_mode_enable |
0 |
| prof23_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof23_fgt_rx_pll_fout_hz |
0 |
| prof23_fgt_rx_pll_vco_MHz |
|
| prof23_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof24_num_xcvr |
1 |
| prof24_fgt_protocol_mode |
DISABLED |
| prof24_pma_modulation |
PAM4 |
| prof24_pma_data_rate |
26562.5 |
| prof24_pma_width |
32 |
| prof24_pma_secondary_profile_refclk_en |
0 |
| prof24_fgt_tx_serdes_gray_coding_enable |
0 |
| prof24_fgt_tx_serdes_pre_coding_enable |
0 |
| prof24_fgt_tx_pll_txuserclk1_enable |
0 |
| prof24_fgt_tx_pll_txuserclk2_enable |
0 |
| prof24_fgt_tx_pll_txuserclk_div |
32 |
| prof24_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof24_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof24_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof24_bk_tx_precode_en |
0 |
| prof24_bk_tx_predivider_en |
0 |
| prof24_bk_tx_user_clk1_en |
0 |
| prof24_bk_tx_user_clk1_sel |
0 |
| prof24_bk_tx_user_clk2_en |
0 |
| prof24_bk_tx_user_clk2_sel |
0 |
| prof24_fgt_rx_serdes_gray_coding_enable |
0 |
| prof24_fgt_rx_serdes_pre_coding_enable |
0 |
| prof24_fgt_rx_sata_squelch_det_enable |
0 |
| prof24_fgt_rx_serdes_adapt_mode |
auto |
| prof24_fgt_rx_cdr_lock_mode |
auto |
| prof24_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof24_fgt_rx_cdr_rxuserclk_div |
32 |
| prof24_bk_alt_pam4_grey_code |
0 |
| prof24_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof24_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof24_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof24_bk_rx_precode_en |
0 |
| prof24_bk_rx_user_clk1_en |
0 |
| prof24_bk_rx_user_clk1_sel |
0 |
| prof24_bk_rx_user_clk2_en |
0 |
| prof24_bk_rx_user_clk2_sel |
0 |
| prof24_fec_en |
0 |
| prof24_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof24_fec_802p3ck |
0 |
| prof24_fgt_tx_pll_fout_hz |
|
| prof24_fgt_tx_pll_vco_MHz |
|
| prof24_fgt_tx_pll_cascade_enable |
0 |
| prof24_fgt_tx_pll_frac_mode_enable |
0 |
| prof24_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof24_fgt_rx_pll_fout_hz |
0 |
| prof24_fgt_rx_pll_vco_MHz |
|
| prof24_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof25_num_xcvr |
1 |
| prof25_fgt_protocol_mode |
DISABLED |
| prof25_pma_modulation |
PAM4 |
| prof25_pma_data_rate |
26562.5 |
| prof25_pma_width |
32 |
| prof25_pma_secondary_profile_refclk_en |
0 |
| prof25_fgt_tx_serdes_gray_coding_enable |
0 |
| prof25_fgt_tx_serdes_pre_coding_enable |
0 |
| prof25_fgt_tx_pll_txuserclk1_enable |
0 |
| prof25_fgt_tx_pll_txuserclk2_enable |
0 |
| prof25_fgt_tx_pll_txuserclk_div |
32 |
| prof25_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof25_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof25_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof25_bk_tx_precode_en |
0 |
| prof25_bk_tx_predivider_en |
0 |
| prof25_bk_tx_user_clk1_en |
0 |
| prof25_bk_tx_user_clk1_sel |
0 |
| prof25_bk_tx_user_clk2_en |
0 |
| prof25_bk_tx_user_clk2_sel |
0 |
| prof25_fgt_rx_serdes_gray_coding_enable |
0 |
| prof25_fgt_rx_serdes_pre_coding_enable |
0 |
| prof25_fgt_rx_sata_squelch_det_enable |
0 |
| prof25_fgt_rx_serdes_adapt_mode |
auto |
| prof25_fgt_rx_cdr_lock_mode |
auto |
| prof25_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof25_fgt_rx_cdr_rxuserclk_div |
32 |
| prof25_bk_alt_pam4_grey_code |
0 |
| prof25_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof25_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof25_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof25_bk_rx_precode_en |
0 |
| prof25_bk_rx_user_clk1_en |
0 |
| prof25_bk_rx_user_clk1_sel |
0 |
| prof25_bk_rx_user_clk2_en |
0 |
| prof25_bk_rx_user_clk2_sel |
0 |
| prof25_fec_en |
0 |
| prof25_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof25_fec_802p3ck |
0 |
| prof25_fgt_tx_pll_fout_hz |
|
| prof25_fgt_tx_pll_vco_MHz |
|
| prof25_fgt_tx_pll_cascade_enable |
0 |
| prof25_fgt_tx_pll_frac_mode_enable |
0 |
| prof25_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof25_fgt_rx_pll_fout_hz |
0 |
| prof25_fgt_rx_pll_vco_MHz |
|
| prof25_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof26_num_xcvr |
1 |
| prof26_fgt_protocol_mode |
DISABLED |
| prof26_pma_modulation |
PAM4 |
| prof26_pma_data_rate |
26562.5 |
| prof26_pma_width |
32 |
| prof26_pma_secondary_profile_refclk_en |
0 |
| prof26_fgt_tx_serdes_gray_coding_enable |
0 |
| prof26_fgt_tx_serdes_pre_coding_enable |
0 |
| prof26_fgt_tx_pll_txuserclk1_enable |
0 |
| prof26_fgt_tx_pll_txuserclk2_enable |
0 |
| prof26_fgt_tx_pll_txuserclk_div |
32 |
| prof26_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof26_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof26_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof26_bk_tx_precode_en |
0 |
| prof26_bk_tx_predivider_en |
0 |
| prof26_bk_tx_user_clk1_en |
0 |
| prof26_bk_tx_user_clk1_sel |
0 |
| prof26_bk_tx_user_clk2_en |
0 |
| prof26_bk_tx_user_clk2_sel |
0 |
| prof26_fgt_rx_serdes_gray_coding_enable |
0 |
| prof26_fgt_rx_serdes_pre_coding_enable |
0 |
| prof26_fgt_rx_sata_squelch_det_enable |
0 |
| prof26_fgt_rx_serdes_adapt_mode |
auto |
| prof26_fgt_rx_cdr_lock_mode |
auto |
| prof26_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof26_fgt_rx_cdr_rxuserclk_div |
32 |
| prof26_bk_alt_pam4_grey_code |
0 |
| prof26_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof26_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof26_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof26_bk_rx_precode_en |
0 |
| prof26_bk_rx_user_clk1_en |
0 |
| prof26_bk_rx_user_clk1_sel |
0 |
| prof26_bk_rx_user_clk2_en |
0 |
| prof26_bk_rx_user_clk2_sel |
0 |
| prof26_fec_en |
0 |
| prof26_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof26_fec_802p3ck |
0 |
| prof26_fgt_tx_pll_fout_hz |
|
| prof26_fgt_tx_pll_vco_MHz |
|
| prof26_fgt_tx_pll_cascade_enable |
0 |
| prof26_fgt_tx_pll_frac_mode_enable |
0 |
| prof26_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof26_fgt_rx_pll_fout_hz |
0 |
| prof26_fgt_rx_pll_vco_MHz |
|
| prof26_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof27_num_xcvr |
1 |
| prof27_fgt_protocol_mode |
DISABLED |
| prof27_pma_modulation |
PAM4 |
| prof27_pma_data_rate |
26562.5 |
| prof27_pma_width |
32 |
| prof27_pma_secondary_profile_refclk_en |
0 |
| prof27_fgt_tx_serdes_gray_coding_enable |
0 |
| prof27_fgt_tx_serdes_pre_coding_enable |
0 |
| prof27_fgt_tx_pll_txuserclk1_enable |
0 |
| prof27_fgt_tx_pll_txuserclk2_enable |
0 |
| prof27_fgt_tx_pll_txuserclk_div |
32 |
| prof27_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof27_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof27_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof27_bk_tx_precode_en |
0 |
| prof27_bk_tx_predivider_en |
0 |
| prof27_bk_tx_user_clk1_en |
0 |
| prof27_bk_tx_user_clk1_sel |
0 |
| prof27_bk_tx_user_clk2_en |
0 |
| prof27_bk_tx_user_clk2_sel |
0 |
| prof27_fgt_rx_serdes_gray_coding_enable |
0 |
| prof27_fgt_rx_serdes_pre_coding_enable |
0 |
| prof27_fgt_rx_sata_squelch_det_enable |
0 |
| prof27_fgt_rx_serdes_adapt_mode |
auto |
| prof27_fgt_rx_cdr_lock_mode |
auto |
| prof27_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof27_fgt_rx_cdr_rxuserclk_div |
32 |
| prof27_bk_alt_pam4_grey_code |
0 |
| prof27_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof27_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof27_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof27_bk_rx_precode_en |
0 |
| prof27_bk_rx_user_clk1_en |
0 |
| prof27_bk_rx_user_clk1_sel |
0 |
| prof27_bk_rx_user_clk2_en |
0 |
| prof27_bk_rx_user_clk2_sel |
0 |
| prof27_fec_en |
0 |
| prof27_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof27_fec_802p3ck |
0 |
| prof27_fgt_tx_pll_fout_hz |
|
| prof27_fgt_tx_pll_vco_MHz |
|
| prof27_fgt_tx_pll_cascade_enable |
0 |
| prof27_fgt_tx_pll_frac_mode_enable |
0 |
| prof27_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof27_fgt_rx_pll_fout_hz |
0 |
| prof27_fgt_rx_pll_vco_MHz |
|
| prof27_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof28_num_xcvr |
1 |
| prof28_fgt_protocol_mode |
DISABLED |
| prof28_pma_modulation |
PAM4 |
| prof28_pma_data_rate |
26562.5 |
| prof28_pma_width |
32 |
| prof28_pma_secondary_profile_refclk_en |
0 |
| prof28_fgt_tx_serdes_gray_coding_enable |
0 |
| prof28_fgt_tx_serdes_pre_coding_enable |
0 |
| prof28_fgt_tx_pll_txuserclk1_enable |
0 |
| prof28_fgt_tx_pll_txuserclk2_enable |
0 |
| prof28_fgt_tx_pll_txuserclk_div |
32 |
| prof28_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof28_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof28_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof28_bk_tx_precode_en |
0 |
| prof28_bk_tx_predivider_en |
0 |
| prof28_bk_tx_user_clk1_en |
0 |
| prof28_bk_tx_user_clk1_sel |
0 |
| prof28_bk_tx_user_clk2_en |
0 |
| prof28_bk_tx_user_clk2_sel |
0 |
| prof28_fgt_rx_serdes_gray_coding_enable |
0 |
| prof28_fgt_rx_serdes_pre_coding_enable |
0 |
| prof28_fgt_rx_sata_squelch_det_enable |
0 |
| prof28_fgt_rx_serdes_adapt_mode |
auto |
| prof28_fgt_rx_cdr_lock_mode |
auto |
| prof28_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof28_fgt_rx_cdr_rxuserclk_div |
32 |
| prof28_bk_alt_pam4_grey_code |
0 |
| prof28_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof28_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof28_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof28_bk_rx_precode_en |
0 |
| prof28_bk_rx_user_clk1_en |
0 |
| prof28_bk_rx_user_clk1_sel |
0 |
| prof28_bk_rx_user_clk2_en |
0 |
| prof28_bk_rx_user_clk2_sel |
0 |
| prof28_fec_en |
0 |
| prof28_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof28_fec_802p3ck |
0 |
| prof28_fgt_tx_pll_fout_hz |
|
| prof28_fgt_tx_pll_vco_MHz |
|
| prof28_fgt_tx_pll_cascade_enable |
0 |
| prof28_fgt_tx_pll_frac_mode_enable |
0 |
| prof28_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof28_fgt_rx_pll_fout_hz |
0 |
| prof28_fgt_rx_pll_vco_MHz |
|
| prof28_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof29_num_xcvr |
1 |
| prof29_fgt_protocol_mode |
DISABLED |
| prof29_pma_modulation |
PAM4 |
| prof29_pma_data_rate |
26562.5 |
| prof29_pma_width |
32 |
| prof29_pma_secondary_profile_refclk_en |
0 |
| prof29_fgt_tx_serdes_gray_coding_enable |
0 |
| prof29_fgt_tx_serdes_pre_coding_enable |
0 |
| prof29_fgt_tx_pll_txuserclk1_enable |
0 |
| prof29_fgt_tx_pll_txuserclk2_enable |
0 |
| prof29_fgt_tx_pll_txuserclk_div |
32 |
| prof29_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof29_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof29_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof29_bk_tx_precode_en |
0 |
| prof29_bk_tx_predivider_en |
0 |
| prof29_bk_tx_user_clk1_en |
0 |
| prof29_bk_tx_user_clk1_sel |
0 |
| prof29_bk_tx_user_clk2_en |
0 |
| prof29_bk_tx_user_clk2_sel |
0 |
| prof29_fgt_rx_serdes_gray_coding_enable |
0 |
| prof29_fgt_rx_serdes_pre_coding_enable |
0 |
| prof29_fgt_rx_sata_squelch_det_enable |
0 |
| prof29_fgt_rx_serdes_adapt_mode |
auto |
| prof29_fgt_rx_cdr_lock_mode |
auto |
| prof29_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof29_fgt_rx_cdr_rxuserclk_div |
32 |
| prof29_bk_alt_pam4_grey_code |
0 |
| prof29_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof29_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof29_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof29_bk_rx_precode_en |
0 |
| prof29_bk_rx_user_clk1_en |
0 |
| prof29_bk_rx_user_clk1_sel |
0 |
| prof29_bk_rx_user_clk2_en |
0 |
| prof29_bk_rx_user_clk2_sel |
0 |
| prof29_fec_en |
0 |
| prof29_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof29_fec_802p3ck |
0 |
| prof29_fgt_tx_pll_fout_hz |
|
| prof29_fgt_tx_pll_vco_MHz |
|
| prof29_fgt_tx_pll_cascade_enable |
0 |
| prof29_fgt_tx_pll_frac_mode_enable |
0 |
| prof29_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof29_fgt_rx_pll_fout_hz |
0 |
| prof29_fgt_rx_pll_vco_MHz |
|
| prof29_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof30_num_xcvr |
1 |
| prof30_fgt_protocol_mode |
DISABLED |
| prof30_pma_modulation |
PAM4 |
| prof30_pma_data_rate |
26562.5 |
| prof30_pma_width |
32 |
| prof30_pma_secondary_profile_refclk_en |
0 |
| prof30_fgt_tx_serdes_gray_coding_enable |
0 |
| prof30_fgt_tx_serdes_pre_coding_enable |
0 |
| prof30_fgt_tx_pll_txuserclk1_enable |
0 |
| prof30_fgt_tx_pll_txuserclk2_enable |
0 |
| prof30_fgt_tx_pll_txuserclk_div |
32 |
| prof30_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof30_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof30_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof30_bk_tx_precode_en |
0 |
| prof30_bk_tx_predivider_en |
0 |
| prof30_bk_tx_user_clk1_en |
0 |
| prof30_bk_tx_user_clk1_sel |
0 |
| prof30_bk_tx_user_clk2_en |
0 |
| prof30_bk_tx_user_clk2_sel |
0 |
| prof30_fgt_rx_serdes_gray_coding_enable |
0 |
| prof30_fgt_rx_serdes_pre_coding_enable |
0 |
| prof30_fgt_rx_sata_squelch_det_enable |
0 |
| prof30_fgt_rx_serdes_adapt_mode |
auto |
| prof30_fgt_rx_cdr_lock_mode |
auto |
| prof30_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof30_fgt_rx_cdr_rxuserclk_div |
32 |
| prof30_bk_alt_pam4_grey_code |
0 |
| prof30_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof30_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof30_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof30_bk_rx_precode_en |
0 |
| prof30_bk_rx_user_clk1_en |
0 |
| prof30_bk_rx_user_clk1_sel |
0 |
| prof30_bk_rx_user_clk2_en |
0 |
| prof30_bk_rx_user_clk2_sel |
0 |
| prof30_fec_en |
0 |
| prof30_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof30_fec_802p3ck |
0 |
| prof30_fgt_tx_pll_fout_hz |
|
| prof30_fgt_tx_pll_vco_MHz |
|
| prof30_fgt_tx_pll_cascade_enable |
0 |
| prof30_fgt_tx_pll_frac_mode_enable |
0 |
| prof30_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof30_fgt_rx_pll_fout_hz |
0 |
| prof30_fgt_rx_pll_vco_MHz |
|
| prof30_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof31_num_xcvr |
1 |
| prof31_fgt_protocol_mode |
DISABLED |
| prof31_pma_modulation |
PAM4 |
| prof31_pma_data_rate |
26562.5 |
| prof31_pma_width |
32 |
| prof31_pma_secondary_profile_refclk_en |
0 |
| prof31_fgt_tx_serdes_gray_coding_enable |
0 |
| prof31_fgt_tx_serdes_pre_coding_enable |
0 |
| prof31_fgt_tx_pll_txuserclk1_enable |
0 |
| prof31_fgt_tx_pll_txuserclk2_enable |
0 |
| prof31_fgt_tx_pll_txuserclk_div |
32 |
| prof31_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof31_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof31_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof31_bk_tx_precode_en |
0 |
| prof31_bk_tx_predivider_en |
0 |
| prof31_bk_tx_user_clk1_en |
0 |
| prof31_bk_tx_user_clk1_sel |
0 |
| prof31_bk_tx_user_clk2_en |
0 |
| prof31_bk_tx_user_clk2_sel |
0 |
| prof31_fgt_rx_serdes_gray_coding_enable |
0 |
| prof31_fgt_rx_serdes_pre_coding_enable |
0 |
| prof31_fgt_rx_sata_squelch_det_enable |
0 |
| prof31_fgt_rx_serdes_adapt_mode |
auto |
| prof31_fgt_rx_cdr_lock_mode |
auto |
| prof31_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof31_fgt_rx_cdr_rxuserclk_div |
32 |
| prof31_bk_alt_pam4_grey_code |
0 |
| prof31_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof31_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof31_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof31_bk_rx_precode_en |
0 |
| prof31_bk_rx_user_clk1_en |
0 |
| prof31_bk_rx_user_clk1_sel |
0 |
| prof31_bk_rx_user_clk2_en |
0 |
| prof31_bk_rx_user_clk2_sel |
0 |
| prof31_fec_en |
0 |
| prof31_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof31_fec_802p3ck |
0 |
| prof31_fgt_tx_pll_fout_hz |
|
| prof31_fgt_tx_pll_vco_MHz |
|
| prof31_fgt_tx_pll_cascade_enable |
0 |
| prof31_fgt_tx_pll_frac_mode_enable |
0 |
| prof31_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof31_fgt_rx_pll_fout_hz |
0 |
| prof31_fgt_rx_pll_vco_MHz |
|
| prof31_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| prof32_num_xcvr |
1 |
| prof32_fgt_protocol_mode |
DISABLED |
| prof32_pma_modulation |
PAM4 |
| prof32_pma_data_rate |
26562.5 |
| prof32_pma_width |
32 |
| prof32_pma_secondary_profile_refclk_en |
0 |
| prof32_fgt_tx_serdes_gray_coding_enable |
0 |
| prof32_fgt_tx_serdes_pre_coding_enable |
0 |
| prof32_fgt_tx_pll_txuserclk1_enable |
0 |
| prof32_fgt_tx_pll_txuserclk2_enable |
0 |
| prof32_fgt_tx_pll_txuserclk_div |
32 |
| prof32_bk_tx_invert_p_and_n |
TX_INVERT_PN_DIS |
| prof32_bk_refclk_source_lane_pll |
PLL_156_MHZ |
| prof32_bk_pll_pcs3334_ratio |
DIV_33_BY_2 |
| prof32_bk_tx_precode_en |
0 |
| prof32_bk_tx_predivider_en |
0 |
| prof32_bk_tx_user_clk1_en |
0 |
| prof32_bk_tx_user_clk1_sel |
0 |
| prof32_bk_tx_user_clk2_en |
0 |
| prof32_bk_tx_user_clk2_sel |
0 |
| prof32_fgt_rx_serdes_gray_coding_enable |
0 |
| prof32_fgt_rx_serdes_pre_coding_enable |
0 |
| prof32_fgt_rx_sata_squelch_det_enable |
0 |
| prof32_fgt_rx_serdes_adapt_mode |
auto |
| prof32_fgt_rx_cdr_lock_mode |
auto |
| prof32_fgt_rx_cdr_rxuserclk_enable |
0 |
| prof32_fgt_rx_cdr_rxuserclk_div |
32 |
| prof32_bk_alt_pam4_grey_code |
0 |
| prof32_bk_rx_invert_p_and_n |
RX_INVERT_PN_DIS |
| prof32_bk_en_rxdat_profile |
RXDAT_PROF_EN |
| prof32_bk_pll_rx_pcs3334_ratio |
RX_DIV_33_BY_2 |
| prof32_bk_rx_precode_en |
0 |
| prof32_bk_rx_user_clk1_en |
0 |
| prof32_bk_rx_user_clk1_sel |
0 |
| prof32_bk_rx_user_clk2_en |
0 |
| prof32_bk_rx_user_clk2_sel |
0 |
| prof32_fec_en |
0 |
| prof32_fec_mode |
IEEE 802.3 RS(528,514) (CL 91,KR) |
| prof32_fec_802p3ck |
0 |
| prof32_fgt_tx_pll_fout_hz |
|
| prof32_fgt_tx_pll_vco_MHz |
|
| prof32_fgt_tx_pll_cascade_enable |
0 |
| prof32_fgt_tx_pll_frac_mode_enable |
0 |
| prof32_fgt_tx_pll_refclk_freq_mhz |
156.250000 |
| prof32_fgt_rx_pll_fout_hz |
0 |
| prof32_fgt_rx_pll_vco_MHz |
|
| prof32_fgt_rx_pll_refclk_freq_mhz |
156.250000 |
| rcfg_subset_Prof0 |
25G-1 |
| pma_trgt_4profile_Prof0 |
ALL |
| profile_group_id_prof0 |
0 |
| Use_profile_startup_Prof0 |
1 |
| Prof1_Reference_Profile |
2 |
| rcfg_subset_Prof1 |
1x25G-1 |
| pma_trgt_4profile_Prof1 |
ALL |
| profile_group_id_prof1 |
1 |
| Use_profile_startup_Prof1 |
0 |
| Prof2_Reference_Profile |
1 |
| rcfg_subset_Prof2 |
1x25G-1 |
| pma_trgt_4profile_Prof2 |
ALL |
| profile_group_id_prof2 |
2 |
| Use_profile_startup_Prof2 |
0 |
| Prof3_Reference_Profile |
1 |
| rcfg_subset_Prof3 |
1x25G-1 |
| pma_trgt_4profile_Prof3 |
ALL |
| profile_group_id_prof3 |
3 |
| Use_profile_startup_Prof3 |
0 |
| rcfg_subset_Prof4 |
1x25G-1 |
| pma_trgt_4profile_Prof4 |
ALL |
| profile_group_id_prof4 |
4 |
| Use_profile_startup_Prof4 |
0 |
| rcfg_subset_Prof5 |
1x25G-1 |
| pma_trgt_4profile_Prof5 |
ALL |
| profile_group_id_prof5 |
5 |
| Use_profile_startup_Prof5 |
0 |
| rcfg_subset_Prof6 |
1x25G-1 |
| pma_trgt_4profile_Prof6 |
ALL |
| profile_group_id_prof6 |
6 |
| Use_profile_startup_Prof6 |
0 |
| rcfg_subset_Prof7 |
1x25G-1 |
| pma_trgt_4profile_Prof7 |
ALL |
| profile_group_id_prof7 |
7 |
| Use_profile_startup_Prof7 |
0 |
| rcfg_subset_Prof8 |
1x25G-1 |
| pma_trgt_4profile_Prof8 |
ALL |
| profile_group_id_prof8 |
8 |
| Use_profile_startup_Prof8 |
0 |
| rcfg_subset_Prof9 |
1x25G-1 |
| pma_trgt_4profile_Prof9 |
ALL |
| profile_group_id_prof9 |
9 |
| Use_profile_startup_Prof9 |
0 |
| rcfg_subset_Prof10 |
1x25G-1 |
| pma_trgt_4profile_Prof10 |
ALL |
| profile_group_id_prof10 |
10 |
| Use_profile_startup_Prof10 |
0 |
| rcfg_subset_Prof11 |
1x25G-1 |
| pma_trgt_4profile_Prof11 |
ALL |
| profile_group_id_prof11 |
11 |
| Use_profile_startup_Prof11 |
0 |
| rcfg_subset_Prof12 |
1x25G-1 |
| pma_trgt_4profile_Prof12 |
ALL |
| profile_group_id_prof12 |
12 |
| Use_profile_startup_Prof12 |
0 |
| rcfg_subset_Prof13 |
1x25G-1 |
| pma_trgt_4profile_Prof13 |
ALL |
| profile_group_id_prof13 |
13 |
| Use_profile_startup_Prof13 |
0 |
| rcfg_subset_Prof14 |
1x25G-1 |
| pma_trgt_4profile_Prof14 |
ALL |
| profile_group_id_prof14 |
14 |
| Use_profile_startup_Prof14 |
0 |
| rcfg_subset_Prof15 |
1x25G-1 |
| pma_trgt_4profile_Prof15 |
ALL |
| profile_group_id_prof15 |
15 |
| Use_profile_startup_Prof15 |
0 |
| rcfg_subset_Prof16 |
1x25G-1 |
| pma_trgt_4profile_Prof16 |
ALL |
| profile_group_id_prof16 |
16 |
| Use_profile_startup_Prof16 |
0 |
| rcfg_subset_Prof17 |
1x25G-1 |
| pma_trgt_4profile_Prof17 |
ALL |
| profile_group_id_prof17 |
17 |
| Use_profile_startup_Prof17 |
0 |
| rcfg_subset_Prof18 |
1x25G-1 |
| pma_trgt_4profile_Prof18 |
ALL |
| profile_group_id_prof18 |
18 |
| Use_profile_startup_Prof18 |
0 |
| rcfg_subset_Prof19 |
1x25G-1 |
| pma_trgt_4profile_Prof19 |
ALL |
| profile_group_id_prof19 |
19 |
| Use_profile_startup_Prof19 |
0 |
| rcfg_subset_Prof20 |
1x25G-1 |
| pma_trgt_4profile_Prof20 |
ALL |
| profile_group_id_prof20 |
20 |
| Use_profile_startup_Prof20 |
0 |
| rcfg_subset_Prof21 |
1x25G-1 |
| pma_trgt_4profile_Prof21 |
ALL |
| profile_group_id_prof21 |
21 |
| Use_profile_startup_Prof21 |
0 |
| rcfg_subset_Prof22 |
1x25G-1 |
| pma_trgt_4profile_Prof22 |
ALL |
| profile_group_id_prof22 |
22 |
| Use_profile_startup_Prof22 |
0 |
| rcfg_subset_Prof23 |
1x25G-1 |
| pma_trgt_4profile_Prof23 |
ALL |
| profile_group_id_prof23 |
23 |
| Use_profile_startup_Prof23 |
0 |
| rcfg_subset_Prof24 |
1x25G-1 |
| pma_trgt_4profile_Prof24 |
ALL |
| profile_group_id_prof24 |
24 |
| Use_profile_startup_Prof24 |
0 |
| rcfg_subset_Prof25 |
1x25G-1 |
| pma_trgt_4profile_Prof25 |
ALL |
| profile_group_id_prof25 |
25 |
| Use_profile_startup_Prof25 |
0 |
| rcfg_subset_Prof26 |
1x25G-1 |
| pma_trgt_4profile_Prof26 |
ALL |
| profile_group_id_prof26 |
26 |
| Use_profile_startup_Prof26 |
0 |
| rcfg_subset_Prof27 |
1x25G-1 |
| pma_trgt_4profile_Prof27 |
ALL |
| profile_group_id_prof27 |
27 |
| Use_profile_startup_Prof27 |
0 |
| rcfg_subset_Prof28 |
1x25G-1 |
| pma_trgt_4profile_Prof28 |
ALL |
| profile_group_id_prof28 |
28 |
| Use_profile_startup_Prof28 |
0 |
| rcfg_subset_Prof29 |
1x25G-1 |
| pma_trgt_4profile_Prof29 |
ALL |
| profile_group_id_prof29 |
29 |
| Use_profile_startup_Prof29 |
0 |
| rcfg_subset_Prof30 |
1x25G-1 |
| pma_trgt_4profile_Prof30 |
ALL |
| profile_group_id_prof30 |
30 |
| Use_profile_startup_Prof30 |
0 |
| rcfg_subset_Prof31 |
1x25G-1 |
| pma_trgt_4profile_Prof31 |
ALL |
| profile_group_id_prof31 |
31 |
| Use_profile_startup_Prof31 |
0 |
| rcfg_subset_Prof32 |
1x25G-1 |
| pma_trgt_4profile_Prof32 |
ALL |
| profile_group_id_prof32 |
32 |
| Use_profile_startup_Prof32 |
0 |
| enable_port_rx_clkout2 |
0 |
| enable_port_rx_fifo_full |
0 |
| enable_port_rx_fifo_empty |
0 |
| enable_port_rx_fifo_pfull |
0 |
| enable_port_rx_fifo_pempty |
0 |
| enable_port_rx_fifo_rd_en |
0 |
| prof0_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof0_pldif_rx_clkout_freq_mhz |
450.0 |
| prof0_enable_port_rx_clkout2 |
1 |
| prof0_pldif_rx_clkout2_sel |
RX_USER_CLK1 |
| prof0_pldif_rx_clkout2_div |
2 |
| prof0_pldif_rx_clkout2_freq_mhz |
148.5 |
| prof0_pldif_rx_double_width_transfer_enable |
1 |
| prof1_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof1_pldif_rx_clkout_freq_mhz |
450.0 |
| prof1_pldif_rx_clkout2_sel |
RX_USER_CLK1 |
| prof1_pldif_rx_clkout2_div |
2 |
| prof1_pldif_rx_clkout2_freq_mhz |
148.5 |
| prof1_pldif_rx_double_width_transfer_enable |
1 |
| prof2_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof2_pldif_rx_clkout_freq_mhz |
450.0 |
| prof2_pldif_rx_clkout2_sel |
RX_USER_CLK1 |
| prof2_pldif_rx_clkout2_div |
2 |
| prof2_pldif_rx_clkout2_freq_mhz |
148.5 |
| prof2_pldif_rx_double_width_transfer_enable |
1 |
| prof3_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof3_pldif_rx_clkout_freq_mhz |
450.0 |
| prof3_pldif_rx_clkout2_sel |
RX_USER_CLK1 |
| prof3_pldif_rx_clkout2_div |
2 |
| prof3_pldif_rx_clkout2_freq_mhz |
74.25 |
| prof3_pldif_rx_double_width_transfer_enable |
1 |
| prof4_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof4_pldif_rx_clkout_freq_mhz |
|
| prof4_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof4_pldif_rx_clkout2_div |
1 |
| prof4_pldif_rx_clkout2_freq_mhz |
|
| prof4_pldif_rx_double_width_transfer_enable |
1 |
| prof5_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof5_pldif_rx_clkout_freq_mhz |
|
| prof5_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof5_pldif_rx_clkout2_div |
1 |
| prof5_pldif_rx_clkout2_freq_mhz |
|
| prof5_pldif_rx_double_width_transfer_enable |
1 |
| prof6_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof6_pldif_rx_clkout_freq_mhz |
|
| prof6_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof6_pldif_rx_clkout2_div |
1 |
| prof6_pldif_rx_clkout2_freq_mhz |
|
| prof6_pldif_rx_double_width_transfer_enable |
1 |
| prof7_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof7_pldif_rx_clkout_freq_mhz |
|
| prof7_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof7_pldif_rx_clkout2_div |
1 |
| prof7_pldif_rx_clkout2_freq_mhz |
|
| prof7_pldif_rx_double_width_transfer_enable |
1 |
| prof8_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof8_pldif_rx_clkout_freq_mhz |
|
| prof8_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof8_pldif_rx_clkout2_div |
1 |
| prof8_pldif_rx_clkout2_freq_mhz |
|
| prof8_pldif_rx_double_width_transfer_enable |
1 |
| prof9_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof9_pldif_rx_clkout_freq_mhz |
|
| prof9_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof9_pldif_rx_clkout2_div |
1 |
| prof9_pldif_rx_clkout2_freq_mhz |
|
| prof9_pldif_rx_double_width_transfer_enable |
1 |
| prof10_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof10_pldif_rx_clkout_freq_mhz |
|
| prof10_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof10_pldif_rx_clkout2_div |
1 |
| prof10_pldif_rx_clkout2_freq_mhz |
|
| prof10_pldif_rx_double_width_transfer_enable |
1 |
| prof11_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof11_pldif_rx_clkout_freq_mhz |
|
| prof11_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof11_pldif_rx_clkout2_div |
1 |
| prof11_pldif_rx_clkout2_freq_mhz |
|
| prof11_pldif_rx_double_width_transfer_enable |
1 |
| prof12_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof12_pldif_rx_clkout_freq_mhz |
|
| prof12_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof12_pldif_rx_clkout2_div |
1 |
| prof12_pldif_rx_clkout2_freq_mhz |
|
| prof12_pldif_rx_double_width_transfer_enable |
1 |
| prof13_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof13_pldif_rx_clkout_freq_mhz |
|
| prof13_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof13_pldif_rx_clkout2_div |
1 |
| prof13_pldif_rx_clkout2_freq_mhz |
|
| prof13_pldif_rx_double_width_transfer_enable |
1 |
| prof14_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof14_pldif_rx_clkout_freq_mhz |
|
| prof14_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof14_pldif_rx_clkout2_div |
1 |
| prof14_pldif_rx_clkout2_freq_mhz |
|
| prof14_pldif_rx_double_width_transfer_enable |
1 |
| prof15_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof15_pldif_rx_clkout_freq_mhz |
|
| prof15_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof15_pldif_rx_clkout2_div |
1 |
| prof15_pldif_rx_clkout2_freq_mhz |
|
| prof15_pldif_rx_double_width_transfer_enable |
1 |
| prof16_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof16_pldif_rx_clkout_freq_mhz |
|
| prof16_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof16_pldif_rx_clkout2_div |
1 |
| prof16_pldif_rx_clkout2_freq_mhz |
|
| prof16_pldif_rx_double_width_transfer_enable |
1 |
| prof17_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof17_pldif_rx_clkout_freq_mhz |
|
| prof17_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof17_pldif_rx_clkout2_div |
1 |
| prof17_pldif_rx_clkout2_freq_mhz |
|
| prof17_pldif_rx_double_width_transfer_enable |
1 |
| prof18_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof18_pldif_rx_clkout_freq_mhz |
|
| prof18_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof18_pldif_rx_clkout2_div |
1 |
| prof18_pldif_rx_clkout2_freq_mhz |
|
| prof18_pldif_rx_double_width_transfer_enable |
1 |
| prof19_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof19_pldif_rx_clkout_freq_mhz |
|
| prof19_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof19_pldif_rx_clkout2_div |
1 |
| prof19_pldif_rx_clkout2_freq_mhz |
|
| prof19_pldif_rx_double_width_transfer_enable |
1 |
| prof20_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof20_pldif_rx_clkout_freq_mhz |
|
| prof20_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof20_pldif_rx_clkout2_div |
1 |
| prof20_pldif_rx_clkout2_freq_mhz |
|
| prof20_pldif_rx_double_width_transfer_enable |
1 |
| prof21_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof21_pldif_rx_clkout_freq_mhz |
|
| prof21_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof21_pldif_rx_clkout2_div |
1 |
| prof21_pldif_rx_clkout2_freq_mhz |
|
| prof21_pldif_rx_double_width_transfer_enable |
1 |
| prof22_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof22_pldif_rx_clkout_freq_mhz |
|
| prof22_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof22_pldif_rx_clkout2_div |
1 |
| prof22_pldif_rx_clkout2_freq_mhz |
|
| prof22_pldif_rx_double_width_transfer_enable |
1 |
| prof23_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof23_pldif_rx_clkout_freq_mhz |
|
| prof23_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof23_pldif_rx_clkout2_div |
1 |
| prof23_pldif_rx_clkout2_freq_mhz |
|
| prof23_pldif_rx_double_width_transfer_enable |
1 |
| prof24_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof24_pldif_rx_clkout_freq_mhz |
|
| prof24_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof24_pldif_rx_clkout2_div |
1 |
| prof24_pldif_rx_clkout2_freq_mhz |
|
| prof24_pldif_rx_double_width_transfer_enable |
1 |
| prof25_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof25_pldif_rx_clkout_freq_mhz |
|
| prof25_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof25_pldif_rx_clkout2_div |
1 |
| prof25_pldif_rx_clkout2_freq_mhz |
|
| prof25_pldif_rx_double_width_transfer_enable |
1 |
| prof26_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof26_pldif_rx_clkout_freq_mhz |
|
| prof26_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof26_pldif_rx_clkout2_div |
1 |
| prof26_pldif_rx_clkout2_freq_mhz |
|
| prof26_pldif_rx_double_width_transfer_enable |
1 |
| prof27_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof27_pldif_rx_clkout_freq_mhz |
|
| prof27_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof27_pldif_rx_clkout2_div |
1 |
| prof27_pldif_rx_clkout2_freq_mhz |
|
| prof27_pldif_rx_double_width_transfer_enable |
1 |
| prof28_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof28_pldif_rx_clkout_freq_mhz |
|
| prof28_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof28_pldif_rx_clkout2_div |
1 |
| prof28_pldif_rx_clkout2_freq_mhz |
|
| prof28_pldif_rx_double_width_transfer_enable |
1 |
| prof29_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof29_pldif_rx_clkout_freq_mhz |
|
| prof29_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof29_pldif_rx_clkout2_div |
1 |
| prof29_pldif_rx_clkout2_freq_mhz |
|
| prof29_pldif_rx_double_width_transfer_enable |
1 |
| prof30_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof30_pldif_rx_clkout_freq_mhz |
|
| prof30_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof30_pldif_rx_clkout2_div |
1 |
| prof30_pldif_rx_clkout2_freq_mhz |
|
| prof30_pldif_rx_double_width_transfer_enable |
1 |
| prof31_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof31_pldif_rx_clkout_freq_mhz |
|
| prof31_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof31_pldif_rx_clkout2_div |
1 |
| prof31_pldif_rx_clkout2_freq_mhz |
|
| prof31_pldif_rx_double_width_transfer_enable |
1 |
| prof32_pldif_rx_clkout_sel |
PLL_DIV2 |
| prof32_pldif_rx_clkout_freq_mhz |
|
| prof32_pldif_rx_clkout2_sel |
RX_WORD_CLK |
| prof32_pldif_rx_clkout2_div |
1 |
| prof32_pldif_rx_clkout2_freq_mhz |
|
| prof32_pldif_rx_double_width_transfer_enable |
1 |
| bk_rx_invert_p_and_n_Prof0 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof0 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof0 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof0 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof0 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof0 |
0.0 |
| bk_txeq_post_tap_3_Prof0 |
0.0 |
| bk_txeq_post_tap_2_Prof0 |
0.0 |
| bk_txeq_post_tap_1_Prof0 |
0.0 |
| bk_txeq_main_tap_Prof0 |
41.5 |
| bk_txeq_pre_tap_1_Prof0 |
0.0 |
| bk_txeq_pre_tap_2_Prof0 |
0.0 |
| bk_txeq_pre_tap_3_Prof0 |
0.0 |
| bk_ext_ac_cap_Prof0 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof0 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof0 |
ENABLE |
| ux_txeq_post_tap_1_Prof0 |
0 |
| ux_txeq_main_tap_Prof0 |
35 |
| ux_txeq_pre_tap_1_Prof0 |
5 |
| ux_txeq_pre_tap_2_Prof0 |
0 |
| vsr_mode_Prof0 |
VSR_MODE_DISABLE |
| bk_rx_invert_p_and_n_Prof1 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof1 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof1 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof1 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof1 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof1 |
0.0 |
| bk_txeq_post_tap_3_Prof1 |
0.0 |
| bk_txeq_post_tap_2_Prof1 |
0.0 |
| bk_txeq_post_tap_1_Prof1 |
0.0 |
| bk_txeq_main_tap_Prof1 |
41.5 |
| bk_txeq_pre_tap_1_Prof1 |
0.0 |
| bk_txeq_pre_tap_2_Prof1 |
0.0 |
| bk_txeq_pre_tap_3_Prof1 |
0.0 |
| bk_ext_ac_cap_Prof1 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof1 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof1 |
ENABLE |
| ux_txeq_post_tap_1_Prof1 |
0 |
| ux_txeq_main_tap_Prof1 |
35 |
| ux_txeq_pre_tap_1_Prof1 |
5 |
| ux_txeq_pre_tap_2_Prof1 |
0 |
| vsr_mode_Prof1 |
VSR_MODE_DISABLE |
| bk_rx_invert_p_and_n_Prof2 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof2 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof2 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof2 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof2 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof2 |
0.0 |
| bk_txeq_post_tap_3_Prof2 |
0.0 |
| bk_txeq_post_tap_2_Prof2 |
0.0 |
| bk_txeq_post_tap_1_Prof2 |
0.0 |
| bk_txeq_main_tap_Prof2 |
41.5 |
| bk_txeq_pre_tap_1_Prof2 |
0.0 |
| bk_txeq_pre_tap_2_Prof2 |
0.0 |
| bk_txeq_pre_tap_3_Prof2 |
0.0 |
| bk_ext_ac_cap_Prof2 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof2 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof2 |
ENABLE |
| ux_txeq_post_tap_1_Prof2 |
0 |
| ux_txeq_main_tap_Prof2 |
35 |
| ux_txeq_pre_tap_1_Prof2 |
5 |
| ux_txeq_pre_tap_2_Prof2 |
0 |
| vsr_mode_Prof2 |
VSR_MODE_DISABLE |
| bk_rx_invert_p_and_n_Prof3 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof3 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof3 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof3 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof3 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof3 |
0.0 |
| bk_txeq_post_tap_3_Prof3 |
0.0 |
| bk_txeq_post_tap_2_Prof3 |
0.0 |
| bk_txeq_post_tap_1_Prof3 |
0.0 |
| bk_txeq_main_tap_Prof3 |
41.5 |
| bk_txeq_pre_tap_1_Prof3 |
0.0 |
| bk_txeq_pre_tap_2_Prof3 |
0.0 |
| bk_txeq_pre_tap_3_Prof3 |
0.0 |
| bk_ext_ac_cap_Prof3 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof3 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof3 |
ENABLE |
| ux_txeq_post_tap_1_Prof3 |
0 |
| ux_txeq_main_tap_Prof3 |
35 |
| ux_txeq_pre_tap_1_Prof3 |
5 |
| ux_txeq_pre_tap_2_Prof3 |
0 |
| vsr_mode_Prof3 |
VSR_MODE_DISABLE |
| bk_rx_invert_p_and_n_Prof4 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof4 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof4 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof4 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof4 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof4 |
0.0 |
| bk_txeq_post_tap_3_Prof4 |
0.0 |
| bk_txeq_post_tap_2_Prof4 |
0.0 |
| bk_txeq_post_tap_1_Prof4 |
0.0 |
| bk_txeq_main_tap_Prof4 |
41.5 |
| bk_txeq_pre_tap_1_Prof4 |
0.0 |
| bk_txeq_pre_tap_2_Prof4 |
0.0 |
| bk_txeq_pre_tap_3_Prof4 |
0.0 |
| bk_ext_ac_cap_Prof4 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof4 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof4 |
ENABLE |
| ux_txeq_post_tap_1_Prof4 |
0 |
| ux_txeq_main_tap_Prof4 |
35 |
| ux_txeq_pre_tap_1_Prof4 |
5 |
| ux_txeq_pre_tap_2_Prof4 |
0 |
| vsr_mode_Prof4 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof4 |
0 |
| rxeq_hf_boost_Prof4 |
0 |
| rxeq_dfe_data_tap_1_Prof4 |
0 |
| bk_rx_invert_p_and_n_Prof5 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof5 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof5 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof5 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof5 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof5 |
0.0 |
| bk_txeq_post_tap_3_Prof5 |
0.0 |
| bk_txeq_post_tap_2_Prof5 |
0.0 |
| bk_txeq_post_tap_1_Prof5 |
0.0 |
| bk_txeq_main_tap_Prof5 |
41.5 |
| bk_txeq_pre_tap_1_Prof5 |
0.0 |
| bk_txeq_pre_tap_2_Prof5 |
0.0 |
| bk_txeq_pre_tap_3_Prof5 |
0.0 |
| bk_ext_ac_cap_Prof5 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof5 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof5 |
ENABLE |
| ux_txeq_post_tap_1_Prof5 |
0 |
| ux_txeq_main_tap_Prof5 |
35 |
| ux_txeq_pre_tap_1_Prof5 |
5 |
| ux_txeq_pre_tap_2_Prof5 |
0 |
| vsr_mode_Prof5 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof5 |
0 |
| rxeq_hf_boost_Prof5 |
0 |
| rxeq_dfe_data_tap_1_Prof5 |
0 |
| bk_rx_invert_p_and_n_Prof6 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof6 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof6 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof6 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof6 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof6 |
0.0 |
| bk_txeq_post_tap_3_Prof6 |
0.0 |
| bk_txeq_post_tap_2_Prof6 |
0.0 |
| bk_txeq_post_tap_1_Prof6 |
0.0 |
| bk_txeq_main_tap_Prof6 |
41.5 |
| bk_txeq_pre_tap_1_Prof6 |
0.0 |
| bk_txeq_pre_tap_2_Prof6 |
0.0 |
| bk_txeq_pre_tap_3_Prof6 |
0.0 |
| bk_ext_ac_cap_Prof6 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof6 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof6 |
ENABLE |
| ux_txeq_post_tap_1_Prof6 |
0 |
| ux_txeq_main_tap_Prof6 |
35 |
| ux_txeq_pre_tap_1_Prof6 |
5 |
| ux_txeq_pre_tap_2_Prof6 |
0 |
| vsr_mode_Prof6 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof6 |
0 |
| rxeq_hf_boost_Prof6 |
0 |
| rxeq_dfe_data_tap_1_Prof6 |
0 |
| bk_rx_invert_p_and_n_Prof7 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof7 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof7 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof7 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof7 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof7 |
0.0 |
| bk_txeq_post_tap_3_Prof7 |
0.0 |
| bk_txeq_post_tap_2_Prof7 |
0.0 |
| bk_txeq_post_tap_1_Prof7 |
0.0 |
| bk_txeq_main_tap_Prof7 |
41.5 |
| bk_txeq_pre_tap_1_Prof7 |
0.0 |
| bk_txeq_pre_tap_2_Prof7 |
0.0 |
| bk_txeq_pre_tap_3_Prof7 |
0.0 |
| bk_ext_ac_cap_Prof7 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof7 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof7 |
ENABLE |
| ux_txeq_post_tap_1_Prof7 |
0 |
| ux_txeq_main_tap_Prof7 |
35 |
| ux_txeq_pre_tap_1_Prof7 |
5 |
| ux_txeq_pre_tap_2_Prof7 |
0 |
| vsr_mode_Prof7 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof7 |
0 |
| rxeq_hf_boost_Prof7 |
0 |
| rxeq_dfe_data_tap_1_Prof7 |
0 |
| bk_rx_invert_p_and_n_Prof8 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof8 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof8 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof8 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof8 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof8 |
0.0 |
| bk_txeq_post_tap_3_Prof8 |
0.0 |
| bk_txeq_post_tap_2_Prof8 |
0.0 |
| bk_txeq_post_tap_1_Prof8 |
0.0 |
| bk_txeq_main_tap_Prof8 |
41.5 |
| bk_txeq_pre_tap_1_Prof8 |
0.0 |
| bk_txeq_pre_tap_2_Prof8 |
0.0 |
| bk_txeq_pre_tap_3_Prof8 |
0.0 |
| bk_ext_ac_cap_Prof8 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof8 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof8 |
ENABLE |
| ux_txeq_post_tap_1_Prof8 |
0 |
| ux_txeq_main_tap_Prof8 |
35 |
| ux_txeq_pre_tap_1_Prof8 |
5 |
| ux_txeq_pre_tap_2_Prof8 |
0 |
| vsr_mode_Prof8 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof8 |
0 |
| rxeq_hf_boost_Prof8 |
0 |
| rxeq_dfe_data_tap_1_Prof8 |
0 |
| bk_rx_invert_p_and_n_Prof9 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof9 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof9 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof9 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof9 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof9 |
0.0 |
| bk_txeq_post_tap_3_Prof9 |
0.0 |
| bk_txeq_post_tap_2_Prof9 |
0.0 |
| bk_txeq_post_tap_1_Prof9 |
0.0 |
| bk_txeq_main_tap_Prof9 |
41.5 |
| bk_txeq_pre_tap_1_Prof9 |
0.0 |
| bk_txeq_pre_tap_2_Prof9 |
0.0 |
| bk_txeq_pre_tap_3_Prof9 |
0.0 |
| bk_ext_ac_cap_Prof9 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof9 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof9 |
ENABLE |
| ux_txeq_post_tap_1_Prof9 |
0 |
| ux_txeq_main_tap_Prof9 |
35 |
| ux_txeq_pre_tap_1_Prof9 |
5 |
| ux_txeq_pre_tap_2_Prof9 |
0 |
| vsr_mode_Prof9 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof9 |
0 |
| rxeq_hf_boost_Prof9 |
0 |
| rxeq_dfe_data_tap_1_Prof9 |
0 |
| bk_rx_invert_p_and_n_Prof10 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof10 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof10 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof10 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof10 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof10 |
0.0 |
| bk_txeq_post_tap_3_Prof10 |
0.0 |
| bk_txeq_post_tap_2_Prof10 |
0.0 |
| bk_txeq_post_tap_1_Prof10 |
0.0 |
| bk_txeq_main_tap_Prof10 |
41.5 |
| bk_txeq_pre_tap_1_Prof10 |
0.0 |
| bk_txeq_pre_tap_2_Prof10 |
0.0 |
| bk_txeq_pre_tap_3_Prof10 |
0.0 |
| bk_ext_ac_cap_Prof10 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof10 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof10 |
ENABLE |
| ux_txeq_post_tap_1_Prof10 |
0 |
| ux_txeq_main_tap_Prof10 |
35 |
| ux_txeq_pre_tap_1_Prof10 |
5 |
| ux_txeq_pre_tap_2_Prof10 |
0 |
| vsr_mode_Prof10 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof10 |
0 |
| rxeq_hf_boost_Prof10 |
0 |
| rxeq_dfe_data_tap_1_Prof10 |
0 |
| bk_rx_invert_p_and_n_Prof11 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof11 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof11 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof11 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof11 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof11 |
0.0 |
| bk_txeq_post_tap_3_Prof11 |
0.0 |
| bk_txeq_post_tap_2_Prof11 |
0.0 |
| bk_txeq_post_tap_1_Prof11 |
0.0 |
| bk_txeq_main_tap_Prof11 |
41.5 |
| bk_txeq_pre_tap_1_Prof11 |
0.0 |
| bk_txeq_pre_tap_2_Prof11 |
0.0 |
| bk_txeq_pre_tap_3_Prof11 |
0.0 |
| bk_ext_ac_cap_Prof11 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof11 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof11 |
ENABLE |
| ux_txeq_post_tap_1_Prof11 |
0 |
| ux_txeq_main_tap_Prof11 |
35 |
| ux_txeq_pre_tap_1_Prof11 |
5 |
| ux_txeq_pre_tap_2_Prof11 |
0 |
| vsr_mode_Prof11 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof11 |
0 |
| rxeq_hf_boost_Prof11 |
0 |
| rxeq_dfe_data_tap_1_Prof11 |
0 |
| bk_rx_invert_p_and_n_Prof12 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof12 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof12 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof12 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof12 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof12 |
0.0 |
| bk_txeq_post_tap_3_Prof12 |
0.0 |
| bk_txeq_post_tap_2_Prof12 |
0.0 |
| bk_txeq_post_tap_1_Prof12 |
0.0 |
| bk_txeq_main_tap_Prof12 |
41.5 |
| bk_txeq_pre_tap_1_Prof12 |
0.0 |
| bk_txeq_pre_tap_2_Prof12 |
0.0 |
| bk_txeq_pre_tap_3_Prof12 |
0.0 |
| bk_ext_ac_cap_Prof12 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof12 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof12 |
ENABLE |
| ux_txeq_post_tap_1_Prof12 |
0 |
| ux_txeq_main_tap_Prof12 |
35 |
| ux_txeq_pre_tap_1_Prof12 |
5 |
| ux_txeq_pre_tap_2_Prof12 |
0 |
| vsr_mode_Prof12 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof12 |
0 |
| rxeq_hf_boost_Prof12 |
0 |
| rxeq_dfe_data_tap_1_Prof12 |
0 |
| bk_rx_invert_p_and_n_Prof13 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof13 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof13 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof13 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof13 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof13 |
0.0 |
| bk_txeq_post_tap_3_Prof13 |
0.0 |
| bk_txeq_post_tap_2_Prof13 |
0.0 |
| bk_txeq_post_tap_1_Prof13 |
0.0 |
| bk_txeq_main_tap_Prof13 |
41.5 |
| bk_txeq_pre_tap_1_Prof13 |
0.0 |
| bk_txeq_pre_tap_2_Prof13 |
0.0 |
| bk_txeq_pre_tap_3_Prof13 |
0.0 |
| bk_ext_ac_cap_Prof13 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof13 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof13 |
ENABLE |
| ux_txeq_post_tap_1_Prof13 |
0 |
| ux_txeq_main_tap_Prof13 |
35 |
| ux_txeq_pre_tap_1_Prof13 |
5 |
| ux_txeq_pre_tap_2_Prof13 |
0 |
| vsr_mode_Prof13 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof13 |
0 |
| rxeq_hf_boost_Prof13 |
0 |
| rxeq_dfe_data_tap_1_Prof13 |
0 |
| bk_rx_invert_p_and_n_Prof14 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof14 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof14 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof14 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof14 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof14 |
0.0 |
| bk_txeq_post_tap_3_Prof14 |
0.0 |
| bk_txeq_post_tap_2_Prof14 |
0.0 |
| bk_txeq_post_tap_1_Prof14 |
0.0 |
| bk_txeq_main_tap_Prof14 |
41.5 |
| bk_txeq_pre_tap_1_Prof14 |
0.0 |
| bk_txeq_pre_tap_2_Prof14 |
0.0 |
| bk_txeq_pre_tap_3_Prof14 |
0.0 |
| bk_ext_ac_cap_Prof14 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof14 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof14 |
ENABLE |
| ux_txeq_post_tap_1_Prof14 |
0 |
| ux_txeq_main_tap_Prof14 |
35 |
| ux_txeq_pre_tap_1_Prof14 |
5 |
| ux_txeq_pre_tap_2_Prof14 |
0 |
| vsr_mode_Prof14 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof14 |
0 |
| rxeq_hf_boost_Prof14 |
0 |
| rxeq_dfe_data_tap_1_Prof14 |
0 |
| bk_rx_invert_p_and_n_Prof15 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof15 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof15 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof15 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof15 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof15 |
0.0 |
| bk_txeq_post_tap_3_Prof15 |
0.0 |
| bk_txeq_post_tap_2_Prof15 |
0.0 |
| bk_txeq_post_tap_1_Prof15 |
0.0 |
| bk_txeq_main_tap_Prof15 |
41.5 |
| bk_txeq_pre_tap_1_Prof15 |
0.0 |
| bk_txeq_pre_tap_2_Prof15 |
0.0 |
| bk_txeq_pre_tap_3_Prof15 |
0.0 |
| bk_ext_ac_cap_Prof15 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof15 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof15 |
ENABLE |
| ux_txeq_post_tap_1_Prof15 |
0 |
| ux_txeq_main_tap_Prof15 |
35 |
| ux_txeq_pre_tap_1_Prof15 |
5 |
| ux_txeq_pre_tap_2_Prof15 |
0 |
| vsr_mode_Prof15 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof15 |
0 |
| rxeq_hf_boost_Prof15 |
0 |
| rxeq_dfe_data_tap_1_Prof15 |
0 |
| bk_rx_invert_p_and_n_Prof16 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof16 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof16 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof16 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof16 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof16 |
0.0 |
| bk_txeq_post_tap_3_Prof16 |
0.0 |
| bk_txeq_post_tap_2_Prof16 |
0.0 |
| bk_txeq_post_tap_1_Prof16 |
0.0 |
| bk_txeq_main_tap_Prof16 |
41.5 |
| bk_txeq_pre_tap_1_Prof16 |
0.0 |
| bk_txeq_pre_tap_2_Prof16 |
0.0 |
| bk_txeq_pre_tap_3_Prof16 |
0.0 |
| bk_ext_ac_cap_Prof16 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof16 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof16 |
ENABLE |
| ux_txeq_post_tap_1_Prof16 |
0 |
| ux_txeq_main_tap_Prof16 |
35 |
| ux_txeq_pre_tap_1_Prof16 |
5 |
| ux_txeq_pre_tap_2_Prof16 |
0 |
| vsr_mode_Prof16 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof16 |
0 |
| rxeq_hf_boost_Prof16 |
0 |
| rxeq_dfe_data_tap_1_Prof16 |
0 |
| bk_rx_invert_p_and_n_Prof17 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof17 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof17 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof17 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof17 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof17 |
0.0 |
| bk_txeq_post_tap_3_Prof17 |
0.0 |
| bk_txeq_post_tap_2_Prof17 |
0.0 |
| bk_txeq_post_tap_1_Prof17 |
0.0 |
| bk_txeq_main_tap_Prof17 |
41.5 |
| bk_txeq_pre_tap_1_Prof17 |
0.0 |
| bk_txeq_pre_tap_2_Prof17 |
0.0 |
| bk_txeq_pre_tap_3_Prof17 |
0.0 |
| bk_ext_ac_cap_Prof17 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof17 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof17 |
ENABLE |
| ux_txeq_post_tap_1_Prof17 |
0 |
| ux_txeq_main_tap_Prof17 |
35 |
| ux_txeq_pre_tap_1_Prof17 |
5 |
| ux_txeq_pre_tap_2_Prof17 |
0 |
| vsr_mode_Prof17 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof17 |
0 |
| rxeq_hf_boost_Prof17 |
0 |
| rxeq_dfe_data_tap_1_Prof17 |
0 |
| bk_rx_invert_p_and_n_Prof18 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof18 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof18 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof18 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof18 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof18 |
0.0 |
| bk_txeq_post_tap_3_Prof18 |
0.0 |
| bk_txeq_post_tap_2_Prof18 |
0.0 |
| bk_txeq_post_tap_1_Prof18 |
0.0 |
| bk_txeq_main_tap_Prof18 |
41.5 |
| bk_txeq_pre_tap_1_Prof18 |
0.0 |
| bk_txeq_pre_tap_2_Prof18 |
0.0 |
| bk_txeq_pre_tap_3_Prof18 |
0.0 |
| bk_ext_ac_cap_Prof18 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof18 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof18 |
ENABLE |
| ux_txeq_post_tap_1_Prof18 |
0 |
| ux_txeq_main_tap_Prof18 |
35 |
| ux_txeq_pre_tap_1_Prof18 |
5 |
| ux_txeq_pre_tap_2_Prof18 |
0 |
| vsr_mode_Prof18 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof18 |
0 |
| rxeq_hf_boost_Prof18 |
0 |
| rxeq_dfe_data_tap_1_Prof18 |
0 |
| bk_rx_invert_p_and_n_Prof19 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof19 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof19 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof19 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof19 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof19 |
0.0 |
| bk_txeq_post_tap_3_Prof19 |
0.0 |
| bk_txeq_post_tap_2_Prof19 |
0.0 |
| bk_txeq_post_tap_1_Prof19 |
0.0 |
| bk_txeq_main_tap_Prof19 |
41.5 |
| bk_txeq_pre_tap_1_Prof19 |
0.0 |
| bk_txeq_pre_tap_2_Prof19 |
0.0 |
| bk_txeq_pre_tap_3_Prof19 |
0.0 |
| bk_ext_ac_cap_Prof19 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof19 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof19 |
ENABLE |
| ux_txeq_post_tap_1_Prof19 |
0 |
| ux_txeq_main_tap_Prof19 |
35 |
| ux_txeq_pre_tap_1_Prof19 |
5 |
| ux_txeq_pre_tap_2_Prof19 |
0 |
| vsr_mode_Prof19 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof19 |
0 |
| rxeq_hf_boost_Prof19 |
0 |
| rxeq_dfe_data_tap_1_Prof19 |
0 |
| bk_rx_invert_p_and_n_Prof20 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof20 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof20 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof20 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof20 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof20 |
0.0 |
| bk_txeq_post_tap_3_Prof20 |
0.0 |
| bk_txeq_post_tap_2_Prof20 |
0.0 |
| bk_txeq_post_tap_1_Prof20 |
0.0 |
| bk_txeq_main_tap_Prof20 |
41.5 |
| bk_txeq_pre_tap_1_Prof20 |
0.0 |
| bk_txeq_pre_tap_2_Prof20 |
0.0 |
| bk_txeq_pre_tap_3_Prof20 |
0.0 |
| bk_ext_ac_cap_Prof20 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof20 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof20 |
ENABLE |
| ux_txeq_post_tap_1_Prof20 |
0 |
| ux_txeq_main_tap_Prof20 |
35 |
| ux_txeq_pre_tap_1_Prof20 |
5 |
| ux_txeq_pre_tap_2_Prof20 |
0 |
| vsr_mode_Prof20 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof20 |
0 |
| rxeq_hf_boost_Prof20 |
0 |
| rxeq_dfe_data_tap_1_Prof20 |
0 |
| bk_rx_invert_p_and_n_Prof21 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof21 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof21 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof21 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof21 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof21 |
0.0 |
| bk_txeq_post_tap_3_Prof21 |
0.0 |
| bk_txeq_post_tap_2_Prof21 |
0.0 |
| bk_txeq_post_tap_1_Prof21 |
0.0 |
| bk_txeq_main_tap_Prof21 |
41.5 |
| bk_txeq_pre_tap_1_Prof21 |
0.0 |
| bk_txeq_pre_tap_2_Prof21 |
0.0 |
| bk_txeq_pre_tap_3_Prof21 |
0.0 |
| bk_ext_ac_cap_Prof21 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof21 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof21 |
ENABLE |
| ux_txeq_post_tap_1_Prof21 |
0 |
| ux_txeq_main_tap_Prof21 |
35 |
| ux_txeq_pre_tap_1_Prof21 |
5 |
| ux_txeq_pre_tap_2_Prof21 |
0 |
| vsr_mode_Prof21 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof21 |
0 |
| rxeq_hf_boost_Prof21 |
0 |
| rxeq_dfe_data_tap_1_Prof21 |
0 |
| bk_rx_invert_p_and_n_Prof22 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof22 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof22 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof22 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof22 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof22 |
0.0 |
| bk_txeq_post_tap_3_Prof22 |
0.0 |
| bk_txeq_post_tap_2_Prof22 |
0.0 |
| bk_txeq_post_tap_1_Prof22 |
0.0 |
| bk_txeq_main_tap_Prof22 |
41.5 |
| bk_txeq_pre_tap_1_Prof22 |
0.0 |
| bk_txeq_pre_tap_2_Prof22 |
0.0 |
| bk_txeq_pre_tap_3_Prof22 |
0.0 |
| bk_ext_ac_cap_Prof22 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof22 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof22 |
ENABLE |
| ux_txeq_post_tap_1_Prof22 |
0 |
| ux_txeq_main_tap_Prof22 |
35 |
| ux_txeq_pre_tap_1_Prof22 |
5 |
| ux_txeq_pre_tap_2_Prof22 |
0 |
| vsr_mode_Prof22 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof22 |
0 |
| rxeq_hf_boost_Prof22 |
0 |
| rxeq_dfe_data_tap_1_Prof22 |
0 |
| bk_rx_invert_p_and_n_Prof23 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof23 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof23 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof23 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof23 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof23 |
0.0 |
| bk_txeq_post_tap_3_Prof23 |
0.0 |
| bk_txeq_post_tap_2_Prof23 |
0.0 |
| bk_txeq_post_tap_1_Prof23 |
0.0 |
| bk_txeq_main_tap_Prof23 |
41.5 |
| bk_txeq_pre_tap_1_Prof23 |
0.0 |
| bk_txeq_pre_tap_2_Prof23 |
0.0 |
| bk_txeq_pre_tap_3_Prof23 |
0.0 |
| bk_ext_ac_cap_Prof23 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof23 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof23 |
ENABLE |
| ux_txeq_post_tap_1_Prof23 |
0 |
| ux_txeq_main_tap_Prof23 |
35 |
| ux_txeq_pre_tap_1_Prof23 |
5 |
| ux_txeq_pre_tap_2_Prof23 |
0 |
| vsr_mode_Prof23 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof23 |
0 |
| rxeq_hf_boost_Prof23 |
0 |
| rxeq_dfe_data_tap_1_Prof23 |
0 |
| bk_rx_invert_p_and_n_Prof24 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof24 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof24 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof24 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof24 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof24 |
0.0 |
| bk_txeq_post_tap_3_Prof24 |
0.0 |
| bk_txeq_post_tap_2_Prof24 |
0.0 |
| bk_txeq_post_tap_1_Prof24 |
0.0 |
| bk_txeq_main_tap_Prof24 |
41.5 |
| bk_txeq_pre_tap_1_Prof24 |
0.0 |
| bk_txeq_pre_tap_2_Prof24 |
0.0 |
| bk_txeq_pre_tap_3_Prof24 |
0.0 |
| bk_ext_ac_cap_Prof24 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof24 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof24 |
ENABLE |
| ux_txeq_post_tap_1_Prof24 |
0 |
| ux_txeq_main_tap_Prof24 |
35 |
| ux_txeq_pre_tap_1_Prof24 |
5 |
| ux_txeq_pre_tap_2_Prof24 |
0 |
| vsr_mode_Prof24 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof24 |
0 |
| rxeq_hf_boost_Prof24 |
0 |
| rxeq_dfe_data_tap_1_Prof24 |
0 |
| bk_rx_invert_p_and_n_Prof25 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof25 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof25 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof25 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof25 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof25 |
0.0 |
| bk_txeq_post_tap_3_Prof25 |
0.0 |
| bk_txeq_post_tap_2_Prof25 |
0.0 |
| bk_txeq_post_tap_1_Prof25 |
0.0 |
| bk_txeq_main_tap_Prof25 |
41.5 |
| bk_txeq_pre_tap_1_Prof25 |
0.0 |
| bk_txeq_pre_tap_2_Prof25 |
0.0 |
| bk_txeq_pre_tap_3_Prof25 |
0.0 |
| bk_ext_ac_cap_Prof25 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof25 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof25 |
ENABLE |
| ux_txeq_post_tap_1_Prof25 |
0 |
| ux_txeq_main_tap_Prof25 |
35 |
| ux_txeq_pre_tap_1_Prof25 |
5 |
| ux_txeq_pre_tap_2_Prof25 |
0 |
| vsr_mode_Prof25 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof25 |
0 |
| rxeq_hf_boost_Prof25 |
0 |
| rxeq_dfe_data_tap_1_Prof25 |
0 |
| bk_rx_invert_p_and_n_Prof26 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof26 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof26 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof26 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof26 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof26 |
0.0 |
| bk_txeq_post_tap_3_Prof26 |
0.0 |
| bk_txeq_post_tap_2_Prof26 |
0.0 |
| bk_txeq_post_tap_1_Prof26 |
0.0 |
| bk_txeq_main_tap_Prof26 |
41.5 |
| bk_txeq_pre_tap_1_Prof26 |
0.0 |
| bk_txeq_pre_tap_2_Prof26 |
0.0 |
| bk_txeq_pre_tap_3_Prof26 |
0.0 |
| bk_ext_ac_cap_Prof26 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof26 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof26 |
ENABLE |
| ux_txeq_post_tap_1_Prof26 |
0 |
| ux_txeq_main_tap_Prof26 |
35 |
| ux_txeq_pre_tap_1_Prof26 |
5 |
| ux_txeq_pre_tap_2_Prof26 |
0 |
| vsr_mode_Prof26 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof26 |
0 |
| rxeq_hf_boost_Prof26 |
0 |
| rxeq_dfe_data_tap_1_Prof26 |
0 |
| bk_rx_invert_p_and_n_Prof27 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof27 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof27 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof27 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof27 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof27 |
0.0 |
| bk_txeq_post_tap_3_Prof27 |
0.0 |
| bk_txeq_post_tap_2_Prof27 |
0.0 |
| bk_txeq_post_tap_1_Prof27 |
0.0 |
| bk_txeq_main_tap_Prof27 |
41.5 |
| bk_txeq_pre_tap_1_Prof27 |
0.0 |
| bk_txeq_pre_tap_2_Prof27 |
0.0 |
| bk_txeq_pre_tap_3_Prof27 |
0.0 |
| bk_ext_ac_cap_Prof27 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof27 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof27 |
ENABLE |
| ux_txeq_post_tap_1_Prof27 |
0 |
| ux_txeq_main_tap_Prof27 |
35 |
| ux_txeq_pre_tap_1_Prof27 |
5 |
| ux_txeq_pre_tap_2_Prof27 |
0 |
| vsr_mode_Prof27 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof27 |
0 |
| rxeq_hf_boost_Prof27 |
0 |
| rxeq_dfe_data_tap_1_Prof27 |
0 |
| bk_rx_invert_p_and_n_Prof28 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof28 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof28 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof28 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof28 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof28 |
0.0 |
| bk_txeq_post_tap_3_Prof28 |
0.0 |
| bk_txeq_post_tap_2_Prof28 |
0.0 |
| bk_txeq_post_tap_1_Prof28 |
0.0 |
| bk_txeq_main_tap_Prof28 |
41.5 |
| bk_txeq_pre_tap_1_Prof28 |
0.0 |
| bk_txeq_pre_tap_2_Prof28 |
0.0 |
| bk_txeq_pre_tap_3_Prof28 |
0.0 |
| bk_ext_ac_cap_Prof28 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof28 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof28 |
ENABLE |
| ux_txeq_post_tap_1_Prof28 |
0 |
| ux_txeq_main_tap_Prof28 |
35 |
| ux_txeq_pre_tap_1_Prof28 |
5 |
| ux_txeq_pre_tap_2_Prof28 |
0 |
| vsr_mode_Prof28 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof28 |
0 |
| rxeq_hf_boost_Prof28 |
0 |
| rxeq_dfe_data_tap_1_Prof28 |
0 |
| bk_rx_invert_p_and_n_Prof29 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof29 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof29 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof29 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof29 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof29 |
0.0 |
| bk_txeq_post_tap_3_Prof29 |
0.0 |
| bk_txeq_post_tap_2_Prof29 |
0.0 |
| bk_txeq_post_tap_1_Prof29 |
0.0 |
| bk_txeq_main_tap_Prof29 |
41.5 |
| bk_txeq_pre_tap_1_Prof29 |
0.0 |
| bk_txeq_pre_tap_2_Prof29 |
0.0 |
| bk_txeq_pre_tap_3_Prof29 |
0.0 |
| bk_ext_ac_cap_Prof29 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof29 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof29 |
ENABLE |
| ux_txeq_post_tap_1_Prof29 |
0 |
| ux_txeq_main_tap_Prof29 |
35 |
| ux_txeq_pre_tap_1_Prof29 |
5 |
| ux_txeq_pre_tap_2_Prof29 |
0 |
| vsr_mode_Prof29 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof29 |
0 |
| rxeq_hf_boost_Prof29 |
0 |
| rxeq_dfe_data_tap_1_Prof29 |
0 |
| bk_rx_invert_p_and_n_Prof30 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof30 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof30 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof30 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof30 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof30 |
0.0 |
| bk_txeq_post_tap_3_Prof30 |
0.0 |
| bk_txeq_post_tap_2_Prof30 |
0.0 |
| bk_txeq_post_tap_1_Prof30 |
0.0 |
| bk_txeq_main_tap_Prof30 |
41.5 |
| bk_txeq_pre_tap_1_Prof30 |
0.0 |
| bk_txeq_pre_tap_2_Prof30 |
0.0 |
| bk_txeq_pre_tap_3_Prof30 |
0.0 |
| bk_ext_ac_cap_Prof30 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof30 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof30 |
ENABLE |
| ux_txeq_post_tap_1_Prof30 |
0 |
| ux_txeq_main_tap_Prof30 |
35 |
| ux_txeq_pre_tap_1_Prof30 |
5 |
| ux_txeq_pre_tap_2_Prof30 |
0 |
| vsr_mode_Prof30 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof30 |
0 |
| rxeq_hf_boost_Prof30 |
0 |
| rxeq_dfe_data_tap_1_Prof30 |
0 |
| bk_rx_invert_p_and_n_Prof31 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof31 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof31 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof31 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof31 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof31 |
0.0 |
| bk_txeq_post_tap_3_Prof31 |
0.0 |
| bk_txeq_post_tap_2_Prof31 |
0.0 |
| bk_txeq_post_tap_1_Prof31 |
0.0 |
| bk_txeq_main_tap_Prof31 |
41.5 |
| bk_txeq_pre_tap_1_Prof31 |
0.0 |
| bk_txeq_pre_tap_2_Prof31 |
0.0 |
| bk_txeq_pre_tap_3_Prof31 |
0.0 |
| bk_ext_ac_cap_Prof31 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof31 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof31 |
ENABLE |
| ux_txeq_post_tap_1_Prof31 |
0 |
| ux_txeq_main_tap_Prof31 |
35 |
| ux_txeq_pre_tap_1_Prof31 |
5 |
| ux_txeq_pre_tap_2_Prof31 |
0 |
| vsr_mode_Prof31 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof31 |
0 |
| rxeq_hf_boost_Prof31 |
0 |
| rxeq_dfe_data_tap_1_Prof31 |
0 |
| bk_rx_invert_p_and_n_Prof32 |
RX_INVERT_PN_DIS |
| bk_rx_termination_Prof32 |
RXTERM_OFFSET_P0 |
| bk_tx_invert_p_and_n_Prof32 |
TX_INVERT_PN_DIS |
| bk_txout_tristate_en_Prof32 |
TXOUT_TRISTATE_DIS |
| bk_tx_termination_Prof32 |
TXTERM_OFFSET_P0 |
| bk_txeq_post_tap_4_Prof32 |
0.0 |
| bk_txeq_post_tap_3_Prof32 |
0.0 |
| bk_txeq_post_tap_2_Prof32 |
0.0 |
| bk_txeq_post_tap_1_Prof32 |
0.0 |
| bk_txeq_main_tap_Prof32 |
41.5 |
| bk_txeq_pre_tap_1_Prof32 |
0.0 |
| bk_txeq_pre_tap_2_Prof32 |
0.0 |
| bk_txeq_pre_tap_3_Prof32 |
0.0 |
| bk_ext_ac_cap_Prof32 |
EXTERNAL_AC_CAP_ENABLE |
| rx_onchip_termination_Prof32 |
RX_ONCHIP_TERMINATION_R_2 |
| rx_ac_couple_enable_Prof32 |
ENABLE |
| ux_txeq_post_tap_1_Prof32 |
0 |
| ux_txeq_main_tap_Prof32 |
35 |
| ux_txeq_pre_tap_1_Prof32 |
5 |
| ux_txeq_pre_tap_2_Prof32 |
0 |
| vsr_mode_Prof32 |
VSR_MODE_DISABLE |
| rxeq_vga_gain_Prof32 |
0 |
| rxeq_hf_boost_Prof32 |
0 |
| rxeq_dfe_data_tap_1_Prof32 |
0 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |