pattgen_ctrl

2023.12.22.15:17:50 Datasheet
Overview

All Components
   mm_clock_crossing_bridge mm_ccb 19.2.1
   pattgen_ctrl_pio altera_avalon_pio 19.2.3
Memory Map
pattgen_ctrl_master
 master
  pattgen_ctrl_pio
s1  0x00000000

avmm_clk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

avmm_rst

altera_reset_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_clock_crossing_bridge

mm_ccb v19.2.1
pattgen_ctrl_master master   mm_clock_crossing_bridge
  s0
master_reset  
  m0_reset
master_reset  
  s0_reset
tx_clkout out_clk  
  m0_clk
avmm_clk out_clk  
  s0_clk
m0   pattgen_ctrl_pio
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

pattgen_ctrl_master

altera_jtag_avalon_master v19.1
avmm_clk out_clk   pattgen_ctrl_master
  clk
avmm_rst out_reset  
  clk_reset
master   mm_clock_crossing_bridge
  s0
master_reset  
  m0_reset
master_reset  
  s0_reset
master_reset   pattgen_ctrl_pio
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pattgen_ctrl_pio

altera_avalon_pio v19.2.3
mm_clock_crossing_bridge m0   pattgen_ctrl_pio
  s1
tx_clkout out_clk  
  clk
pattgen_ctrl_master master_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 12
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 148500000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 2048

pattgen_rst

altera_reset_controller v19.2.2
tx_clkout out_clk   pattgen_rst
  clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

tx_clkout

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)
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