| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u1 |
33 |
0 |
1 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u8|u0 |
35 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| u8 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe8 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe5 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo|dcfifo_mixed_widths_component|auto_generated |
21 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read2_fifo |
21 |
1 |
0 |
1 |
25 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe8 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|ws_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|ws_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe5 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo|dcfifo_mixed_widths_component|auto_generated |
21 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_read1_fifo |
21 |
1 |
0 |
1 |
25 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo|dcfifo_mixed_widths_component|auto_generated |
21 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write2_fifo |
21 |
1 |
0 |
1 |
25 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp |
20 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|ws_dgrp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13 |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rs_bwp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rs_brp |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|fifo_ram |
40 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin |
10 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo|dcfifo_mixed_widths_component|auto_generated |
21 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_write1_fifo |
21 |
1 |
0 |
1 |
25 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u7|u_sdr_data_path |
20 |
2 |
0 |
2 |
18 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u7|u_command |
35 |
0 |
2 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u7|u_control_interface |
30 |
1 |
0 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u7 |
262 |
219 |
0 |
219 |
54 |
219 |
219 |
219 |
16 |
0 |
0 |
0 |
0 |
| u6|sdram_pll_inst |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u6 |
2 |
1 |
0 |
1 |
4 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u5|u5 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u4 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u3 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u2 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u1 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5|u0 |
4 |
0 |
0 |
0 |
7 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5 |
24 |
0 |
0 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|ALTSHIFT_TAPS_component|auto_generated|cntr1|cmpr4 |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|ALTSHIFT_TAPS_component|auto_generated|cntr1 |
2 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|ALTSHIFT_TAPS_component|auto_generated|altsyncram2 |
49 |
1 |
0 |
1 |
24 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u4|u0|ALTSHIFT_TAPS_component|auto_generated |
14 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4|u0 |
14 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u4 |
37 |
0 |
20 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u3 |
18 |
0 |
0 |
0 |
77 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u2 |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |