Qsys

2020.08.13.15:01:51 Datasheet
Overview
Processor
   nios2_gen2 Nios II 19.1.0
All Components
   address_span_extender_ddr4 altera_address_span_extender 19.2.0
   button altera_avalon_pio 19.1.0
   ddr4_local_reset_req altera_avalon_pio 19.1.0
   ddr4_status altera_avalon_pio 19.1.0
   emif_agilex_a altera_emif_fm 2.2.0
   emif_agilex_b altera_emif_fm 2.2.0
   emif_agilex_c altera_emif_fm 2.2.0
   emif_agilex_d altera_emif_fm 2.2.0
   jtag_uart altera_avalon_jtag_uart 19.1.0
   mm_clock_crossing_bridge_50M altera_avalon_mm_clock_crossing_bridge 19.2.0
   nios2_gen2 altera_nios2_gen2 19.1.0
   onchip_memory2 altera_avalon_onchip_memory2 19.2.0
   sysid_qsys altera_avalon_sysid_qsys 19.1.0
   timer altera_avalon_timer 19.1.0
Memory Map
address_span_extender_ddr4 nios2_gen2
 expanded_master  data_master  instruction_master
  address_span_extender_ddr4
windowed_slave  0x00000000
cntl  0x40000050
  button
s1  0x40000040
  ddr4_local_reset_req
s1  0x40000020
  ddr4_status
s1  0x40000030
  emif_agilex_a
ctrl_amm_0  0x00000000
  emif_agilex_b
ctrl_amm_0  0x0000000200000000
  emif_agilex_c
ctrl_amm_0  0x0000000400000000
  emif_agilex_d
ctrl_amm_0  0x0000000600000000
  jtag_uart
avalon_jtag_slave  0x40000060
  nios2_gen2
debug_mem_slave  0x80100800 0x80100800
  onchip_memory2
s1  0x80080000 0x80080000
  sysid_qsys
control_slave  0x40000058
  timer
s1  0x40000000

address_span_extender_ddr4

altera_address_span_extender v19.2.0
mm_clock_crossing_bridge_50M m0   address_span_extender_ddr4
  cntl
m0  
  windowed_slave
clock_in out_clk  
  clock
reset_in out_reset  
  reset
expanded_master   emif_agilex_a
  ctrl_amm_0
expanded_master   emif_agilex_b
  ctrl_amm_0
expanded_master   emif_agilex_c
  ctrl_amm_0
expanded_master   emif_agilex_d
  ctrl_amm_0


Parameters

generateLegacySim false
  

Software Assignments

BURSTCOUNT_WIDTH 1
BYTEENABLE_WIDTH 4
CNTL_ADDRESS_WIDTH 1
DATA_WIDTH 32
MASTER_ADDRESS_WIDTH 35
MAX_BURST_BYTES 4
MAX_BURST_WORDS 1
SLAVE_ADDRESS_SHIFT 2
SLAVE_ADDRESS_WIDTH 28
SUB_WINDOW_COUNT 1

button

altera_avalon_pio v19.1.0
mm_clock_crossing_bridge_50M m0   button
  s1
clock_in out_clk  
  clk
nios2_gen2 irq  
  irq
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

ddr4_local_reset_req

altera_avalon_pio v19.1.0
mm_clock_crossing_bridge_50M m0   ddr4_local_reset_req
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

ddr4_status

altera_avalon_pio v19.1.0
mm_clock_crossing_bridge_50M m0   ddr4_status
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 12
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

emif_agilex_a

altera_emif_fm v2.2.0
address_span_extender_ddr4 expanded_master   emif_agilex_a
  ctrl_amm_0
emif_cal_ab emif_calbus_clk  
  emif_calbus_clk
emif_calbus   emif_cal_ab
  emif_calbus_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_agilex_b

altera_emif_fm v2.2.0
address_span_extender_ddr4 expanded_master   emif_agilex_b
  ctrl_amm_0
emif_cal_ab emif_calbus_clk  
  emif_calbus_clk
emif_calbus   emif_cal_ab
  emif_calbus_1


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_agilex_c

altera_emif_fm v2.2.0
address_span_extender_ddr4 expanded_master   emif_agilex_c
  ctrl_amm_0
emif_cal_cd emif_calbus_clk  
  emif_calbus_clk
emif_calbus   emif_cal_cd
  emif_calbus_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_agilex_d

altera_emif_fm v2.2.0
address_span_extender_ddr4 expanded_master   emif_agilex_d
  ctrl_amm_0
emif_cal_cd emif_calbus_clk  
  emif_calbus_clk
emif_calbus   emif_cal_cd
  emif_calbus_1


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_cal_ab

altera_emif_cal v2.2.0
emif_agilex_a emif_calbus   emif_cal_ab
  emif_calbus_0
emif_agilex_b emif_calbus  
  emif_calbus_1
emif_calbus_clk   emif_agilex_a
  emif_calbus_clk
emif_calbus_clk   emif_agilex_b
  emif_calbus_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_cal_cd

altera_emif_cal v2.2.0
emif_agilex_c emif_calbus   emif_cal_cd
  emif_calbus_0
emif_agilex_d emif_calbus  
  emif_calbus_1
emif_calbus_clk   emif_agilex_c
  emif_calbus_clk
emif_calbus_clk   emif_agilex_d
  emif_calbus_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll

altera_iopll v19.3.0
clock_in out_clk   iopll
  refclk
reset_in out_reset  
  reset
outclk0   nios2_gen2
  clk
outclk0   onchip_memory2
  clk1
outclk0   mm_clock_crossing_bridge_50M
  s0_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v19.1.0
mm_clock_crossing_bridge_50M m0   jtag_uart
  avalon_jtag_slave
clock_in out_clk  
  clk
nios2_gen2 irq  
  irq
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

mm_clock_crossing_bridge_50M

altera_avalon_mm_clock_crossing_bridge v19.2.0
nios2_gen2 data_master   mm_clock_crossing_bridge_50M
  s0
clock_in out_clk  
  m0_clk
iopll outclk0  
  s0_clk
reset_in out_reset  
  m0_reset
out_reset  
  s0_reset
m0   jtag_uart
  avalon_jtag_slave
m0   address_span_extender_ddr4
  cntl
m0  
  windowed_slave
m0   sysid_qsys
  control_slave
m0   timer
  s1
m0   button
  s1
m0   ddr4_status
  s1
m0   ddr4_local_reset_req
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

nios2_gen2

altera_nios2_gen2 v19.1.0
iopll outclk0   nios2_gen2
  clk
reset_in out_reset  
  reset
data_master   mm_clock_crossing_bridge_50M
  s0
data_master   onchip_memory2
  s1
instruction_master  
  s1
irq   jtag_uart
  irq
irq   timer
  irq
irq   button
  irq


Parameters

generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x80100820
CPU_ARCH_NIOS2_R1
CPU_FREQ 200000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 32
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
EXCEPTION_ADDR 0x80080020
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 2048
INITDA_SUPPORTED
INST_ADDR_WIDTH 32
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x80080000

onchip_memory2

altera_avalon_onchip_memory2 v19.2.0
nios2_gen2 data_master   onchip_memory2
  s1
instruction_master  
  s1
iopll outclk0  
  clk1
reset_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE Qsys_onchip_memory2_0_onchip_memory2_0
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 512000
WRITABLE 1

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   mm_clock_crossing_bridge_50M
  m0_reset
out_reset  
  s0_reset
out_reset   nios2_gen2
  reset
out_reset   jtag_uart
  reset
out_reset   timer
  reset
out_reset   sysid_qsys
  reset
out_reset   button
  reset
out_reset   ddr4_status
  reset
out_reset   ddr4_local_reset_req
  reset
out_reset   address_span_extender_ddr4
  reset
out_reset   iopll
  reset
out_reset   onchip_memory2
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)

sysid_qsys

altera_avalon_sysid_qsys v19.1.0
mm_clock_crossing_bridge_50M m0   sysid_qsys
  control_slave
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

timer

altera_avalon_timer v19.1.0
mm_clock_crossing_bridge_50M m0   timer
  s1
clock_in out_clk  
  clk
nios2_gen2 irq  
  irq
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
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