DE10_Agilex_System

2020.07.23.14:36:50 Datasheet
Overview
Processor
   nios2_gen2 Nios II 19.1.0
All Components
   QSFPDDA_REFCLK TERASIC_CLOCK_COUNT 1.0
   QSFPDDB_REFCLK TERASIC_CLOCK_COUNT 1.0
   QSFPDDRSV_REFCLK TERASIC_CLOCK_COUNT 1.0
   board_info_core_current1 altera_avalon_pio 19.1.0
   board_info_core_current2 altera_avalon_pio 19.1.0
   board_info_core_voltage1 altera_avalon_pio 19.1.0
   board_info_core_voltage2 altera_avalon_pio 19.1.0
   board_info_fan_speed1 altera_avalon_pio 19.1.0
   board_info_fan_speed2 altera_avalon_pio 19.1.0
   board_info_pin_status altera_avalon_pio 19.1.0
   board_info_power_in_current altera_avalon_pio 19.1.0
   board_info_power_in_voltage altera_avalon_pio 19.1.0
   board_info_temperature_board1 altera_avalon_pio 19.1.0
   board_info_temperature_board2 altera_avalon_pio 19.1.0
   board_info_temperature_e_tile altera_avalon_pio 19.1.0
   board_info_temperature_fpga altera_avalon_pio 19.1.0
   board_info_temperature_p_tile altera_avalon_pio 19.1.0
   board_info_temperature_sdm altera_avalon_pio 19.1.0
   jtag_uart altera_avalon_jtag_uart 19.1.0
   nios2_gen2 altera_nios2_gen2 19.1.0
   onchip_memory2 altera_avalon_onchip_memory2 19.2.0
   si5340a_i2c i2c_opencores 12.0
   si5340a_oe_n altera_avalon_pio 19.1.0
   si5340a_rst_n altera_avalon_pio 19.1.0
   sysid_qsys altera_avalon_sysid_qsys 19.1.0
   timer altera_avalon_timer 19.1.0
Memory Map
nios2_gen2
 data_master  instruction_master
  QSFPDDA_REFCLK
Slave  0x00102150
  QSFPDDB_REFCLK
Slave  0x00102140
  QSFPDDRSV_REFCLK
Slave  0x00102130
  board_info_core_current1
s1  0x00101050
  board_info_core_current2
s1  0x001010f0
  board_info_core_voltage1
s1  0x00101040
  board_info_core_voltage2
s1  0x001010e0
  board_info_fan_speed1
s1  0x00101060
  board_info_fan_speed2
s1  0x00101070
  board_info_pin_status
s1  0x001010a0
  board_info_power_in_current
s1  0x00101030
  board_info_power_in_voltage
s1  0x00101020
  board_info_temperature_board1
s1  0x00101090
  board_info_temperature_board2
s1  0x00101100
  board_info_temperature_e_tile
s1  0x001010c0
  board_info_temperature_fpga
s1  0x00101080
  board_info_temperature_p_tile
s1  0x001010d0
  board_info_temperature_sdm
s1  0x001010b0
  jtag_uart
avalon_jtag_slave  0x00102168
  nios2_gen2
debug_mem_slave  0x00102800 0x00102800
  onchip_memory2
s1  0x00080000 0x00080000
  si5340a_i2c
avalon_slave_0  0x00102000
  si5340a_oe_n
s1  0x00102120
  si5340a_rst_n
s1  0x00102110
  sysid_qsys
control_slave  0x00102160
  timer
s1  0x00102180

QSFPDDA_REFCLK

TERASIC_CLOCK_COUNT v1.0
nios2_gen2 data_master   QSFPDDA_REFCLK
  Slave
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

QSFPDDB_REFCLK

TERASIC_CLOCK_COUNT v1.0
nios2_gen2 data_master   QSFPDDB_REFCLK
  Slave
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

QSFPDDRSV_REFCLK

TERASIC_CLOCK_COUNT v1.0
nios2_gen2 data_master   QSFPDDRSV_REFCLK
  Slave
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

board_info_core_current1

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_core_current1
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_core_current2

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_core_current2
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_core_voltage1

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_core_voltage1
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_core_voltage2

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_core_voltage2
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_fan_speed1

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_fan_speed1
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_fan_speed2

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_fan_speed2
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_pin_status

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_pin_status
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_power_in_current

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_power_in_current
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_power_in_voltage

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_power_in_voltage
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_temperature_board1

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_temperature_board1
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_temperature_board2

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_temperature_board2
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_temperature_e_tile

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_temperature_e_tile
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_temperature_fpga

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_temperature_fpga
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_temperature_p_tile

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_temperature_p_tile
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

board_info_temperature_sdm

altera_avalon_pio v19.1.0
nios2_gen2 data_master   board_info_temperature_sdm
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v19.1.0
nios2_gen2 data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

nios2_gen2

altera_nios2_gen2 v19.1.0
clock_in out_clk   nios2_gen2
  clk
reset_controller reset_out  
  reset
data_master   QSFPDDA_REFCLK
  Slave
data_master   QSFPDDB_REFCLK
  Slave
data_master   QSFPDDRSV_REFCLK
  Slave
data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
data_master   si5340a_i2c
  avalon_slave_0
irq  
  interrupt_sender
data_master   sysid_qsys
  control_slave
data_master   onchip_memory2
  s1
instruction_master  
  s1
data_master   si5340a_oe_n
  s1
data_master   si5340a_rst_n
  s1
data_master   board_info_temperature_fpga
  s1
data_master   board_info_temperature_board1
  s1
data_master   board_info_fan_speed1
  s1
data_master   board_info_fan_speed2
  s1
data_master   board_info_core_current1
  s1
data_master   board_info_core_voltage1
  s1
data_master   board_info_power_in_current
  s1
data_master   board_info_power_in_voltage
  s1
data_master   board_info_pin_status
  s1
data_master   board_info_temperature_sdm
  s1
data_master   board_info_temperature_e_tile
  s1
data_master   board_info_core_current2
  s1
data_master   board_info_core_voltage2
  s1
data_master   board_info_temperature_board2
  s1
data_master   board_info_temperature_p_tile
  s1
data_master   timer
  s1
irq  
  irq


Parameters

generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x00102820
CPU_ARCH_NIOS2_R1
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 21
DCACHE_BYPASS_MASK 0x80000000
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
EXCEPTION_ADDR 0x00080020
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 2048
INITDA_SUPPORTED
INST_ADDR_WIDTH 21
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x00080000

onchip_memory2

altera_avalon_onchip_memory2 v19.2.0
nios2_gen2 data_master   onchip_memory2
  s1
instruction_master  
  s1
clock_in out_clk  
  clk1
reset_controller reset_out  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE onchip_memory2_onchip_memory2
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

reset_controller

altera_reset_controller v19.2.0
clock_in out_clk   reset_controller
  clk
reset_out   si5340a_i2c
  clock_reset
reset_out   nios2_gen2
  reset
reset_out   jtag_uart
  reset
reset_out   sysid_qsys
  reset
reset_out   si5340a_oe_n
  reset
reset_out   si5340a_rst_n
  reset
reset_out   QSFPDDA_REFCLK
  reset
reset_out   QSFPDDB_REFCLK
  reset
reset_out   QSFPDDRSV_REFCLK
  reset
reset_out   board_info_temperature_fpga
  reset
reset_out   board_info_temperature_board1
  reset
reset_out   board_info_fan_speed1
  reset
reset_out   board_info_fan_speed2
  reset
reset_out   board_info_core_current1
  reset
reset_out   board_info_core_voltage1
  reset
reset_out   board_info_pin_status
  reset
reset_out   board_info_temperature_sdm
  reset
reset_out   board_info_temperature_e_tile
  reset
reset_out   board_info_temperature_p_tile
  reset
reset_out   board_info_core_current2
  reset
reset_out   board_info_temperature_board2
  reset
reset_out   board_info_core_voltage2
  reset
reset_out   board_info_power_in_current
  reset
reset_out   board_info_power_in_voltage
  reset
reset_out   timer
  reset
reset_out   onchip_memory2
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)

si5340a_i2c

i2c_opencores v12.0
nios2_gen2 data_master   si5340a_i2c
  avalon_slave_0
irq  
  interrupt_sender
clock_in out_clk  
  clock
reset_controller reset_out  
  clock_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

si5340a_oe_n

altera_avalon_pio v19.1.0
nios2_gen2 data_master   si5340a_oe_n
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

si5340a_rst_n

altera_avalon_pio v19.1.0
nios2_gen2 data_master   si5340a_rst_n
  s1
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

sysid_qsys

altera_avalon_sysid_qsys v19.1.0
nios2_gen2 data_master   sysid_qsys
  control_slave
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

timer

altera_avalon_timer v19.1.0
nios2_gen2 data_master   timer
  s1
irq  
  irq
clock_in out_clk  
  clk
reset_controller reset_out  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
generation took 0.01 seconds rendering took 0.12 seconds