demo_control

2020.07.24.17:47:21 Datasheet
Overview

All Components
   demo_mgmt altera_avalon_mm_bridge 19.2.0
   measure_payload_pio_h altera_avalon_pio 19.1.0
   measure_payload_pio_l altera_avalon_pio 19.1.0
   measure_time_pio altera_avalon_pio 19.1.0
   phy_mgmt altera_avalon_mm_bridge 19.2.0
   rx_coreclk_cnt_pio altera_avalon_pio 19.1.0
   rx_lanes_status_pio altera_avalon_pio 19.1.0
   system_status_pio altera_avalon_pio 19.1.0
   tx_lanes_status_pio altera_avalon_pio 19.1.0
   txrx_lanes_status_pio altera_avalon_pio 19.1.0
Memory Map
demo_jtag_m phy_jtag_m
 master  master
  measure_payload_pio_h
s1  0x00000260
  measure_payload_pio_l
s1  0x00000250
  measure_time_pio
s1  0x00000240
  rx_coreclk_cnt_pio
s1  0x00000270
  rx_lanes_status_pio
s1  0x00000220
  system_status_pio
s1  0x00000200
  tx_lanes_status_pio
s1  0x00000210
  txrx_lanes_status_pio
s1  0x00000230

clock_bridge

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

demo_jtag_m

altera_jtag_avalon_master v19.1
clock_bridge out_clk   demo_jtag_m
  clk
reset_bridge out_reset  
  clk_reset
master   demo_mgmt
  s0
master   system_status_pio
  s1
master   measure_time_pio
  s1
master   measure_payload_pio_l
  s1
master   rx_lanes_status_pio
  s1
master   tx_lanes_status_pio
  s1
master   measure_payload_pio_h
  s1
master   txrx_lanes_status_pio
  s1
master   rx_coreclk_cnt_pio
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

demo_mgmt

altera_avalon_mm_bridge v19.2.0
demo_jtag_m master   demo_mgmt
  s0
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

issp

altera_in_system_sources_probes v19.2.0
clock_bridge out_clk   issp
  source_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

measure_payload_pio_h

altera_avalon_pio v19.1.0
demo_jtag_m master   measure_payload_pio_h
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

measure_payload_pio_l

altera_avalon_pio v19.1.0
demo_jtag_m master   measure_payload_pio_l
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

measure_time_pio

altera_avalon_pio v19.1.0
demo_jtag_m master   measure_time_pio
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

phy_jtag_m

altera_jtag_avalon_master v19.1
clock_bridge out_clk   phy_jtag_m
  clk
reset_bridge out_reset  
  clk_reset
master   phy_mgmt
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

phy_mgmt

altera_avalon_mm_bridge v19.2.0
phy_jtag_m master   phy_mgmt
  s0
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_bridge

altera_reset_bridge v19.2.0
clock_bridge out_clk   reset_bridge
  clk
out_reset   phy_jtag_m
  clk_reset
out_reset   demo_jtag_m
  clk_reset
out_reset   sync_reset
  in_reset
out_reset   phy_mgmt
  reset
out_reset   demo_mgmt
  reset
out_reset   system_status_pio
  reset
out_reset   measure_time_pio
  reset
out_reset   measure_payload_pio_l
  reset
out_reset   rx_lanes_status_pio
  reset
out_reset   tx_lanes_status_pio
  reset
out_reset   measure_payload_pio_h
  reset
out_reset   txrx_lanes_status_pio
  reset
out_reset   rx_coreclk_cnt_pio
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

rx_coreclk_cnt_pio

altera_avalon_pio v19.1.0
demo_jtag_m master   rx_coreclk_cnt_pio
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

rx_coreclk_sync

altera_reset_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

rx_lanes_status_pio

altera_avalon_pio v19.1.0
demo_jtag_m master   rx_lanes_status_pio
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

sync_reset

altera_reset_bridge v19.2.0
clock_bridge out_clk   sync_reset
  clk
reset_bridge out_reset  
  in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

system_status_pio

altera_avalon_pio v19.1.0
demo_jtag_m master   system_status_pio
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

tx_coreclk_sync

altera_reset_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

tx_lanes_status_pio

altera_avalon_pio v19.1.0
demo_jtag_m master   tx_lanes_status_pio
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

txrx_lanes_status_pio

altera_avalon_pio v19.1.0
demo_jtag_m master   txrx_lanes_status_pio
  s1
clock_bridge out_clk  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0
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