mm_clock_crossing_bridge_ddr4
2020.07.09.15:03:59
Datasheet
Overview
All Components
mm_clock_crossing_bridge_ddr4
altera_avalon_mm_clock_crossing_bridge 19.2.0
Memory Map
mm_clock_crossing_bridge_ddr4
altera_avalon_mm_clock_crossing_bridge v19.2.0
Parameters
DATA_WIDTH
512
SYMBOL_WIDTH
8
ADDRESS_WIDTH
10
USE_AUTO_ADDRESS_WIDTH
1
AUTO_ADDRESS_WIDTH
33
ADDRESS_UNITS
SYMBOLS
MAX_BURST_SIZE
8
COMMAND_FIFO_DEPTH
64
RESPONSE_FIFO_DEPTH
512
MASTER_SYNC_DEPTH
2
SLAVE_SYNC_DEPTH
2
SYNC_RESET
1
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.01 seconds
rendering took 0.06 seconds