Sample behavioral waveforms for design file I2S_TX_FIFO.v

The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design I2S_TX_FIFO.v. The design I2S_TX_FIFO.v has a depth of 256 words of 32 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.

The above waveform shows the behavior of the design under normal read and write conditions .

Fig. 2 : Wave showing FIFO full operation.

The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.