DE10 Standard Board Configuration

DE10 Standard Board Configuration

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Copyright © 2003-2016 Terasic Inc. All Rights Reserved.

Pin Assignments:

CLOCK
Name Location Direction IO Standard
CLOCK2_50 AA16 input 3.3-V LVTTL
CLOCK3_50 Y26 input 2.5 V
CLOCK4_50 K14 input 3.3-V LVTTL
CLOCK_50 AF14 input 3.3-V LVTTL

KEY
Name Location Direction IO Standard
KEY[0] AJ4 input 3.3-V LVTTL
KEY[1] AK4 input 3.3-V LVTTL
KEY[2] AA14 input 3.3-V LVTTL
KEY[3] AA15 input 3.3-V LVTTL

SW
Name Location Direction IO Standard
SW[0] AB30 input 2.5 V
SW[1] Y27 input 2.5 V
SW[2] AB28 input 2.5 V
SW[3] AC30 input 2.5 V
SW[4] W25 input 2.5 V
SW[5] V25 input 2.5 V
SW[6] AC28 input 2.5 V
SW[7] AD30 input 2.5 V
SW[8] AC29 input 2.5 V
SW[9] AA30 input 2.5 V

LED
Name Location Direction IO Standard
LEDR[0] AA24 output 3.3-V LVTTL
LEDR[1] AB23 output 3.3-V LVTTL
LEDR[2] AC23 output 3.3-V LVTTL
LEDR[3] AD24 output 3.3-V LVTTL
LEDR[4] AG25 output 3.3-V LVTTL
LEDR[5] AF25 output 3.3-V LVTTL
LEDR[6] AE24 output 3.3-V LVTTL
LEDR[7] AF24 output 3.3-V LVTTL
LEDR[8] AB22 output 3.3-V LVTTL
LEDR[9] AC22 output 3.3-V LVTTL

Seg7
Name Location Direction IO Standard
HEX0[0] W17 output 3.3-V LVTTL
HEX0[1] V18 output 3.3-V LVTTL
HEX0[2] AG17 output 3.3-V LVTTL
HEX0[3] AG16 output 3.3-V LVTTL
HEX0[4] AH17 output 3.3-V LVTTL
HEX0[5] AG18 output 3.3-V LVTTL
HEX0[6] AH18 output 3.3-V LVTTL
HEX1[0] AF16 output 3.3-V LVTTL
HEX1[1] V16 output 3.3-V LVTTL
HEX1[2] AE16 output 3.3-V LVTTL
HEX1[3] AD17 output 3.3-V LVTTL
HEX1[4] AE18 output 3.3-V LVTTL
HEX1[5] AE17 output 3.3-V LVTTL
HEX1[6] V17 output 3.3-V LVTTL
HEX2[0] AA21 output 3.3-V LVTTL
HEX2[1] AB17 output 3.3-V LVTTL
HEX2[2] AA18 output 3.3-V LVTTL
HEX2[3] Y17 output 3.3-V LVTTL
HEX2[4] Y18 output 3.3-V LVTTL
HEX2[5] AF18 output 3.3-V LVTTL
HEX2[6] W16 output 3.3-V LVTTL
HEX3[0] Y19 output 3.3-V LVTTL
HEX3[1] W19 output 3.3-V LVTTL
HEX3[2] AD19 output 3.3-V LVTTL
HEX3[3] AA20 output 3.3-V LVTTL
HEX3[4] AC20 output 3.3-V LVTTL
HEX3[5] AA19 output 3.3-V LVTTL
HEX3[6] AD20 output 3.3-V LVTTL
HEX4[0] AD21 output 3.3-V LVTTL
HEX4[1] AG22 output 3.3-V LVTTL
HEX4[2] AE22 output 3.3-V LVTTL
HEX4[3] AE23 output 3.3-V LVTTL
HEX4[4] AG23 output 3.3-V LVTTL
HEX4[5] AF23 output 3.3-V LVTTL
HEX4[6] AH22 output 3.3-V LVTTL
HEX5[0] AF21 output 3.3-V LVTTL
HEX5[1] AG21 output 3.3-V LVTTL
HEX5[2] AF20 output 3.3-V LVTTL
HEX5[3] AG20 output 3.3-V LVTTL
HEX5[4] AE19 output 3.3-V LVTTL
HEX5[5] AF19 output 3.3-V LVTTL
HEX5[6] AB21 output 3.3-V LVTTL

SDRAM
Name Location Direction IO Standard
DRAM_CLK AH12 output 3.3-V LVTTL
DRAM_CKE AK13 output 3.3-V LVTTL
DRAM_ADDR[0] AK14 output 3.3-V LVTTL
DRAM_ADDR[1] AH14 output 3.3-V LVTTL
DRAM_ADDR[2] AG15 output 3.3-V LVTTL
DRAM_ADDR[3] AE14 output 3.3-V LVTTL
DRAM_ADDR[4] AB15 output 3.3-V LVTTL
DRAM_ADDR[5] AC14 output 3.3-V LVTTL
DRAM_ADDR[6] AD14 output 3.3-V LVTTL
DRAM_ADDR[7] AF15 output 3.3-V LVTTL
DRAM_ADDR[8] AH15 output 3.3-V LVTTL
DRAM_ADDR[9] AG13 output 3.3-V LVTTL
DRAM_ADDR[10] AG12 output 3.3-V LVTTL
DRAM_ADDR[11] AH13 output 3.3-V LVTTL
DRAM_ADDR[12] AJ14 output 3.3-V LVTTL
DRAM_BA[0] AF13 output 3.3-V LVTTL
DRAM_BA[1] AJ12 output 3.3-V LVTTL
DRAM_DQ[0] AK6 inout 3.3-V LVTTL
DRAM_DQ[1] AJ7 inout 3.3-V LVTTL
DRAM_DQ[2] AK7 inout 3.3-V LVTTL
DRAM_DQ[3] AK8 inout 3.3-V LVTTL
DRAM_DQ[4] AK9 inout 3.3-V LVTTL
DRAM_DQ[5] AG10 inout 3.3-V LVTTL
DRAM_DQ[6] AK11 inout 3.3-V LVTTL
DRAM_DQ[7] AJ11 inout 3.3-V LVTTL
DRAM_DQ[8] AH10 inout 3.3-V LVTTL
DRAM_DQ[9] AJ10 inout 3.3-V LVTTL
DRAM_DQ[10] AJ9 inout 3.3-V LVTTL
DRAM_DQ[11] AH9 inout 3.3-V LVTTL
DRAM_DQ[12] AH8 inout 3.3-V LVTTL
DRAM_DQ[13] AH7 inout 3.3-V LVTTL
DRAM_DQ[14] AJ6 inout 3.3-V LVTTL
DRAM_DQ[15] AJ5 inout 3.3-V LVTTL
DRAM_LDQM AB13 output 3.3-V LVTTL
DRAM_UDQM AK12 output 3.3-V LVTTL
DRAM_CS_N AG11 output 3.3-V LVTTL
DRAM_WE_N AA13 output 3.3-V LVTTL
DRAM_CAS_N AF11 output 3.3-V LVTTL
DRAM_RAS_N AE13 output 3.3-V LVTTL

Video-In
Name Location Direction IO Standard
TD_CLK27 AC18 input 3.3-V LVTTL
TD_HS AH28 input 3.3-V LVTTL
TD_VS AG28 input 3.3-V LVTTL
TD_DATA[0] AG27 input 3.3-V LVTTL
TD_DATA[1] AF28 input 3.3-V LVTTL
TD_DATA[2] AE28 input 3.3-V LVTTL
TD_DATA[3] AE27 input 3.3-V LVTTL
TD_DATA[4] AE26 input 3.3-V LVTTL
TD_DATA[5] AD27 input 3.3-V LVTTL
TD_DATA[6] AD26 input 3.3-V LVTTL
TD_DATA[7] AD25 input 3.3-V LVTTL
TD_RESET_N AC27 output 3.3-V LVTTL

VGA
Name Location Direction IO Standard
VGA_CLK AK21 output 3.3-V LVTTL
VGA_HS AK19 output 3.3-V LVTTL
VGA_VS AK18 output 3.3-V LVTTL
VGA_R[0] AK29 output 3.3-V LVTTL
VGA_R[1] AK28 output 3.3-V LVTTL
VGA_R[2] AK27 output 3.3-V LVTTL
VGA_R[3] AJ27 output 3.3-V LVTTL
VGA_R[4] AH27 output 3.3-V LVTTL
VGA_R[5] AF26 output 3.3-V LVTTL
VGA_R[6] AG26 output 3.3-V LVTTL
VGA_R[7] AJ26 output 3.3-V LVTTL
VGA_G[0] AK26 output 3.3-V LVTTL
VGA_G[1] AJ25 output 3.3-V LVTTL
VGA_G[2] AH25 output 3.3-V LVTTL
VGA_G[3] AK24 output 3.3-V LVTTL
VGA_G[4] AJ24 output 3.3-V LVTTL
VGA_G[5] AH24 output 3.3-V LVTTL
VGA_G[6] AK23 output 3.3-V LVTTL
VGA_G[7] AH23 output 3.3-V LVTTL
VGA_B[0] AJ21 output 3.3-V LVTTL
VGA_B[1] AJ20 output 3.3-V LVTTL
VGA_B[2] AH20 output 3.3-V LVTTL
VGA_B[3] AJ19 output 3.3-V LVTTL
VGA_B[4] AH19 output 3.3-V LVTTL
VGA_B[5] AJ17 output 3.3-V LVTTL
VGA_B[6] AJ16 output 3.3-V LVTTL
VGA_B[7] AK16 output 3.3-V LVTTL
VGA_BLANK_N AK22 output 3.3-V LVTTL
VGA_SYNC_N AJ22 output 3.3-V LVTTL

Audio
Name Location Direction IO Standard
AUD_BCLK AF30 inout 3.3-V LVTTL
AUD_XCK AH30 output 3.3-V LVTTL
AUD_ADCLRCK AH29 inout 3.3-V LVTTL
AUD_ADCDAT AJ29 input 3.3-V LVTTL
AUD_DACLRCK AG30 inout 3.3-V LVTTL
AUD_DACDAT AF29 output 3.3-V LVTTL

IR
Name Location Direction IO Standard
IRDA_TXD W21 output 3.3-V LVTTL
IRDA_RXD W20 input 3.3-V LVTTL

PS2
Name Location Direction IO Standard
PS2_CLK AB25 inout 3.3-V LVTTL
PS2_CLK2 AC25 inout 3.3-V LVTTL
PS2_DAT AA25 inout 3.3-V LVTTL
PS2_DAT2 AB26 inout 3.3-V LVTTL

ADC
Name Location Direction IO Standard
ADC_SCLK W24 output 3.3-V LVTTL
ADC_DOUT V23 input 3.3-V LVTTL
ADC_DIN W22 output 3.3-V LVTTL
ADC_CONVST Y21 output 3.3-V LVTTL

I2C for Audio and Video-In
Name Location Direction IO Standard
FPGA_I2C_SCLK Y24 output 3.3-V LVTTL
FPGA_I2C_SDAT Y23 inout 3.3-V LVTTL

GPIO
Name Location Direction IO Standard
GPIO[0] W15 inout 3.3-V LVTTL
GPIO[1] AK2 inout 3.3-V LVTTL
GPIO[2] Y16 inout 3.3-V LVTTL
GPIO[3] AK3 inout 3.3-V LVTTL
GPIO[4] AJ1 inout 3.3-V LVTTL
GPIO[5] AJ2 inout 3.3-V LVTTL
GPIO[6] AH2 inout 3.3-V LVTTL
GPIO[7] AH3 inout 3.3-V LVTTL
GPIO[8] AH4 inout 3.3-V LVTTL
GPIO[9] AH5 inout 3.3-V LVTTL
GPIO[10] AG1 inout 3.3-V LVTTL
GPIO[11] AG2 inout 3.3-V LVTTL
GPIO[12] AG3 inout 3.3-V LVTTL
GPIO[13] AG5 inout 3.3-V LVTTL
GPIO[14] AG6 inout 3.3-V LVTTL
GPIO[15] AG7 inout 3.3-V LVTTL
GPIO[16] AG8 inout 3.3-V LVTTL
GPIO[17] AF4 inout 3.3-V LVTTL
GPIO[18] AF5 inout 3.3-V LVTTL
GPIO[19] AF6 inout 3.3-V LVTTL
GPIO[20] AF8 inout 3.3-V LVTTL
GPIO[21] AF9 inout 3.3-V LVTTL
GPIO[22] AF10 inout 3.3-V LVTTL
GPIO[23] AE7 inout 3.3-V LVTTL
GPIO[24] AE9 inout 3.3-V LVTTL
GPIO[25] AE11 inout 3.3-V LVTTL
GPIO[26] AE12 inout 3.3-V LVTTL
GPIO[27] AD7 inout 3.3-V LVTTL
GPIO[28] AD9 inout 3.3-V LVTTL
GPIO[29] AD10 inout 3.3-V LVTTL
GPIO[30] AD11 inout 3.3-V LVTTL
GPIO[31] AD12 inout 3.3-V LVTTL
GPIO[32] AC9 inout 3.3-V LVTTL
GPIO[33] AC12 inout 3.3-V LVTTL
GPIO[34] AB12 inout 3.3-V LVTTL
GPIO[35] AA12 inout 3.3-V LVTTL

HSMC
Name Location Direction IO Standard
HSMC_CLKIN_P1 AA26 input 2.5 V
HSMC_CLKIN_N1 AB27 input 2.5 V
HSMC_CLKIN_P2 H15 output 2.5 V
HSMC_CLKIN_N2 G15 input 2.5 V
HSMC_CLKOUT_P1 E7 input 2.5 V
HSMC_CLKOUT_N1 E6 output 2.5 V
HSMC_CLKOUT_P2 A11 output 2.5 V
HSMC_CLKOUT_N2 A10 output 2.5 V
HSMC_TX_D_P[0] A9 inout 2.5 V
HSMC_TX_D_P[1] E8 inout 2.5 V
HSMC_TX_D_P[2] G7 inout 2.5 V
HSMC_TX_D_P[3] D6 inout 2.5 V
HSMC_TX_D_P[4] D5 inout 2.5 V
HSMC_TX_D_P[5] E3 inout 2.5 V
HSMC_TX_D_P[6] E4 inout 2.5 V
HSMC_TX_D_P[7] C3 inout 2.5 V
HSMC_TX_D_P[8] E1 inout 2.5 V
HSMC_TX_D_P[9] D2 inout 2.5 V
HSMC_TX_D_P[10] B2 inout 2.5 V
HSMC_TX_D_P[11] A4 inout 2.5 V
HSMC_TX_D_P[12] A6 inout 2.5 V
HSMC_TX_D_P[13] C7 inout 2.5 V
HSMC_TX_D_P[14] C8 inout 2.5 V
HSMC_TX_D_P[15] C12 inout 2.5 V
HSMC_TX_D_P[16] B13 inout 2.5 V
HSMC_TX_D_N[0] A8 inout 2.5 V
HSMC_TX_D_N[1] D7 inout 2.5 V
HSMC_TX_D_N[2] F6 inout 2.5 V
HSMC_TX_D_N[3] C5 inout 2.5 V
HSMC_TX_D_N[4] C4 inout 2.5 V
HSMC_TX_D_N[5] E2 inout 2.5 V
HSMC_TX_D_N[6] D4 inout 2.5 V
HSMC_TX_D_N[7] B3 inout 2.5 V
HSMC_TX_D_N[8] D1 inout 2.5 V
HSMC_TX_D_N[9] C2 inout 2.5 V
HSMC_TX_D_N[10] B1 inout 2.5 V
HSMC_TX_D_N[11] A3 inout 2.5 V
HSMC_TX_D_N[12] A5 inout 2.5 V
HSMC_TX_D_N[13] B7 inout 2.5 V
HSMC_TX_D_N[14] B8 inout 2.5 V
HSMC_TX_D_N[15] B11 inout 2.5 V
HSMC_TX_D_N[16] A13 inout 2.5 V
HSMC_RX_D_P[0] G12 inout 2.5 V
HSMC_RX_D_P[1] K12 inout 2.5 V
HSMC_RX_D_P[2] G10 inout 2.5 V
HSMC_RX_D_P[3] J10 inout 2.5 V
HSMC_RX_D_P[4] K7 inout 2.5 V
HSMC_RX_D_P[5] J7 inout 2.5 V
HSMC_RX_D_P[6] H8 inout 2.5 V
HSMC_RX_D_P[7] F9 inout 2.5 V
HSMC_RX_D_P[8] F11 inout 2.5 V
HSMC_RX_D_P[9] B6 inout 2.5 V
HSMC_RX_D_P[10] E9 inout 2.5 V
HSMC_RX_D_P[11] E12 inout 2.5 V
HSMC_RX_D_P[12] D11 inout 2.5 V
HSMC_RX_D_P[13] C13 inout 2.5 V
HSMC_RX_D_P[14] F13 inout 2.5 V
HSMC_RX_D_P[15] H14 inout 2.5 V
HSMC_RX_D_P[16] F15 inout 2.5 V
HSMC_RX_D_N[0] G11 inout 2.5 V
HSMC_RX_D_N[1] J12 inout 2.5 V
HSMC_RX_D_N[2] F10 inout 2.5 V
HSMC_RX_D_N[3] J9 inout 2.5 V
HSMC_RX_D_N[4] K8 inout 2.5 V
HSMC_RX_D_N[5] H7 inout 2.5 V
HSMC_RX_D_N[6] G8 inout 2.5 V
HSMC_RX_D_N[7] F8 inout 2.5 V
HSMC_RX_D_N[8] E11 inout 2.5 V
HSMC_RX_D_N[9] B5 inout 2.5 V
HSMC_RX_D_N[10] D9 inout 2.5 V
HSMC_RX_D_N[11] D12 inout 2.5 V
HSMC_RX_D_N[12] D10 inout 2.5 V
HSMC_RX_D_N[13] B12 inout 2.5 V
HSMC_RX_D_N[14] E13 inout 2.5 V
HSMC_RX_D_N[15] G13 inout 2.5 V
HSMC_RX_D_N[16] F14 inout 2.5 V
HSMC_CLKIN[0] J14 input 2.5 V
HSMC_CLKOUT[0] AD29 output 2.5 V
HSMC_D[0] C10 inout 2.5 V
HSMC_D[1] H13 inout 2.5 V
HSMC_D[2] C9 inout 2.5 V
HSMC_D[3] H12 inout 2.5 V
HSMC_SCL AA28 output 2.5 V
HSMC_SDA AE29 inout 2.5 V

HPS
Name Location Direction IO Standard
HPS_CONV_USB_N B15 inout 3.3-V LVTTL
HPS_DDR3_ADDR[0] F26 output SSTL-15 Class I
HPS_DDR3_ADDR[1] G30 output SSTL-15 Class I
HPS_DDR3_ADDR[2] F28 output SSTL-15 Class I
HPS_DDR3_ADDR[3] F30 output SSTL-15 Class I
HPS_DDR3_ADDR[4] J25 output SSTL-15 Class I
HPS_DDR3_ADDR[5] J27 output SSTL-15 Class I
HPS_DDR3_ADDR[6] F29 output SSTL-15 Class I
HPS_DDR3_ADDR[7] E28 output SSTL-15 Class I
HPS_DDR3_ADDR[8] H27 output SSTL-15 Class I
HPS_DDR3_ADDR[9] G26 output SSTL-15 Class I
HPS_DDR3_ADDR[10] D29 output SSTL-15 Class I
HPS_DDR3_ADDR[11] C30 output SSTL-15 Class I
HPS_DDR3_ADDR[12] B30 output SSTL-15 Class I
HPS_DDR3_ADDR[13] C29 output SSTL-15 Class I
HPS_DDR3_ADDR[14] H25 output SSTL-15 Class I
HPS_DDR3_BA[0] E29 output SSTL-15 Class I
HPS_DDR3_BA[1] J24 output SSTL-15 Class I
HPS_DDR3_BA[2] J23 output SSTL-15 Class I
HPS_DDR3_CAS_N E27 output SSTL-15 Class I
HPS_DDR3_CKE L29 output SSTL-15 Class I
HPS_DDR3_CK_N L23 output Differential 1.5-V SSTL Class I
HPS_DDR3_CK_P M23 output Differential 1.5-V SSTL Class I
HPS_DDR3_CS_N H24 output SSTL-15 Class I
HPS_DDR3_DM[0] K28 output SSTL-15 Class I
HPS_DDR3_DM[1] M28 output SSTL-15 Class I
HPS_DDR3_DM[2] R28 output SSTL-15 Class I
HPS_DDR3_DM[3] W30 output SSTL-15 Class I
HPS_DDR3_DQ[0] K23 inout SSTL-15 Class I
HPS_DDR3_DQ[1] K22 inout SSTL-15 Class I
HPS_DDR3_DQ[2] H30 inout SSTL-15 Class I
HPS_DDR3_DQ[3] G28 inout SSTL-15 Class I
HPS_DDR3_DQ[4] L25 inout SSTL-15 Class I
HPS_DDR3_DQ[5] L24 inout SSTL-15 Class I
HPS_DDR3_DQ[6] J30 inout SSTL-15 Class I
HPS_DDR3_DQ[7] J29 inout SSTL-15 Class I
HPS_DDR3_DQ[8] K26 inout SSTL-15 Class I
HPS_DDR3_DQ[9] L26 inout SSTL-15 Class I
HPS_DDR3_DQ[10] K29 inout SSTL-15 Class I
HPS_DDR3_DQ[11] K27 inout SSTL-15 Class I
HPS_DDR3_DQ[12] M26 inout SSTL-15 Class I
HPS_DDR3_DQ[13] M27 inout SSTL-15 Class I
HPS_DDR3_DQ[14] L28 inout SSTL-15 Class I
HPS_DDR3_DQ[15] M30 inout SSTL-15 Class I
HPS_DDR3_DQ[16] U26 inout SSTL-15 Class I
HPS_DDR3_DQ[17] T26 inout SSTL-15 Class I
HPS_DDR3_DQ[18] N29 inout SSTL-15 Class I
HPS_DDR3_DQ[19] N28 inout SSTL-15 Class I
HPS_DDR3_DQ[20] P26 inout SSTL-15 Class I
HPS_DDR3_DQ[21] P27 inout SSTL-15 Class I
HPS_DDR3_DQ[22] N27 inout SSTL-15 Class I
HPS_DDR3_DQ[23] R29 inout SSTL-15 Class I
HPS_DDR3_DQ[24] P24 inout SSTL-15 Class I
HPS_DDR3_DQ[25] P25 inout SSTL-15 Class I
HPS_DDR3_DQ[26] T29 inout SSTL-15 Class I
HPS_DDR3_DQ[27] T28 inout SSTL-15 Class I
HPS_DDR3_DQ[28] R27 inout SSTL-15 Class I
HPS_DDR3_DQ[29] R26 inout SSTL-15 Class I
HPS_DDR3_DQ[30] V30 inout SSTL-15 Class I
HPS_DDR3_DQ[31] W29 inout SSTL-15 Class I
HPS_DDR3_DQS_N[0] M19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[1] N24 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[2] R18 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_N[3] R21 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[0] N18 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[1] N25 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[2] R19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_P[3] R22 inout Differential 1.5-V SSTL Class I
HPS_DDR3_ODT H28 output SSTL-15 Class I
HPS_DDR3_RAS_N D30 output SSTL-15 Class I
HPS_DDR3_RESET_N P30 output SSTL-15 Class I
HPS_DDR3_RZQ D27 input 1.5 V
HPS_DDR3_WE_N C28 output SSTL-15 Class I
HPS_ENET_GTX_CLK H19 output 3.3-V LVTTL
HPS_ENET_INT_N C19 inout 3.3-V LVTTL
HPS_ENET_MDC B21 output 3.3-V LVTTL
HPS_ENET_MDIO E21 inout 3.3-V LVTTL
HPS_ENET_RX_CLK G20 input 3.3-V LVTTL
HPS_ENET_RX_DATA[0] A21 input 3.3-V LVTTL
HPS_ENET_RX_DATA[1] B20 input 3.3-V LVTTL
HPS_ENET_RX_DATA[2] B18 input 3.3-V LVTTL
HPS_ENET_RX_DATA[3] D21 input 3.3-V LVTTL
HPS_ENET_RX_DV K17 input 3.3-V LVTTL
HPS_ENET_TX_DATA[0] F20 output 3.3-V LVTTL
HPS_ENET_TX_DATA[1] J19 output 3.3-V LVTTL
HPS_ENET_TX_DATA[2] F21 output 3.3-V LVTTL
HPS_ENET_TX_DATA[3] F19 output 3.3-V LVTTL
HPS_ENET_TX_EN A20 output 3.3-V LVTTL
HPS_FLASH_DATA[0] C20 inout 3.3-V LVTTL
HPS_FLASH_DATA[1] H18 inout 3.3-V LVTTL
HPS_FLASH_DATA[2] A19 inout 3.3-V LVTTL
HPS_FLASH_DATA[3] E19 inout 3.3-V LVTTL
HPS_FLASH_DCLK D19 output 3.3-V LVTTL
HPS_FLASH_NCSO A18 output 3.3-V LVTTL
HPS_GSENSOR_INT B22 inout 3.3-V LVTTL
HPS_I2C1_SCLK E23 inout 3.3-V LVTTL
HPS_I2C1_SDAT C24 inout 3.3-V LVTTL
HPS_I2C2_SCLK H23 inout 3.3-V LVTTL
HPS_I2C2_SDAT A25 inout 3.3-V LVTTL
HPS_I2C_CONTROL B26 inout 3.3-V LVTTL
HPS_KEY G21 inout 3.3-V LVTTL
HPS_LCM_BK B17 inout 3.3-V LVTTL
HPS_LCM_D_C C18 inout 3.3-V LVTTL
HPS_LCM_RST_N E17 inout 3.3-V LVTTL
HPS_LCM_SPIM_CLK A23 input 3.3-V LVTTL
HPS_LCM_SPIM_MOSI C22 output 3.3-V LVTTL
HPS_LCM_SPIM_SS H20 output 3.3-V LVTTL
HPS_LED A24 inout 3.3-V LVTTL
HPS_LTC_GPIO H17 inout 3.3-V LVTTL
HPS_RESET_N F23 inout 3.3-V LVTTL
HPS_SD_CLK A16 output 3.3-V LVTTL
HPS_SD_CMD F18 inout 3.3-V LVTTL
HPS_SD_DATA[0] G18 inout 3.3-V LVTTL
HPS_SD_DATA[1] C17 inout 3.3-V LVTTL
HPS_SD_DATA[2] D17 inout 3.3-V LVTTL
HPS_SD_DATA[3] B16 inout 3.3-V LVTTL
HPS_SPIM_CLK C23 output 3.3-V LVTTL
HPS_SPIM_MISO E24 input 3.3-V LVTTL
HPS_SPIM_MOSI D22 output 3.3-V LVTTL
HPS_SPIM_SS D24 output 3.3-V LVTTL
HPS_UART_RX B25 input 3.3-V LVTTL
HPS_UART_TX C25 output 3.3-V LVTTL
HPS_USB_CLKOUT N16 input 3.3-V LVTTL
HPS_USB_DATA[0] E16 inout 3.3-V LVTTL
HPS_USB_DATA[1] G16 inout 3.3-V LVTTL
HPS_USB_DATA[2] D16 inout 3.3-V LVTTL
HPS_USB_DATA[3] D14 inout 3.3-V LVTTL
HPS_USB_DATA[4] A15 inout 3.3-V LVTTL
HPS_USB_DATA[5] C14 inout 3.3-V LVTTL
HPS_USB_DATA[6] D15 inout 3.3-V LVTTL
HPS_USB_DATA[7] M17 inout 3.3-V LVTTL
HPS_USB_DIR E14 input 3.3-V LVTTL
HPS_USB_NXT A14 input 3.3-V LVTTL
HPS_USB_STP C15 output 3.3-V LVTTL