DE10_Standard_VIP_Qsys

2017.02.06.09:18:49 Datasheet
Overview
  clk_50  DE10_Standard_VIP_Qsys

All Components
   sdram altera_avalon_new_sdram_controller 16.1
Memory Map
alt_vip_cl_vfb_0
 mem_master_wr  mem_master_rd
  sdram
s1  0x00000000 0x00000000

alt_vip_cl_cps_0

alt_vip_cl_cps v16.1
alt_vip_cl_cvi_0 dout_0   alt_vip_cl_cps_0
  din_0
pll_0 outclk1  
  main_clock
clk_50 clk_reset  
  main_reset
dout_0   alt_vip_cl_dil_0
  din


Parameters

BITS_PER_SYMBOL 8
NUMBER_OF_INPUTS 1
NUMBER_OF_OUTPUTS 1
INPUT_0_FIFO 0
INPUT_0_FIFO_SIZE 128
INPUT_0_NUMBER_OF_COLOR_PLANES 2
INPUT_0_COLOR_PLANES_ARE_IN_PARALLEL 0
INPUT_0_PIXELS_IN_PARALLEL 1
INPUT_0_TWO_PIXELS_PATTERN 0
INPUT_0_PATTERN C,Y
INPUT_1_FIFO 0
INPUT_1_FIFO_SIZE 8
INPUT_1_NUMBER_OF_COLOR_PLANES 3
INPUT_1_COLOR_PLANES_ARE_IN_PARALLEL 1
INPUT_1_PIXELS_IN_PARALLEL 1
INPUT_1_TWO_PIXELS_PATTERN 0
INPUT_1_PATTERN C0,C1,C2
OUTPUT_0_FIFO 0
OUTPUT_0_FIFO_SIZE 128
OUTPUT_0_NUMBER_OF_COLOR_PLANES 2
OUTPUT_0_COLOR_PLANES_ARE_IN_PARALLEL 1
OUTPUT_0_PIXELS_IN_PARALLEL 1
OUTPUT_0_TWO_PIXELS_PATTERN 0
OUTPUT_0_PATTERN C,Y
OUTPUT_1_FIFO 0
OUTPUT_1_FIFO_SIZE 8
OUTPUT_1_NUMBER_OF_COLOR_PLANES 3
OUTPUT_1_COLOR_PLANES_ARE_IN_PARALLEL 1
OUTPUT_1_PIXELS_IN_PARALLEL 1
OUTPUT_1_TWO_PIXELS_PATTERN 0
OUTPUT_1_PATTERN C0,C1,C2
USER_PACKET_SUPPORT PASSTHROUGH
USER_PKT_0_TO_0 1
USER_PKT_1_TO_0 0
USER_PKT_0_TO_1 0
USER_PKT_1_TO_1 1
EXTRA_PIPELINING 0
INPUT_VALIDATION 1
OUTPUT_VALIDATION 1
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cl_crs_0

alt_vip_cl_crs v16.1
alt_vip_cl_vfb_0 dout   alt_vip_cl_crs_0
  din
pll_0 outclk1  
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_csc_0
  din


Parameters

SHOW_HIDDEN_FEATURES 0
BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 2
COLOR_PLANES_ARE_IN_PARALLEL 1
PIXELS_IN_PARALLEL 1
PIP_IN 1
PIP_OUT 1
MAX_WIDTH 720
MAX_HEIGHT 480
HORIZ_ALGORITHM NEAREST_NEIGHBOUR
HORIZ_CO_SITING LEFT
HORIZ_ENABLE_LUMA_ADAPT 0
VERT_ALGORITHM BILINEAR
VERT_CO_SITING TOP
VERT_ENABLE_LUMA_ADAPT 0
VARIABLE_SIDE NEITHER
ENABLE_444_IN 0
ENABLE_422_IN 1
ENABLE_420_IN 0
ENABLE_444_OUT 1
ENABLE_422_OUT 0
ENABLE_420_OUT 0
USER_PACKET_SUPPORT PASSTHROUGH
USER_PACKET_FIFO_DEPTH 0
PIPELINE_READY 0
LIMITED_READBACK 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cl_csc_0

alt_vip_cl_csc v16.1
alt_vip_cl_crs_0 dout   alt_vip_cl_csc_0
  din
pll_0 outclk1  
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_scl_0
  din


Parameters

INPUT_BITS_PER_SYMBOL 8
OUTPUT_BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 3
COLOR_PLANES_ARE_IN_PARALLEL 1
PIXELS_IN_PARALLEL 1
REQ_FCOEFF_A0 2.018
REQ_FCOEFF_A1 -0.391
REQ_FCOEFF_A2 0.0
REQ_FCOEFF_B0 0.0
REQ_FCOEFF_B1 -0.813
REQ_FCOEFF_B2 1.596
REQ_FCOEFF_C0 1.164
REQ_FCOEFF_C1 1.164
REQ_FCOEFF_C2 1.164
REQ_FCOEFF_S0 -276.928
REQ_FCOEFF_S1 135.488
REQ_FCOEFF_S2 -222.912
INPUT_DATA_TYPE_SIGNED 0
INPUT_DATA_TYPE_GUARD_BAND 1
INPUT_DATA_TYPE_MIN 16
INPUT_DATA_TYPE_MAX 240
OUTPUT_DATA_TYPE_SIGNED 0
OUTPUT_DATA_TYPE_GUARD_BAND 0
OUTPUT_DATA_TYPE_MIN 0
OUTPUT_DATA_TYPE_MAX 255
COEFFICIENT_SIGNED 1
COEFFICIENT_INT_BITS 2
SUMMAND_SIGNED 1
SUMMAND_INT_BITS 9
COEF_SUM_FRACTION_BITS 8
MOVE_BINARY_POINT_RIGHT 0
REMOVE_FRACTION_METHOD 1
SIGN_TO_UNSIGN_METHOD 0
PIPELINE_DATA_OUTPUT 0
USER_PACKET_SUPPORT PASSTHROUGH
CONVERSION_MODE LSB
RUNTIME_CONTROL 0
LIMITED_READBACK 0
FAMILY CYCLONEV
COEFFICIENT_A0 0
COEFFICIENT_A1 0
COEFFICIENT_A2 0
COEFFICIENT_B0 0
COEFFICIENT_B1 0
COEFFICIENT_B2 0
COEFFICIENT_C0 0
COEFFICIENT_C1 0
COEFFICIENT_C2 0
COEFFICIENT_S0 0
COEFFICIENT_S1 0
COEFFICIENT_S2 0
min_output_s1 0.0
max_output_s1 0.0
min_output_s2 0.0
max_output_s2 0.0
min_output_s3 0
max_output_s3 0
min_output_s4 0
max_output_s4 0
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cl_cvi_0

alt_vip_cl_cvi v16.1
pll_0 outclk1   alt_vip_cl_cvi_0
  main_clock
clk_50 clk_reset  
  main_reset
dout_0   alt_vip_cl_cps_0
  din_0


Parameters

BPS 8
NUMBER_OF_COLOUR_PLANES 2
COLOUR_PLANES_ARE_IN_PARALLEL 0
PIXELS_IN_PARALLEL 1
SYNC_TO 0
NO_OF_CHANNELS 1
MATCH_CTRLDATA_PKT_CLIP_BASIC 0
MATCH_CTRLDATA_PKT_PAD_ADV 0
OVERFLOW_HANDLING 0
USE_EMBEDDED_SYNCS 1
USE_HDMI_DEPRICATION 0
ACCEPT_COLOURS_IN_SEQ 0
GENERATE_VID_F 0
USE_STD 0
STD_WIDTH 1
GENERATE_ANC 0
ANC_DEPTH 1
EXTRACT_TOTAL_RESOLUTION 1
INTERLACED 1
H_ACTIVE_PIXELS_F0 720
V_ACTIVE_LINES_F0 288
V_ACTIVE_LINES_F1 288
FIFO_DEPTH 2048
CLOCKS_ARE_SAME 0
USE_CONTROL 0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cl_dil_0

alt_vip_cl_dil v16.1
alt_vip_cl_cps_0 dout_0   alt_vip_cl_dil_0
  din
pll_0 outclk1  
  av_st_clock
clk_50 clk_reset  
  av_st_reset
dout   alt_vip_clip_1
  din


Parameters

FAMILY CYCLONEV
MAX_WIDTH 720
MAX_HEIGHT 576
USER_PACKET_SUPPORT PASSTHROUGH
USER_PACKET_FIFO_DEPTH 0
PIXELS_IN_PARALLEL 1
BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 2
COLOR_PLANES_ARE_IN_PARALLEL 1
IS_422 1
IS_YCBCR 1
DEINTERLACE_ALGORITHM BOB
MOTION_BLEED 1
RUNTIME_CONTROL 0
MOTION_BPS 7
FIELD_LATENCY 0
BOB_BEHAVIOUR FRAME_FOR_FIELD
DISABLE_EMBEDDED_STREAM_CLEANER 0
ENABLE_422_PROCESSING_FOR_INTERLACED_VIDEO 1
CADENCE_DETECTION 0
CADENCE_ALGORITHM_NAME CADENCE_32_22_VOF
CLOCKS_ARE_SEPARATE 0
MEM_PORT_WIDTH 256
WRITE_MASTER_FIFO_DEPTH 64
WRITE_MASTER_BURST_TARGET 32
EDI_READ_MASTER_FIFO_DEPTH 64
EDI_READ_MASTER_BURST_TARGET 32
MA_READ_MASTER_FIFO_DEPTH 64
MA_READ_MASTER_BURST_TARGET 32
MOTION_WRITE_MASTER_FIFO_DEPTH 64
MOTION_WRITE_MASTER_BURST_TARGET 32
MOTION_READ_MASTER_FIFO_DEPTH 64
MOTION_READ_MASTER_BURST_TARGET 32
MEM_BASE_ADDR 0
MEM_TOP_ADDR 3244032
USER_PACKETS_MAX_STORAGE 0
MAX_SYMBOLS_PER_PACKET 10
LINE_BUFFER_SIZE 2048
FIELD_BUFFER_SIZE_IN_BYTES 589824
MOTION_LINE_BUFFER_SIZE 3072
MOTION_BUFFER_SIZE_IN_BYTES 884736
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cl_vfb_0

alt_vip_cl_vfb v16.1
alt_vip_clip_1 dout   alt_vip_cl_vfb_0
  din
pll_0 outclk1  
  main_clock
outclk1  
  mem_clock
clk_50 clk_reset  
  main_reset
clk_reset  
  mem_reset
mem_master_rd   sdram
  s1
mem_master_wr  
  s1
dout   alt_vip_cl_crs_0
  din


Parameters

BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 2
COLOR_PLANES_ARE_IN_PARALLEL 1
PIXELS_IN_PARALLEL 1
READY_LATENCY 1
MAX_WIDTH 720
MAX_HEIGHT 480
CLOCKS_ARE_SEPARATE 1
MEM_PORT_WIDTH 32
MEM_BASE_ADDR 0
USE_BUFFER_OFFSET 0
MEM_BUFFER_OFFSET 16777216
BURST_ALIGNMENT 1
WRITE_FIFO_DEPTH 512
WRITE_BURST_TARGET 64
READ_FIFO_DEPTH 512
READ_BURST_TARGET 64
WRITER_RUNTIME_CONTROL 0
READER_RUNTIME_CONTROL 0
IS_FRAME_WRITER 0
IS_FRAME_READER 0
DROP_FRAMES 1
REPEAT_FRAMES 1
DROP_REPEAT_USER 1
INTERLACED_SUPPORT 0
CONTROLLED_DROP_REPEAT 0
DROP_INVALID_FIELDS 1
MULTI_FRAME_DELAY 1
IS_SYNC_MASTER 0
IS_SYNC_SLAVE 0
USER_PACKETS_MAX_STORAGE 0
MAX_SYMBOLS_PER_PACKET 10
TEST_INIT 0
ANC_BUFFER_LENGTH 256
ACTUAL_MAX_SYM_ANC_PACKET 10
FRAME_BUFFER_LENGTH 691200
NUM_BUFFERS 3
FAMILY CYCLONEV
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_clip_1

alt_vip_cl_clp v16.1
alt_vip_cl_dil_0 dout   alt_vip_clip_1
  din
pll_0 outclk1  
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_cl_vfb_0
  din


Parameters

BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 2
COLOR_PLANES_ARE_IN_PARALLEL 1
PIXELS_IN_PARALLEL 1
MAX_IN_WIDTH 720
MAX_IN_HEIGHT 576
CLIPPING_METHOD RECTANGLE
LEFT_OFFSET 0
RIGHT_OFFSET 10
TOP_OFFSET 24
BOTTOM_OFFSET 10
RECTANGLE_WIDTH 720
RECTANGLE_HEIGHT 480
EXTRA_PIPELINING 0
USER_PACKET_SUPPORT PASSTHROUGH
USER_PACKET_FIFO_DEPTH 0
RUNTIME_CONTROL 0
LIMITED_READBACK 0
FAMILY CYCLONEV
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_itc_0

alt_vip_itc v14.0
alt_vip_scl_0 dout   alt_vip_itc_0
  din
pll_0 outclk1  
  is_clk_rst
clk_50 clk_reset  
  is_clk_rst_reset


Parameters

FAMILY CYCLONEV
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
BPS 8
INTERLACED 0
H_ACTIVE_PIXELS 640
V_ACTIVE_LINES 480
ACCEPT_COLOURS_IN_SEQ 0
FIFO_DEPTH 1280
CLOCKS_ARE_SAME 0
USE_CONTROL 0
NO_OF_MODES 1
THRESHOLD 639
STD_WIDTH 1
GENERATE_SYNC 0
USE_EMBEDDED_SYNCS 0
AP_LINE 0
V_BLANK 0
H_BLANK 0
H_SYNC_LENGTH 96
H_FRONT_PORCH 16
H_BACK_PORCH 48
V_SYNC_LENGTH 2
V_FRONT_PORCH 10
V_BACK_PORCH 33
F_RISING_EDGE 0
F_FALLING_EDGE 0
FIELD0_V_RISING_EDGE 0
FIELD0_V_BLANK 0
FIELD0_V_SYNC_LENGTH 0
FIELD0_V_FRONT_PORCH 0
FIELD0_V_BACK_PORCH 0
ANC_LINE 0
FIELD0_ANC_LINE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_scl_0

alt_vip_cl_scl v16.1
alt_vip_cl_csc_0 dout   alt_vip_scl_0
  din
pll_0 outclk1  
  main_clock
clk_50 clk_reset  
  main_reset
dout   alt_vip_itc_0
  din


Parameters

SYMBOLS_IN_SEQ 1
SYMBOLS_IN_PAR 3
BITS_PER_SYMBOL 8
PIXELS_IN_PARALLEL 1
EXTRA_PIPELINING 0
IS_422 0
NO_BLANKING 0
MAX_IN_WIDTH 720
MAX_IN_HEIGHT 480
MAX_OUT_WIDTH 640
MAX_OUT_HEIGHT 480
RUNTIME_CONTROL 0
ALGORITHM_NAME BILINEAR
DEFAULT_EDGE_THRESH 7
ARE_IDENTICAL 0
V_TAPS 8
V_PHASES 16
H_TAPS 8
H_PHASES 16
V_SIGNED 1
V_INTEGER_BITS 1
V_FRACTION_BITS 7
H_SIGNED 1
H_INTEGER_BITS 1
H_FRACTION_BITS 7
PRESERVE_BITS 0
LOAD_AT_RUNTIME 0
V_BANKS 1
V_FUNCTION LANCZOS_2
V_COEFF_FILE <enter file name (including full path)>
H_BANKS 1
H_FUNCTION LANCZOS_2
H_COEFF_FILE <enter file name (including full path)>
USER_PACKET_SUPPORT PASSTHROUGH
USER_PACKET_FIFO_DEPTH 0
LIMITED_READBACK 0
IS_420 0
ALWAYS_DOWNSCALE 0
DEFAULT_UPPER_BLUR 15
DEFAULT_LOWER_BLUR 0
ENABLE_FIR 0
V_SYMMETRIC 0
H_SYMMETRIC 0
FAMILY CYCLONEV
AUTO_DEVICE 5CSXFC6D6F31C6
AUTO_DEVICE_SPEEDGRADE 6_H6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

clk_50

clock_source v16.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

pll_0

altera_pll v16.1
clk_50 clk   pll_0
  refclk
clk_reset  
  reset
outclk1   alt_vip_cl_dil_0
  av_st_clock
outclk1   sdram
  clk
outclk1   alt_vip_itc_0
  is_clk_rst
outclk1   alt_vip_cl_cvi_0
  main_clock
outclk1   alt_vip_cl_cps_0
  main_clock
outclk1   alt_vip_clip_1
  main_clock
outclk1   alt_vip_cl_vfb_0
  main_clock
outclk1  
  mem_clock
outclk1   alt_vip_cl_crs_0
  main_clock
outclk1   alt_vip_cl_csc_0
  main_clock
outclk1   alt_vip_scl_0
  main_clock


Parameters

debug_print_output false
debug_use_rbc_taf_method false
device_family CYCLONEV
device 5CSXFC6D6F31C6
gui_device_speed_grade 1
gui_pll_mode Integer-N PLL
fractional_vco_multiplier false
gui_reference_clock_frequency 50.0
reference_clock_frequency 50.0 MHz
gui_channel_spacing 0.0
gui_operation_mode direct
gui_feedback_clock Global Clock
gui_fractional_cout 32
pll_fractional_cout 32
gui_dsm_out_sel 1st_order
pll_dsm_out_sel 1st_order
operation_mode direct
gui_use_locked true
gui_en_adv_params false
gui_number_of_clocks 4
number_of_clocks 4
number_of_cascade_counters 0
gui_multiply_factor 1
gui_frac_multiply_factor 1
gui_divide_factor_n 1
gui_cascade_counter0 false
gui_output_clock_frequency0 100.0
gui_divide_factor_c0 1
gui_actual_multiply_factor0 22
gui_actual_frac_multiply_factor0 1
gui_actual_divide_factor0 11
gui_actual_output_clock_frequency0 0 MHz
gui_ps_units0 ps
gui_phase_shift0 -4000
gui_phase_shift_deg0 0.0
gui_actual_phase_shift0 0
gui_duty_cycle0 50
gui_cascade_counter1 false
gui_output_clock_frequency1 100.0
gui_divide_factor_c1 1
gui_actual_multiply_factor1 22
gui_actual_frac_multiply_factor1 1
gui_actual_divide_factor1 11
gui_actual_output_clock_frequency1 0 MHz
gui_ps_units1 ps
gui_phase_shift1 0
gui_phase_shift_deg1 0.0
gui_actual_phase_shift1 0
gui_duty_cycle1 50
gui_cascade_counter2 false
gui_output_clock_frequency2 25.0
gui_divide_factor_c2 1
gui_actual_multiply_factor2 22
gui_actual_frac_multiply_factor2 1
gui_actual_divide_factor2 44
gui_actual_output_clock_frequency2 0 MHz
gui_ps_units2 ps
gui_phase_shift2 0
gui_phase_shift_deg2 0.0
gui_actual_phase_shift2 0
gui_duty_cycle2 50
gui_cascade_counter3 false
gui_output_clock_frequency3 18.342
gui_divide_factor_c3 1
gui_actual_multiply_factor3 22
gui_actual_frac_multiply_factor3 1
gui_actual_divide_factor3 60
gui_actual_output_clock_frequency3 0 MHz
gui_ps_units3 ps
gui_phase_shift3 0
gui_phase_shift_deg3 0.0
gui_actual_phase_shift3 0
gui_duty_cycle3 50
gui_cascade_counter4 false
gui_output_clock_frequency4 100.0
gui_divide_factor_c4 1
gui_actual_multiply_factor4 1
gui_actual_frac_multiply_factor4 1
gui_actual_divide_factor4 1
gui_actual_output_clock_frequency4 0 MHz
gui_ps_units4 ps
gui_phase_shift4 0
gui_phase_shift_deg4 0.0
gui_actual_phase_shift4 0
gui_duty_cycle4 50
gui_cascade_counter5 false
gui_output_clock_frequency5 100.0
gui_divide_factor_c5 1
gui_actual_multiply_factor5 1
gui_actual_frac_multiply_factor5 1
gui_actual_divide_factor5 1
gui_actual_output_clock_frequency5 0 MHz
gui_ps_units5 ps
gui_phase_shift5 0
gui_phase_shift_deg5 0.0
gui_actual_phase_shift5 0
gui_duty_cycle5 50
gui_cascade_counter6 false
gui_output_clock_frequency6 100.0
gui_divide_factor_c6 1
gui_actual_multiply_factor6 1
gui_actual_frac_multiply_factor6 1
gui_actual_divide_factor6 1
gui_actual_output_clock_frequency6 0 MHz
gui_ps_units6 ps
gui_phase_shift6 0
gui_phase_shift_deg6 0.0
gui_actual_phase_shift6 0
gui_duty_cycle6 50
gui_cascade_counter7 false
gui_output_clock_frequency7 100.0
gui_divide_factor_c7 1
gui_actual_multiply_factor7 1
gui_actual_frac_multiply_factor7 1
gui_actual_divide_factor7 1
gui_actual_output_clock_frequency7 0 MHz
gui_ps_units7 ps
gui_phase_shift7 0
gui_phase_shift_deg7 0.0
gui_actual_phase_shift7 0
gui_duty_cycle7 50
gui_cascade_counter8 false
gui_output_clock_frequency8 100.0
gui_divide_factor_c8 1
gui_actual_multiply_factor8 1
gui_actual_frac_multiply_factor8 1
gui_actual_divide_factor8 1
gui_actual_output_clock_frequency8 0 MHz
gui_ps_units8 ps
gui_phase_shift8 0
gui_phase_shift_deg8 0.0
gui_actual_phase_shift8 0
gui_duty_cycle8 50
gui_cascade_counter9 false
gui_output_clock_frequency9 100.0
gui_divide_factor_c9 1
gui_actual_multiply_factor9 1
gui_actual_frac_multiply_factor9 1
gui_actual_divide_factor9 1
gui_actual_output_clock_frequency9 0 MHz
gui_ps_units9 ps
gui_phase_shift9 0
gui_phase_shift_deg9 0.0
gui_actual_phase_shift9 0
gui_duty_cycle9 50
gui_cascade_counter10 false
gui_output_clock_frequency10 100.0
gui_divide_factor_c10 1
gui_actual_multiply_factor10 1
gui_actual_frac_multiply_factor10 1
gui_actual_divide_factor10 1
gui_actual_output_clock_frequency10 0 MHz
gui_ps_units10 ps
gui_phase_shift10 0
gui_phase_shift_deg10 0.0
gui_actual_phase_shift10 0
gui_duty_cycle10 50
gui_cascade_counter11 false
gui_output_clock_frequency11 100.0
gui_divide_factor_c11 1
gui_actual_multiply_factor11 1
gui_actual_frac_multiply_factor11 1
gui_actual_divide_factor11 1
gui_actual_output_clock_frequency11 0 MHz
gui_ps_units11 ps
gui_phase_shift11 0
gui_phase_shift_deg11 0.0
gui_actual_phase_shift11 0
gui_duty_cycle11 50
gui_cascade_counter12 false
gui_output_clock_frequency12 100.0
gui_divide_factor_c12 1
gui_actual_multiply_factor12 1
gui_actual_frac_multiply_factor12 1
gui_actual_divide_factor12 1
gui_actual_output_clock_frequency12 0 MHz
gui_ps_units12 ps
gui_phase_shift12 0
gui_phase_shift_deg12 0.0
gui_actual_phase_shift12 0
gui_duty_cycle12 50
gui_cascade_counter13 false
gui_output_clock_frequency13 100.0
gui_divide_factor_c13 1
gui_actual_multiply_factor13 1
gui_actual_frac_multiply_factor13 1
gui_actual_divide_factor13 1
gui_actual_output_clock_frequency13 0 MHz
gui_ps_units13 ps
gui_phase_shift13 0
gui_phase_shift_deg13 0.0
gui_actual_phase_shift13 0
gui_duty_cycle13 50
gui_cascade_counter14 false
gui_output_clock_frequency14 100.0
gui_divide_factor_c14 1
gui_actual_multiply_factor14 1
gui_actual_frac_multiply_factor14 1
gui_actual_divide_factor14 1
gui_actual_output_clock_frequency14 0 MHz
gui_ps_units14 ps
gui_phase_shift14 0
gui_phase_shift_deg14 0.0
gui_actual_phase_shift14 0
gui_duty_cycle14 50
gui_cascade_counter15 false
gui_output_clock_frequency15 100.0
gui_divide_factor_c15 1
gui_actual_multiply_factor15 1
gui_actual_frac_multiply_factor15 1
gui_actual_divide_factor15 1
gui_actual_output_clock_frequency15 0 MHz
gui_ps_units15 ps
gui_phase_shift15 0
gui_phase_shift_deg15 0.0
gui_actual_phase_shift15 0
gui_duty_cycle15 50
gui_cascade_counter16 false
gui_output_clock_frequency16 100.0
gui_divide_factor_c16 1
gui_actual_multiply_factor16 1
gui_actual_frac_multiply_factor16 1
gui_actual_divide_factor16 1
gui_actual_output_clock_frequency16 0 MHz
gui_ps_units16 ps
gui_phase_shift16 0
gui_phase_shift_deg16 0.0
gui_actual_phase_shift16 0
gui_duty_cycle16 50
gui_cascade_counter17 false
gui_output_clock_frequency17 100.0
gui_divide_factor_c17 1
gui_actual_multiply_factor17 1
gui_actual_frac_multiply_factor17 1
gui_actual_divide_factor17 1
gui_actual_output_clock_frequency17 0 MHz
gui_ps_units17 ps
gui_phase_shift17 0
gui_phase_shift_deg17 0.0
gui_actual_phase_shift17 0
gui_duty_cycle17 50
output_clock_frequency0 100.000000 MHz
phase_shift0 -3977 ps
duty_cycle0 50
output_clock_frequency1 100.000000 MHz
phase_shift1 0 ps
duty_cycle1 50
output_clock_frequency2 25.000000 MHz
phase_shift2 0 ps
duty_cycle2 50
output_clock_frequency3 18.333333 MHz
phase_shift3 0 ps
duty_cycle3 50
output_clock_frequency4 0 MHz
phase_shift4 0 ps
duty_cycle4 50
output_clock_frequency5 0 MHz
phase_shift5 0 ps
duty_cycle5 50
output_clock_frequency6 0 MHz
phase_shift6 0 ps
duty_cycle6 50
output_clock_frequency7 0 MHz
phase_shift7 0 ps
duty_cycle7 50
output_clock_frequency8 0 MHz
phase_shift8 0 ps
duty_cycle8 50
output_clock_frequency9 0 MHz
phase_shift9 0 ps
duty_cycle9 50
output_clock_frequency10 0 MHz
phase_shift10 0 ps
duty_cycle10 50
output_clock_frequency11 0 MHz
phase_shift11 0 ps
duty_cycle11 50
output_clock_frequency12 0 MHz
phase_shift12 0 ps
duty_cycle12 50
output_clock_frequency13 0 MHz
phase_shift13 0 ps
duty_cycle13 50
output_clock_frequency14 0 MHz
phase_shift14 0 ps
duty_cycle14 50
output_clock_frequency15 0 MHz
phase_shift15 0 ps
duty_cycle15 50
output_clock_frequency16 0 MHz
phase_shift16 0 ps
duty_cycle16 50
output_clock_frequency17 0 MHz
phase_shift17 0 ps
duty_cycle17 50
gui_pll_auto_reset Off
gui_pll_bandwidth_preset Auto
gui_en_reconf false
gui_en_dps_ports false
gui_en_phout_ports false
gui_phout_division 1
pll_vcoph_div 1
pll_type General
pll_subtype General
m_cnt_hi_div 11
m_cnt_lo_div 11
n_cnt_hi_div 256
n_cnt_lo_div 256
m_cnt_bypass_en false
n_cnt_bypass_en true
m_cnt_odd_div_duty_en false
n_cnt_odd_div_duty_en false
c_cnt_hi_div0 6
c_cnt_lo_div0 5
c_cnt_prst0 7
c_cnt_ph_mux_prst0 5
c_cnt_in_src0 ph_mux_clk
c_cnt_bypass_en0 false
c_cnt_odd_div_duty_en0 true
c_cnt_hi_div1 6
c_cnt_lo_div1 5
c_cnt_prst1 1
c_cnt_ph_mux_prst1 0
c_cnt_in_src1 ph_mux_clk
c_cnt_bypass_en1 false
c_cnt_odd_div_duty_en1 true
c_cnt_hi_div2 22
c_cnt_lo_div2 22
c_cnt_prst2 1
c_cnt_ph_mux_prst2 0
c_cnt_in_src2 ph_mux_clk
c_cnt_bypass_en2 false
c_cnt_odd_div_duty_en2 false
c_cnt_hi_div3 30
c_cnt_lo_div3 30
c_cnt_prst3 1
c_cnt_ph_mux_prst3 0
c_cnt_in_src3 ph_mux_clk
c_cnt_bypass_en3 false
c_cnt_odd_div_duty_en3 false
c_cnt_hi_div4 1
c_cnt_lo_div4 1
c_cnt_prst4 1
c_cnt_ph_mux_prst4 0
c_cnt_in_src4 ph_mux_clk
c_cnt_bypass_en4 true
c_cnt_odd_div_duty_en4 false
c_cnt_hi_div5 1
c_cnt_lo_div5 1
c_cnt_prst5 1
c_cnt_ph_mux_prst5 0
c_cnt_in_src5 ph_mux_clk
c_cnt_bypass_en5 true
c_cnt_odd_div_duty_en5 false
c_cnt_hi_div6 1
c_cnt_lo_div6 1
c_cnt_prst6 1
c_cnt_ph_mux_prst6 0
c_cnt_in_src6 ph_mux_clk
c_cnt_bypass_en6 true
c_cnt_odd_div_duty_en6 false
c_cnt_hi_div7 1
c_cnt_lo_div7 1
c_cnt_prst7 1
c_cnt_ph_mux_prst7 0
c_cnt_in_src7 ph_mux_clk
c_cnt_bypass_en7 true
c_cnt_odd_div_duty_en7 false
c_cnt_hi_div8 1
c_cnt_lo_div8 1
c_cnt_prst8 1
c_cnt_ph_mux_prst8 0
c_cnt_in_src8 ph_mux_clk
c_cnt_bypass_en8 true
c_cnt_odd_div_duty_en8 false
c_cnt_hi_div9 1
c_cnt_lo_div9 1
c_cnt_prst9 1
c_cnt_ph_mux_prst9 0
c_cnt_in_src9 ph_mux_clk
c_cnt_bypass_en9 true
c_cnt_odd_div_duty_en9 false
c_cnt_hi_div10 1
c_cnt_lo_div10 1
c_cnt_prst10 1
c_cnt_ph_mux_prst10 0
c_cnt_in_src10 ph_mux_clk
c_cnt_bypass_en10 true
c_cnt_odd_div_duty_en10 false
c_cnt_hi_div11 1
c_cnt_lo_div11 1
c_cnt_prst11 1
c_cnt_ph_mux_prst11 0
c_cnt_in_src11 ph_mux_clk
c_cnt_bypass_en11 true
c_cnt_odd_div_duty_en11 false
c_cnt_hi_div12 1
c_cnt_lo_div12 1
c_cnt_prst12 1
c_cnt_ph_mux_prst12 0
c_cnt_in_src12 ph_mux_clk
c_cnt_bypass_en12 true
c_cnt_odd_div_duty_en12 false
c_cnt_hi_div13 1
c_cnt_lo_div13 1
c_cnt_prst13 1
c_cnt_ph_mux_prst13 0
c_cnt_in_src13 ph_mux_clk
c_cnt_bypass_en13 true
c_cnt_odd_div_duty_en13 false
c_cnt_hi_div14 1
c_cnt_lo_div14 1
c_cnt_prst14 1
c_cnt_ph_mux_prst14 0
c_cnt_in_src14 ph_mux_clk
c_cnt_bypass_en14 true
c_cnt_odd_div_duty_en14 false
c_cnt_hi_div15 1
c_cnt_lo_div15 1
c_cnt_prst15 1
c_cnt_ph_mux_prst15 0
c_cnt_in_src15 ph_mux_clk
c_cnt_bypass_en15 true
c_cnt_odd_div_duty_en15 false
c_cnt_hi_div16 1
c_cnt_lo_div16 1
c_cnt_prst16 1
c_cnt_ph_mux_prst16 0
c_cnt_in_src16 ph_mux_clk
c_cnt_bypass_en16 true
c_cnt_odd_div_duty_en16 false
c_cnt_hi_div17 1
c_cnt_lo_div17 1
c_cnt_prst17 1
c_cnt_ph_mux_prst17 0
c_cnt_in_src17 ph_mux_clk
c_cnt_bypass_en17 true
c_cnt_odd_div_duty_en17 false
pll_vco_div 1
pll_cp_current 20
pll_bwctrl 4000
pll_output_clk_frequency 1100.0 MHz
pll_fractional_division 1
mimic_fbclk_type none
pll_fbclk_mux_1 glb
pll_fbclk_mux_2 m_cnt
pll_m_cnt_in_src ph_mux_clk
pll_slf_rst false
gui_parameter_list M-Counter Hi Divide,M-Counter Low Divide,N-Counter Hi Divide,N-Counter Low Divide,M-Counter Bypass Enable,N-Counter Bypass Enable,M-Counter Odd Divide Enable,N-Counter Odd Divide Enable,C-Counter-0 Hi Divide,C-Counter-0 Low Divide,C-Counter-0 Coarse Phase Shift,C-Counter-0 VCO Phase Tap,C-Counter-0 Input Source,C-Counter-0 Bypass Enable,C-Counter-0 Odd Divide Enable,C-Counter-1 Hi Divide,C-Counter-1 Low Divide,C-Counter-1 Coarse Phase Shift,C-Counter-1 VCO Phase Tap,C-Counter-1 Input Source,C-Counter-1 Bypass Enable,C-Counter-1 Odd Divide Enable,C-Counter-2 Hi Divide,C-Counter-2 Low Divide,C-Counter-2 Coarse Phase Shift,C-Counter-2 VCO Phase Tap,C-Counter-2 Input Source,C-Counter-2 Bypass Enable,C-Counter-2 Odd Divide Enable,C-Counter-3 Hi Divide,C-Counter-3 Low Divide,C-Counter-3 Coarse Phase Shift,C-Counter-3 VCO Phase Tap,C-Counter-3 Input Source,C-Counter-3 Bypass Enable,C-Counter-3 Odd Divide Enable,VCO Post Divide Counter Enable,Charge Pump current (uA),Loop Filter Bandwidth Resistor (Ohms) ,PLL Output VCO Frequency,K-Fractional Division Value (DSM),Feedback Clock Type,Feedback Clock MUX 1,Feedback Clock MUX 2,M Counter Source MUX,PLL Auto Reset
gui_parameter_values 11,11,256,256,false,true,false,false,6,5,7,5,ph_mux_clk,false,true,6,5,1,0,ph_mux_clk,false,true,22,22,1,0,ph_mux_clk,false,false,30,30,1,0,ph_mux_clk,false,false,1,20,4000,1100.0 MHz,1,none,glb,m_cnt,ph_mux_clk,false
gui_mif_generate false
gui_enable_mif_dps false
gui_dps_cntr C0
gui_dps_num 1
gui_dps_dir Positive
gui_refclk_switch false
gui_refclk1_frequency 100.0
gui_switchover_mode Automatic Switchover
gui_switchover_delay 0
gui_active_clk false
gui_clk_bad false
refclk1_frequency 100.0 MHz
pll_clk_loss_sw_en false
pll_manu_clk_sw_en false
pll_auto_clk_sw_en false
pll_clkin_1_src clk_0
pll_clk_sw_dly 0
gui_enable_cascade_out false
gui_cascade_outclk_index 0
gui_enable_cascade_in false
pll_clkin_0_src clk_0
gui_pll_cascading_mode Create an adjpllin signal to connect with an upstream PLL
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sdram

altera_avalon_new_sdram_controller v16.1
alt_vip_cl_vfb_0 mem_master_rd   sdram
  s1
mem_master_wr  
  s1
pll_0 outclk1  
  clk
clk_50 clk_reset  
  reset


Parameters

TAC 5.5
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
columnWidth 10
dataWidth 16
generateSimulationModel true
initRefreshCommands 2
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
rowWidth 13
masteredTristateBridgeSlave 0
TMRD 3
initNOPDelay 0.0
registerDataIn true
clockRate 100000000
componentName DE10_Standard_VIP_Qsys_sdram
size 67108864
addressWidth 25
bankWidth 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CAS_LATENCY 3
CONTENTS_INFO
INIT_NOP_DELAY 0.0
INIT_REFRESH_COMMANDS 2
IS_INITIALIZED 1
POWERUP_DELAY 100.0
REFRESH_PERIOD 15.625
REGISTER_DATA_IN 1
SDRAM_ADDR_WIDTH 25
SDRAM_BANK_WIDTH 2
SDRAM_COL_WIDTH 10
SDRAM_DATA_WIDTH 16
SDRAM_NUM_BANKS 4
SDRAM_NUM_CHIPSELECTS 1
SDRAM_ROW_WIDTH 13
SHARED_DATA 0
SIM_MODEL_BASE 1
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
T_AC 5.5
T_MRD 3
T_RCD 20.0
T_RFC 70.0
T_RP 20.0
T_WR 14.0
generation took 0.01 seconds rendering took 0.12 seconds