DE2_70_SOPC

generated 2009.06.18.18:59:59

Overview

  clk_50  DE2_70_SOPC
  clk_25 
   pio_green_led
 out_port  
 out_port  
 in_port  
 in_port  
   lcd
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
   sdram_u1
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
   uart
 rxd  
 txd  
 cts_n  
 rts_n  
 out_port  
 bidir_port  
 out_port  
 bidir_port  
 bidir_port  
 bidir_port  
Processor
   cpu Nios II 9.0
Peripherals
   cpu altera_nios2 9.0
   onchip_mem altera_avalon_onchip_memory2 9.0
   pio_green_led altera_avalon_pio 9.0
   pio_red_led altera_avalon_pio 9.0
   pio_switch altera_avalon_pio 9.0
   pio_button altera_avalon_pio 9.0
   lcd altera_avalon_lcd_16207 9.0
   sdram_u1 altera_avalon_new_sdram_controller 9.0
   sdram_u2 altera_avalon_new_sdram_controller 9.0
   tristate_bridge_ssram altera_avalon_tri_state_bridge 9.0
   sysid altera_avalon_sysid 9.0
   timer altera_avalon_timer 9.0
   timer_stamp altera_avalon_timer 9.0
   jtag_uart altera_avalon_jtag_uart 9.0
   uart altera_avalon_uart 9.0
   pll altera_avalon_pll 9.0
   tristate_bridge_flash altera_avalon_tri_state_bridge 9.0
   ISP1362 ISP1362_IF 1.0
   i2c_sclk altera_avalon_pio 9.0
   i2c_sdat altera_avalon_pio 9.0
   sd_clk altera_avalon_pio 9.0
   sd_cmd altera_avalon_pio 9.0
   sd_dat altera_avalon_pio 9.0
   sd_dat3 altera_avalon_pio 9.0
   SEG7 SEG7_IF 1.0
   AUDIO AUDIO_IF 1.0
   VGA VGA_NIOS_CTRL 1.0
   DM9000A DM9000A_IF 1.0
   ps2_mouse altera_up_avalon_ps2 9.0
   ps2_keyboard altera_up_avalon_ps2 9.0
cpu
 instruction_master  data_master
  cpu
jtag_debug_module  0x09608800 0x09608800
  onchip_mem
s1  0x09604000 0x09604000
  pio_green_led
s1  0x09609120
  pio_red_led
s1  0x09609130
  pio_switch
s1  0x09609140
  pio_button
s1  0x09609150
  lcd
control_slave  0x09609160
  sdram_u1
s1  0x04000000 0x04000000
  sdram_u2
s1  0x06000000 0x06000000
  sysid
control_slave  0x096091d0
  timer
s1  0x09609080
  timer_stamp
s1  0x096090a0
  jtag_uart
avalon_jtag_slave  0x096091e8
  uart
s1  0x096090c0
  pll
s1  0x096090e0
  ISP1362
hc  0x096091d8 dc  0x096091e0
  i2c_sclk
s1  0x09609170
  i2c_sdat
s1  0x09609180
  sd_clk
s1  0x09609190
  sd_cmd
s1  0x096091a0
  sd_dat
s1  0x096091b0
  sd_dat3
s1  0x096091c0
  SEG7
s1  0x09609100
  AUDIO
s1  0x09609000
  VGA
s1  0x09400000
  DM9000A
s1  0x09609200
  ps2_mouse
avalon_ps2_slave  0x00000000
  ps2_keyboard
avalon_ps2_slave  0x00000008

clk_50

clock_source v9.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
  

Software Assignments

(none)

cpu

altera_nios2 v9.0
pll c0   cpu
  clk
instruction_master   onchip_mem
  s1
data_master  
  s1
data_master   pio_green_led
  s1
data_master   pio_red_led
  s1
data_master   pio_switch
  s1
data_master   pio_button
  s1
d_irq  
  irq
data_master   lcd
  control_slave
instruction_master   sdram_u1
  s1
data_master  
  s1
instruction_master   sdram_u2
  s1
data_master  
  s1
instruction_master   tristate_bridge_ssram
  avalon_slave
data_master  
  avalon_slave
data_master   sysid
  control_slave
data_master   timer
  s1
d_irq  
  irq
data_master   timer_stamp
  s1
d_irq  
  irq
d_irq   jtag_uart
  irq
data_master  
  avalon_jtag_slave
data_master   uart
  s1
d_irq  
  irq
data_master   pll
  s1
instruction_master   tristate_bridge_flash
  avalon_slave
data_master  
  avalon_slave
d_irq   ISP1362
  hc_irq
data_master  
  hc
d_irq  
  dc_irq
data_master  
  dc
data_master   i2c_sclk
  s1
data_master   i2c_sdat
  s1
data_master   sd_clk
  s1
data_master   sd_cmd
  s1
data_master   sd_dat
  s1
data_master   sd_dat3
  s1
data_master   SEG7
  s1
data_master   AUDIO
  s1
data_master   VGA
  s1
data_master   DM9000A
  s1
d_irq  
  s1_irq
data_master   ps2_mouse
  avalon_ps2_slave
d_irq  
  interrupt
data_master   ps2_keyboard
  avalon_ps2_slave
d_irq  
  interrupt


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSetsPresent false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_numShadowRegisterSets 1
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_eicPresent false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_autoAssignNumShadowRegisterSets true
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave onchip_mem.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _2
mmu_udtlbNumEntries _2
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _10
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_mem.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 100000000
breakSlave cpu.jtag_debug_module
breakOffset 32
  

Software Assignments

CPU_IMPLEMENTATION "fast"
CPU_FREQ 100000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x9604020
RESET_ADDR 0x9604000
BREAK_ADDR 0x9608820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 28
DATA_ADDR_WIDTH 28

onchip_mem

altera_avalon_onchip_memory2 v9.0
cpu instruction_master   onchip_mem
  s1
data_master  
  s1
pll c0  
  clk1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName onchip_mem
instanceID NONE
memorySize 16384
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_mem"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 16384u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

pio_green_led

altera_avalon_pio v9.0
cpu data_master   pio_green_led
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 9
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 9
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

pio_red_led

altera_avalon_pio v9.0
cpu data_master   pio_red_led
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 18
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

pio_switch

altera_avalon_pio v9.0
cpu data_master   pio_switch
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 18
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

pio_button

altera_avalon_pio v9.0
cpu data_master   pio_button
  s1
d_irq  
  irq
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 100000000
direction Input
edgeType RISING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "RISING"
IRQ_TYPE "EDGE"
FREQ 100000000u

lcd

altera_avalon_lcd_16207 v9.0
cpu data_master   lcd
  control_slave
pll c0  
  clk


Parameters

(none)
  

Software Assignments

(none)

sdram_u1

altera_avalon_new_sdram_controller v9.0
cpu instruction_master   sdram_u1
  s1
data_master  
  s1
pll c0  
  clk


Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 100000000
columnWidth 9
dataWidth 16
generateSimulationModel true
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 200.0
refreshPeriod 7.8125
registerDataIn true
rowWidth 13
size 33554432
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 1
SDRAM_DATA_WIDTH 16
SDRAM_ADDR_WIDTH 24
SDRAM_ROW_WIDTH 13
SDRAM_COL_WIDTH 9
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 7.8125
POWERUP_DELAY 200.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

sdram_u2

altera_avalon_new_sdram_controller v9.0
cpu instruction_master   sdram_u2
  s1
data_master  
  s1
pll c0  
  clk


Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 100000000
columnWidth 9
dataWidth 16
generateSimulationModel true
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 200.0
refreshPeriod 7.8125
registerDataIn true
rowWidth 13
size 33554432
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 1
SDRAM_DATA_WIDTH 16
SDRAM_ADDR_WIDTH 24
SDRAM_ROW_WIDTH 13
SDRAM_COL_WIDTH 9
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 7.8125
POWERUP_DELAY 200.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

ssram

altera_avalon_cy7c1380_ssram v9.0
tristate_bridge_ssram tristate_master   ssram
  s1
pll c0  
  clk


Parameters

readLatency 2
sharedPorts
simMakeModel true
size 2
  

Software Assignments

SRAM_MEMORY_SIZE 2
SRAM_MEMORY_UNITS 1048576
SSRAM_DATA_WIDTH 32
SSRAM_READ_LATENCY 2

tristate_bridge_ssram

altera_avalon_tri_state_bridge v9.0
cpu instruction_master   tristate_bridge_ssram
  avalon_slave
data_master  
  avalon_slave
pll c0  
  clk
tristate_master   ssram
  s1


Parameters

registerIncomingSignals true
  

Software Assignments

(none)

cfi_flash

altera_avalon_cfi_flash v9.0
pll c0   cfi_flash
  clk
tristate_bridge_flash tristate_master  
  s1


Parameters

actualHoldTime 0.0
actualSetupTime 0.0
actualWaitTime 100.0
addressWidth 22
clockRate 100000000
corePreset CUSTOM
dataWidth 16
holdTime 0
setupTime 0
sharedPorts
timingUnits NS
waitTime 100
  

Software Assignments

SETUP_VALUE 0
WAIT_VALUE 100
HOLD_VALUE 0
TIMING_UNITS "ns"
SIZE 8388608u

sysid

altera_avalon_sysid v9.0
cpu data_master   sysid
  control_slave
pll c0  
  clk


Parameters

id 1221836186
timestamp 1245322795
  

Software Assignments

ID 1221836186u
TIMESTAMP 1245322795u

timer

altera_avalon_timer v9.0
cpu data_master   timer
  s1
d_irq  
  irq
pll c0  
  clk


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1.0
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 100000000
timeoutPulseOutput false
timerPreset CUSTOM
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1.0
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 100000000u
LOAD_VALUE 99999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

timer_stamp

altera_avalon_timer v9.0
cpu data_master   timer_stamp
  s1
d_irq  
  irq
pll c0  
  clk


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1.0
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 100000000
timeoutPulseOutput false
timerPreset CUSTOM
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1.0
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 100000000u
LOAD_VALUE 99999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

jtag_uart

altera_avalon_jtag_uart v9.0
cpu d_irq   jtag_uart
  irq
data_master  
  avalon_jtag_slave
pll c0  
  clk


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
writeBufferDepth 64
writeIRQThreshold 8
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

uart

altera_avalon_uart v9.0
cpu data_master   uart
  s1
d_irq  
  irq
pll c0  
  clk


Parameters

baud 115200
baudError 0.01
clockRate 100000000
dataBits 8
fixedBaud true
parity NONE
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts true
useEopRegister false
  

Software Assignments

BAUD 115200
DATA_BITS 8
FIXED_BAUD 1
PARITY 'N'
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 1
USE_EOP_REGISTER 0
SIM_TRUE_BAUD 0
SIM_CHAR_STREAM ""
FREQ 100000000u

pll

altera_avalon_pll v9.0
cpu data_master   pll
  s1
clk_50 clk  
  inclk0
c0   cpu
  clk
c0   onchip_mem
  clk1
c0   pio_green_led
  clk
c0   pio_red_led
  clk
c0   pio_switch
  clk
c0   pio_button
  clk
c0   lcd
  clk
c0   sdram_u1
  clk
c0   sdram_u2
  clk
c0   ssram
  clk
c0   cfi_flash
  clk
c0   sysid
  clk
c0   timer
  clk
c0   timer_stamp
  clk
c0   uart
  clk
c0   tristate_bridge_ssram
  clk
c0   tristate_bridge_flash
  clk
c0   ISP1362
  dc_clock
c0  
  hc_clock
c0   i2c_sclk
  clk
c0   i2c_sdat
  clk
c0   sd_clk
  clk
c0   sd_cmd
  clk
c0   sd_dat
  clk
c0   sd_dat3
  clk
c0   SEG7
  s1_clock
c0   jtag_uart
  clk
c0   AUDIO
  s1_clock
c0   VGA
  s1_clock
c0   ps2_mouse
  clock_reset
c0   ps2_keyboard
  clock_reset


Parameters

c0 tap c0 mult 2 div 1 phase 0 enabled true inputfreq 50000000 outputfreq 100000000
c1 tap c1 mult 2 div 1 phase -1806 enabled true inputfreq 50000000 outputfreq 100000000
c2 tap c2 mult 4 div 11 phase 0 enabled true inputfreq 50000000 outputfreq 18181818
c3 tap c3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c4 tap c4 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c5 tap c5 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c6 tap c6 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c7 tap c7 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c8 tap c8 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c9 tap c9 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
deviceFamily CYCLONEII
e0 tap e0 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e1 tap e1 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e2 tap e2 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e3 tap e3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
inputClockFrequency 50000000
inputClockRate 50000000
lockedOutputPortOption Export
pfdenaInputPortOption Register
pllHdl // megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "11" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.0" // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.00010000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "18.32400000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-65.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1806" // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
resetInputPortOption Register
  

Software Assignments

ARESET "None"
PFDENA "None"
LOCKED "None"
PLLENA "None"
SCANCLK "None"
SCANDATA "None"
SCANREAD "None"
SCANWRITE "None"
SCANCLKENA "None"
SCANACLR "None"
SCANDATAOUT "None"
SCANDONE "None"
CONFIGUPDATE "None"
PHASECOUNTERSELECT "None"
PHASEDONE "None"
PHASEUPDOWN "None"
PHASESTEP "None"

tristate_bridge_flash

altera_avalon_tri_state_bridge v9.0
pll c0   tristate_bridge_flash
  clk
cpu instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   cfi_flash
  s1


Parameters

registerIncomingSignals true
  

Software Assignments

(none)

ISP1362

ISP1362_IF v1.0
cpu d_irq   ISP1362
  hc_irq
data_master  
  hc
d_irq  
  dc_irq
data_master  
  dc
pll c0  
  dc_clock
c0  
  hc_clock


Parameters

AUTO_HC_CLOCK_CLOCK_RATE 100000000
AUTO_DC_CLOCK_CLOCK_RATE 100000000
  

Software Assignments

(none)

i2c_sclk

altera_avalon_pio v9.0
pll c0   i2c_sclk
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

i2c_sdat

altera_avalon_pio v9.0
pll c0   i2c_sdat
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sd_clk

altera_avalon_pio v9.0
pll c0   sd_clk
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sd_cmd

altera_avalon_pio v9.0
pll c0   sd_cmd
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sd_dat

altera_avalon_pio v9.0
pll c0   sd_dat
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sd_dat3

altera_avalon_pio v9.0
pll c0   sd_dat3
  clk
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

clk_25

clock_source v9.0


Parameters

clockFrequency 25000000
clockFrequencyKnown true
  

Software Assignments

(none)

SEG7

SEG7_IF v1.0
pll c0   SEG7
  s1_clock
cpu data_master  
  s1


Parameters

SEG7_NUM 8
ADDR_WIDTH 3
DEFAULT_ACTIVE 1
LOW_ACTIVE 1
AUTO_S1_CLOCK_CLOCK_RATE 100000000
  

Software Assignments

(none)

AUDIO

AUDIO_IF v1.0
pll c0   AUDIO
  s1_clock
cpu data_master  
  s1


Parameters

AUTO_S1_CLOCK_CLOCK_RATE 100000000
  

Software Assignments

(none)

VGA

VGA_NIOS_CTRL v1.0
pll c0   VGA
  s1_clock
cpu data_master  
  s1


Parameters

RAM_SIZE 307200
AUTO_S1_CLOCK_CLOCK_RATE 100000000
  

Software Assignments

(none)

DM9000A

DM9000A_IF v1.0
cpu data_master   DM9000A
  s1
d_irq  
  s1_irq
clk_25 clk  
  s1_clock


Parameters

AUTO_S1_CLOCK_CLOCK_RATE 25000000
  

Software Assignments

(none)

ps2_mouse

altera_up_avalon_ps2 v9.0
pll c0   ps2_mouse
  clock_reset
cpu data_master  
  avalon_ps2_slave
d_irq  
  interrupt


Parameters

AUTO_CLOCK_RESET_CLOCK_RATE 100000000
  

Software Assignments

(none)

ps2_keyboard

altera_up_avalon_ps2 v9.0
pll c0   ps2_keyboard
  clock_reset
cpu data_master  
  avalon_ps2_slave
d_irq  
  interrupt


Parameters

AUTO_CLOCK_RESET_CLOCK_RATE 100000000
  

Software Assignments

(none)

generation took 0.02 seconds
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