system_0



2009.11.04.11:10:34 Datasheet
Overview
  clk_50  system_0
  clk_25 
   pio_green_led
 out_port  
 out_port  
 in_port  
 in_port  
   lcd
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
   sd_clk
 out_port  
 bidir_port  
 bidir_port  
 bidir_port  
 out_port  
 bidir_port  
   sdram_u1
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
   uart
 rxd  
 txd  
 cts_n  
 rts_n  
   sdram_u2
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
Processor

   cpu Nios II 9.1

Peripherals

   cpu altera_nios2 9.1

   onchip_mem altera_avalon_onchip_memory2 9.1

   jtag_uart altera_avalon_jtag_uart 9.1

   pio_green_led altera_avalon_pio 9.1

   pio_red_led altera_avalon_pio 9.1

   pio_button altera_avalon_pio 9.1

   pio_switch altera_avalon_pio 9.1

   lcd altera_avalon_lcd_16207 9.1

   timer altera_avalon_timer 9.1

   timer_stamp altera_avalon_timer 9.1

   sysid altera_avalon_sysid 9.1

   sd_clk altera_avalon_pio 9.1

   sd_cmd altera_avalon_pio 9.1

   sd_dat altera_avalon_pio 9.1

   sd_dat3 altera_avalon_pio 9.1

   pll altera_avalon_pll 9.1

   i2c_sclk altera_avalon_pio 9.1

   i2c_sdat altera_avalon_pio 9.1

   sdram_u1 altera_avalon_new_sdram_controller 9.1

   uart altera_avalon_uart 9.1

   sdram_u2 altera_avalon_new_sdram_controller 9.1

   tristate_bridge_ssram altera_avalon_tri_state_bridge 9.1

   tristate_bridge_flash altera_avalon_tri_state_bridge 9.1

   ISP1362 ISP1362_IF 1.0

   SEG7 SEG7_IF 1.0

   AUDIO AUDIO_IF 1.0
Memory Map
cpu
 instruction_master  data_master
  cpu
jtag_debug_module  0x09404800 0x09404800
  onchip_mem
s1  0x09402000 0x09402000
  jtag_uart
avalon_jtag_slave  0x09405170
  pio_green_led
s1  0x094050c0
  pio_red_led
s1  0x094050d0
  pio_button
s1  0x094050e0
  pio_switch
s1  0x094050f0
  lcd
control_slave  0x09405100
  timer
s1  0x09405000
  timer_stamp
s1  0x09405020
  sysid
control_slave  0x09405178
  sd_clk
s1  0x09405110
  sd_cmd
s1  0x09405120
  sd_dat
s1  0x09405130
  sd_dat3
s1  0x09405140
  pll
s1  0x09405040
  i2c_sclk
s1  0x09405150
  i2c_sdat
s1  0x09405160
  sdram_u1
s1  0x04000000 0x04000000
  uart
s1  0x09405060
  sdram_u2
s1  0x06000000 0x06000000
  ssram
s1  0x09200000 0x09200000
  cfi_flash
s1  0x08800000 0x08800000
  ISP1362
hc  0x09405180
dc  0x09405188
  SEG7
s1  0x09405080
  AUDIO
s1  0x094050a0

clk_50

clock_source v9.1





Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2 v9.1

pll c0   cpu
  clk
instruction_master   onchip_mem
  s1
data_master  
  s1
data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
data_master   pio_green_led
  s1
data_master   pio_red_led
  s1
data_master   pio_button
  s1
data_master   pio_switch
  s1
data_master   lcd
  control_slave
data_master   timer
  s1
d_irq  
  irq
data_master   timer_stamp
  s1
d_irq  
  irq
data_master   sysid
  control_slave
data_master   sd_clk
  s1
data_master   sd_cmd
  s1
data_master   sd_dat
  s1
data_master   sd_dat3
  s1
data_master   pll
  s1
data_master   i2c_sclk
  s1
data_master   i2c_sdat
  s1
instruction_master   sdram_u1
  s1
data_master  
  s1
data_master   uart
  s1
d_irq  
  irq
instruction_master   sdram_u2
  s1
data_master  
  s1
instruction_master   tristate_bridge_ssram
  avalon_slave
data_master  
  avalon_slave
instruction_master   tristate_bridge_flash
  avalon_slave
data_master  
  avalon_slave
data_master   ISP1362
  hc
d_irq  
  hc_irq
data_master  
  dc
d_irq  
  dc_irq
data_master   SEG7
  s1
data_master   AUDIO
  s1




Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave sdram_u1.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _2
mmu_udtlbNumEntries _2
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _10
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave sdram_u1.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 100000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 100000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x4000020
RESET_ADDR 0x4000000
BREAK_ADDR 0x9404820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 28
DATA_ADDR_WIDTH 28
NUM_OF_SHADOW_REG_SETS 0

onchip_mem

altera_avalon_onchip_memory2 v9.1

cpu instruction_master   onchip_mem
  s1
data_master  
  s1
pll c0  
  clk1




Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Cyclone II
dualPort false
initMemContent true
initializationFileName onchip_mem
instanceID NONE
memorySize 8192
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_mem"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 8192u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

jtag_uart

altera_avalon_jtag_uart v9.1

cpu data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
pll c0  
  clk




Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

pio_green_led

altera_avalon_pio v9.1

cpu data_master   pio_green_led
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 9
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 9
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

pio_red_led

altera_avalon_pio v9.1

cpu data_master   pio_red_led
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 18
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

pio_button

altera_avalon_pio v9.1

cpu data_master   pio_button
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 100000000
direction Input
edgeType FALLING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "NONE"
FREQ 100000000u

pio_switch

altera_avalon_pio v9.1

cpu data_master   pio_switch
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 18
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

lcd

altera_avalon_lcd_16207 v9.1

cpu data_master   lcd
  control_slave
pll c0  
  clk




Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

timer

altera_avalon_timer v9.1

cpu data_master   timer
  s1
d_irq  
  irq
pll c0  
  clk




Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1.0
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 100000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1.0
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 100000000u
LOAD_VALUE 99999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

timer_stamp

altera_avalon_timer v9.1

cpu data_master   timer_stamp
  s1
d_irq  
  irq
pll c0  
  clk




Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1.0
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 100000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1.0
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 100000000u
LOAD_VALUE 99999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

sysid

altera_avalon_sysid v9.1

cpu data_master   sysid
  control_slave
pll c0  
  clk




Parameters

id 1188866619
timestamp 1257304226
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 1188866619u
TIMESTAMP 1257304226u

sd_clk

altera_avalon_pio v9.1

cpu data_master   sd_clk
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sd_cmd

altera_avalon_pio v9.1

cpu data_master   sd_cmd
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sd_dat

altera_avalon_pio v9.1

cpu data_master   sd_dat
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sd_dat3

altera_avalon_pio v9.1

cpu data_master   sd_dat3
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

pll

altera_avalon_pll v9.1

cpu data_master   pll
  s1
clk_50 clk  
  inclk0
c0   onchip_mem
  clk1
c0   jtag_uart
  clk
c0   timer
  clk
c0   timer_stamp
  clk
c0   cpu
  clk
c0   sdram_u1
  clk
c0   sdram_u2
  clk
c0   ssram
  clk
c0   tristate_bridge_ssram
  clk
c0   cfi_flash
  clk
c0   tristate_bridge_flash
  clk
c0   ISP1362
  hc_clock
c0  
  dc_clock
c0   sd_dat3
  clk
c0   sd_dat
  clk
c0   sd_cmd
  clk
c0   sd_clk
  clk
c0   uart
  clk
c0   pio_button
  clk
c0   lcd
  clk
c0   pio_green_led
  clk
c0   pio_red_led
  clk
c0   pio_switch
  clk
c0   sysid
  clk
c0   i2c_sclk
  clk
c0   i2c_sdat
  clk
c0   SEG7
  s1_clock
c2   AUDIO
  s1_clock




Parameters

c0
c1
c2
c3
c4
c5
c6
c7
c8
c9
deviceFamily CYCLONEII
e0
e1
e2
e3
inputClockFrequency 50000000
inputClockRate 50000000
lockedOutputPortOption Export
pfdenaInputPortOption Register
pllHdl
resetInputPortOption Register
generateLegacySim false
  

Software Assignments

ARESET "None"
PFDENA "None"
LOCKED "None"
PLLENA "None"
SCANCLK "None"
SCANDATA "None"
SCANREAD "None"
SCANWRITE "None"
SCANCLKENA "None"
SCANACLR "None"
SCANDATAOUT "None"
SCANDONE "None"
CONFIGUPDATE "None"
PHASECOUNTERSELECT "None"
PHASEDONE "None"
PHASEUPDOWN "None"
PHASESTEP "None"

i2c_sclk

altera_avalon_pio v9.1

cpu data_master   i2c_sclk
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

i2c_sdat

altera_avalon_pio v9.1

cpu data_master   i2c_sdat
  s1
pll c0  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

sdram_u1

altera_avalon_new_sdram_controller v9.1

pll c0   sdram_u1
  clk
cpu instruction_master  
  s1
data_master  
  s1




Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 100000000
columnWidth 9
dataWidth 16
generateSimulationModel true
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 7.8125
registerDataIn true
rowWidth 13
size 33554432
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 1
SDRAM_DATA_WIDTH 16
SDRAM_ADDR_WIDTH 24
SDRAM_ROW_WIDTH 13
SDRAM_COL_WIDTH 9
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 7.8125
POWERUP_DELAY 100.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

clk_25

clock_source v9.1





Parameters

clockFrequency 25000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

uart

altera_avalon_uart v9.1

cpu data_master   uart
  s1
d_irq  
  irq
pll c0  
  clk




Parameters

baud 115200
baudError 0.01
clockRate 100000000
dataBits 8
fixedBaud true
parity NONE
simCharStream
simInteractiveInputEnable false
simInteractiveOutputEnable false
simTrueBaud false
stopBits 1
syncRegDepth 2
useCtsRts true
useEopRegister false
useRelativePathForSimFile false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BAUD 115200
DATA_BITS 8
FIXED_BAUD 1
PARITY 'N'
STOP_BITS 1
SYNC_REG_DEPTH 2
USE_CTS_RTS 1
USE_EOP_REGISTER 0
SIM_TRUE_BAUD 0
SIM_CHAR_STREAM ""
FREQ 100000000u

sdram_u2

altera_avalon_new_sdram_controller v9.1

pll c0   sdram_u2
  clk
cpu instruction_master  
  s1
data_master  
  s1




Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 100000000
columnWidth 9
dataWidth 16
generateSimulationModel true
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 200.0
refreshPeriod 7.8125
registerDataIn true
rowWidth 13
size 33554432
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 1
SDRAM_DATA_WIDTH 16
SDRAM_ADDR_WIDTH 24
SDRAM_ROW_WIDTH 13
SDRAM_COL_WIDTH 9
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 7.8125
POWERUP_DELAY 200.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

ssram

altera_avalon_cy7c1380_ssram v9.1

pll c0   ssram
  clk
tristate_bridge_ssram tristate_master  
  s1




Parameters

readLatency 2
sharedPorts
simMakeModel true
size 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SRAM_MEMORY_SIZE 2
SRAM_MEMORY_UNITS 1048576
SSRAM_DATA_WIDTH 32
SSRAM_READ_LATENCY 2

tristate_bridge_ssram

altera_avalon_tri_state_bridge v9.1

pll c0   tristate_bridge_ssram
  clk
cpu instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   ssram
  s1




Parameters

registerIncomingSignals true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cfi_flash

altera_avalon_cfi_flash v9.1

pll c0   cfi_flash
  clk
tristate_bridge_flash tristate_master  
  s1




Parameters

actualHoldTime 0.0
actualSetupTime 0.0
actualWaitTime 0.0
addressWidth 22
clockRate 100000000
corePreset CUSTOM
dataWidth 16
holdTime 0
setupTime 0
sharedPorts
timingUnits NS
waitTime 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SETUP_VALUE 0
WAIT_VALUE 0
HOLD_VALUE 0
TIMING_UNITS "ns"
SIZE 8388608u

tristate_bridge_flash

altera_avalon_tri_state_bridge v9.1

pll c0   tristate_bridge_flash
  clk
cpu instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   cfi_flash
  s1




Parameters

registerIncomingSignals true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ISP1362

ISP1362_IF v1.0

pll c0   ISP1362
  hc_clock
c0  
  dc_clock
cpu data_master  
  hc
d_irq  
  hc_irq
data_master  
  dc
d_irq  
  dc_irq




Parameters

AUTO_HC_CLOCK_CLOCK_RATE 100000000
AUTO_DC_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

SEG7

SEG7_IF v1.0

cpu data_master   SEG7
  s1
pll c0  
  s1_clock




Parameters

SEG7_NUM 8
ADDR_WIDTH 3
DEFAULT_ACTIVE 1
LOW_ACTIVE 1
AUTO_S1_CLOCK_CLOCK_RATE 100000000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)

AUDIO

AUDIO_IF v1.0

cpu data_master   AUDIO
  s1
pll c2  
  s1_clock




Parameters

AUTO_S1_CLOCK_CLOCK_RATE 18510000
AUTO_DEVICE_FAMILY Cyclone II
deviceFamily Cyclone II
generateLegacySim false
  

Software Assignments

(none)
generation took 0.02 seconds rendering took 8.88 seconds