name: DE3_QSYS_uniphy_ddr2_s0
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/DE3_QSYS_uniphy_ddr2_s0.v (322377)
generated files (children of this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_rst.sv (3310)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v (86160)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v (33750)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_mgr.sv (30919)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_siii_wrapper.sv (4704)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_siii_phase_decode.v (11473)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_sv_wrapper.sv (7107)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_sv_phase_decode.v (3939)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_acv_wrapper.sv (5253)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_acv_phase_decode.v (1836)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_reg_file.v (2545)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_reg_file.sv (7189)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_phy_mgr.sv (18655)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_data_mgr.sv (3684)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ddr2.v (6718)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ac_ROM_reg.v (1407)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_bitcheck.v (3299)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_core.sv (19015)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_data_broadcast.v (2289)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_data_decoder.v (2809)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_datamux.v (1691)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_di_buffer.v (3934)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_di_buffer_wrap.v (2631)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_dm_decoder.v (1685)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_generic.sv (7777)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_inst_ROM_reg.v (1430)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_jumplogic.v (3232)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_lfsr72.v (1337)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_lfsr36.v (2025)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_lfsr12.v (1390)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_pattern_fifo.v (2756)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ram.v (1263)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ram_csr.v (2433)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_read_datapath.v (3483)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_write_decoder.v (2746)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ac_ROM_no_ifdef_params.v (3035)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_inst_ROM_no_ifdef_params.v (2953)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv (2997)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_avalon_mm_bridge.v (11552)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_master_translator.sv (20918)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_slave_translator.sv (17113)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_master_agent.sv (12286)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_slave_agent.sv (27956)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_burst_uncompressor.sv (12943)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_avalon_sc_fifo.v (32190)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router.sv (9022)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_001.sv (7994)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_002.sv (7618)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_id_router.sv (7500)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_003.sv (7680)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_005.sv (7595)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_traffic_limiter.sv (15504)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_avalon_st_pipeline_base.v (4993)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux.sv (6686)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_001.sv (4199)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002.sv (3559)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv (9447)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_003.sv (12969)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_005.sv (12118)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_003.sv (4827)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_005.sv (4193)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux.sv (14650)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux_001.sv (11430)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_irq_mapper.sv (1705)
Instantiates the following:
   sequencer_rst : altera_mem_if_sequencer_rst
   cpu_inst : altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst
   sequencer_scc_mgr_inst : sequencer_scc_mgr
   sequencer_reg_file_inst : sequencer_reg_file
   sequencer_phy_mgr_inst : sequencer_phy_mgr
   sequencer_data_mgr_inst : sequencer_data_mgr
   sequencer_rw_mgr_inst : rw_manager_ddr2
   sequencer_mem : altera_mem_if_sequencer_mem_no_ifdef_params
   seq_bridge : altera_avalon_mm_bridge
   cpu_inst_data_master_translator, seq_bridge_m0_translator, cpu_inst_instruction_master_translator : altera_merlin_master_translator
   sequencer_phy_mgr_inst_avl_translator, sequencer_data_mgr_inst_avl_translator, sequencer_rw_mgr_inst_avl_translator, sequencer_mem_s1_translator, sequencer_scc_mgr_inst_avl_translator, sequencer_reg_file_inst_avl_translator : altera_merlin_slave_translator
   cpu_inst_data_master_translator_avalon_universal_master_0_agent, seq_bridge_m0_translator_avalon_universal_master_0_agent, cpu_inst_instruction_master_translator_avalon_universal_master_0_agent : altera_merlin_master_agent
   sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent, sequencer_mem_s1_translator_avalon_universal_slave_0_agent, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent : altera_merlin_slave_agent
   sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo : altera_avalon_sc_fifo
   addr_router : DE3_QSYS_uniphy_ddr2_s0_addr_router
   addr_router_001 : DE3_QSYS_uniphy_ddr2_s0_addr_router_001
   addr_router_002 : DE3_QSYS_uniphy_ddr2_s0_addr_router_002
   id_router, id_router_001, id_router_002, id_router_004 : DE3_QSYS_uniphy_ddr2_s0_id_router
   id_router_003 : DE3_QSYS_uniphy_ddr2_s0_id_router_003
   id_router_005 : DE3_QSYS_uniphy_ddr2_s0_id_router_005
   limiter : altera_merlin_traffic_limiter
   cmd_xbar_demux : DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux
   cmd_xbar_demux_001 : DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_001
   cmd_xbar_demux_002, rsp_xbar_demux, rsp_xbar_demux_001, rsp_xbar_demux_002, rsp_xbar_demux_004 : DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002
   cmd_xbar_mux_003 : DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_003
   cmd_xbar_mux_005 : DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_005
   rsp_xbar_demux_003 : DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_003
   rsp_xbar_demux_005 : DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_005
   rsp_xbar_mux : DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux
   rsp_xbar_mux_001 : DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux_001
   irq_mapper : DE3_QSYS_uniphy_ddr2_s0_irq_mapper
 
name: altera_mem_if_sequencer_rst
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_rst.sv (3310)
 
name: altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v (86160)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v (33750)
 
name: sequencer_scc_mgr
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_mgr.sv (30919)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_siii_wrapper.sv (4704)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_siii_phase_decode.v (11473)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_sv_wrapper.sv (7107)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_sv_phase_decode.v (3939)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_acv_wrapper.sv (5253)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_acv_phase_decode.v (1836)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_scc_reg_file.v (2545)
 
name: sequencer_reg_file
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_reg_file.sv (7189)
 
name: sequencer_phy_mgr
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_phy_mgr.sv (18655)
 
name: sequencer_data_mgr
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/sequencer_data_mgr.sv (3684)
 
name: rw_manager_ddr2
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ddr2.v (6718)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ac_ROM_reg.v (1407)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_bitcheck.v (3299)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_core.sv (19015)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_data_broadcast.v (2289)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_data_decoder.v (2809)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_datamux.v (1691)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_di_buffer.v (3934)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_di_buffer_wrap.v (2631)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_dm_decoder.v (1685)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_generic.sv (7777)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_inst_ROM_reg.v (1430)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_jumplogic.v (3232)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_lfsr72.v (1337)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_lfsr36.v (2025)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_lfsr12.v (1390)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_pattern_fifo.v (2756)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ram.v (1263)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ram_csr.v (2433)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_read_datapath.v (3483)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_write_decoder.v (2746)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_ac_ROM_no_ifdef_params.v (3035)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/rw_manager_inst_ROM_no_ifdef_params.v (2953)
 
name: altera_mem_if_sequencer_mem_no_ifdef_params
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv (2997)
 
name: altera_avalon_mm_bridge
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_avalon_mm_bridge.v (11552)
 
name: altera_merlin_master_translator
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_master_translator.sv (20918)
 
name: altera_merlin_slave_translator
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_slave_translator.sv (17113)
 
name: altera_merlin_master_agent
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_master_agent.sv (12286)
 
name: altera_merlin_slave_agent
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_slave_agent.sv (27956)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_burst_uncompressor.sv (12943)
 
name: altera_avalon_sc_fifo
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_avalon_sc_fifo.v (32190)
 
name: DE3_QSYS_uniphy_ddr2_s0_addr_router
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router.sv (9022)
 
name: DE3_QSYS_uniphy_ddr2_s0_addr_router_001
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_001.sv (7994)
 
name: DE3_QSYS_uniphy_ddr2_s0_addr_router_002
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_002.sv (7618)
 
name: DE3_QSYS_uniphy_ddr2_s0_id_router
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_id_router.sv (7500)
 
name: DE3_QSYS_uniphy_ddr2_s0_id_router_003
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_003.sv (7680)
 
name: DE3_QSYS_uniphy_ddr2_s0_id_router_005
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_005.sv (7595)
 
name: altera_merlin_traffic_limiter
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_traffic_limiter.sv (15504)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_avalon_st_pipeline_base.v (4993)
 
name: DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux.sv (6686)
 
name: DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_001
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_001.sv (4199)
 
name: DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002.sv (3559)
 
name: DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_003
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv (9447)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_003.sv (12969)
 
name: DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_005
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv (9447)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_005.sv (12118)
 
name: DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_003
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_003.sv (4827)
 
name: DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_005
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_005.sv (4193)
 
name: DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv (9447)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux.sv (14650)
 
name: DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux_001
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv (9447)
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux_001.sv (11430)
 
name: DE3_QSYS_uniphy_ddr2_s0_irq_mapper
generated files (just this core):
   E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/DE3_QSYS_uniphy_ddr2_s0_irq_mapper.sv (1705)
 
 
 [Debug] DE3_QSYS_uniphy_ddr2_s0.avl_clk: Timing: ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.sequencer_rst: Timing: VAL:1/0.000s ELA:1/0.110s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.cpu_inst: Timing: VAL:15/0.001s/0.015s ELA:15/0.025s/0.328s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.sequencer_scc_mgr_inst: Timing: VAL:1/0.000s ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.sequencer_reg_file_inst: Timing: VAL:1/0.015s ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.sequencer_phy_mgr_inst: Timing: VAL:1/0.000s ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.sequencer_data_mgr_inst: Timing: VAL:1/0.000s ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.afi_clk: Timing: ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.afi_reset: Timing: ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.sequencer_rw_mgr_inst: Timing: VAL:1/0.000s ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.sequencer_mem: Timing: VAL:2/0.000s/0.000s ELA:2/0.000s/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.scc_clk: Timing: ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.scc_reset: Timing: ELA:1/0.000s
 [Debug] DE3_QSYS_uniphy_ddr2_s0.seq_bridge: Timing: ELA:2/0.000s/0.000s
 [Warning] DE3_QSYS_uniphy_ddr2_s0.sequencer_rw_mgr_inst: <b>sequencer_rw_mgr_inst.csr</b> must be exported, or connected to a matching conduit.
 [Debug] DE3_QSYS_uniphy_ddr2_s0: Timing: VAL:1/0.000s COM:1/2.215s
 [Info] DE3_QSYS_uniphy_ddr2_s0: Generating <b>qsys_sequencer_110</b> "<b>DE3_QSYS_uniphy_ddr2_s0</b>" for QUARTUS_SYNTH
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 0 starting:qsys_sequencer_110 "DE3_QSYS_uniphy_ddr2_s0"
 [Debug] Transform: PipelineBridgeSwap
 [Info] pipeline_bridge_swap_transform: After transform: <b>14</b> modules, <b>31</b> connections
 [Debug] Transform: ClockCrossingBridgeSwap
 [Debug] Transform: QsysBetaIPSwap
 [Debug] Transform: CustomInstructionTransform
 [Info] No custom instruction connections, skipping transform 
 [Debug] Transform: MMTransform
 [Debug] Transform: TranslatorTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
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 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] merlin_translator_transform: After transform: <b>23</b> modules, <b>58</b> connections
 [Debug] Transform: IDPadTransform
 [Debug] Transform: DomainTransform
 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_inst.data_master and cpu_inst_data_master_translator.avalon_anti_master_0
 [Debug] Transform merlin_domain_transform not run on matched interfaces seq_bridge.m0 and seq_bridge_m0_translator.avalon_anti_master_0
 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_inst.instruction_master and cpu_inst_instruction_master_translator.avalon_anti_master_0
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
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 [Progress] min: 0
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 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_phy_mgr_inst_avl_translator.avalon_anti_slave_0 and sequencer_phy_mgr_inst.avl
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_data_mgr_inst_avl_translator.avalon_anti_slave_0 and sequencer_data_mgr_inst.avl
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_rw_mgr_inst_avl_translator.avalon_anti_slave_0 and sequencer_rw_mgr_inst.avl
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_mem_s1_translator.avalon_anti_slave_0 and sequencer_mem.s1
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_scc_mgr_inst_avl_translator.avalon_anti_slave_0 and sequencer_scc_mgr_inst.avl
 [Debug] Transform merlin_domain_transform not run on matched interfaces sequencer_reg_file_inst_avl_translator.avalon_anti_slave_0 and sequencer_reg_file_inst.avl
 [Info] merlin_domain_transform: After transform: <b>39</b> modules, <b>142</b> connections
 [Debug] Transform: RouterTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
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 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] merlin_router_transform: After transform: <b>48</b> modules, <b>169</b> connections
 [Debug] Transform: TrafficLimiterTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] merlin_traffic_limiter_transform: After transform: <b>49</b> modules, <b>173</b> connections
 [Debug] Transform: BurstTransform
 [Debug] Transform: CombinedWidthTransform
 [Debug] Transform: ResetAdaptation
 [Debug] Transform: NetworkToSwitchTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
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 [Progress] current: 1
 [Progress] min: 0
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 [Progress] min: 0
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 [Progress] min: 0
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 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
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 [Progress] min: 0
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 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] merlin_network_to_switch_transform: After transform: <b>66</b> modules, <b>209</b> connections
 [Debug] Transform: WidthTransform
 [Debug] Transform: RouterTableTransform
 [Debug] Transform: ClockCrossingTransform
 [Debug] Transform: TrafficLimiterUpdateTransform
 [Info] limiter_update_transform: After transform: <b>66</b> modules, <b>210</b> connections
 [Info] merlin_mm_transform: After transform: <b>66</b> modules, <b>210</b> connections
 [Debug] Transform: InterruptMapperTransform
 [Progress] min: 0
 [Progress] max: 1
 [Progress] current: 1
 [Info] merlin_interrupt_mapper_transform: After transform: <b>67</b> modules, <b>213</b> connections
 [Debug] Transform: InterruptSyncTransform
 [Debug] Transform: InterruptFanoutTransform
 [Debug] Transform: AvalonStreamingTransform
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_mem_if_sequencer_rst</b> "<b>submodules/altera_mem_if_sequencer_rst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_mem_if_sequencer_cpu</b> "<b>submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>sequencer_scc_mgr_110</b> "<b>submodules/sequencer_scc_mgr</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>sequencer_reg_file_111</b> "<b>submodules/sequencer_reg_file</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>sequencer_phy_mgr_100</b> "<b>submodules/sequencer_phy_mgr</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>sequencer_data_mgr_110</b> "<b>submodules/sequencer_data_mgr</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>sequencer_rw_mgr_ddr2_110</b> "<b>submodules/rw_manager_ddr2</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_mem_if_sequencer_mem</b> "<b>submodules/altera_mem_if_sequencer_mem_no_ifdef_params</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_avalon_mm_bridge</b> "<b>submodules/altera_avalon_mm_bridge</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_master_translator</b> "<b>submodules/altera_merlin_master_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_translator</b> "<b>submodules/altera_merlin_slave_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_master_agent</b> "<b>submodules/altera_merlin_master_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_slave_agent</b> "<b>submodules/altera_merlin_slave_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_avalon_sc_fifo</b> "<b>submodules/altera_avalon_sc_fifo</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_001</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_id_router</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_id_router</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_id_router</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_003</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_id_router</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_router</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_005</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_traffic_limiter</b> "<b>submodules/altera_merlin_traffic_limiter</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_001</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_003</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_005</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_003</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_demultiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_005</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_merlin_multiplexer</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux_001</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" reuses <b>altera_irq_mapper</b> "<b>submodules/DE3_QSYS_uniphy_ddr2_s0_irq_mapper</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 56 starting:altera_mem_if_sequencer_rst "submodules/altera_mem_if_sequencer_rst"
 [Info] sequencer_rst: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_mem_if_sequencer_rst</b> "<b>sequencer_rst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 55 starting:altera_mem_if_sequencer_cpu "submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst"
 [Info] cpu_inst: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_mem_if_sequencer_cpu</b> "<b>cpu_inst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 54 starting:sequencer_scc_mgr_110 "submodules/sequencer_scc_mgr"
 [Info] sequencer_scc_mgr_inst: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>sequencer_scc_mgr_110</b> "<b>sequencer_scc_mgr_inst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 53 starting:sequencer_reg_file_111 "submodules/sequencer_reg_file"
 [Info] sequencer_reg_file_inst: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>sequencer_reg_file_111</b> "<b>sequencer_reg_file_inst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 52 starting:sequencer_phy_mgr_100 "submodules/sequencer_phy_mgr"
 [Info] sequencer_phy_mgr_inst: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>sequencer_phy_mgr_100</b> "<b>sequencer_phy_mgr_inst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 51 starting:sequencer_data_mgr_110 "submodules/sequencer_data_mgr"
 [Info] sequencer_data_mgr_inst: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>sequencer_data_mgr_110</b> "<b>sequencer_data_mgr_inst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 50 starting:sequencer_rw_mgr_ddr2_110 "submodules/rw_manager_ddr2"
 [Info] sequencer_rw_mgr_inst: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>sequencer_rw_mgr_ddr2_110</b> "<b>sequencer_rw_mgr_inst</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 49 starting:altera_mem_if_sequencer_mem "submodules/altera_mem_if_sequencer_mem_no_ifdef_params"
 [Info] sequencer_mem: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_mem_if_sequencer_mem</b> "<b>sequencer_mem</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 48 starting:altera_avalon_mm_bridge "submodules/altera_avalon_mm_bridge"
 [Info] seq_bridge: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_avalon_mm_bridge</b> "<b>seq_bridge</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 47 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator"
 [Info] cpu_inst_data_master_translator: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_master_translator</b> "<b>cpu_inst_data_master_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 44 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"
 [Info] sequencer_phy_mgr_inst_avl_translator: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_slave_translator</b> "<b>sequencer_phy_mgr_inst_avl_translator</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 38 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent"
 [Info] cpu_inst_data_master_translator_avalon_universal_master_0_agent: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_master_agent</b> "<b>cpu_inst_data_master_translator_avalon_universal_master_0_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 35 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"
 [Info] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_slave_agent</b> "<b>sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 34 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"
 [Info] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_avalon_sc_fifo</b> "<b>sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 23 starting:altera_merlin_router "submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router"
 [Info] addr_router: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_router</b> "<b>addr_router</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 22 starting:altera_merlin_router "submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_001"
 [Info] addr_router_001: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_router</b> "<b>addr_router_001</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 21 starting:altera_merlin_router "submodules/DE3_QSYS_uniphy_ddr2_s0_addr_router_002"
 [Info] addr_router_002: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_router</b> "<b>addr_router_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 20 starting:altera_merlin_router "submodules/DE3_QSYS_uniphy_ddr2_s0_id_router"
 [Info] id_router: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_router</b> "<b>id_router</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 17 starting:altera_merlin_router "submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_003"
 [Info] id_router_003: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_router</b> "<b>id_router_003</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 15 starting:altera_merlin_router "submodules/DE3_QSYS_uniphy_ddr2_s0_id_router_005"
 [Info] id_router_005: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_router</b> "<b>id_router_005</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 14 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"
 [Info] limiter: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_traffic_limiter</b> "<b>limiter</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 13 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux"
 [Info] cmd_xbar_demux: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_xbar_demux</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 12 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_001"
 [Info] cmd_xbar_demux_001: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_xbar_demux_001</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 11 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_demux_002"
 [Info] cmd_xbar_demux_002: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>cmd_xbar_demux_002</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 10 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_003"
 [Info] cmd_xbar_mux_003: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_xbar_mux_003</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 9 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_cmd_xbar_mux_005"
 [Info] cmd_xbar_mux_005: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>cmd_xbar_mux_005</b>"
 [Info] Reusing file <b>E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv</b>
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 5 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_003"
 [Info] rsp_xbar_demux_003: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_xbar_demux_003</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 3 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_demux_005"
 [Info] rsp_xbar_demux_005: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_demultiplexer</b> "<b>rsp_xbar_demux_005</b>"
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 2 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux"
 [Info] rsp_xbar_mux: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_xbar_mux</b>"
 [Info] Reusing file <b>E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv</b>
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 1 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_uniphy_ddr2_s0_rsp_xbar_mux_001"
 [Info] rsp_xbar_mux_001: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_merlin_multiplexer</b> "<b>rsp_xbar_mux_001</b>"
 [Info] Reusing file <b>E:/SVN/de3_uniphy_ddr2/DE3_QSYS_uniphy_ddr2_s0/submodules/altera_merlin_arbitrator.sv</b>
 [Debug] DE3_QSYS_uniphy_ddr2_s0: queue size: 0 starting:altera_irq_mapper "submodules/DE3_QSYS_uniphy_ddr2_s0_irq_mapper"
 [Info] irq_mapper: "<b>DE3_QSYS_uniphy_ddr2_s0</b>" instantiated <b>altera_irq_mapper</b> "<b>irq_mapper</b>"
 [Info] DE3_QSYS_uniphy_ddr2_s0: Done <b>DE3_QSYS_uniphy_ddr2_s0</b>" with 32 modules, 96 files, 1470037 bytes
