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clk_50

clock_source v9.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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onchip_mem

altera_avalon_onchip_memory2 v9.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 deviceFamily Stratix III dualPort false initMemContent true initializationFileName onchip_mem_release instanceID NONE memorySize 131072 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile true useShallowMemBlocks false writable true generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "onchip_mem_release" NON_DEFAULT_INIT_FILE_ENABLED 1 GUI_RAM_BLOCK_TYPE "Automatic" WRITABLE 1 DUAL_PORT 0 SIZE_VALUE 131072u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "Auto" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

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sysid

altera_avalon_sysid v9.1

Parameters id 229358434 timestamp 1260247210 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 229358434u TIMESTAMP 1260247210u

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timer

altera_avalon_timer v9.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true systemFrequency 50000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 50000000u LOAD_VALUE 49999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

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altmemddr

altmemddr2 v9.1

Parameters pipeline_commands false debug_en false export_debug_port false use_generated_memory_model true dedicated_memory_clk_phase_label Dedicated memory clock phase: mem_if_clk_mhz 266.667 quartus_project_exists false local_if_drate Half enable_v72_rsu false local_if_clk_mhz_label 133.3 new_variant true mem_if_memtype DDR2 SDRAM pll_ref_clk_mhz 50.0 mem_if_clk_ps_label (3750 ps) family Stratix III project_family Stratix III speed_grade 2 dedicated_memory_clk_phase 0 pll_ref_clk_ps_label (20000 ps) avalon_burst_length 1 mem_if_clk_pair_count 2 mem_if_cs_per_dimm 1 pre_latency_label Fix read latency at: dedicated_memory_clk_en false mirror_addressing 0 mem_if_bankaddr_width 3 register_control_word_9 0000 mem_if_rowaddr_width 14 mem_dyn_deskew_en false post_latency_label cycles (0 cycles=minimum latency, non-deterministic) mem_if_dm_pins_en Yes local_if_dwidth_label 256 register_control_word_7 0000 register_control_word_8 0000 mem_if_preset Custom (TERASIC, Transcend 1G DDR2 667 CL5 RANK1 531956-5818) mem_if_pchaddr_bit 10 WIDTH_RATIO 4 vendor JEDEC register_control_word_3 0000 register_control_word_4 0000 chip_or_dimm Unbuffered DIMM register_control_word_5 0000 register_control_word_6 0000 mem_fmax 333.3 register_control_word_0 0000 register_control_word_size 4 register_control_word_1 0000 register_control_word_2 0000 register_control_word_11 0000 register_control_word_10 0000 mem_if_cs_width 1 mem_if_preset_rlat 0 mem_if_cs_per_rank 1 fast_simulation_en FAST register_control_word_15 0000 register_control_word_14 0000 mem_if_dwidth 64 mem_if_dq_per_dqs 8 mem_if_coladdr_width 10 register_control_word_13 0000 register_control_word_12 0000 mem_tiha_ps 275 mem_tdsh_ck 0.2 mem_if_trfc_ns 105.0 mem_tqh_ck 0.36 mem_tisa_ps 200 mem_tdss_ck 0.2 mem_trtp_ns 7.5 mem_if_tinit_us 200.0 mem_if_trcd_ns 15.0 mem_if_twtr_ck 2 mem_trrd_ns 7.5 mem_tdqss_ck 0.25 mem_tqhs_ps 400 mem_tdsa_ps 100 mem_tac_ps 500 mem_tdha_ps 175 mem_if_tras_ns 45.0 mem_if_twr_ns 15.0 mem_tdqsck_ps 450 mem_if_trp_ns 15.0 mem_tdqsq_ps 240 mem_if_tmrd_ns 8.0 mem_tfaw_ns 0.0 mem_if_trefi_us 7.8 mem_tcl_40_fmax 266.667 mem_odt 50 mp_WLH_percent 0.6 mem_drv_str Normal mp_DH_percent 0.5 input_period 0 mp_QH_percent 0.5 mp_QHS_percent 0.5 mem_tcl_30_fmax 200.0 ac_clk_select dedicated mp_DQSQ_percent 0.65 mp_DS_percent 0.6 pll_reconfig_ports_en false mem_btype Sequential mp_IS_percent 0.7 mem_tcl 5.0 mp_DQSS_percent 0.5 export_bank_info false mp_DSS_percent 0.6 mem_dll_en Yes ac_phase 240 mem_if_oct_en true mem_tcl_60_fmax 333.3 mp_DSH_percent 0.6 mem_if_dqsn_en true enable_mp_calibration true mp_IH_percent 0.6 mem_tcl_15_fmax 533.0 dll_external false mem_bl 4 mp_WLS_percent 0.7 mem_tcl_50_fmax 333.3 mp_DQSCK_percent 0.5 mem_tcl_25_fmax 533.0 mem_tcl_20_fmax 533.0 mem_addr_mapping CHIP_ROW_BANK_COL ctl_ecc_en false user_refresh_en false ctl_hrb_en false clk_source_sharing_en false ctl_lookahead_depth 4 ref_clk_source clk_50 ctl_autopch_en false multicast_wr_en false ctl_powerdn_en false auto_powerdn_cycles 0 csr_en false local_if_type_avalon true auto_powerdn_en false ctl_auto_correct_en false ctl_self_refresh_en false phy_if_type_afi true shared_sys_clk_source controller_type hp_ctl max_local_size 4 tool_context SOPC_BUILDER mem_srtr Normal mem_mpr_loc Predefined Pattern dss_tinit_rst_us 200.0 mem_tcl_90_fmax 400.0 mem_rtt_wr Dynamic ODT off mem_tcl_100_fmax 400.0 mem_pasr Full Array mem_asrm Manual SR Reference (SRT) mem_mpr_oper Predefined Pattern mem_tcl_80_fmax 400.0 mem_drv_impedance RZQ/7 mem_rtt_nom ODT Disabled mem_tcl_70_fmax 400.0 mem_wtcl 5.0 mem_dll_pch Fast Exit mem_atcl Disabled board_settings_valid true t_IH 0.275 board_intra_DQS_group_skew 0.05 isi_DQS 0.0 addr_cmd_slew_rate 1.0 board_tpd_inter_DIMM 0.05 board_addresscmd_CK_skew 0.0 t_DS_calculated 0.100 isi_addresscmd_hold 0.0 t_IS 0.2 restore_default_toggle true dqs_dqsn_slew_rate 2.0 dq_slew_rate 1.0 board_inter_DQS_group_skew 0.02 isi_addresscmd_setup 0.0 board_minCK_DQS_skew -0.01 t_IS_calculated 0.200 num_slots_or_devices 1 board_maxCK_DQS_skew 0.01 board_skew_ps 50 t_DH 0.175 ck_ckn_slew_rate 2.0 isi_DQ 0.0 t_IH_calculated 0.275 t_DH_calculated 0.175 t_DS 0.1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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ddr2_i2c_scl

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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ddr2_i2c_sda

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 1 HAS_OUT 0 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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pio_led

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 24 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 24 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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pio_button

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 50000000 direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 4 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 50000000u

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clock_crossing_bridge

altera_avalon_clock_crossing v9.1

Parameters dataWidth 32 downstreamFIFODepth 32 downstreamUseRegister false masterSyncDepth 3 maxBurstSize 8 slaveAddressWidth 5 slaveSyncDepth 3 upstreamFIFODepth 1024 upstreamUseRegister false useBurstCount false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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jtag_uart

altera_avalon_jtag_uart v9.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

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cpu

altera_nios2 v9.1

Parameters userDefinedSettings setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave onchip_mem.s1 resetOffset 0 muldiv_multiplierType DSPBlock muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false impl Fast icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave onchip_mem.s1 exceptionOffset 32 debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false cpuReset false cpuID 0 clockFrequency 133333499 breakSlave cpu.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 133333499u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 2048 INITDA_SUPPORTED FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x41020020 RESET_ADDR 0x41020000 BREAK_ADDR 0x41040820 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 1 INST_ADDR_WIDTH 31 DATA_ADDR_WIDTH 31 NUM_OF_SHADOW_REG_SETS 0