DE3_QSYS DE3_QSYS
1.0
2011.07.29.17:27:23 Generation Report
Output Directory E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/
Files E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/DE3_QSYS.v (493301 bytes VERILOG)

E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu.ocp (848 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu.sdc (3743 bytes SDC)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu.v (422592 bytes VERILOG_ENCRYPT)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_bht_ram.mif (2392 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_dc_tag_ram.mif (984 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_ic_tag_ram.mif (2009 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_jtag_debug_module_sysclk.v (7033 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_jtag_debug_module_tck.v (8319 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_jtag_debug_module_wrapper.v (10163 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_ociram_default_contents.mif (5878 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_oci_test_bench.v (1468 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_rf_ram_a.mif (600 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_rf_ram_b.mif (600 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cpu_test_bench.v (31415 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_sysid.v (1447 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2.v (13387 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_c0.v (19278 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd.v (25980 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v (51432 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v (19238 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v (10002 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v (16552 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_odt_gen.v (14757 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v (46253 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_arbiter.v (50108 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_burst_gen.v (64113 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_cmd_gen.v (121966 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_csr.v (53869 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_buffer.v (4779 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_buffer_manager.v (8991 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_burst_tracking.v (4707 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_dataid_manager.v (33821 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_fifo.v (8340 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_list.v (8754 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_rdata_path.v (51877 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_wdata_path.v (44528 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_define.iv (2237 bytes VERILOG_INCLUDE)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v (13702 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v (32973 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v (59259 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v (10730 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v (14064 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v (22231 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v (49920 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_input_if.v (10699 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_rank_timer.v (116132 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_sideband.v (57384 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_tbp.v (175785 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_timing_param.v (52437 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_controller.v (161675 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_controller_st_top.v (90484 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_if_nextgen_ddr2_controller_core.sv (26488 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v (6961 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_clock_pair_generator.v (3528 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_pll_memphy.v (23414 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_dll_memphy.v (6011 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_oct_control.v (3796 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_controller_phy.sv (15532 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_memphy_top.sv (23800 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_read_valid_selector.v (2379 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_addr_cmd_datapath.v (5972 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_reset.v (4421 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_addr_cmd_pads.v (11820 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_memphy.v (43885 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_reset_sync.v (1978 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_afi_mux.v (6023 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_new_io_pads.v (10904 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_fr_cycle_shifter.v (3669 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_read_datapath.v (22652 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_write_datapath.v (4099 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_hr_to_fr.v (1348 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_sequencer_mux_bridge.sv (17257 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_phy_csr.sv (5949 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_iss_probe.v (1784 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_flop_mem.v (2755 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_nios_sequencer.sv (10932 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0.sv (13068 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_altdqdqs.v (5563 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altdq_dqs2_ddio_3reg_stratixiii.sv (54074 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/software/sequencer.c (131340 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/software/sequencer.h (10140 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer.v (352722 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v (32198 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv (9448 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10392 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_master_agent.sv (8662 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_master_translator.sv (16415 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv (17560 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv (15976 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv (13743 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_addr_router.sv (6409 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_addr_router_001.sv (8029 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cmd_xbar_demux.sv (4169 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cmd_xbar_demux_001.sv (7987 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cmd_xbar_mux.sv (12302 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst.sdc (5808 bytes SDC)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst.v (208385 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk.v (7838 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck.v (9544 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper.v (12055 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_ociram_default_contents.mif (5878 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_oci_test_bench.v (1713 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_rf_ram_a.mif (600 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_rf_ram_b.mif (600 bytes MIF)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_cpu_inst_test_bench.v (32285 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_id_router.sv (5987 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_id_router_002.sv (5918 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_irq_mapper.sv (1714 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_rsp_xbar_demux.sv (4163 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_rsp_xbar_demux_002.sv (3539 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_rsp_xbar_mux.sv (12268 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_rsp_xbar_mux_001.sv (17364 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_sequencer_ram.v (4415 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_sequencer_rom.hex (86029 bytes HEX)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_qsys_sequencer_sequencer_rom.v (4563 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_ac_ROM_no_ifdef_params.v (10403 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_ac_ROM_reg.v (1478 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_bitcheck.v (2624 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_core.sv (16455 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_datamux.v (1733 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_data_broadcast.v (2347 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_data_decoder.v (2892 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_ddr2.v (6926 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_di_buffer.v (10123 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_di_buffer_wrap.v (2076 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_dm_decoder.v (1735 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_generic.sv (7209 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_inst_ROM_no_ifdef_params.v (10442 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_inst_ROM_reg.v (1504 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_jumplogic.v (3333 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_lfsr12.v (1438 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_lfsr36.v (2097 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_lfsr72.v (1381 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_pattern_fifo.v (10125 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_ram.v (1317 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_ram_csr.v (2442 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_read_datapath.v (3610 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/rw_manager_write_decoder.v (2858 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/sequencer_data_mgr.sv (3779 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/sequencer_phy_mgr.sv (13764 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/sequencer_ptr_mgr.sv (3133 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/sequencer_scc_mgr.sv (17682 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/sequencer_scc_phase_decode.v (13160 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/sequencer_scc_reg_file.v (2631 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_sequencer_rom.hex (86046 bytes HEX)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_AC_ROM.hex (1357 bytes HEX)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_inst_ROM.hex (2445 bytes HEX)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0.ppf (37601 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0.sdc (31323 bytes SDC)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_timing.tcl (6138 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_report_timing.tcl (18298 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_report_timing_core.tcl (89590 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_pin_map.tcl (77962 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_pin_assignments.tcl (14966 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_parameters.tcl (3057 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_uniphy_ddr2_p0_sequencer_cpu.sdc (796 bytes SDC)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_jtag_uart.v (23819 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_jtag_uart_input_mutex.dat (3 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_jtag_uart_input_stream.dat (10 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_jtag_uart_output_stream.dat (0 bytes OTHER)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_onchip_mem.hex (688141 bytes HEX)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_onchip_mem.v (3963 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v (10027 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_dc_fifo.v (23502 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v (1434 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_timer.v (6907 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_ddr2_i2c_scl.v (2293 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_ddr2_i2c_sda.v (2811 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_pio_led.v (2243 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_pio_button.v (1951 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_addr_router.sv (6368 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_addr_router_001.sv (6917 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_id_router.sv (5897 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_id_router_002.sv (5837 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_id_router_003.sv (5828 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_addr_router_002.sv (7571 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_id_router_004.sv (5828 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cmd_xbar_demux.sv (4109 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cmd_xbar_demux_001.sv (5387 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cmd_xbar_mux.sv (11013 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_rsp_xbar_demux.sv (4103 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_rsp_xbar_demux_002.sv (3479 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_rsp_xbar_mux.sv (12208 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_rsp_xbar_mux_001.sv (13912 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_cmd_xbar_demux_002.sv (7292 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_rsp_xbar_demux_004.sv (3479 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_rsp_xbar_mux_002.sv (16456 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_width_adapter.sv (36187 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v (7493 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_st_clock_crosser.v (4900 bytes VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/DE3_QSYS_irq_mapper.sv (1824 bytes SYSTEM_VERILOG)
E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_irq_clock_crosser.sv (1646 bytes SYSTEM_VERILOG)
Instantiations
DE3_QSYS
DE3_QSYS v1.0		 DE3_QSYS_cpu as cpu
DE3_QSYS_sysid as sysid
DE3_QSYS_uniphy_ddr2 as uniphy_ddr2
DE3_QSYS_jtag_uart as jtag_uart
DE3_QSYS_onchip_mem as onchip_mem
altera_avalon_mm_clock_crossing_bridge as clock_crossing_bridge
DE3_QSYS_timer as timer
DE3_QSYS_ddr2_i2c_scl as ddr2_i2c_scl
DE3_QSYS_ddr2_i2c_sda as ddr2_i2c_sda
DE3_QSYS_pio_led as pio_led
DE3_QSYS_pio_button as pio_button
altera_merlin_master_translator as cpu_instruction_master_translator, cpu_data_master_translator, clock_crossing_bridge_m0_translator
altera_merlin_slave_translator as cpu_jtag_debug_module_translator, onchip_mem_s1_translator, uniphy_ddr2_avl_translator, clock_crossing_bridge_s0_translator, timer_s1_translator, ddr2_i2c_scl_s1_translator, ddr2_i2c_sda_s1_translator, pio_led_s1_translator, pio_button_s1_translator, sysid_control_slave_translator, jtag_uart_avalon_jtag_slave_translator
altera_merlin_master_agent as cpu_instruction_master_translator_avalon_universal_master_0_agent, cpu_data_master_translator_avalon_universal_master_0_agent, clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent
altera_merlin_slave_agent as cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent, onchip_mem_s1_translator_avalon_universal_slave_0_agent, uniphy_ddr2_avl_translator_avalon_universal_slave_0_agent, clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent, timer_s1_translator_avalon_universal_slave_0_agent, ddr2_i2c_scl_s1_translator_avalon_universal_slave_0_agent, ddr2_i2c_sda_s1_translator_avalon_universal_slave_0_agent, pio_led_s1_translator_avalon_universal_slave_0_agent, pio_button_s1_translator_avalon_universal_slave_0_agent, sysid_control_slave_translator_avalon_universal_slave_0_agent, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent
altera_avalon_sc_fifo as cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo, onchip_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, onchip_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo, uniphy_ddr2_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo, timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, ddr2_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, ddr2_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
DE3_QSYS_addr_router as addr_router
DE3_QSYS_addr_router_001 as addr_router_001
DE3_QSYS_id_router as id_router, id_router_001
DE3_QSYS_id_router_002 as id_router_002
DE3_QSYS_id_router_003 as id_router_003
DE3_QSYS_addr_router_002 as addr_router_002
DE3_QSYS_id_router_004 as id_router_004, id_router_005, id_router_006, id_router_007, id_router_008, id_router_009, id_router_010
altera_merlin_traffic_limiter as limiter, limiter_001, limiter_002
altera_reset_controller as rst_controller, rst_controller_001, rst_controller_002
DE3_QSYS_cmd_xbar_demux as cmd_xbar_demux
DE3_QSYS_cmd_xbar_demux_001 as cmd_xbar_demux_001
DE3_QSYS_cmd_xbar_mux as cmd_xbar_mux, cmd_xbar_mux_001
DE3_QSYS_rsp_xbar_demux as rsp_xbar_demux, rsp_xbar_demux_001
DE3_QSYS_rsp_xbar_demux_002 as rsp_xbar_demux_002, rsp_xbar_demux_003
DE3_QSYS_rsp_xbar_mux as rsp_xbar_mux
DE3_QSYS_rsp_xbar_mux_001 as rsp_xbar_mux_001
DE3_QSYS_cmd_xbar_demux_002 as cmd_xbar_demux_002
DE3_QSYS_rsp_xbar_demux_004 as rsp_xbar_demux_004, rsp_xbar_demux_005, rsp_xbar_demux_006, rsp_xbar_demux_007, rsp_xbar_demux_008, rsp_xbar_demux_009, rsp_xbar_demux_010
DE3_QSYS_rsp_xbar_mux_002 as rsp_xbar_mux_002
altera_merlin_width_adapter as width_adapter, width_adapter_001
altera_avalon_st_handshake_clock_crosser as crosser, crosser_001, crosser_002, crosser_003
DE3_QSYS_irq_mapper as irq_mapper
altera_irq_clock_crosser as irq_synchronizer, irq_synchronizer_001
DE3_QSYS_cpu
altera_nios2_qsys v11.0
DE3_QSYS_sysid
altera_avalon_sysid_qsys v11.0
DE3_QSYS_uniphy_ddr2
altera_mem_if_ddr2_emif v11.0		 DE3_QSYS_uniphy_ddr2_c0 as c0
DE3_QSYS_uniphy_ddr2_p0 as p0
DE3_QSYS_jtag_uart
altera_avalon_jtag_uart v11.0
DE3_QSYS_onchip_mem
altera_avalon_onchip_memory2 v11.0
altera_avalon_mm_clock_crossing_bridge
altera_avalon_mm_clock_crossing_bridge v11.0
DE3_QSYS_timer
altera_avalon_timer v11.0
DE3_QSYS_ddr2_i2c_scl
altera_avalon_pio v11.0
DE3_QSYS_ddr2_i2c_sda
altera_avalon_pio v11.0
DE3_QSYS_pio_led
altera_avalon_pio v11.0
DE3_QSYS_pio_button
altera_avalon_pio v11.0
altera_merlin_master_translator
altera_merlin_master_translator v11.0
altera_merlin_slave_translator
altera_merlin_slave_translator v11.0
altera_merlin_master_agent
altera_merlin_master_agent v11.0
altera_merlin_slave_agent
altera_merlin_slave_agent v11.0
altera_avalon_sc_fifo
altera_avalon_sc_fifo v11.0
DE3_QSYS_addr_router
altera_merlin_router v11.0
DE3_QSYS_addr_router_001
altera_merlin_router v11.0
DE3_QSYS_id_router
altera_merlin_router v11.0
DE3_QSYS_id_router_002
altera_merlin_router v11.0
DE3_QSYS_id_router_003
altera_merlin_router v11.0
DE3_QSYS_addr_router_002
altera_merlin_router v11.0
DE3_QSYS_id_router_004
altera_merlin_router v11.0
altera_merlin_traffic_limiter
altera_merlin_traffic_limiter v11.0
altera_reset_controller
altera_reset_controller v11.0
DE3_QSYS_cmd_xbar_demux
altera_merlin_demultiplexer v11.0
DE3_QSYS_cmd_xbar_demux_001
altera_merlin_demultiplexer v11.0
DE3_QSYS_cmd_xbar_mux
altera_merlin_multiplexer v11.0
DE3_QSYS_rsp_xbar_demux
altera_merlin_demultiplexer v11.0
DE3_QSYS_rsp_xbar_demux_002
altera_merlin_demultiplexer v11.0
DE3_QSYS_rsp_xbar_mux
altera_merlin_multiplexer v11.0
DE3_QSYS_rsp_xbar_mux_001
altera_merlin_multiplexer v11.0
DE3_QSYS_cmd_xbar_demux_002
altera_merlin_demultiplexer v11.0
DE3_QSYS_rsp_xbar_demux_004
altera_merlin_demultiplexer v11.0
DE3_QSYS_rsp_xbar_mux_002
altera_merlin_multiplexer v11.0
altera_merlin_width_adapter
altera_merlin_width_adapter v11.0
altera_avalon_st_handshake_clock_crosser
altera_avalon_st_handshake_clock_crosser v11.0
DE3_QSYS_irq_mapper
altera_irq_mapper v11.0
altera_irq_clock_crosser
altera_irq_clock_crosser v11.0
DE3_QSYS_uniphy_ddr2_c0
altera_mem_if_nextgen_ddr2_controller v11.0		 alt_mem_if_nextgen_ddr2_controller_core as ng0
alt_mem_ddrx_mm_st_converter as a0
DE3_QSYS_uniphy_ddr2_p0
altera_mem_if_ddr2_phy v11.0
alt_mem_if_nextgen_ddr2_controller_core
altera_mem_if_nextgen_ddr2_controller_core v11.0
alt_mem_ddrx_mm_st_converter
alt_mem_ddrx_mm_st_converter v11.0
Generation Messages
2011.07.29.17:10:37 [Debug] DE3_QSYS.altera_nios2_qsys: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.07.29.17:22:45 [Debug] DE3_QSYS.cpu: Timing: VAL:1/0.047s ELA:1/0.000s 2011.07.29.17:22:45 [Info] DE3_QSYS.sysid: System ID will no longer be automatically assigned. 2011.07.29.17:22:45 [Info] DE3_QSYS.sysid: Time stamp will be automatically updated when this component is generated. 2011.07.29.17:22:45 [Debug] DE3_QSYS.sysid: Timing: VAL:2/0.000s/0.000s 2011.07.29.17:22:44 [Info] DE3_QSYS.uniphy_ddr2: Auto interface leveling mode set to 'Leveling' 2011.07.29.17:10:40 [Debug] DE3_QSYS.uniphy_ddr2.c0.altera_mem_if_nextgen_ddr2_controller_core: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.c0.ng0: Timing: VAL:1/0.032s ELA:1/0.015s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.c0.afi_reset: Timing: ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.c0.afi_clk: Timing: ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.c0.afi_half_clk: Timing: ELA:1/0.000s 2011.07.29.17:10:41 [Debug] DE3_QSYS.uniphy_ddr2.c0.alt_mem_ddrx_mm_st_converter: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.c0.a0: Timing: VAL:1/0.000s ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.c0: Timing: VAL:1/0.031s COM:1/0.125s 2011.07.29.17:10:40 [Debug] DE3_QSYS.uniphy_ddr2.altera_mem_if_ddr2_phy: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.p0: Timing: VAL:1/0.235s ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.pll_ref_clk: Timing: ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.global_reset: Timing: ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.soft_reset: Timing: ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.afi_clk: Timing: ELA:2/0.007s/0.015s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.afi_half_clk: Timing: ELA:2/0.000s/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2.afi_reset: Timing: ELA:1/0.000s 2011.07.29.17:22:45 [Debug] DE3_QSYS.uniphy_ddr2: Timing: VAL:1/0.266s COM:1/0.813s 2011.07.29.17:22:45 [Info] DE3_QSYS.onchip_mem: Memory will be initialized from onchip_mem.hex 2011.07.29.17:22:45 [Debug] DE3_QSYS.clock_crossing_bridge: Timing: ELA:1/0.000s 2011.07.29.17:22:45 [Info] DE3_QSYS.ddr2_i2c_sda: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2011.07.29.17:22:45 [Info] DE3_QSYS.pio_button: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2011.07.29.17:22:45 [Info] DE3_QSYS: Generating DE3_QSYS "DE3_QSYS" for QUARTUS_SYNTH 2011.07.29.17:22:46 [Debug] DE3_QSYS: queue size: 0 starting:DE3_QSYS "DE3_QSYS" 2011.07.29.17:22:47 [Debug] Transform: PipelineBridgeSwap 2011.07.29.17:22:48 [Info] pipeline_bridge_swap_transform: After transform: 12 modules, 40 connections 2011.07.29.17:22:48 [Debug] Transform: ClockCrossingBridgeSwap 2011.07.29.17:22:49 [Debug] Transform: QsysBetaIPSwap 2011.07.29.17:22:50 [Debug] Transform: CustomInstructionTransform 2011.07.29.17:22:51 [Info] No custom instruction connections, skipping transform 2011.07.29.17:22:51 [Debug] Transform: TristateConduitUpgradeTransform 2011.07.29.17:22:54 [Debug] Transform: TranslatorTransform 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Progress] min: 0 2011.07.29.17:22:55 [Progress] max: 1 2011.07.29.17:22:55 [Progress] current: 1 2011.07.29.17:22:55 [Info] merlin_translator_transform: After transform: 26 modules, 82 connections 2011.07.29.17:22:55 [Debug] Transform: DomainTransform 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_jtag_debug_module_translator.avalon_anti_slave_0 and cpu.jtag_debug_module 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces onchip_mem_s1_translator.avalon_anti_slave_0 and onchip_mem.s1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces uniphy_ddr2_avl_translator.avalon_anti_slave_0 and uniphy_ddr2.avl 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_bridge_s0_translator.avalon_anti_slave_0 and clock_crossing_bridge.s0 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_bridge.m0 and clock_crossing_bridge_m0_translator.avalon_anti_master_0 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Progress] min: 0 2011.07.29.17:22:57 [Progress] max: 1 2011.07.29.17:22:57 [Progress] current: 1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces timer_s1_translator.avalon_anti_slave_0 and timer.s1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces ddr2_i2c_scl_s1_translator.avalon_anti_slave_0 and ddr2_i2c_scl.s1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces ddr2_i2c_sda_s1_translator.avalon_anti_slave_0 and ddr2_i2c_sda.s1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces pio_led_s1_translator.avalon_anti_slave_0 and pio_led.s1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces pio_button_s1_translator.avalon_anti_slave_0 and pio_button.s1 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave 2011.07.29.17:22:57 [Debug] Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave 2011.07.29.17:22:57 [Info] merlin_domain_transform: After transform: 54 modules, 225 connections 2011.07.29.17:22:57 [Debug] Transform: RouterTransform 2011.07.29.17:22:58 [Progress] min: 0 2011.07.29.17:22:58 [Progress] max: 1 2011.07.29.17:22:58 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Progress] min: 0 2011.07.29.17:22:59 [Progress] max: 1 2011.07.29.17:22:59 [Progress] current: 1 2011.07.29.17:22:59 [Info] merlin_router_transform: After transform: 68 modules, 267 connections 2011.07.29.17:22:59 [Debug] Transform: TrafficLimiterTransform 2011.07.29.17:23:00 [Progress] min: 0 2011.07.29.17:23:00 [Progress] max: 1 2011.07.29.17:23:00 [Progress] current: 1 2011.07.29.17:23:00 [Progress] min: 0 2011.07.29.17:23:00 [Progress] max: 1 2011.07.29.17:23:00 [Progress] current: 1 2011.07.29.17:23:00 [Progress] min: 0 2011.07.29.17:23:00 [Progress] max: 1 2011.07.29.17:23:00 [Progress] current: 1 2011.07.29.17:23:00 [Info] merlin_traffic_limiter_transform: After transform: 71 modules, 279 connections 2011.07.29.17:23:00 [Debug] Transform: BurstTransform 2011.07.29.17:23:02 [Debug] Transform: ResetAdaptation 2011.07.29.17:23:03 [Progress] min: 0 2011.07.29.17:23:03 [Progress] max: 1 2011.07.29.17:23:03 [Progress] current: 1 2011.07.29.17:23:03 [Progress] min: 0 2011.07.29.17:23:03 [Progress] max: 1 2011.07.29.17:23:03 [Progress] current: 1 2011.07.29.17:23:03 [Progress] min: 0 2011.07.29.17:23:03 [Progress] max: 1 2011.07.29.17:23:03 [Progress] current: 1 2011.07.29.17:23:03 [Info] reset_adaptation_transform: After transform: 74 modules, 285 connections 2011.07.29.17:23:03 [Debug] Transform: NetworkToSwitchTransform 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Progress] min: 0 2011.07.29.17:23:05 [Progress] max: 1 2011.07.29.17:23:05 [Progress] current: 1 2011.07.29.17:23:05 [Info] merlin_network_to_switch_transform: After transform: 100 modules, 339 connections 2011.07.29.17:23:05 [Debug] Transform: WidthTransform 2011.07.29.17:23:07 [Progress] min: 0 2011.07.29.17:23:07 [Progress] max: 1 2011.07.29.17:23:07 [Progress] current: 1 2011.07.29.17:23:07 [Progress] min: 0 2011.07.29.17:23:07 [Progress] max: 1 2011.07.29.17:23:07 [Progress] current: 1 2011.07.29.17:23:07 [Info] merlin_width_transform: After transform: 102 modules, 345 connections 2011.07.29.17:23:07 [Debug] Transform: RouterTableTransform 2011.07.29.17:23:08 [Debug] Transform: ClockCrossingTransform 2011.07.29.17:23:10 [Info] Inserting clock-crossing logic between cmd_xbar_demux.src1 and cmd_xbar_mux_001.sink0 2011.07.29.17:23:10 [Progress] min: 0 2011.07.29.17:23:10 [Progress] max: 1 2011.07.29.17:23:10 [Progress] current: 1 2011.07.29.17:23:10 [Info] Inserting clock-crossing logic between cmd_xbar_demux_001.src1 and cmd_xbar_mux_001.sink1 2011.07.29.17:23:10 [Progress] min: 0 2011.07.29.17:23:10 [Progress] max: 1 2011.07.29.17:23:10 [Progress] current: 1 2011.07.29.17:23:10 [Info] Inserting clock-crossing logic between rsp_xbar_demux_001.src0 and rsp_xbar_mux.sink1 2011.07.29.17:23:10 [Progress] min: 0 2011.07.29.17:23:10 [Progress] max: 1 2011.07.29.17:23:10 [Progress] current: 1 2011.07.29.17:23:10 [Info] Inserting clock-crossing logic between rsp_xbar_demux_001.src1 and rsp_xbar_mux_001.sink1 2011.07.29.17:23:10 [Progress] min: 0 2011.07.29.17:23:10 [Progress] max: 1 2011.07.29.17:23:10 [Progress] current: 1 2011.07.29.17:23:10 [Info] com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform: After transform: 106 modules, 365 connections 2011.07.29.17:23:10 [Debug] Transform: PipelineTransform 2011.07.29.17:23:11 [Debug] Transform: TrafficLimiterUpdateTransform 2011.07.29.17:23:13 [Info] limiter_update_transform: After transform: 106 modules, 368 connections 2011.07.29.17:23:13 [Debug] Transform: InterruptMapperTransform 2011.07.29.17:23:14 [Progress] min: 0 2011.07.29.17:23:14 [Progress] max: 1 2011.07.29.17:23:14 [Progress] current: 1 2011.07.29.17:23:15 [Info] merlin_interrupt_mapper_transform: After transform: 107 modules, 371 connections 2011.07.29.17:23:15 [Debug] Transform: InterruptSyncTransform 2011.07.29.17:23:16 [Progress] min: 0 2011.07.29.17:23:16 [Progress] max: 1 2011.07.29.17:23:16 [Progress] current: 1 2011.07.29.17:23:16 [Progress] min: 0 2011.07.29.17:23:16 [Progress] max: 1 2011.07.29.17:23:16 [Progress] current: 1 2011.07.29.17:23:16 [Info] merlin_interrupt_sync_transform: After transform: 109 modules, 381 connections 2011.07.29.17:23:16 [Debug] Transform: InterruptFanoutTransform 2011.07.29.17:23:19 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:dataavailable (dataavailable)" 2011.07.29.17:23:19 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:readyfordata (readyfordata)" 2011.07.29.17:23:19 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_nios2_qsys "submodules/DE3_QSYS_cpu" 2011.07.29.17:23:19 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sysid_qsys "submodules/DE3_QSYS_sysid" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_mem_if_ddr2_emif "submodules/DE3_QSYS_uniphy_ddr2" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_jtag_uart "submodules/DE3_QSYS_jtag_uart" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_onchip_memory2 "submodules/DE3_QSYS_onchip_mem" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_timer "submodules/DE3_QSYS_timer" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_pio "submodules/DE3_QSYS_ddr2_i2c_scl" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_pio "submodules/DE3_QSYS_ddr2_i2c_sda" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_pio "submodules/DE3_QSYS_pio_led" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_pio "submodules/DE3_QSYS_pio_button" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_addr_router" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_addr_router_001" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_002" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_003" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_addr_router_002" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_cmd_xbar_demux" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_cmd_xbar_demux_001" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_multiplexer "submodules/DE3_QSYS_cmd_xbar_mux" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_multiplexer "submodules/DE3_QSYS_cmd_xbar_mux" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_002" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_002" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_multiplexer "submodules/DE3_QSYS_rsp_xbar_mux" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_multiplexer "submodules/DE3_QSYS_rsp_xbar_mux_001" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_cmd_xbar_demux_002" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_multiplexer "submodules/DE3_QSYS_rsp_xbar_mux_002" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_irq_mapper "submodules/DE3_QSYS_irq_mapper" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2011.07.29.17:23:20 [Debug] DE3_QSYS: "DE3_QSYS" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2011.07.29.17:23:20 [Debug] DE3_QSYS: queue size: 98 starting:altera_nios2_qsys "submodules/DE3_QSYS_cpu" 2011.07.29.17:23:20 [Info] cpu: Starting RTL generation for module 'DE3_QSYS_cpu' 2011.07.29.17:23:20 [Info] cpu: Generation command is [exec C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/11.0/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/11.0/quartus/sopc_builder/bin/europa -I C:/altera/11.0/quartus/sopc_builder/bin/perl_lib -I C:/altera/11.0/quartus/sopc_builder/bin -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=DE3_QSYS_cpu --dir=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0001_cpu_gen/ --quartus_dir=C:/altera/11.0/quartus --verilog --config=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0001_cpu_gen//DE3_QSYS_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:21 (*) Starting Nios II generation 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:21 (*) Checking for encrypted license (non-evaluation). 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:33 (*) Encrypted license found. SOF will not be time-limited. 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:33 (*) Elaborating CPU configuration settings 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:33 (*) Creating all objects for CPU 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:33 (*) Testbench 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:33 (*) Instruction decoding 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:33 (*) Instruction fields 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:33 (*) Instruction decodes 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:34 (*) Signals for RTL simulation waveforms 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:34 (*) Instruction controls 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:34 (*) Pipeline frontend 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:35 (*) Pipeline backend 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:39 (*) Generating RTL from CPU objects 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:43 (*) Creating encrypted RTL 2011.07.29.17:23:44 [Info] cpu: # 2011.07.29 17:23:44 (*) Done Nios II generation 2011.07.29.17:23:44 [Info] cpu: Done RTL generation for module 'DE3_QSYS_cpu' 2011.07.29.17:23:44 [Info] cpu: "DE3_QSYS" instantiated altera_nios2_qsys "cpu" 2011.07.29.17:23:44 [Debug] DE3_QSYS: queue size: 97 starting:altera_avalon_sysid_qsys "submodules/DE3_QSYS_sysid" 2011.07.29.17:23:44 [Info] sysid: "DE3_QSYS" instantiated altera_avalon_sysid_qsys "sysid" 2011.07.29.17:23:44 [Debug] DE3_QSYS: queue size: 96 starting:altera_mem_if_ddr2_emif "submodules/DE3_QSYS_uniphy_ddr2" 2011.07.29.17:23:44 [Info] uniphy_ddr2: Running transform AvalonTransform 2011.07.29.17:23:45 [Debug] Transform: PipelineBridgeSwap 2011.07.29.17:23:45 [Info] pipeline_bridge_swap_transform: After transform: 8 modules, 10 connections 2011.07.29.17:23:45 [Debug] Transform: ClockCrossingBridgeSwap 2011.07.29.17:23:46 [Debug] Transform: QsysBetaIPSwap 2011.07.29.17:23:46 [Debug] Transform: CustomInstructionTransform 2011.07.29.17:23:47 [Info] No custom instruction connections, skipping transform 2011.07.29.17:23:47 [Debug] Transform: TristateConduitUpgradeTransform 2011.07.29.17:23:48 [Debug] Transform: TranslatorTransform 2011.07.29.17:23:48 [Info] No Avalon connections, skipping transform 2011.07.29.17:23:48 [Debug] Transform: DomainTransform 2011.07.29.17:23:49 [Debug] Transform: RouterTransform 2011.07.29.17:23:49 [Debug] Transform: TrafficLimiterTransform 2011.07.29.17:23:50 [Debug] Transform: BurstTransform 2011.07.29.17:23:50 [Debug] Transform: ResetAdaptation 2011.07.29.17:23:50 [Debug] Transform: NetworkToSwitchTransform 2011.07.29.17:23:51 [Debug] Transform: WidthTransform 2011.07.29.17:23:52 [Debug] Transform: RouterTableTransform 2011.07.29.17:23:52 [Debug] Transform: ClockCrossingTransform 2011.07.29.17:23:53 [Debug] Transform: TrafficLimiterUpdateTransform 2011.07.29.17:23:53 [Debug] Transform: InterruptMapperTransform 2011.07.29.17:23:53 [Debug] Transform: InterruptSyncTransform 2011.07.29.17:23:54 [Debug] Transform: InterruptFanoutTransform 2011.07.29.17:23:55 [Info] uniphy_ddr2: Running transform AvalonTransform took 10.312s 2011.07.29.17:23:55 [Debug] uniphy_ddr2: "uniphy_ddr2" reuses altera_mem_if_nextgen_ddr2_controller "submodules/DE3_QSYS_uniphy_ddr2_c0" 2011.07.29.17:23:55 [Debug] uniphy_ddr2: "uniphy_ddr2" reuses altera_mem_if_ddr2_phy "submodules/DE3_QSYS_uniphy_ddr2_p0" 2011.07.29.17:23:55 [Info] uniphy_ddr2: "DE3_QSYS" instantiated altera_mem_if_ddr2_emif "uniphy_ddr2" 2011.07.29.17:23:55 [Debug] DE3_QSYS: queue size: 97 starting:altera_avalon_jtag_uart "submodules/DE3_QSYS_jtag_uart" 2011.07.29.17:23:55 [Info] Starting classic module elaboration. 2011.07.29.17:23:57 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0003_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:23:59 [Info] Finished elaborating classic module. 2011.07.29.17:23:59 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0003_sopclgen/yysystem.ptf 2011.07.29.17:23:59 [Info] Running sopc_builder... 2011.07.29.17:24:01 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0003_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:03 [Progress] No .sopc_builder configuration file(!) 2011.07.29.17:24:03 [Progress] . 2011.07.29.17:24:04 [Progress] # 2011.07.29 17:24:04 (*) Success: sopc_builder finished. 2011.07.29.17:24:05 [Info] jtag_uart: "DE3_QSYS" instantiated altera_avalon_jtag_uart "jtag_uart" 2011.07.29.17:24:05 [Debug] DE3_QSYS: queue size: 96 starting:altera_avalon_onchip_memory2 "submodules/DE3_QSYS_onchip_mem" 2011.07.29.17:24:05 [Info] Starting classic module elaboration. 2011.07.29.17:24:06 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0004_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:08 [Info] Finished elaborating classic module. 2011.07.29.17:24:08 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0004_sopclgen/yysystem.ptf 2011.07.29.17:24:08 [Info] Running sopc_builder... 2011.07.29.17:24:10 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0004_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:12 [Progress] No .sopc_builder configuration file(!) 2011.07.29.17:24:12 [Progress] . 2011.07.29.17:24:14 [Progress] # 2011.07.29 17:24:14 (*) Success: sopc_builder finished. 2011.07.29.17:24:15 [Info] onchip_mem: "DE3_QSYS" instantiated altera_avalon_onchip_memory2 "onchip_mem" 2011.07.29.17:24:15 [Debug] DE3_QSYS: queue size: 95 starting:altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" 2011.07.29.17:24:15 [Info] clock_crossing_bridge: "DE3_QSYS" instantiated altera_avalon_mm_clock_crossing_bridge "clock_crossing_bridge" 2011.07.29.17:24:15 [Debug] DE3_QSYS: queue size: 94 starting:altera_avalon_timer "submodules/DE3_QSYS_timer" 2011.07.29.17:24:15 [Info] Starting classic module elaboration. 2011.07.29.17:24:16 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0005_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:18 [Info] Finished elaborating classic module. 2011.07.29.17:24:18 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0005_sopclgen/yysystem.ptf 2011.07.29.17:24:18 [Info] Running sopc_builder... 2011.07.29.17:24:19 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0005_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:21 [Progress] No .sopc_builder configuration file(!) 2011.07.29.17:24:21 [Progress] . 2011.07.29.17:24:23 [Progress] # 2011.07.29 17:24:23 (*) Success: sopc_builder finished. 2011.07.29.17:24:23 [Info] timer: "DE3_QSYS" instantiated altera_avalon_timer "timer" 2011.07.29.17:24:23 [Debug] DE3_QSYS: queue size: 93 starting:altera_avalon_pio "submodules/DE3_QSYS_ddr2_i2c_scl" 2011.07.29.17:24:23 [Info] Starting classic module elaboration. 2011.07.29.17:24:25 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0006_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:27 [Info] Finished elaborating classic module. 2011.07.29.17:24:27 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0006_sopclgen/yysystem.ptf 2011.07.29.17:24:27 [Info] Running sopc_builder... 2011.07.29.17:24:28 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0006_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:30 [Progress] No .sopc_builder configuration file(!) 2011.07.29.17:24:30 [Progress] . 2011.07.29.17:24:32 [Progress] # 2011.07.29 17:24:31 (*) Success: sopc_builder finished. 2011.07.29.17:24:32 [Info] ddr2_i2c_scl: "DE3_QSYS" instantiated altera_avalon_pio "ddr2_i2c_scl" 2011.07.29.17:24:32 [Debug] DE3_QSYS: queue size: 92 starting:altera_avalon_pio "submodules/DE3_QSYS_ddr2_i2c_sda" 2011.07.29.17:24:32 [Info] Starting classic module elaboration. 2011.07.29.17:24:33 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0007_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:36 [Info] Finished elaborating classic module. 2011.07.29.17:24:36 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0007_sopclgen/yysystem.ptf 2011.07.29.17:24:36 [Info] Running sopc_builder... 2011.07.29.17:24:37 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0007_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:39 [Progress] No .sopc_builder configuration file(!) 2011.07.29.17:24:39 [Progress] . 2011.07.29.17:24:40 [Progress] # 2011.07.29 17:24:40 (*) Success: sopc_builder finished. 2011.07.29.17:24:41 [Info] ddr2_i2c_sda: "DE3_QSYS" instantiated altera_avalon_pio "ddr2_i2c_sda" 2011.07.29.17:24:41 [Debug] DE3_QSYS: queue size: 91 starting:altera_avalon_pio "submodules/DE3_QSYS_pio_led" 2011.07.29.17:24:41 [Info] Starting classic module elaboration. 2011.07.29.17:24:42 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0008_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:44 [Info] Finished elaborating classic module. 2011.07.29.17:24:44 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0008_sopclgen/yysystem.ptf 2011.07.29.17:24:44 [Info] Running sopc_builder... 2011.07.29.17:24:45 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0008_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:47 [Progress] No .sopc_builder configuration file(!) 2011.07.29.17:24:47 [Progress] . 2011.07.29.17:24:49 [Progress] # 2011.07.29 17:24:49 (*) Success: sopc_builder finished. 2011.07.29.17:24:49 [Info] pio_led: "DE3_QSYS" instantiated altera_avalon_pio "pio_led" 2011.07.29.17:24:49 [Debug] DE3_QSYS: queue size: 90 starting:altera_avalon_pio "submodules/DE3_QSYS_pio_button" 2011.07.29.17:24:49 [Info] Starting classic module elaboration. 2011.07.29.17:24:50 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0009_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:52 [Info] Finished elaborating classic module. 2011.07.29.17:24:52 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0009_sopclgen/yysystem.ptf 2011.07.29.17:24:52 [Info] Running sopc_builder... 2011.07.29.17:24:54 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0009_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5184_7691993211129750310.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.07.29.17:24:55 [Progress] No .sopc_builder configuration file(!) 2011.07.29.17:24:56 [Progress] . 2011.07.29.17:24:57 [Progress] # 2011.07.29 17:24:57 (*) Success: sopc_builder finished. 2011.07.29.17:24:57 [Info] pio_button: "DE3_QSYS" instantiated altera_avalon_pio "pio_button" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 89 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.07.29.17:24:57 [Info] cpu_instruction_master_translator: "DE3_QSYS" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 87 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.07.29.17:24:57 [Info] cpu_jtag_debug_module_translator: "DE3_QSYS" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 75 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.07.29.17:24:57 [Info] cpu_instruction_master_translator_avalon_universal_master_0_agent: "DE3_QSYS" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 73 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.07.29.17:24:57 [Info] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "DE3_QSYS" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 72 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.07.29.17:24:57 [Info] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "DE3_QSYS" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 49 starting:altera_merlin_router "submodules/DE3_QSYS_addr_router" 2011.07.29.17:24:57 [Info] addr_router: "DE3_QSYS" instantiated altera_merlin_router "addr_router" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 48 starting:altera_merlin_router "submodules/DE3_QSYS_addr_router_001" 2011.07.29.17:24:57 [Info] addr_router_001: "DE3_QSYS" instantiated altera_merlin_router "addr_router_001" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 47 starting:altera_merlin_router "submodules/DE3_QSYS_id_router" 2011.07.29.17:24:57 [Info] id_router: "DE3_QSYS" instantiated altera_merlin_router "id_router" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 45 starting:altera_merlin_router "submodules/DE3_QSYS_id_router_002" 2011.07.29.17:24:57 [Info] id_router_002: "DE3_QSYS" instantiated altera_merlin_router "id_router_002" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 44 starting:altera_merlin_router "submodules/DE3_QSYS_id_router_003" 2011.07.29.17:24:57 [Info] id_router_003: "DE3_QSYS" instantiated altera_merlin_router "id_router_003" 2011.07.29.17:24:57 [Debug] DE3_QSYS: queue size: 43 starting:altera_merlin_router "submodules/DE3_QSYS_addr_router_002" 2011.07.29.17:24:58 [Info] addr_router_002: "DE3_QSYS" instantiated altera_merlin_router "addr_router_002" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 42 starting:altera_merlin_router "submodules/DE3_QSYS_id_router_004" 2011.07.29.17:24:58 [Info] id_router_004: "DE3_QSYS" instantiated altera_merlin_router "id_router_004" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 35 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.07.29.17:24:58 [Info] limiter: "DE3_QSYS" instantiated altera_merlin_traffic_limiter "limiter" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 32 starting:altera_reset_controller "submodules/altera_reset_controller" 2011.07.29.17:24:58 [Info] rst_controller: "DE3_QSYS" instantiated altera_reset_controller "rst_controller" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 29 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_cmd_xbar_demux" 2011.07.29.17:24:58 [Info] cmd_xbar_demux: "DE3_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 28 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_cmd_xbar_demux_001" 2011.07.29.17:24:58 [Info] cmd_xbar_demux_001: "DE3_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 27 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_cmd_xbar_mux" 2011.07.29.17:24:58 [Info] cmd_xbar_mux: "DE3_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 25 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux" 2011.07.29.17:24:58 [Info] rsp_xbar_demux: "DE3_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 23 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_002" 2011.07.29.17:24:58 [Info] rsp_xbar_demux_002: "DE3_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 21 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_rsp_xbar_mux" 2011.07.29.17:24:58 [Info] rsp_xbar_mux: "DE3_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux" 2011.07.29.17:24:58 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 20 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_rsp_xbar_mux_001" 2011.07.29.17:24:58 [Info] rsp_xbar_mux_001: "DE3_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" 2011.07.29.17:24:58 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 19 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_cmd_xbar_demux_002" 2011.07.29.17:24:58 [Info] cmd_xbar_demux_002: "DE3_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_002" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 18 starting:altera_merlin_demultiplexer "submodules/DE3_QSYS_rsp_xbar_demux_004" 2011.07.29.17:24:58 [Info] rsp_xbar_demux_004: "DE3_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_004" 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 11 starting:altera_merlin_multiplexer "submodules/DE3_QSYS_rsp_xbar_mux_002" 2011.07.29.17:24:58 [Info] rsp_xbar_mux_002: "DE3_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_002" 2011.07.29.17:24:58 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 10 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.07.29.17:24:58 [Info] width_adapter: "DE3_QSYS" instantiated altera_merlin_width_adapter "width_adapter" 2011.07.29.17:24:58 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 8 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.07.29.17:24:58 [Info] crosser: "DE3_QSYS" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2011.07.29.17:24:58 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v 2011.07.29.17:24:58 [Debug] DE3_QSYS: queue size: 4 starting:altera_irq_mapper "submodules/DE3_QSYS_irq_mapper" 2011.07.29.17:24:59 [Info] irq_mapper: "DE3_QSYS" instantiated altera_irq_mapper "irq_mapper" 2011.07.29.17:24:59 [Debug] DE3_QSYS: queue size: 3 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2011.07.29.17:24:59 [Info] irq_synchronizer: "DE3_QSYS" instantiated altera_irq_clock_crosser "irq_synchronizer" 2011.07.29.17:24:59 [Debug] DE3_QSYS: queue size: 1 starting:altera_mem_if_nextgen_ddr2_controller "submodules/DE3_QSYS_uniphy_ddr2_c0" 2011.07.29.17:24:59 [Info] c0: Running transform AvalonTransform 2011.07.29.17:24:59 [Debug] Transform: PipelineBridgeSwap 2011.07.29.17:24:59 [Info] pipeline_bridge_swap_transform: After transform: 5 modules, 8 connections 2011.07.29.17:24:59 [Debug] Transform: ClockCrossingBridgeSwap 2011.07.29.17:24:59 [Debug] Transform: QsysBetaIPSwap 2011.07.29.17:24:59 [Debug] Transform: CustomInstructionTransform 2011.07.29.17:24:59 [Info] No custom instruction connections, skipping transform 2011.07.29.17:24:59 [Debug] Transform: TristateConduitUpgradeTransform 2011.07.29.17:24:59 [Debug] Transform: TranslatorTransform 2011.07.29.17:24:59 [Info] No Avalon connections, skipping transform 2011.07.29.17:24:59 [Debug] Transform: DomainTransform 2011.07.29.17:24:59 [Debug] Transform: RouterTransform 2011.07.29.17:24:59 [Debug] Transform: TrafficLimiterTransform 2011.07.29.17:24:59 [Debug] Transform: BurstTransform 2011.07.29.17:24:59 [Debug] Transform: ResetAdaptation 2011.07.29.17:25:00 [Debug] Transform: NetworkToSwitchTransform 2011.07.29.17:25:00 [Debug] Transform: WidthTransform 2011.07.29.17:25:00 [Debug] Transform: RouterTableTransform 2011.07.29.17:25:00 [Debug] Transform: ClockCrossingTransform 2011.07.29.17:25:00 [Debug] Transform: TrafficLimiterUpdateTransform 2011.07.29.17:25:00 [Debug] Transform: InterruptMapperTransform 2011.07.29.17:25:00 [Debug] Transform: InterruptSyncTransform 2011.07.29.17:25:00 [Debug] Transform: InterruptFanoutTransform 2011.07.29.17:25:00 [Info] c0: Running transform AvalonTransform took 1.578s 2011.07.29.17:25:00 [Debug] c0: "c0" reuses altera_mem_if_nextgen_ddr2_controller_core "submodules/alt_mem_if_nextgen_ddr2_controller_core" 2011.07.29.17:25:00 [Debug] c0: "c0" reuses alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2011.07.29.17:25:00 [Info] c0: "uniphy_ddr2" instantiated altera_mem_if_nextgen_ddr2_controller "c0" 2011.07.29.17:25:00 [Debug] DE3_QSYS: queue size: 2 starting:altera_mem_if_ddr2_phy "submodules/DE3_QSYS_uniphy_ddr2_p0" 2011.07.29.17:27:21 [Info] p0: "uniphy_ddr2" instantiated altera_mem_if_ddr2_phy "p0" 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_master_agent.sv 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_master_translator.sv 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_reset_controller.sdc 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_reset_controller.v 2011.07.29.17:27:21 [Info] Reusing file E:/SVN/DE3/demo/100/DE3_150/DE3_150_DDR2_UniPHY_1G_1RANK_QSYS/DE3_QSYS/synthesis/submodules/altera_reset_synchronizer.v 2011.07.29.17:27:21 [Debug] DE3_QSYS: queue size: 1 starting:altera_mem_if_nextgen_ddr2_controller_core "submodules/alt_mem_if_nextgen_ddr2_controller_core" 2011.07.29.17:27:22 [Info] ng0: "c0" instantiated altera_mem_if_nextgen_ddr2_controller_core "ng0" 2011.07.29.17:27:22 [Debug] DE3_QSYS: queue size: 0 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2011.07.29.17:27:22 [Info] a0: "c0" instantiated alt_mem_ddrx_mm_st_converter "a0" 2011.07.29.17:27:22 [Info] DE3_QSYS: Done DE3_QSYS" with 44 modules, 281 files, 6538155 bytes