PLL_Name	DE3_QSYS:u0|DE3_QSYS_uniphy_ddr2:uniphy_ddr2|DE3_QSYS_uniphy_ddr2_p0:p0|DE3_QSYS_uniphy_ddr2_p0_controller_phy:controller_phy_inst|DE3_QSYS_uniphy_ddr2_p0_memphy_top:memphy_top_inst|DE3_QSYS_uniphy_ddr2_p0_pll_memphy:upll_memphy|altpll:altpll_component|DE3_QSYS_uniphy_ddr2_p0_pll_memphy_altpll:auto_generated|pll1
PLLJITTER	25
PLLSPEmax	84
PLLSPEmin	-53

