DE4 FPGA Board Configuration



Pin Assignments:




Pin Assignment Table:



CLOCK
Name Location Direction Standard
OSC_50_BANK2 AC35 input 2.5 V
OSC_50_BANK3 AV22 input 1.8 V
OSC_50_BANK4 AV19 input 1.8 V
OSC_50_BANK5 AC6 input 3.0-V PCI-X
OSC_50_BANK6 AB6 input 2.5 V
OSC_50_BANK7 A19 input 1.8 V
GCLKOUT_FPGA AH19 output 1.8 V
GCLKIN A21 input 1.8 V
PLL_CLKIN_p B22 input LVDS



External PLL
Name Location Direction Standard
MAX_I2C_SCLK AP24 output 1.8 V
MAX_I2C_SDAT AN22 inout 1.8 V



LED x 8
Name Location Direction Standard
LED[0] V28 output 2.5 V
LED[1] W28 output 2.5 V
LED[2] R29 output 2.5 V
LED[3] P29 output 2.5 V
LED[4] N29 output 2.5 V
LED[5] M29 output 2.5 V
LED[6] M30 output 2.5 V
LED[7] N30 output 2.5 V



BUTTON x 4, EXT_IO and CPU_RESET_n
Name Location Direction Standard
BUTTON[0] AH5 input 3.0-V PCI-X
BUTTON[1] AG5 input 3.0-V PCI-X
BUTTON[2] AG7 input 3.0-V PCI-X
BUTTON[3] AG8 input 3.0-V PCI-X
EXT_IO AC11 inout 3.0-V PCI-X
CPU_RESET_n V34 input 2.5 V



SLIDE SWITCH x 4
Name Location Direction Standard
SLIDE_SW[0] J7 input 2.5 V
SLIDE_SW[1] K7 input 2.5 V
SLIDE_SW[2] AK6 input 3.0-V PCI-X
SLIDE_SW[3] L7 input 2.5 V



SEG7
Name Location Direction Standard
SEG0_D[0] L34 output 2.5 V
SEG0_D[1] M34 output 2.5 V
SEG0_D[2] M33 output 2.5 V
SEG0_D[3] H31 output 2.5 V
SEG0_D[4] J33 output 2.5 V
SEG0_D[5] L35 output 2.5 V
SEG0_D[6] K32 output 2.5 V
SEG0_DP AL34 output 2.5 V
SEG1_D[0] E31 output 2.5 V
SEG1_D[1] F31 output 2.5 V
SEG1_D[2] G31 output 2.5 V
SEG1_D[3] C34 output 2.5 V
SEG1_D[4] C33 output 2.5 V
SEG1_D[5] D33 output 2.5 V
SEG1_D[6] D34 output 2.5 V
SEG1_DP AL35 output 2.5 V



Fan
Name Location Direction Standard
FAN_CTRL AP20 output 1.8 V



PCIe x 8
Name Location Direction Standard
PCIE_RX_p[0] AU38 input 1.4-V PCML
PCIE_TX_p[0] AT36 output 1.4-V PCML
PCIE_RX_p[1] AR38 input 1.4-V PCML
PCIE_TX_p[1] AP36 output 1.4-V PCML
PCIE_RX_p[2] AJ38 input 1.4-V PCML
PCIE_TX_p[2] AH36 output 1.4-V PCML
PCIE_RX_p[3] AG38 input 1.4-V PCML
PCIE_TX_p[3] AF36 output 1.4-V PCML
PCIE_RX_p[4] AE38 input 1.4-V PCML
PCIE_TX_p[4] AD36 output 1.4-V PCML
PCIE_RX_p[5] AC38 input 1.4-V PCML
PCIE_TX_p[5] AB36 output 1.4-V PCML
PCIE_RX_p[6] U38 input 1.4-V PCML
PCIE_TX_p[6] T36 output 1.4-V PCML
PCIE_RX_p[7] R38 input 1.4-V PCML
PCIE_TX_p[7] P36 output 1.4-V PCML
PCIE_REFCLK_p AN38 input HCSL
PCIE_PREST_n V30 input 2.5 V
PCIE_WAKE_n U35 output 2.5 V
PCIE_SMBCLK R31 input 2.5 V
PCIE_SMBDAT W33 inout 2.5 V



DDR2 SODIMM_0
Name Location Direction Standard DDR2 SODIMM Pin Index
M1_DDR2_dq[4] AW34 inout SSTL-18 Class I 4
M1_DDR2_dq[0] AV32 inout SSTL-18 Class I 5
M1_DDR2_dq[5] AW33 inout SSTL-18 Class I 6
M1_DDR2_dq[1] AV31 inout SSTL-18 Class I 7
M1_DDR2_dm[0] AW31 output SSTL-18 Class I 10
M1_DDR2_dqs_n[0] AW30 inout Differential 1.8-V SSTL Class I 11
M1_DDR2_dqs[0] AV29 inout Differential 1.8-V SSTL Class I 13
M1_DDR2_dq[6] AW28 inout SSTL-18 Class I 14
M1_DDR2_dq[7] AW27 inout SSTL-18 Class I 16
M1_DDR2_dq[2] AW29 inout SSTL-18 Class I 17
M1_DDR2_dq[3] AV28 inout SSTL-18 Class I 19
M1_DDR2_dq[12] AM25 inout SSTL-18 Class I 20
M1_DDR2_dq[13] AN25 inout SSTL-18 Class I 22
M1_DDR2_dq[8] AP25 inout SSTL-18 Class I 23
M1_DDR2_dq[9] AV26 inout SSTL-18 Class I 25
M1_DDR2_dm[1] AW26 output SSTL-18 Class I 26
M1_DDR2_dqs_n[1] AU26 inout Differential 1.8-V SSTL Class I 29
M1_DDR2_ck[0] AP28 inout Differential 1.8-V SSTL Class I 30
M1_DDR2_dqs[1] AT26 inout Differential 1.8-V SSTL Class I 31
M1_DDR2_ck_n[0] AR28 inout Differential 1.8-V SSTL Class I 32
M1_DDR2_dq[10] AU25 inout SSTL-18 Class I 35
M1_DDR2_dq[14] AR25 inout SSTL-18 Class I 36
M1_DDR2_dq[11] AT25 inout SSTL-18 Class I 37
M1_DDR2_dq[15] AN24 inout SSTL-18 Class I 38
M1_DDR2_dq[16] AN23 inout SSTL-18 Class I 43
M1_DDR2_dq[20] AM23 inout SSTL-18 Class I 44
M1_DDR2_dq[17] AP23 inout SSTL-18 Class I 45
M1_DDR2_dq[21] AR23 inout SSTL-18 Class I 46
M1_DDR2_dqs_n[2] AU24 inout Differential 1.8-V SSTL Class I 49
M1_DDR2_dqs[2] AT24 inout Differential 1.8-V SSTL Class I 51
M1_DDR2_dm[2] AU23 output SSTL-18 Class I 52
M1_DDR2_dq[18] AL22 inout SSTL-18 Class I 55
M1_DDR2_dq[22] AT23 inout SSTL-18 Class I 56
M1_DDR2_dq[19] AM22 inout SSTL-18 Class I 57
M1_DDR2_dq[23] AL21 inout SSTL-18 Class I 58
M1_DDR2_dq[24] AJ22 inout SSTL-18 Class I 61
M1_DDR2_dq[28] AK24 inout SSTL-18 Class I 62
M1_DDR2_dq[25] AH23 inout SSTL-18 Class I 63
M1_DDR2_dq[29] AJ23 inout SSTL-18 Class I 64
M1_DDR2_dm[3] AH22 output SSTL-18 Class I 67
M1_DDR2_dqs_n[3] AL23 inout Differential 1.8-V SSTL Class I 68
M1_DDR2_dqs[3] AK23 inout Differential 1.8-V SSTL Class I 70
M1_DDR2_dq[26] AF22 inout SSTL-18 Class I 73
M1_DDR2_dq[30] AF23 inout SSTL-18 Class I 74
M1_DDR2_dq[27] AE23 inout SSTL-18 Class I 75
M1_DDR2_dq[31] AE22 inout SSTL-18 Class I 76
M1_DDR2_cke[0] AT28 output SSTL-18 Class I 79
M1_DDR2_cke[1] AK27 output SSTL-18 Class I 80
M1_DDR2_a[15] AT29 output SSTL-18 Class I 84
M1_DDR2_ba[2] AP27 output SSTL-18 Class I 85
M1_DDR2_a[14] AU29 output SSTL-18 Class I 86
M1_DDR2_a[12] AP26 output SSTL-18 Class I 89
M1_DDR2_a[11] AU28 output SSTL-18 Class I 90
M1_DDR2_a[9] AN27 output SSTL-18 Class I 91
M1_DDR2_a[7] AT27 output SSTL-18 Class I 92
M1_DDR2_a[8] AL27 output SSTL-18 Class I 93
M1_DDR2_a[6] AU27 output SSTL-18 Class I 94
M1_DDR2_a[5] AK26 output SSTL-18 Class I 97
M1_DDR2_a[4] AN26 output SSTL-18 Class I 98
M1_DDR2_a[3] AM26 output SSTL-18 Class I 99
M1_DDR2_a[2] AW23 output SSTL-18 Class I 100
M1_DDR2_a[1] AL25 output SSTL-18 Class I 101
M1_DDR2_a[0] AV23 output SSTL-18 Class I 102
M1_DDR2_a[10] AJ26 output SSTL-18 Class I 105
M1_DDR2_ba[1] AD25 output SSTL-18 Class I 106
M1_DDR2_ba[0] AH26 output SSTL-18 Class I 107
M1_DDR2_ras_n AE21 output SSTL-18 Class I 108
M1_DDR2_we_n AK25 output SSTL-18 Class I 109
M1_DDR2_cs_n[0] AG21 output SSTL-18 Class I 110
M1_DDR2_cas_n AJ25 output SSTL-18 Class I 113
M1_DDR2_odt[0] AG20 output SSTL-18 Class I 114
M1_DDR2_cs_n[1] AE25 output SSTL-18 Class I 115
M1_DDR2_a[13] AD21 output SSTL-18 Class I 116
M1_DDR2_odt[1] AE24 output SSTL-18 Class I 119
M1_DDR2_dq[32] AK17 inout SSTL-18 Class I 123
M1_DDR2_dq[36] AG16 inout SSTL-18 Class I 124
M1_DDR2_dq[33] AM17 inout SSTL-18 Class I 125
M1_DDR2_dq[37] AH17 inout SSTL-18 Class I 126
M1_DDR2_dqs_n[4] AL16 inout Differential 1.8-V SSTL Class I 129
M1_DDR2_dm[4] AL17 output SSTL-18 Class I 130
M1_DDR2_dqs[4] AK16 inout Differential 1.8-V SSTL Class I 131
M1_DDR2_dq[38] AF17 inout SSTL-18 Class I 134
M1_DDR2_dq[34] AH16 inout SSTL-18 Class I 135
M1_DDR2_dq[39] AE17 inout SSTL-18 Class I 136
M1_DDR2_dq[35] AJ16 inout SSTL-18 Class I 137
M1_DDR2_dq[44] AN17 inout SSTL-18 Class I 140
M1_DDR2_dq[40] AR17 inout SSTL-18 Class I 141
M1_DDR2_dq[45] AP17 inout SSTL-18 Class I 142
M1_DDR2_dq[41] AN16 inout SSTL-18 Class I 143
M1_DDR2_dqs_n[5] AR16 inout Differential 1.8-V SSTL Class I 146
M1_DDR2_dm[5] AT16 output SSTL-18 Class I 147
M1_DDR2_dqs[5] AP16 inout Differential 1.8-V SSTL Class I 148
M1_DDR2_dq[42] AU16 inout SSTL-18 Class I 151
M1_DDR2_dq[46] AU15 inout SSTL-18 Class I 152
M1_DDR2_dq[43] AW16 inout SSTL-18 Class I 153
M1_DDR2_dq[47] AT15 inout SSTL-18 Class I 154
M1_DDR2_dq[48] AW11 inout SSTL-18 Class I 157
M1_DDR2_dq[52] AW14 inout SSTL-18 Class I 158
M1_DDR2_dq[49] AW12 inout SSTL-18 Class I 159
M1_DDR2_dq[53] AV14 inout SSTL-18 Class I 160
M1_DDR2_ck[1] AE20 inout Differential 1.8-V SSTL Class I 164
M1_DDR2_ck_n[1] AF20 inout Differential 1.8-V SSTL Class I 166
M1_DDR2_dqs_n[6] AW13 inout Differential 1.8-V SSTL Class I 167
M1_DDR2_dqs[6] AV13 inout Differential 1.8-V SSTL Class I 169
M1_DDR2_dm[6] AU14 output SSTL-18 Class I 170
M1_DDR2_dq[50] AT14 inout SSTL-18 Class I 173
M1_DDR2_dq[54] AU11 inout SSTL-18 Class I 174
M1_DDR2_dq[51] AU12 inout SSTL-18 Class I 175
M1_DDR2_dq[55] AT12 inout SSTL-18 Class I 176
M1_DDR2_dq[56] AP13 inout SSTL-18 Class I 179
M1_DDR2_dq[60] AR14 inout SSTL-18 Class I 180
M1_DDR2_dq[57] AN14 inout SSTL-18 Class I 181
M1_DDR2_dq[61] AP14 inout SSTL-18 Class I 182
M1_DDR2_dm[7] AN13 output SSTL-18 Class I 185
M1_DDR2_dqs_n[7] AT13 inout Differential 1.8-V SSTL Class I 186
M1_DDR2_dqs[7] AR13 inout Differential 1.8-V SSTL Class I 188
M1_DDR2_dq[58] AL15 inout SSTL-18 Class I 189
M1_DDR2_dq[59] AM14 inout SSTL-18 Class I 191
M1_DDR2_dq[62] AL14 inout SSTL-18 Class I 192
M1_DDR2_dq[63] AL13 inout SSTL-18 Class I 194
M1_DDR2_SDA AG24 inout 1.8 V 195
M1_DDR2_SCL AH24 output 1.8 V 197
M1_DDR2_SA[0] AV25 output 1.8 V 198
M1_DDR2_SA[1] AW25 output 1.8 V 200



DDR2 SODIMM_0 RUP/RDN
Name Location Direction Standard
M1_DDR2_oct_rup AF25 input 1.8 V
M1_DDR2_oct_rdn AG25 input 1.8 V



DDR2 SODIMM_1
Name Location Direction Standard DDR2 SODIMM Pin Index
M2_DDR2_dq[4] J12 inout SSTL-18 Class I 4
M2_DDR2_dq[0] F12 inout SSTL-18 Class I 5
M2_DDR2_dq[5] J13 inout SSTL-18 Class I 6
M2_DDR2_dq[1] H13 inout SSTL-18 Class I 7
M2_DDR2_dm[0] H14 output SSTL-18 Class I 10
M2_DDR2_dqs_n[0] E13 inout Differential 1.8-V SSTL Class I 11
M2_DDR2_dqs[0] F13 inout Differential 1.8-V SSTL Class I 13
M2_DDR2_dq[6] G14 inout SSTL-18 Class I 14
M2_DDR2_dq[7] D13 inout SSTL-18 Class I 16
M2_DDR2_dq[2] E14 inout SSTL-18 Class I 17
M2_DDR2_dq[3] F14 inout SSTL-18 Class I 19
M2_DDR2_dq[12] P16 inout SSTL-18 Class I 20
M2_DDR2_dq[13] N16 inout SSTL-18 Class I 22
M2_DDR2_dq[8] P17 inout SSTL-18 Class I 23
M2_DDR2_dq[9] N17 inout SSTL-18 Class I 25
M2_DDR2_dm[1] M17 output SSTL-18 Class I 26
M2_DDR2_dqs_n[1] J16 inout Differential 1.8-V SSTL Class I 29
M2_DDR2_ck[0] L13 inout Differential 1.8-V SSTL Class I 30
M2_DDR2_dqs[1] K16 inout Differential 1.8-V SSTL Class I 31
M2_DDR2_ck_n[0] K13 inout Differential 1.8-V SSTL Class I 32
M2_DDR2_dq[10] L16 inout SSTL-18 Class I 35
M2_DDR2_dq[14] J17 inout SSTL-18 Class I 36
M2_DDR2_dq[11] K17 inout SSTL-18 Class I 37
M2_DDR2_dq[15] H17 inout SSTL-18 Class I 38
M2_DDR2_dq[16] B16 inout SSTL-18 Class I 43
M2_DDR2_dq[20] C16 inout SSTL-18 Class I 44
M2_DDR2_dq[17] A16 inout SSTL-18 Class I 45
M2_DDR2_dq[21] E16 inout SSTL-18 Class I 46
M2_DDR2_dqs_n[2] C15 inout Differential 1.8-V SSTL Class I 49
M2_DDR2_dqs[2] D15 inout Differential 1.8-V SSTL Class I 51
M2_DDR2_dm[2] G15 output SSTL-18 Class I 52
M2_DDR2_dq[18] F15 inout SSTL-18 Class I 55
M2_DDR2_dq[22] G16 inout SSTL-18 Class I 56
M2_DDR2_dq[19] D16 inout SSTL-18 Class I 57
M2_DDR2_dq[23] G17 inout SSTL-18 Class I 58
M2_DDR2_dq[24] C17 inout SSTL-18 Class I 61
M2_DDR2_dq[28] C18 inout SSTL-18 Class I 62
M2_DDR2_dq[25] E17 inout SSTL-18 Class I 63
M2_DDR2_dq[29] D18 inout SSTL-18 Class I 64
M2_DDR2_dm[3] F17 output SSTL-18 Class I 67
M2_DDR2_dqs_n[3] F18 inout Differential 1.8-V SSTL Class I 68
M2_DDR2_dqs[3] G18 inout Differential 1.8-V SSTL Class I 70
M2_DDR2_dq[26] F19 inout SSTL-18 Class I 73
M2_DDR2_dq[30] F20 inout SSTL-18 Class I 74
M2_DDR2_dq[27] G19 inout SSTL-18 Class I 75
M2_DDR2_dq[31] G20 inout SSTL-18 Class I 76
M2_DDR2_cke[0] D11 output SSTL-18 Class I 79
M2_DDR2_cke[1] K12 output SSTL-18 Class I 80
M2_DDR2_a[15] M13 output SSTL-18 Class I 84
M2_DDR2_ba[2] B10 output SSTL-18 Class I 85
M2_DDR2_a[14] K14 output SSTL-18 Class I 86
M2_DDR2_a[12] N15 output SSTL-18 Class I 89
M2_DDR2_a[11] L14 output SSTL-18 Class I 90
M2_DDR2_a[9] M14 output SSTL-18 Class I 91
M2_DDR2_a[7] N13 output SSTL-18 Class I 92
M2_DDR2_a[8] A10 output SSTL-18 Class I 93
M2_DDR2_a[6] A11 output SSTL-18 Class I 94
M2_DDR2_a[5] C11 output SSTL-18 Class I 97
M2_DDR2_a[4] C13 output SSTL-18 Class I 98
M2_DDR2_a[3] R14 output SSTL-18 Class I 99
M2_DDR2_a[2] D14 output SSTL-18 Class I 100
M2_DDR2_a[1] B11 output SSTL-18 Class I 101
M2_DDR2_a[0] B14 output SSTL-18 Class I 102
M2_DDR2_a[10] R18 output SSTL-18 Class I 105
M2_DDR2_ba[1] C14 output SSTL-18 Class I 106
M2_DDR2_ba[0] C12 output SSTL-18 Class I 107
M2_DDR2_ras_n J18 output SSTL-18 Class I 108
M2_DDR2_we_n P18 output SSTL-18 Class I 109
M2_DDR2_cs_n[0] H19 output SSTL-18 Class I 110
M2_DDR2_cas_n A13 output SSTL-18 Class I 113
M2_DDR2_odt[0] D19 output SSTL-18 Class I 114
M2_DDR2_cs_n[1] B13 output SSTL-18 Class I 115
M2_DDR2_a[13] C19 output SSTL-18 Class I 116
M2_DDR2_odt[1] A14 output SSTL-18 Class I 119
M2_DDR2_dq[32] N22 inout SSTL-18 Class I 123
M2_DDR2_dq[36] R22 inout SSTL-18 Class I 124
M2_DDR2_dq[33] M23 inout SSTL-18 Class I 125
M2_DDR2_dq[37] P22 inout SSTL-18 Class I 126
M2_DDR2_dqs_n[4] K23 inout Differential 1.8-V SSTL Class I 129
M2_DDR2_dm[4] P23 output SSTL-18 Class I 130
M2_DDR2_dqs[4] L23 inout Differential 1.8-V SSTL Class I 131
M2_DDR2_dq[38] M24 inout SSTL-18 Class I 134
M2_DDR2_dq[34] K24 inout SSTL-18 Class I 135
M2_DDR2_dq[39] J24 inout SSTL-18 Class I 136
M2_DDR2_dq[35] J25 inout SSTL-18 Class I 137
M2_DDR2_dq[44] G24 inout SSTL-18 Class I 140
M2_DDR2_dq[40] G25 inout SSTL-18 Class I 141
M2_DDR2_dq[45] F24 inout SSTL-18 Class I 142
M2_DDR2_dq[41] C25 inout SSTL-18 Class I 143
M2_DDR2_dqs_n[5] E25 inout Differential 1.8-V SSTL Class I 146
M2_DDR2_dm[5] B25 output SSTL-18 Class I 147
M2_DDR2_dqs[5] F25 inout Differential 1.8-V SSTL Class I 148
M2_DDR2_dq[42] A26 inout SSTL-18 Class I 151
M2_DDR2_dq[46] D25 inout SSTL-18 Class I 152
M2_DDR2_dq[43] C26 inout SSTL-18 Class I 153
M2_DDR2_dq[47] D26 inout SSTL-18 Class I 154
M2_DDR2_dq[48] F27 inout SSTL-18 Class I 157
M2_DDR2_dq[52] H26 inout SSTL-18 Class I 158
M2_DDR2_dq[49] G27 inout SSTL-18 Class I 159
M2_DDR2_dq[53] J26 inout SSTL-18 Class I 160
M2_DDR2_ck[1] B17 inout Differential 1.8-V SSTL Class I 164
M2_DDR2_ck_n[1] A17 inout Differential 1.8-V SSTL Class I 166
M2_DDR2_dqs_n[6] D29 inout Differential 1.8-V SSTL Class I 167
M2_DDR2_dqs[6] E29 inout Differential 1.8-V SSTL Class I 169
M2_DDR2_dm[6] D28 output SSTL-18 Class I 170
M2_DDR2_dq[50] F28 inout SSTL-18 Class I 173
M2_DDR2_dq[54] E28 inout SSTL-18 Class I 174
M2_DDR2_dq[51] H28 inout SSTL-18 Class I 175
M2_DDR2_dq[55] G29 inout SSTL-18 Class I 176
M2_DDR2_dq[56] C29 inout SSTL-18 Class I 179
M2_DDR2_dq[60] A27 inout SSTL-18 Class I 180
M2_DDR2_dq[57] A31 inout SSTL-18 Class I 181
M2_DDR2_dq[61] A28 inout SSTL-18 Class I 182
M2_DDR2_dm[7] C30 output SSTL-18 Class I 185
M2_DDR2_dqs_n[7] B28 inout Differential 1.8-V SSTL Class I 186
M2_DDR2_dqs[7] C28 inout Differential 1.8-V SSTL Class I 188
M2_DDR2_dq[58] C27 inout SSTL-18 Class I 189
M2_DDR2_dq[59] D27 inout SSTL-18 Class I 191
M2_DDR2_dq[62] B29 inout SSTL-18 Class I 192
M2_DDR2_dq[63] B31 inout SSTL-18 Class I 194
M2_DDR2_SDA J15 inout 1.8 V 195
M2_DDR2_SCL K15 output 1.8 V 197
M2_DDR2_SA[0] A18 output 1.8 V 198
M2_DDR2_SA[1] B19 output 1.8 V 200



DDR2 SODIMM_1 RUP/RDN
Name Location Direction Standard
M2_DDR2_oct_rup P14 input 1.8 V
M2_DDR2_oct_rdn N14 input 1.8 V