DE3_HMB_TEST (DE3 Board) Configuration



IO Group Power Configurations:



Configuration Table
IO Group Voltage Connector Type Connector Description Daughter Board
A 3.3V HSTC Top J1, HSTC-A TOP -
B 1.8V DDR2 SODIMM J9, DDR2 SO-DIMM -
C 2.5V HSTC Top J5, HSTC-C TOP HMB(HMB Board)
D 3.3V HSTC Top J7, HSTC-D TOP -


Pin Assignments:




Pin Assignment Table:



CLOCK
Name Location Direction Standard
OSC_BA AN18 input 3.3-V LVTTL
OSC_BB AN16 input 1.8 V
OSC_BC B17 input 2.5 V
OSC_BD B19 input 3.3-V LVTTL
OSC1_50 T33 input 3.3-V LVTTL
OSC2_50 W2 input 3.3-V LVTTL
CLK_OUT V10 output 3.3-V LVTTL
EXT_CLK U2 input 3.3-V LVTTL



LED
Name Location Direction Standard
LEDR[0] AD1 output 3.3-V LVTTL
LEDR[1] AC1 output 3.3-V LVTTL
LEDR[2] AC2 output 3.3-V LVTTL
LEDR[3] AB2 output 3.3-V LVTTL
LEDR[4] AC4 output 3.3-V LVTTL
LEDR[5] AB4 output 3.3-V LVTTL
LEDR[6] AA3 output 3.3-V LVTTL
LEDR[7] AB3 output 3.3-V LVTTL
LEDG[0] AB1 output 3.3-V LVTTL
LEDG[1] AA1 output 3.3-V LVTTL
LEDG[2] Y1 output 3.3-V LVTTL
LEDG[3] Y2 output 3.3-V LVTTL
LEDG[4] Y3 output 3.3-V LVTTL
LEDG[5] W3 output 3.3-V LVTTL
LEDG[6] AA4 output 3.3-V LVTTL
LEDG[7] Y4 output 3.3-V LVTTL
LEDB[0] AB5 output 3.3-V LVTTL
LEDB[1] AB6 output 3.3-V LVTTL
LEDB[2] AA6 output 3.3-V LVTTL
LEDB[3] AA7 output 3.3-V LVTTL
LEDB[4] Y7 output 3.3-V LVTTL
LEDB[5] Y8 output 3.3-V LVTTL
LEDB[6] Y9 output 3.3-V LVTTL
LEDB[7] Y10 output 3.3-V LVTTL



SEG7
Name Location Direction Standard
HEX0[0] W12 output 3.3-V LVTTL
HEX0[1] Y11 output 3.3-V LVTTL
HEX0[2] W10 output 3.3-V LVTTL
HEX0[3] W8 output 3.3-V LVTTL
HEX0[4] W7 output 3.3-V LVTTL
HEX0[5] Y5 output 3.3-V LVTTL
HEX0[6] Y6 output 3.3-V LVTTL
HEX0_DP V3 output 3.3-V LVTTL
HEX1[0] P3 output 3.3-V LVTTL
HEX1[1] N4 output 3.3-V LVTTL
HEX1[2] N3 output 3.3-V LVTTL
HEX1[3] N1 output 3.3-V LVTTL
HEX1[4] M1 output 3.3-V LVTTL
HEX1[5] L1 output 3.3-V LVTTL
HEX1[6] L2 output 3.3-V LVTTL
HEX1_DP V4 output 3.3-V LVTTL



BUTTON
Name Location Direction Standard
Button[0] K1 input 3.3-V LVTTL
Button[1] K2 input 3.3-V LVTTL
Button[2] M4 input 3.3-V LVTTL
Button[3] M3 input 3.3-V LVTTL



SW (SLIDE SWITCH)
Name Location Direction Standard
SW[0] W5 input 3.3-V LVTTL
SW[1] W6 input 3.3-V LVTTL
SW[2] W9 input 3.3-V LVTTL
SW[3] W11 input 3.3-V LVTTL



DIP_SW (DIP SWITCH)
Name Location Direction Standard
DIP_SW[0] R12 input 3.3-V LVTTL
DIP_SW[1] P5 input 3.3-V LVTTL
DIP_SW[2] R4 input 3.3-V LVTTL
DIP_SW[3] R3 input 3.3-V LVTTL
DIP_SW[4] P2 input 3.3-V LVTTL
DIP_SW[5] R1 input 3.3-V LVTTL
DIP_SW[6] T2 input 3.3-V LVTTL
DIP_SW[7] T1 input 3.3-V LVTTL



USB
Name Location Direction Standard
OTG_D[0] Y25 inout 3.3-V LVTTL
OTG_D[1] AA27 inout 3.3-V LVTTL
OTG_D[2] Y26 inout 3.3-V LVTTL
OTG_D[3] AA30 inout 3.3-V LVTTL
OTG_D[4] AB29 inout 3.3-V LVTTL
OTG_D[5] AA28 inout 3.3-V LVTTL
OTG_D[6] Y31 inout 3.3-V LVTTL
OTG_D[7] AA31 inout 3.3-V LVTTL
OTG_D[8] Y32 inout 3.3-V LVTTL
OTG_D[9] Y34 inout 3.3-V LVTTL
OTG_D[10] AB31 inout 3.3-V LVTTL
OTG_D[11] AA32 inout 3.3-V LVTTL
OTG_D[12] AA33 inout 3.3-V LVTTL
OTG_D[13] AD34 inout 3.3-V LVTTL
OTG_D[14] AA34 inout 3.3-V LVTTL
OTG_D[15] AC34 inout 3.3-V LVTTL
OTG_D[16] AB30 inout 3.3-V LVTTL
OTG_D[17] AB33 inout 3.3-V LVTTL
OTG_D[18] AD33 inout 3.3-V LVTTL
OTG_D[19] AB34 inout 3.3-V LVTTL
OTG_D[20] AB32 inout 3.3-V LVTTL
OTG_D[21] V24 inout 3.3-V LVTTL
OTG_D[22] W26 inout 3.3-V LVTTL
OTG_D[23] V25 inout 3.3-V LVTTL
OTG_D[24] W30 inout 3.3-V LVTTL
OTG_D[25] W27 inout 3.3-V LVTTL
OTG_D[26] W31 inout 3.3-V LVTTL
OTG_D[27] W24 inout 3.3-V LVTTL
OTG_D[28] Y23 inout 3.3-V LVTTL
OTG_D[29] Y29 inout 3.3-V LVTTL
OTG_D[30] Y28 inout 3.3-V LVTTL
OTG_D[31] AA29 inout 3.3-V LVTTL
OTG_A[1] N32 output 3.3-V LVTTL
OTG_A[2] L34 output 3.3-V LVTTL
OTG_A[3] M31 output 3.3-V LVTTL
OTG_A[4] N33 output 3.3-V LVTTL
OTG_A[5] M33 output 3.3-V LVTTL
OTG_A[6] M34 output 3.3-V LVTTL
OTG_A[7] N34 output 3.3-V LVTTL
OTG_A[8] N31 output 3.3-V LVTTL
OTG_A[9] P34 output 3.3-V LVTTL
OTG_A[10] P31 output 3.3-V LVTTL
OTG_A[11] P32 output 3.3-V LVTTL
OTG_A[12] R34 output 3.3-V LVTTL
OTG_A[13] R33 output 3.3-V LVTTL
OTG_A[14] R32 output 3.3-V LVTTL
OTG_A[15] T32 output 3.3-V LVTTL
OTG_A[16] U32 output 3.3-V LVTTL
OTG_A[17] R31 output 3.3-V LVTTL
OTG_CS_n P28 output 3.3-V LVTTL
OTG_WE_n N29 output 3.3-V LVTTL
OTG_OE_n N30 output 3.3-V LVTTL
OTG_HC_IRQ P29 input 3.3-V LVTTL
OTG_DC_IRQ R27 input 3.3-V LVTTL
OTG_RESET_n T23 output 3.3-V LVTTL
OTG_HC_DREQ R28 input 3.3-V LVTTL
OTG_HC_DACK R25 output 3.3-V LVTTL
OTG_DC_DREQ R26 input 3.3-V LVTTL
OTG_DC_DACK R24 output 3.3-V LVTTL



SDCARD
Name Location Direction Standard
SD_CMD R10 inout 3.3-V LVTTL
SD_CLK P8 output 3.3-V LVTTL
SD_DAT[0] P7 inout 3.3-V LVTTL
SD_WPn N5 input 3.3-V LVTTL



Connector Name: HSTCA (J1, HSTC-A TOP)
Name Location Direction Standard Pin Index
HSTCA_CLKOUT_n[0] AE19 inout 3.3-V LVTTL 3
HSTCA_CLKIN_n[0] AE32 inout 3.3-V LVTTL 4
HSTCA_CLKOUT_p[0] AD19 inout 3.3-V LVTTL 5
HSTCA_CLKIN_p[0] AE31 inout 3.3-V LVTTL 6
HSTCA_TX_n[0] AC26 inout 3.3-V LVTTL 9
HSTCA_RX_n[0] AL33 inout 3.3-V LVTTL 10
HSTCA_TX_p[0] AC25 inout 3.3-V LVTTL 11
HSTCA_RX_p[0] AL32 inout 3.3-V LVTTL 12
HSTCA_TX_n[1] AD27 inout 3.3-V LVTTL 15
HSTCA_RX_n[1] AH31 inout 3.3-V LVTTL 16
HSTCA_TX_p[1] AD26 inout 3.3-V LVTTL 17
HSTCA_RX_p[1] AH30 inout 3.3-V LVTTL 18
HSTCA_TX_n[2] AE28 inout 3.3-V LVTTL 21
HSTCA_RX_n[2] AL34 inout 3.3-V LVTTL 22
HSTCA_TX_p[2] AE27 inout 3.3-V LVTTL 23
HSTCA_RX_p[2] AM34 inout 3.3-V LVTTL 24
HSTCA_TX_n[3] AF29 inout 3.3-V LVTTL 27
HSTCA_RX_n[3] AJ32 inout 3.3-V LVTTL 28
HSTCA_TX_p[3] AF28 inout 3.3-V LVTTL 29
HSTCA_RX_p[3] AJ31 inout 3.3-V LVTTL 30
HSTCA_TX_n[4] AD29 inout 3.3-V LVTTL 33
HSTCA_RX_n[4] AK34 inout 3.3-V LVTTL 34
HSTCA_TX_p[4] AD28 inout 3.3-V LVTTL 35
HSTCA_RX_p[4] AK33 inout 3.3-V LVTTL 36
HSTCA_TX_n[5] AE30 inout 3.3-V LVTTL 39
HSTCA_RX_n[5] AG32 inout 3.3-V LVTTL 40
HSTCA_TX_p[5] AE29 inout 3.3-V LVTTL 41
HSTCA_RX_p[5] AG31 inout 3.3-V LVTTL 42
HSTCA_TX_n[6] AB27 inout 3.3-V LVTTL 45
HSTCA_RX_n[6] AH34 inout 3.3-V LVTTL 46
HSTCA_TX_p[6] AB26 inout 3.3-V LVTTL 47
HSTCA_RX_p[6] AJ34 inout 3.3-V LVTTL 48
HSTCA_TX_n[7] AB25 inout 3.3-V LVTTL 51
HSTCA_RX_n[7] AF32 inout 3.3-V LVTTL 52
HSTCA_TX_p[7] AB24 inout 3.3-V LVTTL 53
HSTCA_RX_p[7] AF31 inout 3.3-V LVTTL 54
HSTCA_TX_n[8] AD31 inout 3.3-V LVTTL 57
HSTCA_RX_n[8] AG34 inout 3.3-V LVTTL 58
HSTCA_TX_p[8] AD30 inout 3.3-V LVTTL 59
HSTCA_RX_p[8] AH33 inout 3.3-V LVTTL 60
HSTCA_CLKOUT_n[1] AE18 inout 3.3-V LVTTL 63
HSTCA_CLKIN_n[1] AP19 inout 3.3-V LVTTL 64
HSTCA_CLKOUT_p[1] AD18 inout 3.3-V LVTTL 65
HSTCA_CLKIN_p[1] AN19 inout 3.3-V LVTTL 66
HSTCA_TX_n[9] AP21 inout 3.3-V LVTTL 69
HSTCA_RX_n[9] AM21 inout 3.3-V LVTTL 70
HSTCA_TX_p[9] AN21 inout 3.3-V LVTTL 71
HSTCA_RX_p[9] AP20 inout 3.3-V LVTTL 72
HSTCA_TX_n[10] AP22 inout 3.3-V LVTTL 75
HSTCA_RX_n[10] AJ20 inout 3.3-V LVTTL 76
HSTCA_TX_p[10] AN22 inout 3.3-V LVTTL 77
HSTCA_RX_p[10] AJ21 inout 3.3-V LVTTL 78
HSTCA_TX_n[11] AL21 inout 3.3-V LVTTL 81
HSTCA_RX_n[11] AL22 inout 3.3-V LVTTL 82
HSTCA_TX_p[11] AK21 inout 3.3-V LVTTL 83
HSTCA_RX_p[11] AM22 inout 3.3-V LVTTL 84
HSTCA_TX_n[12] AP24 inout 3.3-V LVTTL 87
HSTCA_RX_n[12] AP26 inout 3.3-V LVTTL 88
HSTCA_TX_p[12] AN24 inout 3.3-V LVTTL 89
HSTCA_RX_p[12] AP23 inout 3.3-V LVTTL 90
HSTCA_TX_n[13] AP25 inout 3.3-V LVTTL 93
HSTCA_RX_n[13] AD21 inout 3.3-V LVTTL 94
HSTCA_TX_p[13] AN25 inout 3.3-V LVTTL 95
HSTCA_RX_p[13] AE20 inout 3.3-V LVTTL 96
HSTCA_TX_n[14] AG21 inout 3.3-V LVTTL 99
HSTCA_RX_n[14] AE22 inout 3.3-V LVTTL 100
HSTCA_TX_p[14] AF21 inout 3.3-V LVTTL 101
HSTCA_RX_p[14] AE21 inout 3.3-V LVTTL 102
HSTCA_TX_n[15] AM23 inout 3.3-V LVTTL 105
HSTCA_RX_n[15] AK24 inout 3.3-V LVTTL 106
HSTCA_TX_p[15] AL23 inout 3.3-V LVTTL 107
HSTCA_RX_p[15] AL25 inout 3.3-V LVTTL 108
HSTCA_TX_n[16] AM24 inout 3.3-V LVTTL 111
HSTCA_RX_n[16] AJ23 inout 3.3-V LVTTL 112
HSTCA_TX_p[16] AL24 inout 3.3-V LVTTL 113
HSTCA_RX_p[16] AK22 inout 3.3-V LVTTL 114
HSTCA_TX_n[17] AJ22 inout 3.3-V LVTTL 117
HSTCA_RX_n[17] AH23 inout 3.3-V LVTTL 118
HSTCA_TX_p[17] AH22 inout 3.3-V LVTTL 119
HSTCA_RX_p[17] AJ24 inout 3.3-V LVTTL 120
HSTCA_CLKOUT_2 AP18 inout 3.3-V LVTTL 123
HSTCA_CLKIN_2 AA24 inout 3.3-V LVTTL 124
HSTCA_SDA V29 inout 3.3-V LVTTL 131
HSTCA_SCL W28 output 3.3-V LVTTL 132
HSTCA_TX_n[18] AM28 inout 3.3-V LVTTL 133
HSTCA_RX_n[18] AP27 inout 3.3-V LVTTL 134
HSTCA_TX_p[18] AP29 inout 3.3-V LVTTL 135
HSTCA_RX_p[18] AN27 inout 3.3-V LVTTL 136
HSTCA_TX_n[19] AK25 inout 3.3-V LVTTL 137
HSTCA_RX_n[19] AP28 inout 3.3-V LVTTL 138
HSTCA_TX_p[19] AM26 inout 3.3-V LVTTL 139
HSTCA_RX_p[19] AN28 inout 3.3-V LVTTL 140
HSTCA_TX_n[20] AK27 inout 3.3-V LVTTL 141
HSTCA_RX_n[20] AL27 inout 3.3-V LVTTL 142
HSTCA_TX_p[20] AL28 inout 3.3-V LVTTL 143
HSTCA_RX_p[20] AL26 inout 3.3-V LVTTL 144
HSTCA_TX_n[21] AP32 inout 3.3-V LVTTL 145
HSTCA_RX_n[21] AP31 inout 3.3-V LVTTL 146
HSTCA_TX_p[21] AP30 inout 3.3-V LVTTL 147
HSTCA_RX_p[21] AN31 inout 3.3-V LVTTL 148
HSTCA_TX_n[22] AH25 inout 3.3-V LVTTL 149
HSTCA_RX_n[22] AP33 inout 3.3-V LVTTL 150
HSTCA_TX_p[22] AF23 inout 3.3-V LVTTL 151
HSTCA_RX_p[22] AN33 inout 3.3-V LVTTL 152
HSTCA_TX_n[23] AH26 inout 3.3-V LVTTL 153
HSTCA_RX_n[23] AH24 inout 3.3-V LVTTL 154
HSTCA_TX_p[23] AF24 inout 3.3-V LVTTL 155
HSTCA_RX_p[23] AG24 inout 3.3-V LVTTL 156
HSTCA_TX_n[24] AH27 inout 3.3-V LVTTL 157
HSTCA_RX_n[24] AN30 inout 3.3-V LVTTL 158
HSTCA_TX_p[24] AJ27 inout 3.3-V LVTTL 159
HSTCA_RX_p[24] AM30 inout 3.3-V LVTTL 160
HSTCA_TX_n[25] AJ29 inout 3.3-V LVTTL 161
HSTCA_RX_n[25] AM32 inout 3.3-V LVTTL 162
HSTCA_TX_p[25] AJ26 inout 3.3-V LVTTL 163
HSTCA_RX_p[25] AM31 inout 3.3-V LVTTL 164
HSTCA_TX_n[26] AL29 inout 3.3-V LVTTL 165
HSTCA_RX_n[26] AM19 inout 3.3-V LVTTL 166
HSTCA_TX_p[26] AM29 inout 3.3-V LVTTL 167
HSTCA_RX_p[26] AL19 inout 3.3-V LVTTL 168
HSTCA_TX_n[27] AE24 inout 3.3-V LVTTL 169
HSTCA_RX_n[27] AD22 inout 3.3-V LVTTL 170
HSTCA_TX_p[27] AE23 inout 3.3-V LVTTL 171
HSTCA_RX_p[27] AC22 inout 3.3-V LVTTL 172
HSTCA_TX_n[28] AL20 inout 3.3-V LVTTL 173
HSTCA_RX_n[28] AK19 inout 3.3-V LVTTL 174
HSTCA_TX_p[28] AM18 inout 3.3-V LVTTL 175
HSTCA_RX_p[28] AJ19 inout 3.3-V LVTTL 176
HSTCA_TX_n[29] AK18 inout 3.3-V LVTTL 177
HSTCA_RX_n[29] AF20 inout 3.3-V LVTTL 178
HSTCA_TX_p[29] AL18 inout 3.3-V LVTTL 179
HSTCA_RX_p[29] AF19 inout 3.3-V LVTTL 180



Connector Name: DDR2 (J9, DDR2 SO-DIMM)
Name Location Direction Standard Pin Index
DDR2_DDR2_DQ[4] AE7 inout SSTL-18 Class II 4
DDR2_DDR2_DQ[0] AM1 inout SSTL-18 Class II 5
DDR2_DDR2_DQ[5] AE8 inout SSTL-18 Class II 6
DDR2_DDR2_DQ[1] AM2 inout SSTL-18 Class II 7
DDR2_DDR2_DM[0] AF5 output SSTL-18 Class II 10
DDR2_DDR2_DQS_n[0] AJ3 inout SSTL-18 Class II 11
DDR2_DDR2_DQS_p[0] AJ4 inout SSTL-18 Class II 13
DDR2_DDR2_DQ[6] AC8 inout SSTL-18 Class II 14
DDR2_DDR2_DQ[7] AC9 inout SSTL-18 Class II 16
DDR2_DDR2_DQ[2] AL1 inout SSTL-18 Class II 17
DDR2_DDR2_DQ[3] AL2 inout SSTL-18 Class II 19
DDR2_DDR2_DQ[12] AE5 inout SSTL-18 Class II 20
DDR2_DDR2_DQ[13] AE6 inout SSTL-18 Class II 22
DDR2_DDR2_DQ[8] AG3 inout SSTL-18 Class II 23
DDR2_DDR2_DQ[9] AG4 inout SSTL-18 Class II 25
DDR2_DDR2_DM[1] AB10 output SSTL-18 Class II 26
DDR2_DDR2_DQS_n[1] AK1 inout SSTL-18 Class II 29
DDR2_DDR2_CLK_p[0] AH8 output SSTL-18 Class II 30
DDR2_DDR2_DQS_p[1] AJ2 inout SSTL-18 Class II 31
DDR2_DDR2_CLK_n[0] AJ8 output SSTL-18 Class II 32
DDR2_DDR2_DQ[10] AJ1 inout SSTL-18 Class II 35
DDR2_DDR2_DQ[14] AD6 inout SSTL-18 Class II 36
DDR2_DDR2_DQ[11] AH2 inout SSTL-18 Class II 37
DDR2_DDR2_DQ[15] AD7 inout SSTL-18 Class II 38
DDR2_DDR2_DQ[16] AF3 inout SSTL-18 Class II 43
DDR2_DDR2_DQ[20] AC7 inout SSTL-18 Class II 44
DDR2_DDR2_DQ[17] AF4 inout SSTL-18 Class II 45
DDR2_DDR2_DQ[21] AB8 inout SSTL-18 Class II 46
DDR2_DDR2_DQS_n[2] AH1 inout SSTL-18 Class II 49
DDR2_DDR2_DQS_p[2] AG1 inout SSTL-18 Class II 51
DDR2_DDR2_DM[2] AB9 output SSTL-18 Class II 52
DDR2_DDR2_DQ[18] AF1 inout SSTL-18 Class II 55
DDR2_DDR2_DQ[22] AC5 inout SSTL-18 Class II 56
DDR2_DDR2_DQ[19] AF2 inout SSTL-18 Class II 57
DDR2_DDR2_DQ[23] AC6 inout SSTL-18 Class II 58
DDR2_DDR2_DQ[24] AJ15 inout SSTL-18 Class II 61
DDR2_DDR2_DQ[28] AK15 inout SSTL-18 Class II 62
DDR2_DDR2_DQ[25] AH15 inout SSTL-18 Class II 63
DDR2_DDR2_DQ[29] AG15 inout SSTL-18 Class II 64
DDR2_DDR2_DM[3] AN13 output SSTL-18 Class II 67
DDR2_DDR2_DQS_n[3] AJ14 inout SSTL-18 Class II 68
DDR2_DDR2_DQS_p[3] AH14 inout SSTL-18 Class II 70
DDR2_DDR2_DQ[26] AP12 inout SSTL-18 Class II 73
DDR2_DDR2_DQ[30] AP13 inout SSTL-18 Class II 74
DDR2_DDR2_DQ[27] AN12 inout SSTL-18 Class II 75
DDR2_DDR2_DQ[31] AM12 inout SSTL-18 Class II 76
DDR2_DDR2_CKE[0] AF6 output SSTL-18 Class II 79
DDR2_DDR2_CKE[1] AC11 output SSTL-18 Class II 80
DDR2_DDR2_A[15] AA10 output SSTL-18 Class II 84
DDR2_DDR2_BA[2] AP14 output SSTL-18 Class II 85
DDR2_DDR2_A[14] AE15 output SSTL-18 Class II 86
DDR2_DDR2_A[12] AM8 output SSTL-18 Class II 89
DDR2_DDR2_A[11] AJ10 output SSTL-18 Class II 90
DDR2_DDR2_A[9] AM6 output SSTL-18 Class II 91
DDR2_DDR2_A[7] AK6 output SSTL-18 Class II 92
DDR2_DDR2_A[8] AK7 output SSTL-18 Class II 93
DDR2_DDR2_A[6] AJ6 output SSTL-18 Class II 94
DDR2_DDR2_A[5] AJ7 output SSTL-18 Class II 97
DDR2_DDR2_A[4] AF10 output SSTL-18 Class II 98
DDR2_DDR2_A[3] AM14 output SSTL-18 Class II 99
DDR2_DDR2_A[2] AE10 output SSTL-18 Class II 100
DDR2_DDR2_A[1] AL14 output SSTL-18 Class II 101
DDR2_DDR2_A[0] AD13 output SSTL-18 Class II 102
DDR2_DDR2_A[10] AD12 output SSTL-18 Class II 105
DDR2_DDR2_BA[1] AE12 output SSTL-18 Class II 106
DDR2_DDR2_BA[0] AC12 output SSTL-18 Class II 107
DDR2_DDR2_RAS_n AL13 output SSTL-18 Class II 108
DDR2_DDR2_WE_n AM17 output SSTL-18 Class II 109
DDR2_DDR2_CS_n[0] AK13 output SSTL-18 Class II 110
DDR2_DDR2_CAS_n AL17 output SSTL-18 Class II 113
DDR2_DDR2_ODT[0] AM15 output SSTL-18 Class II 114
DDR2_DDR2_CS_n[1] AK16 output SSTL-18 Class II 115
DDR2_DDR2_A[13] AJ16 output SSTL-18 Class II 116
DDR2_DDR2_ODT[1] AL15 output SSTL-18 Class II 119
DDR2_DDR2_DQ[32] AP10 inout SSTL-18 Class II 123
DDR2_DDR2_DQ[36] AP11 inout SSTL-18 Class II 124
DDR2_DDR2_DQ[33] AN10 inout SSTL-18 Class II 125
DDR2_DDR2_DQ[37] AP9 inout SSTL-18 Class II 126
DDR2_DDR2_DQS_n[4] AN9 inout SSTL-18 Class II 129
DDR2_DDR2_DM[4] AF15 output SSTL-18 Class II 130
DDR2_DDR2_DQS_p[4] AM9 inout SSTL-18 Class II 131
DDR2_DDR2_DQ[38] AE14 inout SSTL-18 Class II 134
DDR2_DDR2_DQ[34] AF14 inout SSTL-18 Class II 135
DDR2_DDR2_DQ[39] AE13 inout SSTL-18 Class II 136
DDR2_DDR2_DQ[35] AF13 inout SSTL-18 Class II 137
DDR2_DDR2_DQ[44] AM11 inout SSTL-18 Class II 140
DDR2_DDR2_DQ[40] AL12 inout SSTL-18 Class II 141
DDR2_DDR2_DQ[45] AK10 inout SSTL-18 Class II 142
DDR2_DDR2_DQ[41] AK12 inout SSTL-18 Class II 143
DDR2_DDR2_DQS_n[5] AL11 inout SSTL-18 Class II 146
DDR2_DDR2_DM[5] AP8 output SSTL-18 Class II 147
DDR2_DDR2_DQS_p[5] AL10 inout SSTL-18 Class II 148
DDR2_DDR2_DQ[42] AP7 inout SSTL-18 Class II 151
DDR2_DDR2_DQ[46] AM7 inout SSTL-18 Class II 152
DDR2_DDR2_DQ[43] AN7 inout SSTL-18 Class II 153
DDR2_DDR2_DQ[47] AP6 inout SSTL-18 Class II 154
DDR2_DDR2_DQ[48] AJ12 inout SSTL-18 Class II 157
DDR2_DDR2_DQ[52] AJ13 inout SSTL-18 Class II 158
DDR2_DDR2_DQ[49] AH12 inout SSTL-18 Class II 159
DDR2_DDR2_DQ[53] AG12 inout SSTL-18 Class II 160
DDR2_DDR2_CLK_p[1] AE11 output SSTL-18 Class II 164
DDR2_DDR2_CLK_n[1] AF11 output SSTL-18 Class II 166
DDR2_DDR2_DQS_n[6] AJ11 inout SSTL-18 Class II 167
DDR2_DDR2_DQS_p[6] AH11 inout SSTL-18 Class II 169
DDR2_DDR2_DM[6] AL8 output SSTL-18 Class II 170
DDR2_DDR2_DQ[50] AL9 inout SSTL-18 Class II 173
DDR2_DDR2_DQ[54] AJ9 inout SSTL-18 Class II 174
DDR2_DDR2_DQ[51] AK9 inout SSTL-18 Class II 175
DDR2_DDR2_DQ[55] AL7 inout SSTL-18 Class II 176
DDR2_DDR2_DQ[56] AP4 inout SSTL-18 Class II 179
DDR2_DDR2_DQ[60] AP5 inout SSTL-18 Class II 180
DDR2_DDR2_DQ[57] AN4 inout SSTL-18 Class II 181
DDR2_DDR2_DQ[61] AP2 inout SSTL-18 Class II 182
DDR2_DDR2_DM[7] AN6 output SSTL-18 Class II 185
DDR2_DDR2_DQS_n[7] AP3 inout SSTL-18 Class II 186
DDR2_DDR2_DQS_p[7] AN3 inout SSTL-18 Class II 188
DDR2_DDR2_DQ[58] AM5 inout SSTL-18 Class II 189
DDR2_DDR2_DQ[59] AL5 inout SSTL-18 Class II 191
DDR2_DDR2_DQ[62] AM4 inout SSTL-18 Class II 192
DDR2_DDR2_DQ[63] AL4 inout SSTL-18 Class II 194
DDR2_DDR2_SDA T9 inout 3.3-V LVTTL 195
DDR2_DDR2_SCL T8 input 3.3-V LVTTL 197



Connector Name: HSTCC (J5, HSTC-C TOP)
Connect to: HMB(HMB Board)
Name Location Direction Standard Pin Index
HSTCC_ADC_DCLK L16 output 2.5 V 3
HSTCC_TX_CLK K3 input 2.5 V 4
HSTCC_ADC_DIN K16 output 2.5 V 5
HSTCC_ADC_PENIRQ_n K4 input 2.5 V 6
HSTCC_LCD_DATA[2] L8 output 2.5 V 9
HSTCC_LCD_DATA[7] D2 output 2.5 V 10
HSTCC_LCD_DATA[1] L9 output 2.5 V 11
HSTCC_LCD_DATA[6] D3 output 2.5 V 12
HSTCC_LCD_DATA[0] M9 output 2.5 V 15
HSTCC_LCD_DATA[5] D1 output 2.5 V 16
HSTCC_ADC_CS_n M10 output 2.5 V 17
HSTCC_SCEN C1 output 2.5 V 18
HSTCC_MDC K7 output 2.5 V 21
HSTCC_GRESET G4 output 2.5 V 22
HSTCC_TXD[3] K8 output 2.5 V 23
HSTCC_DEN G5 output 2.5 V 24
HSTCC_TXD[2] J6 output 2.5 V 27
HSTCC_TXD[1] J7 output 2.5 V 29
HSTCC_TXD[0] N10 output 2.5 V 33
HSTCC_LCD_DATA[4] E1 output 2.5 V 34
HSTCC_TX_EN N11 output 2.5 V 35
HSTCC_LCD_DATA[3] E2 output 2.5 V 36
HSTCC_ETH_RESET_N K5 output 2.5 V 39
HSTCC_ADC_DOUT H3 input 2.5 V 40
HSTCC_UART_TXD K6 output 2.5 V 41
HSTCC_ADC_BUSY H4 output 2.5 V 42
HSTCC_UART_RXD N8 input 2.5 V 45
HSTCC_RX_DV G1 input 2.5 V 46
HSTCC_AUD_BCLK N9 output 2.5 V 47
HSTCC_RX_COL F1 input 2.5 V 48
HSTCC_AUD_DACDAT L6 output 2.5 V 51
HSTCC_RXD[3] J3 input 2.5 V 52
HSTCC_AUD_DACLRCK L7 output 2.5 V 53
HSTCC_RXD[2] J4 input 2.5 V 54
HSTCC_AUD_ADCLRCK L4 output 2.5 V 57
HSTCC_RXD[1] H1 input 2.5 V 58
HSTCC_SD_CLK L5 output 2.5 V 59
HSTCC_RXD[0] G2 input 2.5 V 60
HSTCC_VGA_CLOCK K17 output 2.5 V 63
HSTCC_TD_27MHZ A16 input 2.5 V 64
HSTCC_NCLK L17 output 2.5 V 65
HSTCC_RX_CLK B16 output 2.5 V 66
HSTCC_VGA_DATA[9] A15 output 2.5 V 69
HSTCC_RX_CRS A14 input 2.5 V 70
HSTCC_VGA_DATA[8] C14 output 2.5 V 71
HSTCC_RX_ERR B14 input 2.5 V 72
HSTCC_VGA_DATA[7] F15 output 2.5 V 75
HSTCC_TD_HS A13 input 2.5 V 76
HSTCC_VGA_DATA[6] D15 output 2.5 V 77
HSTCC_TD_VS B13 input 2.5 V 78
HSTCC_VGA_DATA[5] D14 output 2.5 V 81
HSTCC_TD_RESET E14 output 2.5 V 82
HSTCC_VGA_DATA[4] E13 output 2.5 V 83
HSTCC_TD_D[7] F14 input 2.5 V 84
HSTCC_VGA_DATA[3] A12 output 2.5 V 87
HSTCC_TD_D[6] A11 input 2.5 V 88
HSTCC_VGA_DATA[2] A9 output 2.5 V 89
HSTCC_TD_D[5] B11 input 2.5 V 90
HSTCC_VGA_DATA[1] K15 output 2.5 V 93
HSTCC_TD_D[4] A10 input 2.5 V 94
HSTCC_VGA_DATA[0] L14 output 2.5 V 95
HSTCC_TD_D[3] B10 input 2.5 V 96
HSTCC_VGA_SYNC K14 output 2.5 V 99
HSTCC_TD_D[2] H14 input 2.5 V 100
HSTCC_VGA_BLANK K13 output 2.5 V 101
HSTCC_TD_D[1] J14 input 2.5 V 102
HSTCC_TD_D[0] C12 input 2.5 V 106
HSTCC_SD_DAT3 D10 inout 2.5 V 107
HSTCC_MDIO G13 inout 2.5 V 111
HSTCC_SDA C11 inout 2.5 V 112
HSTCC_PS2_DAT E11 inout 2.5 V 113
HSTCC_SD_DAT D11 inout 2.5 V 114
HSTCC_PS2_CLK G12 inout 2.5 V 117
HSTCC_SD_CMD F12 inout 2.5 V 118
HSTCC_ID_I2CSCL F11 output 2.5 V 119
HSTCC_ID_I2CDAT F13 inout 2.5 V 120
HSTCC_AUD_XCK D7 output 2.5 V 141
HSTCC_AUD_ADCDAT C9 input 2.5 V 142
HSTCC_I2C_SDAT A3 inout 2.5 V 147
HSTCC_I2C_SCLK B4 output 2.5 V 148



Connector Name: HSTCD (J7, HSTC-D TOP)
Name Location Direction Standard Pin Index
HSTCD_CLKOUT_n[0] L20 inout 3.3-V LVTTL 3
HSTCD_CLKIN_n[0] J34 inout 3.3-V LVTTL 4
HSTCD_CLKOUT_p[0] L19 inout 3.3-V LVTTL 5
HSTCD_CLKIN_p[0] J33 inout 3.3-V LVTTL 6
HSTCD_TX_n[0] J30 inout 3.3-V LVTTL 9
HSTCD_RX_n[0] F32 inout 3.3-V LVTTL 10
HSTCD_TX_p[0] J29 inout 3.3-V LVTTL 11
HSTCD_RX_p[0] F31 inout 3.3-V LVTTL 12
HSTCD_TX_n[1] K28 inout 3.3-V LVTTL 15
HSTCD_RX_n[1] C34 inout 3.3-V LVTTL 16
HSTCD_TX_p[1] K27 inout 3.3-V LVTTL 17
HSTCD_RX_p[1] C33 inout 3.3-V LVTTL 18
HSTCD_TX_n[2] N25 inout 3.3-V LVTTL 21
HSTCD_RX_n[2] H32 inout 3.3-V LVTTL 22
HSTCD_TX_p[2] M24 inout 3.3-V LVTTL 23
HSTCD_RX_p[2] H31 inout 3.3-V LVTTL 24
HSTCD_TX_n[3] M27 inout 3.3-V LVTTL 27
HSTCD_RX_n[3] D34 inout 3.3-V LVTTL 28
HSTCD_TX_p[3] M26 inout 3.3-V LVTTL 29
HSTCD_RX_p[3] D33 inout 3.3-V LVTTL 30
HSTCD_TX_n[4] K30 inout 3.3-V LVTTL 33
HSTCD_RX_n[4] J32 inout 3.3-V LVTTL 34
HSTCD_TX_p[4] K29 inout 3.3-V LVTTL 35
HSTCD_RX_p[4] J31 inout 3.3-V LVTTL 36
HSTCD_TX_n[5] L29 inout 3.3-V LVTTL 39
HSTCD_RX_n[5] E34 inout 3.3-V LVTTL 40
HSTCD_TX_p[5] L28 inout 3.3-V LVTTL 41
HSTCD_RX_p[5] F33 inout 3.3-V LVTTL 42
HSTCD_TX_n[6] M28 inout 3.3-V LVTTL 45
HSTCD_RX_n[6] F34 inout 3.3-V LVTTL 46
HSTCD_TX_p[6] N27 inout 3.3-V LVTTL 47
HSTCD_RX_p[6] G33 inout 3.3-V LVTTL 48
HSTCD_TX_n[7] N26 inout 3.3-V LVTTL 51
HSTCD_RX_n[7] K32 inout 3.3-V LVTTL 52
HSTCD_TX_p[7] P25 inout 3.3-V LVTTL 53
HSTCD_RX_p[7] K31 inout 3.3-V LVTTL 54
HSTCD_TX_n[8] L32 inout 3.3-V LVTTL 57
HSTCD_RX_n[8] G34 inout 3.3-V LVTTL 58
HSTCD_TX_p[8] L31 inout 3.3-V LVTTL 59
HSTCD_RX_p[8] H34 inout 3.3-V LVTTL 60
HSTCD_CLKOUT_n[1] J19 inout 3.3-V LVTTL 63
HSTCD_CLKIN_n[1] A20 inout 3.3-V LVTTL 64
HSTCD_CLKOUT_p[1] K19 inout 3.3-V LVTTL 65
HSTCD_CLKIN_p[1] B20 inout 3.3-V LVTTL 66
HSTCD_TX_n[9] H20 inout 3.3-V LVTTL 69
HSTCD_RX_n[9] F20 inout 3.3-V LVTTL 70
HSTCD_TX_p[9] E20 inout 3.3-V LVTTL 71
HSTCD_RX_p[9] G20 inout 3.3-V LVTTL 72
HSTCD_TX_n[10] A21 inout 3.3-V LVTTL 75
HSTCD_RX_n[10] F21 inout 3.3-V LVTTL 76
HSTCD_TX_p[10] A22 inout 3.3-V LVTTL 77
HSTCD_RX_p[10] G21 inout 3.3-V LVTTL 78
HSTCD_TX_n[11] C23 inout 3.3-V LVTTL 81
HSTCD_RX_n[11] A23 inout 3.3-V LVTTL 82
HSTCD_TX_p[11] B22 inout 3.3-V LVTTL 83
HSTCD_RX_p[11] B23 inout 3.3-V LVTTL 84
HSTCD_TX_n[12] A26 inout 3.3-V LVTTL 87
HSTCD_RX_n[12] A25 inout 3.3-V LVTTL 88
HSTCD_TX_p[12] A24 inout 3.3-V LVTTL 89
HSTCD_RX_p[12] B25 inout 3.3-V LVTTL 90
HSTCD_TX_n[13] J20 inout 3.3-V LVTTL 93
HSTCD_RX_n[13] B26 inout 3.3-V LVTTL 94
HSTCD_TX_p[13] K20 inout 3.3-V LVTTL 95
HSTCD_RX_p[13] C26 inout 3.3-V LVTTL 96
HSTCD_TX_n[14] K22 inout 3.3-V LVTTL 99
HSTCD_RX_n[14] J21 inout 3.3-V LVTTL 100
HSTCD_TX_p[14] K21 inout 3.3-V LVTTL 101
HSTCD_RX_p[14] J22 inout 3.3-V LVTTL 102
HSTCD_TX_n[15] E25 inout 3.3-V LVTTL 105
HSTCD_RX_n[15] D24 inout 3.3-V LVTTL 106
HSTCD_TX_p[15] C24 inout 3.3-V LVTTL 107
HSTCD_RX_p[15] D25 inout 3.3-V LVTTL 108
HSTCD_TX_n[16] C27 inout 3.3-V LVTTL 111
HSTCD_RX_n[16] D23 inout 3.3-V LVTTL 112
HSTCD_TX_p[16] A27 inout 3.3-V LVTTL 113
HSTCD_RX_p[16] E23 inout 3.3-V LVTTL 114
HSTCD_TX_n[17] A29 inout 3.3-V LVTTL 117
HSTCD_RX_n[17] A28 inout 3.3-V LVTTL 118
HSTCD_TX_p[17] C28 inout 3.3-V LVTTL 119
HSTCD_RX_p[17] B28 inout 3.3-V LVTTL 120
HSTCD_CLKOUT_2 A19 inout 3.3-V LVTTL 123
HSTCD_CLKIN_2 M29 inout 3.3-V LVTTL 124
HSTCD_SDA R30 inout 3.3-V LVTTL 131
HSTCD_SCL R29 output 3.3-V LVTTL 132
HSTCD_TX_n[18] H23 inout 3.3-V LVTTL 133
HSTCD_RX_n[18] F23 inout 3.3-V LVTTL 134
HSTCD_TX_p[18] F22 inout 3.3-V LVTTL 135
HSTCD_RX_p[18] G23 inout 3.3-V LVTTL 136
HSTCD_TX_n[19] D27 inout 3.3-V LVTTL 137
HSTCD_RX_n[19] F24 inout 3.3-V LVTTL 138
HSTCD_TX_p[19] F25 inout 3.3-V LVTTL 139
HSTCD_RX_p[19] G24 inout 3.3-V LVTTL 140
HSTCD_TX_n[20] D28 inout 3.3-V LVTTL 141
HSTCD_RX_n[20] D26 inout 3.3-V LVTTL 142
HSTCD_TX_p[20] F26 inout 3.3-V LVTTL 143
HSTCD_RX_p[20] E26 inout 3.3-V LVTTL 144
HSTCD_TX_n[21] A33 inout 3.3-V LVTTL 145
HSTCD_RX_n[21] A31 inout 3.3-V LVTTL 146
HSTCD_TX_p[21] A30 inout 3.3-V LVTTL 147
HSTCD_RX_p[21] B31 inout 3.3-V LVTTL 148
HSTCD_TX_n[22] B29 inout 3.3-V LVTTL 149
HSTCD_RX_n[22] A32 inout 3.3-V LVTTL 150
HSTCD_TX_p[22] C29 inout 3.3-V LVTTL 151
HSTCD_RX_p[22] B32 inout 3.3-V LVTTL 152
HSTCD_TX_n[23] D31 inout 3.3-V LVTTL 153
HSTCD_RX_n[23] C30 inout 3.3-V LVTTL 154
HSTCD_TX_p[23] C31 inout 3.3-V LVTTL 155
HSTCD_RX_p[23] D30 inout 3.3-V LVTTL 156
HSTCD_TX_n[24] G27 inout 3.3-V LVTTL 157
HSTCD_RX_n[24] E28 inout 3.3-V LVTTL 158
HSTCD_TX_p[24] F27 inout 3.3-V LVTTL 159
HSTCD_RX_p[24] F28 inout 3.3-V LVTTL 160
HSTCD_TX_n[25] K24 inout 3.3-V LVTTL 161
HSTCD_RX_n[25] E29 inout 3.3-V LVTTL 162
HSTCD_TX_p[25] J24 inout 3.3-V LVTTL 163
HSTCD_RX_p[25] F29 inout 3.3-V LVTTL 164
HSTCD_TX_n[26] K25 inout 3.3-V LVTTL 165
HSTCD_RX_n[26] C21 inout 3.3-V LVTTL 166
HSTCD_TX_p[26] J25 inout 3.3-V LVTTL 167
HSTCD_RX_p[26] D21 inout 3.3-V LVTTL 168
HSTCD_TX_n[27] K23 inout 3.3-V LVTTL 169
HSTCD_RX_n[27] L23 inout 3.3-V LVTTL 170
HSTCD_TX_p[27] L22 inout 3.3-V LVTTL 171
HSTCD_RX_p[27] M23 inout 3.3-V LVTTL 172
HSTCD_TX_n[28] E22 inout 3.3-V LVTTL 173
HSTCD_RX_n[28] C18 inout 3.3-V LVTTL 174
HSTCD_TX_p[28] D22 inout 3.3-V LVTTL 175
HSTCD_RX_p[28] D18 inout 3.3-V LVTTL 176
HSTCD_TX_n[29] D20 inout 3.3-V LVTTL 177
HSTCD_RX_n[29] E19 inout 3.3-V LVTTL 178
HSTCD_TX_p[29] C20 inout 3.3-V LVTTL 179
HSTCD_RX_p[29] F19 inout 3.3-V LVTTL 180



REGULATOR
Name Location Direction Standard
JVC_CLK AE34 output 3.3-V LVTTL
JVC_CS AE33 output 3.3-V LVTTL
JVC_DATAOUT AC31 output 3.3-V LVTTL
JVC_DATAIN AC32 input 3.3-V LVTTL