The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design tv_pll.v. The design tv_pll.v has Stratix III AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 37037 ps.
When input port ARESET is asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted.