userDefinedSettings |
|
setting_showUnpublishedSettings |
false |
setting_showInternalSettings |
false |
setting_shadowRegisterSets |
0 |
setting_preciseSlaveAccessErrorException |
false |
setting_preciseIllegalMemAccessException |
false |
setting_preciseDivisionErrorException |
false |
setting_performanceCounter |
false |
setting_perfCounterWidth |
_32 |
setting_interruptControllerType |
Internal |
setting_illegalMemAccessDetection |
false |
setting_illegalInstructionsTrap |
false |
setting_fullWaveformSignals |
false |
setting_extraExceptionInfo |
false |
setting_exportPCB |
false |
setting_debugSimGen |
false |
setting_clearXBitsLDNonBypass |
true |
setting_branchPredictionType |
Automatic |
setting_bit31BypassDCache |
true |
setting_bigEndian |
false |
setting_bhtPtrSz |
_8 |
setting_bhtIndexPcOnly |
false |
setting_avalonDebugPortPresent |
false |
setting_alwaysEncrypt |
true |
setting_allowFullAddressRange |
false |
setting_activateTrace |
true |
setting_activateTestEndChecker |
false |
setting_activateMonitors |
true |
setting_activateModelChecker |
false |
setting_HDLSimCachesCleared |
true |
setting_HBreakTest |
false |
resetSlave |
ssram.s1 |
resetOffset |
0 |
muldiv_multiplierType |
EmbeddedMulFast |
muldiv_divider |
true |
mpu_useLimit |
false |
mpu_numOfInstRegion |
8 |
mpu_numOfDataRegion |
8 |
mpu_minInstRegionSize |
_12 |
mpu_minDataRegionSize |
_12 |
mpu_enabled |
false |
mmu_uitlbNumEntries |
_4 |
mmu_udtlbNumEntries |
_6 |
mmu_tlbPtrSz |
_7 |
mmu_tlbNumWays |
_16 |
mmu_processIDNumBits |
_8 |
mmu_enabled |
false |
mmu_autoAssignTlbPtrSz |
true |
mmu_TLBMissExcSlave |
|
mmu_TLBMissExcOffset |
0 |
manuallyAssignCpuID |
false |
internalIrqMaskSystemInfo |
15 |
instSlaveMapParam |
<address-map><slave name='peripheral_clock_bridge.s1' start='0x1000000' end='0x1000080' /><slave name='ddr_clock_bridge.s1' start='0x2000000' end='0x4000000' /><slave name='flash_ssram_pipeline_bridge.s1' start='0x4000000' end='0x6000000' /><slave name='cpu.jtag_debug_module' start='0x6001800' end='0x6002000' /></address-map> |
instAddrWidth |
27 |
impl |
Small |
icache_size |
_4096 |
icache_ramBlockType |
Automatic |
icache_numTCIM |
_0 |
icache_burstType |
None |
exceptionSlave |
ssram.s1 |
exceptionOffset |
32 |
deviceFeaturesSystemInfo |
M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 |
deviceFamilyName |
Cyclone III |
debug_triggerArming |
true |
debug_level |
Level1 |
debug_jtagInstanceID |
0 |
debug_embeddedPLL |
true |
debug_debugReqSignals |
false |
debug_assignJtagInstanceID |
false |
debug_OCIOnchipTrace |
_128 |
dcache_size |
_2048 |
dcache_ramBlockType |
Automatic |
dcache_omitDataMaster |
false |
dcache_numTCDM |
_0 |
dcache_lineSize |
_32 |
dcache_bursts |
false |
dataSlaveMapParam |
<address-map><slave name='peripheral_clock_bridge.s1' start='0x1000000' end='0x1000080' /><slave name='ddr_clock_bridge.s1' start='0x2000000' end='0x4000000' /><slave name='flash_ssram_pipeline_bridge.s1' start='0x4000000' end='0x6000000' /><slave name='descriptor_memory.s1' start='0x6000000' end='0x6001000' /><slave name='cpu.jtag_debug_module' start='0x6001800' end='0x6002000' /><slave name='tse_mac.control_port' start='0x6002000' end='0x6002400' /><slave name='sgdma_tx.csr' start='0x6002400' end='0x6002440' /><slave name='sgdma_rx.csr' start='0x6002440' end='0x6002480' /><slave name='pll.s1' start='0x6002480' end='0x60024A0' /><slave name='jtag_uart.avalon_jtag_slave' start='0x60024A0' end='0x60024A8' /></address-map> |
dataAddrWidth |
27 |
cpuReset |
false |
cpuID |
0 |
clockFrequency |
50000000 |
breakSlave |
cpu.jtag_debug_module |
breakOffset |
32 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |