DE3_SOPC

2010.09.14.21:57:49 Datasheet
Overview
  clk  DE3_SOPC
  clk_ddr2 
   ddr2_i2c_scl
 out_port  
 bidir_port  
 out_port  
 in_port  
 in_port  
 in_port  
   tse_mac
 gm_rx_d  
 gm_rx_dv  
 gm_rx_err  
 gm_tx_d  
 gm_tx_en  
 gm_tx_err  
 m_rx_d  
 m_rx_en  
 m_rx_err  
 m_tx_d  
 m_tx_en  
 m_tx_err  
 m_rx_col  
 m_rx_crs  
 tx_clk  
 rx_clk  
 set_10  
 set_1000  
 ena_10  
 eth_mode  
 mdio_out  
 mdio_oen  
 mdio_in  
 mdc  
   net_i2c_scl
 out_port  
 bidir_port  
Processor
   cpu Nios II 10.0
All Components
   cpu altera_nios2 10.0
   jtag_uart altera_avalon_jtag_uart 10.0
   onchip_mem altera_avalon_onchip_memory2 10.0
   sysid altera_avalon_sysid 10.0
   timer altera_avalon_timer 10.0
   altmemddr altmemddr2 10.0
   ddr2_i2c_scl altera_avalon_pio 10.0
   ddr2_i2c_sda altera_avalon_pio 10.0
   pio_led altera_avalon_pio 10.0
   pio_button altera_avalon_pio 10.0
   pll altera_avalon_pll 10.0
   clock_crossing_bridge altera_avalon_clock_crossing 10.0
   SEG7 SEG7 1.0
   pio_dip_sw altera_avalon_pio 10.0
   pio_sw altera_avalon_pio 10.0
   ddr2_clock_bridge altera_avalon_clock_crossing 10.0
   tse_mac triple_speed_ethernet 10.0
   sgdma_tx altera_avalon_sgdma 10.0
   sgdma_rx altera_avalon_sgdma 10.0
   descriptor_memory altera_avalon_onchip_memory2 10.0
   net_i2c_scl altera_avalon_pio 10.0
   net_i2c_sda altera_avalon_pio 10.0
Memory Map
cpu sgdma_tx sgdma_rx
 instruction_master  data_master  descriptor_read  descriptor_write  m_read  descriptor_read  descriptor_write  m_write
  cpu
jtag_debug_module  0x11022800 0x11022800
  jtag_uart
avalon_jtag_slave  0x100000c8
  onchip_mem
s1  0x11000000
  sysid
control_slave  0x100000c0
  timer
s1  0x10000000
  altmemddr
s1  0x00000000 0x00000000 0x00000000 0x00000000
  ddr2_i2c_scl
s1  0x10000040
  ddr2_i2c_sda
s1  0x10000050
  pio_led
s1  0x10000070
  pio_button
s1  0x10000060
  pll
s1  0x11023480
  SEG7
slave  0x10000020
  pio_dip_sw
s1  0x10000080
  pio_sw
s1  0x10000090
  tse_mac
control_port  0x11023000
  sgdma_tx
csr  0x11023400
  sgdma_rx
csr  0x11023440
  descriptor_memory
s1  0x11020000 0x11020000 0x11020000 0x11020000 0x11020000
  net_i2c_scl
s1  0x100000a0
  net_i2c_sda
s1  0x100000b0

clk

clock_source v10.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2 v10.0
pll c2   cpu
  clk
d_irq   jtag_uart
  irq
data_master   onchip_mem
  s1
d_irq   timer
  irq
data_master   pll
  s1
data_master   clock_crossing_bridge
  s1
instruction_master   ddr2_clock_bridge
  s1
data_master  
  s1
data_master   tse_mac
  control_port
data_master   sgdma_tx
  csr
d_irq  
  csr_irq
data_master   sgdma_rx
  csr
d_irq  
  csr_irq
data_master   descriptor_memory
  s1


Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave altmemddr.s1
resetOffset 0
muldiv_multiplierType DSPBlock
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
internalIrqMaskSystemInfo 15
instSlaveMapParam <address-map><slave name='ddr2_clock_bridge.s1' start='0x0' end='0x10000000' /><slave name='cpu.jtag_debug_module' start='0x11022800' end='0x11023000' /></address-map>
instAddrWidth 29
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave altmemddr.s1
exceptionOffset 32
deviceFeaturesSystemInfo M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 1 MRAM_MEMORY 0 MLAB_MEMORY 1 ESB 0 EPCS 1 DSP 1 EMUL 0 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 1
deviceFamilyName Stratix III
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
dataSlaveMapParam <address-map><slave name='ddr2_clock_bridge.s1' start='0x0' end='0x10000000' /><slave name='clock_crossing_bridge.s1' start='0x10000000' end='0x10000100' /><slave name='onchip_mem.s1' start='0x11000000' end='0x11020000' /><slave name='descriptor_memory.s1' start='0x11020000' end='0x11022000' /><slave name='cpu.jtag_debug_module' start='0x11022800' end='0x11023000' /><slave name='tse_mac.control_port' start='0x11023000' end='0x11023400' /><slave name='sgdma_tx.csr' start='0x11023400' end='0x11023440' /><slave name='sgdma_rx.csr' start='0x11023440' end='0x11023480' /><slave name='pll.s1' start='0x11023480' end='0x110234A0' /></address-map>
dataAddrWidth 29
cpuReset false
cpuID 0
clockFrequency 100000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 100000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x20
RESET_ADDR 0x0
BREAK_ADDR 0x11022820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 1
INST_ADDR_WIDTH 29
DATA_ADDR_WIDTH 29
NUM_OF_SHADOW_REG_SETS 0

jtag_uart

altera_avalon_jtag_uart v10.0
cpu d_irq   jtag_uart
  irq
clock_crossing_bridge m1  
  avalon_jtag_slave
pll c0  
  clk


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

onchip_mem

altera_avalon_onchip_memory2 v10.0
cpu data_master   onchip_mem
  s1
pll c2  
  clk1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Stratix III
dualPort false
initMemContent true
initializationFileName onchip_mem
instanceID NONE
memorySize 131072
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_mem"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 131072u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

sysid

altera_avalon_sysid v10.0
clock_crossing_bridge m1   sysid
  control_slave
pll c0  
  clk


Parameters

id 2081806128
timestamp 1284472663
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 2081806128u
TIMESTAMP 1284472663u

timer

altera_avalon_timer v10.0
cpu d_irq   timer
  irq
clock_crossing_bridge m1  
  s1
pll c0  
  clk


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 20000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 20000000u
LOAD_VALUE 19999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

altmemddr

altmemddr2 v10.0
ddr2_clock_bridge m1   altmemddr
  s1
clk_ddr2 clk  
  refclk
sysclk   ddr2_clock_bridge
  clk_m1


Parameters

pipeline_commands false
debug_en false
export_debug_port false
use_generated_memory_model true
dedicated_memory_clk_phase_label Dedicated memory clock phase:
mem_if_clk_mhz 266.667
quartus_project_exists false
local_if_drate HALF
enable_v72_rsu false
local_if_clk_mhz_label 133.3
new_variant false
mem_if_memtype DDR2 SDRAM
pll_ref_clk_mhz 50.0
mem_if_clk_ps_label (3750 ps)
family Stratix III
project_family Stratix III
speed_grade 3
dedicated_memory_clk_phase 0
pll_ref_clk_ps_label (20000 ps)
avalon_burst_length 1
mem_if_clk_pair_count 2
mem_if_cs_per_dimm 1
pre_latency_label Fix read latency at:
dedicated_memory_clk_en false
mirror_addressing 0
mem_if_bankaddr_width 2
register_control_word_9 0000
mem_if_rowaddr_width 13
mem_dyn_deskew_en false
post_latency_label cycles (0 cycles=minimum latency, non-deterministic)
mem_if_dm_pins_en Yes
local_if_dwidth_label 256
register_control_word_7 0000
register_control_word_8 0000
mem_if_preset DE3 256M 533 SODIMM
mem_if_pchaddr_bit 10
WIDTH_RATIO 4
vendor JEDEC
register_control_word_3 0000
register_control_word_4 0000
chip_or_dimm Unbuffered DIMM
register_control_word_5 0000
register_control_word_6 0000
mem_fmax 266.667
register_control_word_0 0000
register_control_word_size 4
register_control_word_1 0000
register_control_word_2 0000
register_control_word_11 0000
register_control_word_10 0000
mem_if_cs_width 1
mem_if_preset_rlat 0
mem_if_cs_per_rank 1
fast_simulation_en FAST
register_control_word_15 0000
register_control_word_14 0000
mem_if_dwidth 64
mem_if_dq_per_dqs 8
mem_if_coladdr_width 10
register_control_word_13 0000
register_control_word_12 0000
mem_tiha_ps 275
mem_tdsh_ck 0.2
mem_if_trfc_ns 105.0
mem_tqh_ck 0.36
mem_tisa_ps 200
mem_tdss_ck 0.2
mem_trtp_ns 0.0
mem_if_tinit_us 200.0
mem_if_trcd_ns 15.0
mem_if_twtr_ck 2
mem_trrd_ns 0.0
mem_tdqss_ck 0.25
mem_tqhs_ps 400
mem_tdsa_ps 100
mem_tac_ps 500
mem_tdha_ps 175
mem_if_tras_ns 45.0
mem_if_twr_ns 15.0
mem_tdqsck_ps 450
mem_if_trp_ns 15.0
mem_tdqsq_ps 240
mem_if_tmrd_ns 8.0
mem_tfaw_ns 0.0
mem_if_trefi_us 7.8
mem_tcl_40_fmax 266.667
mem_odt 50
mp_WLH_percent 0.6
mem_drv_str Normal
mp_DH_percent 0.5
input_period 0
mp_QH_percent 0.5
mp_QHS_percent 0.5
mem_tcl_30_fmax 266.667
ac_clk_select dedicated
mp_DQSQ_percent 0.65
mp_DS_percent 0.6
pll_reconfig_ports_en false
mem_btype Sequential
mp_IS_percent 0.7
mem_tcl 5.0
mp_DQSS_percent 0.5
export_bank_info false
mp_DSS_percent 0.6
mem_dll_en Yes
ac_phase 240
mem_if_oct_en true
mem_tcl_60_fmax 266.667
mp_DSH_percent 0.6
mem_if_dqsn_en true
enable_mp_calibration true
mp_IH_percent 0.6
mem_tcl_15_fmax 533.0
dll_external false
mem_bl 4
mp_WLS_percent 0.7
mem_tcl_50_fmax 266.667
mp_DQSCK_percent 0.5
mem_tcl_25_fmax 533.0
mem_tcl_20_fmax 533.0
ctl_ecc_en false
ctl_hrb_en false
ref_clk_source clk_ddr2
ctl_powerdn_en false
multicast_wr_en false
auto_powerdn_cycles 0
ctl_self_refresh_en false
shared_sys_clk_source
ctl_latency 5
tool_context SOPC_BUILDER
mem_addr_mapping CHIP_ROW_BANK_COL
burst_merge_en false
user_refresh_en false
qsys_mode false
clk_source_sharing_en false
ctl_lookahead_depth 4
ctl_autopch_en false
ctl_dynamic_bank_allocation false
local_if_type_avalon true
csr_en false
ctl_dynamic_bank_num 4
ctl_auto_correct_en false
auto_powerdn_en false
phy_if_type_afi true
controller_type hp_ctl
max_local_size 4
mem_srtr Normal
mem_mpr_loc Predefined Pattern
dss_tinit_rst_us 200.0
mem_tcl_90_fmax 400.0
mem_rtt_wr Dynamic ODT off
mem_tcl_100_fmax 400.0
mem_pasr Full Array
mem_asrm Manual SR Reference (SRT)
mem_mpr_oper Predefined Pattern
mem_tcl_80_fmax 400.0
mem_drv_impedance RZQ/7
mem_rtt_nom ODT Disabled
mem_tcl_70_fmax 400.0
mem_wtcl 5.0
mem_dll_pch Fast Exit
mem_atcl Disabled
board_settings_valid true
t_IH 0.5
board_intra_DQS_group_skew 0.02
isi_DQS 0.0
addr_cmd_slew_rate 1.0
board_tpd_inter_DIMM 0.05
board_addresscmd_CK_skew 0.0
t_DS_calculated 0.350
isi_addresscmd_hold 0.0
t_IS 0.5
restore_default_toggle false
dqs_dqsn_slew_rate 2.0
dq_slew_rate 1.0
board_inter_DQS_group_skew 0.02
isi_addresscmd_setup 0.0
board_minCK_DQS_skew -0.01
t_IS_calculated 0.500
num_slots_or_devices 1
board_maxCK_DQS_skew 0.01
board_skew_ps 50
t_DH 0.35
ck_ckn_slew_rate 2.0
isi_DQ 0.0
t_IH_calculated 0.500
t_DH_calculated 0.350
t_DS 0.35
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr2_i2c_scl

altera_avalon_pio v10.0
clock_crossing_bridge m1   ddr2_i2c_scl
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 1
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x1
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

ddr2_i2c_sda

altera_avalon_pio v10.0
clock_crossing_bridge m1   ddr2_i2c_sda
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 1
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x1
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

pio_led

altera_avalon_pio v10.0
clock_crossing_bridge m1   pio_led
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 16777215
simDoTestBenchWiring false
simDrivenValue 0
width 24
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 24
RESET_VALUE 0xffffff
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

pio_button

altera_avalon_pio v10.0
clock_crossing_bridge m1   pio_button
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

pll

altera_avalon_pll v10.0
cpu data_master   pll
  s1
clk clk  
  inclk0
c0   clock_crossing_bridge
  clk_m1
c2  
  clk_s1
c0   sysid
  clk
c0   timer
  clk
c0   ddr2_i2c_scl
  clk
c0   ddr2_i2c_sda
  clk
c0   pio_led
  clk
c0   pio_button
  clk
c0   jtag_uart
  clk
c0   SEG7
  global_clock
c0   pio_dip_sw
  clk
c0   pio_sw
  clk
c2   cpu
  clk
c2   ddr2_clock_bridge
  clk_s1
c2   onchip_mem
  clk1
c2   tse_mac
  receive_clock_connection
c2  
  transmit_clock_connection
c2  
  control_port_clock_connection
c2   sgdma_tx
  clk
c2   sgdma_rx
  clk
c2   descriptor_memory
  clk1
c0   net_i2c_scl
  clk
c0   net_i2c_sda
  clk


Parameters

c0 tap c0 mult 2 div 5 phase 0 enabled true inputfreq 50000000 outputfreq 20000000
c1 tap c1 mult 1 div 1 phase 0 enabled true inputfreq 50000000 outputfreq 50000000
c2 tap c2 mult 2 div 1 phase 0 enabled true inputfreq 50000000 outputfreq 100000000
c3 tap c3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c4 tap c4 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c5 tap c5 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c6 tap c6 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c7 tap c7 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c8 tap c8 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
c9 tap c9 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
deviceFamily STRATIXIII
e0 tap e0 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e1 tap e1 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e2 tap e2 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
e3 tap e3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0
inputClockFrequency 50000000
inputClockRate 50000000
lockedOutputPortOption Export
pfdenaInputPortOption Register
pllHdl // megafunction wizard: %ALTPLL% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // ============================================================ // CNX file retrieval info // ============================================================ // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "20.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.0" // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III" // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "350.000" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "20.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" // Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpllpll.mif" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III" // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF" // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
resetInputPortOption Register
generateLegacySim false
  

Software Assignments

ARESET "None"
PFDENA "None"
LOCKED "None"
PLLENA "None"
SCANCLK "None"
SCANDATA "None"
SCANREAD "None"
SCANWRITE "None"
SCANCLKENA "None"
SCANACLR "None"
SCANDATAOUT "None"
SCANDONE "None"
CONFIGUPDATE "None"
PHASECOUNTERSELECT "None"
PHASEDONE "None"
PHASEUPDOWN "None"
PHASESTEP "None"

clock_crossing_bridge

altera_avalon_clock_crossing v10.0
cpu data_master   clock_crossing_bridge
  s1
pll c0  
  clk_m1
c2  
  clk_s1
m1   sysid
  control_slave
m1   timer
  s1
m1   ddr2_i2c_scl
  s1
m1   ddr2_i2c_sda
  s1
m1   pio_button
  s1
m1   pio_led
  s1
m1   jtag_uart
  avalon_jtag_slave
m1   SEG7
  slave
m1   pio_dip_sw
  s1
m1   pio_sw
  s1
m1   net_i2c_scl
  s1
m1   net_i2c_sda
  s1


Parameters

dataWidth 32
downstreamFIFODepth 32
downstreamUseRegister false
masterSyncDepth 3
maxBurstSize 8
slaveAddressWidth 6
slaveSyncDepth 3
upstreamFIFODepth 512
upstreamUseRegister false
useBurstCount false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

SEG7

SEG7 v1.0
clock_crossing_bridge m1   SEG7
  slave
pll c0  
  global_clock


Parameters

SEG7_NUM 2
ADDR_WIDTH 3
DEFAULT_ACTIVE 1
LOW_ACTIVE 1
AUTO_GLOBAL_CLOCK_CLOCK_RATE 20000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

pio_dip_sw

altera_avalon_pio v10.0
clock_crossing_bridge m1   pio_dip_sw
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

pio_sw

altera_avalon_pio v10.0
clock_crossing_bridge m1   pio_sw
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

ddr2_clock_bridge

altera_avalon_clock_crossing v10.0
cpu instruction_master   ddr2_clock_bridge
  s1
data_master  
  s1
altmemddr sysclk  
  clk_m1
pll c2  
  clk_s1
sgdma_rx m_write  
  s1
sgdma_tx m_read  
  s1
m1   altmemddr
  s1


Parameters

dataWidth 32
downstreamFIFODepth 32
downstreamUseRegister false
masterSyncDepth 3
maxBurstSize 8
slaveAddressWidth 26
slaveSyncDepth 3
upstreamFIFODepth 128
upstreamUseRegister false
useBurstCount false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

tse_mac

triple_speed_ethernet v10.0
cpu data_master   tse_mac
  control_port
sgdma_tx out  
  transmit
pll c2  
  receive_clock_connection
c2  
  transmit_clock_connection
c2  
  control_port_clock_connection
receive   sgdma_rx
  in


Parameters

atlanticSinkClockRate 0
atlanticSinkClockSource unassigned
atlanticSourceClockRate 0
atlanticSourceClockSource unassigned
avalonSlaveClockRate 0
avalonSlaveClockSource unassigned
avalonStNeighbours {TRANSMIT=sgdma_tx, RECEIVE=sgdma_rx}
channel_count 1
core_variation MAC_ONLY
core_version 2560
crc32check16bit 0
crc32dwidth 8
crc32gendelay 6
crc32s1l2_extern false
cust_version 0
dataBitsPerSymbol 8
dev_version 2560
deviceFamily STRATIXIII
deviceFamilyName Stratix III
eg_addr 11
eg_fifo 2048
ena_hash false
enable_alt_reconfig false
enable_clk_sharing false
enable_ena 32
enable_fifoless false
enable_gmii_loopback false
enable_hd_logic true
enable_mac_flow_ctrl false
enable_mac_txaddr_set true
enable_mac_vlan false
enable_maclite false
enable_magic_detect false
enable_multi_channel false
enable_pkt_class true
enable_pma false
enable_reg_sharing false
enable_sgmii false
enable_shift16 true
enable_sup_addr false
enable_use_internal_fifo true
export_calblkclk false
export_pwrdn false
ext_stat_cnt_ena false
gigeAdvanceMode true
ifGMII MII_GMII
ifPCSuseEmbeddedSerdes false
ing_addr 11
ing_fifo 2048
insert_ta true
maclite_gige false
max_channels 1
mdio_clk_div 40
phy_identifier 0
ramType AUTO
reset_level 1
sopcSystemTopLevelName DE3_SOPC
stat_cnt_ena false
timingAdapterName timingAdapter
toolContext SOPC_BUILDER
transceiver_type LVDS_IO
uiEgFIFOSize 2048 x 32 Bits
uiHostClockFrequency 0
uiIngFIFOSize 2048 x 32 Bits
uiMACFIFO false
uiMACOptions false
uiMDIOFreq 0.0 MHz
uiMIIInterfaceOptions false
uiPCSInterface false
uiPCSInterfaceOptions false
useLvds false
useMAC true
useMDIO true
usePCS false
use_sync_reset false
generateLegacySim false
  

Software Assignments

TRANSMIT "sgdma_tx"
RECEIVE "sgdma_rx"
TRANSMIT_FIFO_DEPTH 2048
RECEIVE_FIFO_DEPTH 2048
FIFO_WIDTH 32
ENABLE_MACLITE 0
MACLITE_GIGE 0
USE_MDIO 1
NUMBER_OF_CHANNEL 1
NUMBER_OF_MAC_MDIO_SHARED 1
IS_MULTICHANNEL_MAC 0
MDIO_SHARED 0
REGISTER_SHARED 0
PCS 0
PCS_SGMII 0
PCS_ID 0u

sgdma_tx

altera_avalon_sgdma v10.0
cpu data_master   sgdma_tx
  csr
d_irq  
  csr_irq
pll c2  
  clk
m_read   ddr2_clock_bridge
  s1
out   tse_mac
  transmit
descriptor_write   descriptor_memory
  s1
descriptor_read  
  s1


Parameters

actualDataTransferFIFODepth 64
addressWidth 32
alwaysDoMaxBurst true
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 0
sourceErrorWidth 1
transferMode MEMORY_TO_STREAM
writeBurstcountWidth 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

READ_BLOCK_DATA_WIDTH 32
WRITE_BLOCK_DATA_WIDTH 32
STREAM_DATA_WIDTH 32
ADDRESS_WIDTH 32
HAS_READ_BLOCK 1
HAS_WRITE_BLOCK 0
READ_BURSTCOUNT_WIDTH 4
WRITE_BURSTCOUNT_WIDTH 4
BURST_TRANSFER 0
ALWAYS_DO_MAX_BURST 1
DESCRIPTOR_READ_BURST 0
UNALIGNED_TRANSFER 0
CONTROL_SLAVE_DATA_WIDTH 32
CONTROL_SLAVE_ADDRESS_WIDTH 4
DESC_DATA_WIDTH 32
CHAIN_WRITEBACK_DATA_WIDTH 32
STATUS_TOKEN_DATA_WIDTH 24
BYTES_TO_TRANSFER_DATA_WIDTH 16
BURST_DATA_WIDTH 8
CONTROL_DATA_WIDTH 8
ATLANTIC_CHANNEL_DATA_WIDTH 4
COMMAND_FIFO_DATA_WIDTH 104
SYMBOLS_PER_BEAT 4
IN_ERROR_WIDTH 0
OUT_ERROR_WIDTH 1

sgdma_rx

altera_avalon_sgdma v10.0
cpu data_master   sgdma_rx
  csr
d_irq  
  csr_irq
tse_mac receive  
  in
pll c2  
  clk
m_write   ddr2_clock_bridge
  s1
descriptor_write   descriptor_memory
  s1
descriptor_read  
  s1


Parameters

actualDataTransferFIFODepth 64
addressWidth 32
alwaysDoMaxBurst true
dataTransferFIFODepth 2
enableBurstTransfers false
enableDescriptorReadMasterBurst false
enableUnalignedTransfers false
internalFIFODepth 2
readBlockDataWidth 32
readBurstcountWidth 4
sinkErrorWidth 6
sourceErrorWidth 0
transferMode STREAM_TO_MEMORY
writeBurstcountWidth 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

READ_BLOCK_DATA_WIDTH 32
WRITE_BLOCK_DATA_WIDTH 32
STREAM_DATA_WIDTH 32
ADDRESS_WIDTH 32
HAS_READ_BLOCK 0
HAS_WRITE_BLOCK 1
READ_BURSTCOUNT_WIDTH 4
WRITE_BURSTCOUNT_WIDTH 4
BURST_TRANSFER 0
ALWAYS_DO_MAX_BURST 1
DESCRIPTOR_READ_BURST 0
UNALIGNED_TRANSFER 0
CONTROL_SLAVE_DATA_WIDTH 32
CONTROL_SLAVE_ADDRESS_WIDTH 4
DESC_DATA_WIDTH 32
CHAIN_WRITEBACK_DATA_WIDTH 32
STATUS_TOKEN_DATA_WIDTH 24
BYTES_TO_TRANSFER_DATA_WIDTH 16
BURST_DATA_WIDTH 8
CONTROL_DATA_WIDTH 8
ATLANTIC_CHANNEL_DATA_WIDTH 4
COMMAND_FIFO_DATA_WIDTH 104
SYMBOLS_PER_BEAT 4
IN_ERROR_WIDTH 6
OUT_ERROR_WIDTH 0

descriptor_memory

altera_avalon_onchip_memory2 v10.0
cpu data_master   descriptor_memory
  s1
sgdma_rx descriptor_write  
  s1
descriptor_read  
  s1
sgdma_tx descriptor_write  
  s1
descriptor_read  
  s1
pll c2  
  clk1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Stratix III
dualPort false
initMemContent true
initializationFileName descriptor_memory
instanceID NONE
memorySize 8192
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "descriptor_memory"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 8192u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

net_i2c_scl

altera_avalon_pio v10.0
clock_crossing_bridge m1   net_i2c_scl
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 1
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x1
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

net_i2c_sda

altera_avalon_pio v10.0
clock_crossing_bridge m1   net_i2c_sda
  s1
pll c0  
  clk


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 20000000
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 1
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 1
HAS_OUT 0
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x1
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 20000000u

clk_ddr2

clock_source v10.0


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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