Sample behavioral waveforms for design file enet_tx_clk_pll.v

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design enet_tx_clk_pll.v. The design enet_tx_clk_pll.v has Stratix III AUTO pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 20000 ps.

Fig. 1 : Wave showing NORMAL mode operation.