Generation Report - ALTMEMPHY v10.0

Entity Namealtmemddr_phy_alt_mem_phy
Variation Namealtmemddr_phy
Variation HDLVerilog HDL
Output DirectoryD:\DaughterBoard\NET\Examples\QB3\QB3_NET_GMII_NET0

File Summary

The MegaWizard interface is creating the following files in the output directory:
FileDescription
altmemddr_phy.vA MegaCore® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
altmemddr_phy.qipContains Quartus II project information for your MegaCore function variation.
altmemddr_phy.htmlThe MegaCore function report file.
altmemddr_phy_alt_mem_phy_seq_wrapper.vA wrapper file that calls the sequencer file, this file is for compilation.
altmemddr_phy_alt_mem_phy_seq.vhdContains the sequencer used during calibration.
altmemddr_phy_alt_mem_phy.vContains all modules of the ALTMEMPHY variation except for the sequencer.
altmemddr_phy_alt_mem_phy_pll.vThe PLL megafunction file for your ALTMEMPHY variation.
altmemddr_phy_pin_assignments.tclContains I/O standard, drive strength, output enable grouping, and termination assignments for your ALTMEMPHY variation. If your top-level design pin names do not match the default pin names or a prefixed version, edit the assignments in this file.
altmemddr_phy_ddr_pins.tclContains procedures used in the altmemddr_phy_report_timing.tcl file.
altmemddr_phy_report_timing.tclScript that reports timing for your ALTMEMPHY variation during compilation.
altmemddr_phy_ddr_timing.sdcContains timing constraints for your ALTMEMPHY variation.
altmemddr_phy_alt_mem_phy_pll.qipQuartus II IP file for the ALTPLL variation, containing the files associated with the ALTPLL megafunction.
alt_mem_phy_defines.vContains constants used in the interface.
altmemddr_phy.ppfPin planner file for your ALTMEMPHY variation.

MegaCore Function Variation File Ports

NameDirectionWidth
pll_ref_clkINPUT1
global_reset_nINPUT1
soft_reset_nINPUT1
reset_request_nOUTPUT1
ctl_clkOUTPUT1
ctl_reset_nOUTPUT1
ctl_dqs_burstINPUT4
ctl_wdata_validINPUT4
ctl_wdataINPUT64
ctl_dmINPUT8
ctl_wlatOUTPUT5
ctl_addrINPUT26
ctl_baINPUT4
ctl_cas_nINPUT2
ctl_ckeINPUT2
ctl_cs_nINPUT2
ctl_odtINPUT2
ctl_ras_nINPUT2
ctl_we_nINPUT2
ctl_rst_nINPUT2
ctl_mem_clk_disableINPUT1
ctl_doing_rdINPUT4
ctl_rdataOUTPUT64
ctl_rdata_validOUTPUT2
ctl_rlatOUTPUT5
ctl_cal_reqINPUT1
ctl_cal_byte_lane_sel_nINPUT2
ctl_cal_successOUTPUT1
ctl_cal_failOUTPUT1
ctl_cal_warningOUTPUT1
mem_addrOUTPUT13
mem_baOUTPUT2
mem_cas_nOUTPUT1
mem_ckeOUTPUT1
mem_cs_nOUTPUT1
mem_dmOUTPUT2
mem_odtOUTPUT1
mem_ras_nOUTPUT1
mem_we_nOUTPUT1
mem_reset_nOUTPUT1
mem_clkBIDIR1
mem_clk_nBIDIR1
mem_dqBIDIR16
mem_dqsBIDIR2
mem_dqs_nBIDIR2
dbg_clkINPUT1
dbg_reset_nINPUT1
dbg_addrINPUT13
dbg_wrINPUT1
dbg_rdINPUT1
dbg_csINPUT1
dbg_wr_dataINPUT32
dbg_rd_dataOUTPUT32
dbg_waitrequestOUTPUT1
aux_half_rate_clkOUTPUT1
aux_full_rate_clkOUTPUT1