enable_example_design_sim_hwtcl |
0 |
enable_example_design_synth_hwtcl |
1 |
select_design_example_rtl_lang_hwtcl |
Verilog |
chosen_devkit_hwtcl |
Agilex F-Series P-Tile ES0 FPGA Development Kit |
top_topology_hwtcl |
Gen4x16, Interface - 512 bit |
virtual_rp_ep_mode_hwtcl |
Native Endpoint |
xcvr_reconfig_user_hwtcl |
0 |
g4_pld_clkfreq_user_hwtcl |
350MHz |
virtual_sris_enable_en_hwtcl |
0 |
sim_mode_user_hwtcl |
0 |
is_cvp_enable_hwtcl |
0 |
core16_enable_power_mgnt_intf_hwtcl |
0 |
core16_enable_legacy_int_hwtcl |
0 |
core16_enable_cii_hwtcl |
0 |
core16_enable_prs_event_hwtcl |
0 |
core16_enable_error_intf_hwtcl |
0 |
core16_enable_10bit_tag_support_intf_hwtcl |
0 |
core16_pf0_gen3_eq_pset_req_vec_hwtcl |
4 |
core16_pf0_gen3_eq_pset_req_vec_atg4_hwtcl |
624 |
core16_virtual_maxpayload_size_hwtcl |
512 |
core16_cap_ext_tag_supp_user_hwtcl |
1 |
core16_user_vsec_cap_enable_hwtcl |
0 |
core16_pf0_pcie_cap_port_num_hwtcl |
1 |
core16_cap_slot_clk_config_hwtcl |
1 |
core16_virtual_pf0_msi_enable_user_hwtcl |
1 |
core16_virtual_pf0_msi_64b_addressing_user_hwtcl |
0 |
core16_pf0_pci_msi_ext_data_cap_hwtcl |
0 |
core16_pf0_pci_msi_multiple_msg_cap_hwtcl |
2 |
core16_virtual_pf0_msix_enable_user_hwtcl |
1 |
core16_pf0_pci_msix_table_size_hwtcl |
8 |
core16_pf0_pci_msix_table_offset_hwtcl |
0 |
core16_pf0_pci_msix_bir_hwtcl |
2 |
core16_pf0_pci_msix_pba_offset_hwtcl |
512 |
core16_pf0_pci_msix_pba_hwtcl |
2 |
core16_exvf_msix_tablesize_pf0 |
0 |
core16_exvf_msixtable_offset_pf0 |
0 |
core16_exvf_msixtable_bir_pf0 |
0 |
core16_exvf_msixpba_offset_pf0 |
0 |
core16_exvf_msixpba_bir_pf0 |
0 |
core16_exvf_msix_tablesize_pf1 |
0 |
core16_exvf_msixtable_offset_pf1 |
0 |
core16_exvf_msixtable_bir_pf1 |
0 |
core16_exvf_msixpba_offset_pf1 |
0 |
core16_exvf_msixpba_bir_pf1 |
0 |
core16_exvf_msix_tablesize_pf2 |
0 |
core16_exvf_msixtable_offset_pf2 |
0 |
core16_exvf_msixtable_bir_pf2 |
0 |
core16_exvf_msixpba_offset_pf2 |
0 |
core16_exvf_msixpba_bir_pf2 |
0 |
core16_exvf_msix_tablesize_pf3 |
0 |
core16_exvf_msixtable_offset_pf3 |
0 |
core16_exvf_msixtable_bir_pf3 |
0 |
core16_exvf_msixpba_offset_pf3 |
0 |
core16_exvf_msixpba_bir_pf3 |
0 |
core16_exvf_msix_tablesize_pf4 |
0 |
core16_exvf_msixtable_offset_pf4 |
0 |
core16_exvf_msixtable_bir_pf4 |
0 |
core16_exvf_msixpba_offset_pf4 |
0 |
core16_exvf_msixpba_bir_pf4 |
0 |
core16_exvf_msix_tablesize_pf5 |
0 |
core16_exvf_msixtable_offset_pf5 |
0 |
core16_exvf_msixtable_bir_pf5 |
0 |
core16_exvf_msixpba_offset_pf5 |
0 |
core16_exvf_msixpba_bir_pf5 |
0 |
core16_exvf_msix_tablesize_pf6 |
0 |
core16_exvf_msixtable_offset_pf6 |
0 |
core16_exvf_msixtable_bir_pf6 |
0 |
core16_exvf_msixpba_offset_pf6 |
0 |
core16_exvf_msixpba_bir_pf6 |
0 |
core16_exvf_msix_tablesize_pf7 |
0 |
core16_exvf_msixtable_offset_pf7 |
0 |
core16_exvf_msixtable_bir_pf7 |
0 |
core16_exvf_msixpba_offset_pf7 |
0 |
core16_exvf_msixpba_bir_pf7 |
0 |
core16_pf0_pcie_slot_imp_hwtcl |
0 |
core16_pf0_pcie_cap_slot_power_limit_scale_hwtcl |
0 |
core16_pf0_pcie_cap_slot_power_limit_value_hwtcl |
0 |
core16_pf0_pcie_cap_phy_slot_num_hwtcl |
0 |
core16_user_pcie_cap_ep_l0s_accpt_latency_hwtcl |
0 |
core16_user_pcie_cap_ep_l1_accpt_latency_hwtcl |
0 |
core16_virtual_pf0_prs_ext_cap_enable_hwtcl |
0 |
core16_virtual_sn_cap_enable_hwtcl |
0 |
core16_sn_ser_num_reg_1_dw_hwtcl |
0 |
core16_sn_ser_num_reg_2_dw_hwtcl |
0 |
core16_virtual_pf0_pasid_cap_enable_hwtcl |
0 |
core16_virtual_pf0_ltr_cap_enable_hwtcl |
0 |
core16_pf0_pci_type0_vendor_id_hwtcl |
4466 |
core16_pf0_pci_type0_device_id_hwtcl |
2500 |
core16_pf0_revision_id_hwtcl |
1 |
core16_pf0_class_code_hwtcl |
16711680 |
core16_pf0_subsys_vendor_id_hwtcl |
0 |
core16_pf0_subsys_dev_id_hwtcl |
0 |
core16_exvf_subsysid_pf0 |
0 |
core16_exvf_subsysid_pf1 |
0 |
core16_exvf_subsysid_pf2 |
0 |
core16_exvf_subsysid_pf3 |
0 |
core16_exvf_subsysid_pf4 |
0 |
core16_exvf_subsysid_pf5 |
0 |
core16_exvf_subsysid_pf6 |
0 |
core16_exvf_subsysid_pf7 |
0 |
core16_cvp_user_id_hwtcl |
0 |
core16_virtual_drop_vendor0_msg_hwtcl |
0 |
core16_virtual_drop_vendor1_msg_hwtcl |
0 |
core16_debug_toolkit_user_hwtcl |
0 |
core16_hip_reconfig_user_hwtcl |
0 |
core16_pf0_int_pin_hwtcl |
NO INT |
core16_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
core16_pf0_bar0_address_width_user_hwtcl |
16 |
core16_pf0_bar1_type_user_hwtcl |
Disabled |
core16_pf0_bar2_type_user_hwtcl |
64-bit prefetchable memory |
core16_pf0_bar2_address_width_user_hwtcl |
16 |
core16_pf0_bar3_type_user_hwtcl |
Disabled |
core16_pf0_bar4_type_user_hwtcl |
64-bit prefetchable memory |
core16_pf0_bar4_address_width_user_hwtcl |
24 |
core16_pf0_bar5_type_user_hwtcl |
Disabled |
core16_pf0_expansion_base_address_register_hwtcl |
0 |
core16_enable_sriov_hwtcl |
0 |
core16_virtual_pf0_ats_cap_enable_hwtcl |
0 |
core16_virtual_pf0_tph_cap_enable_hwtcl |
0 |
core16_virtual_pf0_acs_cap_enable_hwtcl |
0 |
core16_enable_virtio_hwtcl |
0 |
core16_pf0_virtio_capability_present_hwtcl |
0 |
core16_pf0_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf0_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf0_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf0_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf0_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf0_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf0_virtio_notification_structure_length_hwtcl |
0 |
core16_pf0_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf0_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf0_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf0_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf0_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf0_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf0_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf0_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf0vf_virtio_capability_present_hwtcl |
0 |
core16_pf0vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf0vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf0vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf0vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf0vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf0vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf0vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf0vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf0vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf1vf_virtio_capability_present_hwtcl |
0 |
core16_pf1vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf1vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf1vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf1vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf1vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf1vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf1vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf1vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf1vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf2vf_virtio_capability_present_hwtcl |
0 |
core16_pf2vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf2vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf2vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf2vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf2vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf2vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf2vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf2vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf2vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf3vf_virtio_capability_present_hwtcl |
0 |
core16_pf3vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf3vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf3vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf3vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf3vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf3vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf3vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf3vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf3vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf4vf_virtio_capability_present_hwtcl |
0 |
core16_pf4vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf4vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf4vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf4vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf4vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf4vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf4vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf4vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf4vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf4vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf4vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf4vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf4vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf4vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf4vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf4vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf4vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf5vf_virtio_capability_present_hwtcl |
0 |
core16_pf5vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf5vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf5vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf5vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf5vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf5vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf5vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf5vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf5vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf5vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf5vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf5vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf5vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf5vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf5vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf5vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf5vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf6vf_virtio_capability_present_hwtcl |
0 |
core16_pf6vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf6vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf6vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf6vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf6vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf6vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf6vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf6vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf6vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf6vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf6vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf6vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf6vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf6vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf6vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf6vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf6vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
core16_pf7vf_virtio_capability_present_hwtcl |
0 |
core16_pf7vf_virtio_device_specific_cap_present_hwtcl |
0 |
core16_pf7vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
core16_pf7vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
core16_pf7vf_virtio_cmn_config_structure_length_hwtcl |
0 |
core16_pf7vf_virtio_notification_bar_indicator_hwtcl |
0 |
core16_pf7vf_virtio_notification_bar_offset_hwtcl |
0 |
core16_pf7vf_virtio_notification_structure_length_hwtcl |
0 |
core16_pf7vf_virtio_notify_off_multiplier_hwtcl |
0 |
core16_pf7vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
core16_pf7vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
core16_pf7vf_virtio_isrstatus_structure_length_hwtcl |
0 |
core16_pf7vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
core16_pf7vf_virtio_devspecific_bar_offset_hwtcl |
0 |
core16_pf7vf_virtio_devspecific_structure_length_hwtcl |
0 |
core16_pf7vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
core16_pf7vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
core16_pf7vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
hssi_aib_ssm_silicon_rev |
14nm5 |
hssi_aibnd_rx_aib_ber_margining_ctrl |
aib_ber_margining_setting0 |
hssi_aibnd_rx_aib_datasel_gr0 |
aib_datasel0_setting0 |
hssi_aibnd_rx_aib_datasel_gr1 |
aib_datasel1_setting1 |
hssi_aibnd_rx_aib_datasel_gr2 |
aib_datasel2_setting1 |
hssi_aibnd_rx_aib_dllstr_align_clkdiv |
aib_dllstr_align_clkdiv_setting0 |
hssi_aibnd_rx_aib_dllstr_align_dly_pst |
aib_dllstr_align_dly_pst_setting0 |
hssi_aibnd_rx_aib_dllstr_align_dy_ctl_static |
aib_dllstr_align_dy_ctl_static_setting0 |
hssi_aibnd_rx_aib_dllstr_align_dy_ctlsel |
aib_dllstr_align_dy_ctlsel_setting0 |
hssi_aibnd_rx_aib_dllstr_align_entest |
aib_dllstr_align_test_disable |
hssi_aibnd_rx_aib_dllstr_align_halfcode |
aib_dllstr_align_halfcode_enable |
hssi_aibnd_rx_aib_dllstr_align_selflock |
aib_dllstr_align_selflock_enable |
hssi_aibnd_rx_aib_dllstr_align_st_core_dn_prgmnvrt |
aib_dllstr_align_st_core_dn_prgmnvrt_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_core_up_prgmnvrt |
aib_dllstr_align_st_core_up_prgmnvrt_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_core_updnen |
aib_dllstr_align_st_core_updnen_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_dftmuxsel |
aib_dllstr_align_st_dftmuxsel_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_en |
aib_dllstr_align_st_en_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_hps_ctrl_en |
aib_dllstr_align_hps_ctrl_en_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_lockreq_muxsel |
aib_dllstr_align_st_lockreq_muxsel_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_new_dll |
aib_dllstr_align_new_dll_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_rst |
aib_dllstr_align_st_rst_setting0 |
hssi_aibnd_rx_aib_dllstr_align_st_rst_prgmnvrt |
aib_dllstr_align_st_rst_prgmnvrt_setting0 |
hssi_aibnd_rx_aib_dllstr_align_test_clk_pll_en_n |
aib_dllstr_align_test_clk_pll_en_n_disable |
hssi_aibnd_rx_aib_inctrl_gr0 |
aib_inctrl0_setting0 |
hssi_aibnd_rx_aib_inctrl_gr1 |
aib_inctrl1_setting0 |
hssi_aibnd_rx_aib_inctrl_gr2 |
aib_inctrl2_setting0 |
hssi_aibnd_rx_aib_inctrl_gr3 |
aib_inctrl3_setting0 |
hssi_aibnd_rx_aib_outctrl_gr0 |
aib_outen0_setting0 |
hssi_aibnd_rx_aib_outctrl_gr1 |
aib_outen1_setting0 |
hssi_aibnd_rx_aib_outctrl_gr2 |
aib_outen2_setting0 |
hssi_aibnd_rx_aib_outndrv_r12 |
aib_ndrv12_setting1 |
hssi_aibnd_rx_aib_outndrv_r34 |
aib_ndrv34_setting1 |
hssi_aibnd_rx_aib_outndrv_r56 |
aib_ndrv56_setting1 |
hssi_aibnd_rx_aib_outndrv_r78 |
aib_ndrv78_setting1 |
hssi_aibnd_rx_aib_outpdrv_r12 |
aib_pdrv12_setting1 |
hssi_aibnd_rx_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
hssi_aibnd_rx_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
hssi_aibnd_rx_aib_outpdrv_r78 |
aib_pdrv78_setting1 |
hssi_aibnd_rx_aib_red_shift_en |
aib_red_shift_disable |
hssi_aibnd_rx_dft_hssitestip_dll_dcc_en |
disable_dft |
hssi_aibnd_rx_op_mode |
pwr_down |
hssi_aibnd_rx_powerdown_mode |
true |
hssi_aibnd_rx_powermode_ac |
rxdatapath_low_speed_pwr |
hssi_aibnd_rx_powermode_dc |
rxdatapath_powerdown |
hssi_aibnd_rx_powermode_freq_hz_aib_hssi_rx_transfer_clk |
0 |
hssi_aibnd_rx_redundancy_en |
disable |
hssi_aibnd_rx_sup_mode |
user_mode |
hssi_aibnd_rx_silicon_rev |
14nm5 |
hssi_aibnd_tx_aib_datasel_gr0 |
aib_datasel0_setting0 |
hssi_aibnd_tx_aib_datasel_gr1 |
aib_datasel1_setting0 |
hssi_aibnd_tx_aib_datasel_gr2 |
aib_datasel2_setting1 |
hssi_aibnd_tx_aib_datasel_gr3 |
aib_datasel3_setting1 |
hssi_aibnd_tx_aib_ddrctrl_gr0 |
aib_ddr0_setting1 |
hssi_aibnd_tx_aib_hssi_tx_transfer_clk_hz |
0 |
hssi_aibnd_tx_aib_iinasyncen |
aib_inasyncen_setting0 |
hssi_aibnd_tx_aib_iinclken |
aib_inclken_setting0 |
hssi_aibnd_tx_aib_outctrl_gr0 |
aib_outen0_setting0 |
hssi_aibnd_tx_aib_outctrl_gr1 |
aib_outen1_setting0 |
hssi_aibnd_tx_aib_outctrl_gr2 |
aib_outen2_setting0 |
hssi_aibnd_tx_aib_outctrl_gr3 |
aib_outen3_setting0 |
hssi_aibnd_tx_aib_outndrv_r34 |
aib_ndrv34_setting1 |
hssi_aibnd_tx_aib_outndrv_r56 |
aib_ndrv56_setting1 |
hssi_aibnd_tx_aib_outpdrv_r34 |
aib_pdrv34_setting1 |
hssi_aibnd_tx_aib_outpdrv_r56 |
aib_pdrv56_setting1 |
hssi_aibnd_tx_aib_red_dirclkn_shiften |
aib_red_dirclkn_shift_disable |
hssi_aibnd_tx_aib_red_dirclkp_shiften |
aib_red_dirclkp_shift_disable |
hssi_aibnd_tx_aib_red_drx_shiften |
aib_red_drx_shift_disable |
hssi_aibnd_tx_aib_red_dtx_shiften |
aib_red_dtx_shift_disable |
hssi_aibnd_tx_aib_red_pout_shiften |
aib_red_pout_shift_disable |
hssi_aibnd_tx_aib_red_rx_shiften |
aib_red_rx_shift_disable |
hssi_aibnd_tx_aib_red_tx_shiften |
aib_red_tx_shift_disable |
hssi_aibnd_tx_aib_red_txferclkout_shiften |
aib_red_txferclkout_shift_disable |
hssi_aibnd_tx_aib_red_txferclkoutn_shiften |
aib_red_txferclkoutn_shift_disable |
hssi_aibnd_tx_aib_tx_clkdiv |
aib_tx_clkdiv_setting1 |
hssi_aibnd_tx_aib_tx_dcc_byp |
aib_tx_dcc_byp_disable |
hssi_aibnd_tx_aib_tx_dcc_byp_iocsr_unused |
aib_tx_dcc_byp_disable_iocsr_unused |
hssi_aibnd_tx_aib_tx_dcc_cont_cal |
aib_tx_dcc_cal_cont |
hssi_aibnd_tx_aib_tx_dcc_cont_cal_iocsr_unused |
aib_tx_dcc_cal_single_iocsr_unused |
hssi_aibnd_tx_aib_tx_dcc_dft |
aib_tx_dcc_dft_disable |
hssi_aibnd_tx_aib_tx_dcc_dft_sel |
aib_tx_dcc_dft_mode0 |
hssi_aibnd_tx_aib_tx_dcc_dll_dft_sel |
aib_tx_dcc_dll_dft_sel_setting0 |
hssi_aibnd_tx_aib_tx_dcc_dll_entest |
aib_tx_dcc_dll_test_disable |
hssi_aibnd_tx_aib_tx_dcc_dy_ctl_static |
aib_tx_dcc_dy_ctl_static_setting0 |
hssi_aibnd_tx_aib_tx_dcc_dy_ctlsel |
aib_tx_dcc_dy_ctlsel_setting0 |
hssi_aibnd_tx_aib_tx_dcc_en |
aib_tx_dcc_enable |
hssi_aibnd_tx_aib_tx_dcc_en_iocsr_unused |
aib_tx_dcc_disable_iocsr_unused |
hssi_aibnd_tx_aib_tx_dcc_manual_dn |
aib_tx_dcc_manual_dn0 |
hssi_aibnd_tx_aib_tx_dcc_manual_up |
aib_tx_dcc_manual_up0 |
hssi_aibnd_tx_aib_tx_dcc_rst_prgmnvrt |
aib_tx_dcc_st_rst_prgmnvrt_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_core_dn_prgmnvrt |
aib_tx_dcc_st_core_dn_prgmnvrt_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_core_up_prgmnvrt |
aib_tx_dcc_st_core_up_prgmnvrt_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_core_updnen |
aib_tx_dcc_st_core_updnen_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_dftmuxsel |
aib_tx_dcc_st_dftmuxsel_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_dly_pst |
aib_tx_dcc_st_dly_pst_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_en |
aib_tx_dcc_st_en_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_hps_ctrl_en |
aib_tx_dcc_hps_ctrl_en_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_lockreq_muxsel |
aib_tx_dcc_st_lockreq_muxsel_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_new_dll |
aib_tx_dcc_new_dll_setting0 |
hssi_aibnd_tx_aib_tx_dcc_st_rst |
aib_tx_dcc_st_rst_setting0 |
hssi_aibnd_tx_aib_tx_dcc_test_clk_pll_en_n |
aib_tx_dcc_test_clk_pll_en_n_disable |
hssi_aibnd_tx_aib_tx_halfcode |
aib_tx_halfcode_enable |
hssi_aibnd_tx_aib_tx_selflock |
aib_tx_selflock_enable |
hssi_aibnd_tx_dfd_dll_dcc_en |
disable_dfd |
hssi_aibnd_tx_dft_hssitestip_dll_dcc_en |
disable_dft |
hssi_aibnd_tx_op_mode |
tx_dcc_enable |
hssi_aibnd_tx_powerdown_mode |
true |
hssi_aibnd_tx_powermode_ac |
txdatapath_low_speed_pwr |
hssi_aibnd_tx_powermode_dc |
txdatapath_powerdown |
hssi_aibnd_tx_powermode_freq_hz_aib_hssi_tx_transfer_clk |
0 |
hssi_aibnd_tx_redundancy_en |
disable |
hssi_aibnd_tx_sup_mode |
user_mode |
hssi_aibnd_tx_silicon_rev |
14nm5 |
hssi_avmm1_if_pcs_arbiter_ctrl |
avmm1_arbiter_uc_sel |
hssi_avmm1_if_hssiadapt_avmm_clk_dcg_en |
disable |
hssi_avmm1_if_hssiadapt_avmm_clk_scg_en |
disable |
hssi_avmm1_if_pldadapt_avmm_clk_scg_en |
disable |
hssi_avmm1_if_pcs_cal_done |
avmm1_cal_done_assert |
hssi_avmm1_if_pcs_cal_reserved |
0 |
hssi_avmm1_if_pcs_calibration_feature_en |
avmm1_pcs_calibration_dis |
hssi_avmm1_if_pldadapt_gate_dis |
disable |
hssi_avmm1_if_pcs_hip_cal_en |
disable |
hssi_avmm1_if_hssiadapt_nfhssi_calibratio_feature_en |
disable |
hssi_avmm1_if_pldadapt_nfhssi_calibratio_feature_en |
disable |
hssi_avmm1_if_hssiadapt_osc_clk_scg_en |
disable |
hssi_avmm1_if_pldadapt_osc_clk_scg_en |
disable |
hssi_avmm1_if_hssiadapt_read_blocking_enable |
enable |
hssi_avmm1_if_pldadapt_read_blocking_enable |
enable |
hssi_avmm1_if_hssiadapt_uc_blocking_enable |
enable |
hssi_avmm1_if_pldadapt_uc_blocking_enable |
enable |
hssi_avmm1_if_hssiadapt_write_resp_en |
disable |
hssi_avmm1_if_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
hssi_avmm1_if_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
hssi_avmm1_if_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
hssi_avmm1_if_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
hssi_avmm1_if_func_mode |
c3adpt_pmadir |
hssi_avmm1_if_hssiadapt_sr_hip_mode |
disable_hip |
hssi_avmm1_if_hssiadapt_hip_mode |
disable_hip |
hssi_avmm1_if_pldadapt_hip_mode |
disable_hip |
hssi_avmm1_if_hssiadapt_sr_powerdown_mode |
powerup |
hssi_avmm1_if_hssiadapt_sr_sr_free_run_div_clk |
out_of_reset_sync |
hssi_avmm1_if_hssiadapt_sr_sr_hip_en |
disable |
hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_div_sel |
non_div |
hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_scg_en |
disable |
hssi_avmm1_if_hssiadapt_sr_sr_parity_en |
disable |
hssi_avmm1_if_hssiadapt_sr_sr_reserved_in_en |
enable |
hssi_avmm1_if_hssiadapt_sr_sr_reserved_out_en |
enable |
hssi_avmm1_if_hssiadapt_sr_sup_mode |
user_mode |
hssi_avmm1_if_topology |
disabled_block |
hssi_avmm1_if_silicon_rev |
14nm5 |
hssi_avmm1_if_calibration_type |
one_time |
hssi_avmm2_if_pcs_arbiter_ctrl |
avmm2_arbiter_uc_sel |
hssi_avmm2_if_hssiadapt_avmm_clk_dcg_en |
disable |
hssi_avmm2_if_hssiadapt_avmm_clk_scg_en |
disable |
hssi_avmm2_if_pldadapt_avmm_clk_scg_en |
disable |
hssi_avmm2_if_pcs_cal_done |
avmm2_cal_done_assert |
hssi_avmm2_if_pcs_cal_reserved |
0 |
hssi_avmm2_if_pcs_calibration_feature_en |
avmm2_pcs_calibration_dis |
hssi_avmm2_if_pldadapt_gate_dis |
disable |
hssi_avmm2_if_pcs_hip_cal_en |
disable |
hssi_avmm2_if_hssiadapt_osc_clk_scg_en |
disable |
hssi_avmm2_if_pldadapt_osc_clk_scg_en |
disable |
hssi_avmm2_if_hssiadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
hssi_avmm2_if_pldadapt_avmm_osc_clock_setting |
osc_clk_div_by1 |
hssi_avmm2_if_hssiadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
hssi_avmm2_if_pldadapt_avmm_testbus_sel |
avmm1_transfer_testbus |
hssi_avmm2_if_func_mode |
c3adpt_pmadir |
hssi_avmm2_if_hssiadapt_hip_mode |
disable_hip |
hssi_avmm2_if_pldadapt_hip_mode |
disable_hip |
hssi_avmm2_if_topology |
disabled_block |
hssi_avmm2_if_silicon_rev |
14nm5 |
hssi_avmm2_if_calibration_type |
one_time |
hssi_pldadapt_rx_aib_clk1_sel |
aib_clk1_rx_transfer_clk |
hssi_pldadapt_rx_aib_clk2_sel |
aib_clk2_rx_transfer_clk |
hssi_pldadapt_rx_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_sr_clk_in_hz |
0 |
hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_transfer_clk_hz |
0 |
hssi_pldadapt_rx_asn_bypass_pma_pcie_sw_done |
disable |
hssi_pldadapt_rx_asn_en |
disable |
hssi_pldadapt_rx_asn_wait_for_dll_reset_cnt |
0 |
hssi_pldadapt_rx_asn_wait_for_fifo_flush_cnt |
0 |
hssi_pldadapt_rx_asn_wait_for_pma_pcie_sw_done_cnt |
0 |
hssi_pldadapt_rx_bonding_dft_en |
dft_dis |
hssi_pldadapt_rx_bonding_dft_val |
dft_0 |
hssi_pldadapt_rx_chnl_bonding |
disable |
hssi_pldadapt_rx_clock_del_measure_enable |
disable |
hssi_pldadapt_rx_comp_cnt |
0 |
hssi_pldadapt_rx_compin_sel |
compin_master |
hssi_pldadapt_rx_hdpldadapt_csr_clk_hz |
0 |
hssi_pldadapt_rx_ctrl_plane_bonding |
individual |
hssi_pldadapt_rx_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
hssi_pldadapt_rx_ds_last_chnl |
ds_not_last_chnl |
hssi_pldadapt_rx_ds_master |
ds_master_en |
hssi_pldadapt_rx_duplex_mode |
disable |
hssi_pldadapt_rx_dv_mode |
dv_mode_dis |
hssi_pldadapt_rx_fifo_double_read |
fifo_double_read_dis |
hssi_pldadapt_rx_fifo_mode |
phase_comp |
hssi_pldadapt_rx_fifo_rd_clk_ins_sm_scg_en |
disable |
hssi_pldadapt_rx_fifo_rd_clk_scg_en |
disable |
hssi_pldadapt_rx_fifo_rd_clk_sel |
fifo_rd_clk_rx_transfer_clk |
hssi_pldadapt_rx_fifo_stop_rd |
n_rd_empty |
hssi_pldadapt_rx_fifo_stop_wr |
n_wr_full |
hssi_pldadapt_rx_fifo_width |
fifo_single_width |
hssi_pldadapt_rx_fifo_wr_clk_del_sm_scg_en |
disable |
hssi_pldadapt_rx_fifo_wr_clk_scg_en |
disable |
hssi_pldadapt_rx_fifo_wr_clk_sel |
fifo_wr_clk_rx_transfer_clk |
hssi_pldadapt_rx_free_run_div_clk |
out_of_reset_sync |
hssi_pldadapt_rx_fsr_pld_10g_rx_crc32_err_rst_val |
reset_to_zero_crc32 |
hssi_pldadapt_rx_fsr_pld_8g_sigdet_out_rst_val |
reset_to_zero_sigdet |
hssi_pldadapt_rx_fsr_pld_ltd_b_rst_val |
reset_to_zero_ltdb |
hssi_pldadapt_rx_fsr_pld_ltr_rst_val |
reset_to_zero_ltr |
hssi_pldadapt_rx_fsr_pld_rx_fifo_align_clr_rst_val |
reset_to_zero_alignclr |
hssi_pldadapt_rx_gb_rx_idwidth |
idwidth_32 |
hssi_pldadapt_rx_gb_rx_odwidth |
odwidth_66 |
hssi_pldadapt_rx_hip_mode |
disable_hip |
hssi_pldadapt_rx_hrdrst_align_bypass |
disable |
hssi_pldadapt_rx_hrdrst_dll_lock_bypass |
disable |
hssi_pldadapt_rx_hrdrst_rst_sm_dis |
enable_rx_rst_sm |
hssi_pldadapt_rx_hrdrst_rx_osc_clk_scg_en |
disable |
hssi_pldadapt_rx_hrdrst_user_ctl_en |
disable |
hssi_pldadapt_rx_indv |
indv_en |
hssi_pldadapt_rx_internal_clk1_sel1 |
pma_clks_or_txfiford_post_ct_mux_clk1_mux1 |
hssi_pldadapt_rx_internal_clk1_sel2 |
pma_clks_clk1_mux2 |
hssi_pldadapt_rx_internal_clk2_sel1 |
pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1 |
hssi_pldadapt_rx_internal_clk2_sel2 |
pma_clks_clk2_mux2 |
hssi_pldadapt_rx_is_paired_with |
other |
hssi_pldadapt_rx_loopback_mode |
disable |
hssi_pldadapt_rx_low_latency_en |
disable |
hssi_pldadapt_rx_lpbk_mode |
disable |
hssi_pldadapt_rx_osc_clk_scg_en |
disable |
hssi_pldadapt_rx_phcomp_rd_del |
phcomp_rd_del2 |
hssi_pldadapt_rx_pipe_enable |
disable |
hssi_pldadapt_rx_pipe_mode |
disable_pipe |
hssi_pldadapt_rx_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
hssi_pldadapt_rx_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
hssi_pldadapt_rx_pld_clk1_delay_en |
disable |
hssi_pldadapt_rx_pld_clk1_delay_sel |
delay_path0 |
hssi_pldadapt_rx_pld_clk1_inv_en |
disable |
hssi_pldadapt_rx_pld_clk1_sel |
pld_clk1_rowclk |
hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_dcm_hz |
0 |
hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_rowclk_hz |
0 |
hssi_pldadapt_rx_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
hssi_pldadapt_rx_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
hssi_pldadapt_rx_pma_hclk_scg_en |
disable |
hssi_pldadapt_rx_powerdown_mode |
powerdown |
hssi_pldadapt_rx_powermode_dc |
powerdown |
hssi_pldadapt_rx_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
hssi_pldadapt_rx_powermode_freq_hz_pld_rx_clk1_dcm |
0 |
hssi_pldadapt_rx_rx_datapath_tb_sel |
cp_bond |
hssi_pldadapt_rx_rx_fastbond_rden |
rden_ds_del_us_del |
hssi_pldadapt_rx_rx_fastbond_wren |
wren_ds_del_us_del |
hssi_pldadapt_rx_rx_fifo_power_mode |
full_width_full_depth |
hssi_pldadapt_rx_rx_fifo_read_latency_adjust |
disable |
hssi_pldadapt_rx_rx_fifo_write_ctrl |
blklock_stops |
hssi_pldadapt_rx_rx_fifo_write_latency_adjust |
disable |
hssi_pldadapt_rx_rx_osc_clock_setting |
osc_clk_div_by1 |
hssi_pldadapt_rx_rx_pld_8g_eidleinfersel_polling_bypass |
disable |
hssi_pldadapt_rx_rx_pld_pma_eye_monitor_polling_bypass |
disable |
hssi_pldadapt_rx_rx_pld_pma_pcie_switch_polling_bypass |
disable |
hssi_pldadapt_rx_rx_pld_pma_reser_out_polling_bypass |
disable |
hssi_pldadapt_rx_rx_prbs_flags_sr_enable |
disable |
hssi_pldadapt_rx_rx_true_b2b |
b2b |
hssi_pldadapt_rx_rx_usertest_sel |
enable |
hssi_pldadapt_rx_rxfifo_empty |
empty_sw |
hssi_pldadapt_rx_rxfifo_full |
full_pc_sw |
hssi_pldadapt_rx_rxfifo_mode |
rxphase_comp |
hssi_pldadapt_rx_rxfifo_pempty |
2 |
hssi_pldadapt_rx_rxfifo_pfull |
48 |
hssi_pldadapt_rx_rxfiford_post_ct_sel |
rxfiford_sclk_post_ct |
hssi_pldadapt_rx_rxfifowr_post_ct_sel |
rxfifowr_sclk_post_ct |
hssi_pldadapt_rx_sclk_sel |
sclk1_rowclk |
hssi_pldadapt_rx_hdpldadapt_speed_grade |
dash_1 |
hssi_pldadapt_rx_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
hssi_pldadapt_rx_stretch_num_stages |
zero_stage |
hssi_pldadapt_rx_sup_mode |
user_mode |
hssi_pldadapt_rx_txfiford_post_ct_sel |
txfiford_sclk_post_ct |
hssi_pldadapt_rx_txfifowr_post_ct_sel |
txfifowr_sclk_post_ct |
hssi_pldadapt_rx_us_bypass_pipeln |
us_bypass_pipeln_dis |
hssi_pldadapt_rx_us_last_chnl |
us_not_last_chnl |
hssi_pldadapt_rx_us_master |
us_master_en |
hssi_pldadapt_rx_word_align |
wa_en |
hssi_pldadapt_rx_word_align_enable |
disable |
hssi_pldadapt_rx_silicon_rev |
14nm5 |
hssi_pldadapt_rx_reconfig_settings |
{} |
hssi_pldadapt_tx_aib_clk1_sel |
aib_clk1_pld_pcs_tx_clk_out |
hssi_pldadapt_tx_aib_clk2_sel |
aib_clk2_pld_pcs_tx_clk_out |
hssi_pldadapt_tx_hdpldadapt_aib_fabric_pld_pma_hclk_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_aib_fabric_tx_sr_clk_in_hz |
0 |
hssi_pldadapt_tx_bonding_dft_en |
dft_dis |
hssi_pldadapt_tx_bonding_dft_val |
dft_0 |
hssi_pldadapt_tx_chnl_bonding |
disable |
hssi_pldadapt_tx_comp_cnt |
0 |
hssi_pldadapt_tx_compin_sel |
compin_master |
hssi_pldadapt_tx_hdpldadapt_csr_clk_hz |
0 |
hssi_pldadapt_tx_ctrl_plane_bonding |
individual |
hssi_pldadapt_tx_ds_bypass_pipeln |
ds_bypass_pipeln_dis |
hssi_pldadapt_tx_ds_last_chnl |
ds_not_last_chnl |
hssi_pldadapt_tx_ds_master |
ds_master_en |
hssi_pldadapt_tx_duplex_mode |
disable |
hssi_pldadapt_tx_dv_bond |
dv_bond_dis |
hssi_pldadapt_tx_dv_gen |
dv_gen_dis |
hssi_pldadapt_tx_fifo_double_write |
fifo_double_write_dis |
hssi_pldadapt_tx_fifo_mode |
phase_comp |
hssi_pldadapt_tx_fifo_rd_clk_frm_gen_scg_en |
disable |
hssi_pldadapt_tx_fifo_rd_clk_scg_en |
disable |
hssi_pldadapt_tx_fifo_rd_clk_sel |
fifo_rd_pma_aib_tx_clk |
hssi_pldadapt_tx_fifo_stop_rd |
n_rd_empty |
hssi_pldadapt_tx_fifo_stop_wr |
n_wr_full |
hssi_pldadapt_tx_fifo_width |
fifo_single_width |
hssi_pldadapt_tx_fifo_wr_clk_scg_en |
disable |
hssi_pldadapt_tx_fpll_shared_direct_async_in_sel |
fpll_shared_direct_async_in_rowclk |
hssi_pldadapt_tx_frmgen_burst |
frmgen_burst_dis |
hssi_pldadapt_tx_frmgen_bypass |
frmgen_bypass_dis |
hssi_pldadapt_tx_frmgen_mfrm_length |
2048 |
hssi_pldadapt_tx_frmgen_pipeln |
frmgen_pipeln_dis |
hssi_pldadapt_tx_frmgen_pyld_ins |
frmgen_pyld_ins_dis |
hssi_pldadapt_tx_frmgen_wordslip |
frmgen_wordslip_dis |
hssi_pldadapt_tx_fsr_hip_fsr_in_bit0_rst_val |
reset_to_zero_hfsrin0 |
hssi_pldadapt_tx_fsr_hip_fsr_in_bit1_rst_val |
reset_to_zero_hfsrin1 |
hssi_pldadapt_tx_fsr_hip_fsr_in_bit2_rst_val |
reset_to_zero_hfsrin2 |
hssi_pldadapt_tx_fsr_hip_fsr_in_bit3_rst_val |
reset_to_zero_hfsrin3 |
hssi_pldadapt_tx_fsr_hip_fsr_out_bit0_rst_val |
reset_to_zero_hfsrout0 |
hssi_pldadapt_tx_fsr_hip_fsr_out_bit1_rst_val |
reset_to_zero_hfsrout1 |
hssi_pldadapt_tx_fsr_hip_fsr_out_bit2_rst_val |
reset_to_zero_hfsrout2 |
hssi_pldadapt_tx_fsr_hip_fsr_out_bit3_rst_val |
reset_to_zero_hfsrout3 |
hssi_pldadapt_tx_fsr_mask_tx_pll_rst_val |
reset_to_zero_maskpll |
hssi_pldadapt_tx_fsr_pld_txelecidle_rst_val |
reset_to_zero_txelec |
hssi_pldadapt_tx_gb_tx_idwidth |
idwidth_66 |
hssi_pldadapt_tx_gb_tx_odwidth |
odwidth_32 |
hssi_pldadapt_tx_hip_mode |
disable_hip |
hssi_pldadapt_tx_hip_osc_clk_scg_en |
disable |
hssi_pldadapt_tx_hrdrst_dcd_cal_done_bypass |
disable |
hssi_pldadapt_tx_hrdrst_rst_sm_dis |
enable_tx_rst_sm |
hssi_pldadapt_tx_hrdrst_rx_osc_clk_scg_en |
disable |
hssi_pldadapt_tx_hrdrst_user_ctl_en |
disable |
hssi_pldadapt_tx_indv |
indv_en |
hssi_pldadapt_tx_is_paired_with |
other |
hssi_pldadapt_tx_loopback_mode |
disable |
hssi_pldadapt_tx_low_latency_en |
disable |
hssi_pldadapt_tx_osc_clk_scg_en |
disable |
hssi_pldadapt_tx_phcomp_rd_del |
phcomp_rd_del2 |
hssi_pldadapt_tx_pipe_mode |
disable_pipe |
hssi_pldadapt_tx_hdpldadapt_pld_avmm1_clk_rowclk_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_pld_avmm2_clk_rowclk_hz |
0 |
hssi_pldadapt_tx_pld_clk1_delay_en |
disable |
hssi_pldadapt_tx_pld_clk1_delay_sel |
delay_path0 |
hssi_pldadapt_tx_pld_clk1_inv_en |
disable |
hssi_pldadapt_tx_pld_clk1_sel |
pld_clk1_rowclk |
hssi_pldadapt_tx_pld_clk2_sel |
pld_clk2_rowclk |
hssi_pldadapt_tx_hdpldadapt_pld_sclk1_rowclk_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_pld_sclk2_rowclk_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_dcm_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_rowclk_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_dcm_hz |
0 |
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_rowclk_hz |
0 |
hssi_pldadapt_tx_pma_aib_tx_clk_expected_setting |
not_used |
hssi_pldadapt_tx_powerdown_mode |
powerdown |
hssi_pldadapt_tx_powermode_dc |
powerdown |
hssi_pldadapt_tx_powermode_freq_hz_aib_fabric_rx_sr_clk_in |
0 |
hssi_pldadapt_tx_powermode_freq_hz_pld_tx_clk1_dcm |
0 |
hssi_pldadapt_tx_sh_err |
sh_err_dis |
hssi_pldadapt_tx_hdpldadapt_speed_grade |
dash_1 |
hssi_pldadapt_tx_hdpldadapt_sr_sr_testbus_sel |
ssr_testbus |
hssi_pldadapt_tx_stretch_num_stages |
zero_stage |
hssi_pldadapt_tx_sup_mode |
user_mode |
hssi_pldadapt_tx_tx_datapath_tb_sel |
cp_bond |
hssi_pldadapt_tx_tx_fastbond_rden |
rden_ds_del_us_del |
hssi_pldadapt_tx_tx_fastbond_wren |
wren_ds_del_us_del |
hssi_pldadapt_tx_tx_fifo_power_mode |
full_width_full_depth |
hssi_pldadapt_tx_tx_fifo_read_latency_adjust |
disable |
hssi_pldadapt_tx_tx_fifo_write_latency_adjust |
disable |
hssi_pldadapt_tx_tx_hip_aib_ssr_in_polling_bypass |
disable |
hssi_pldadapt_tx_tx_osc_clock_setting |
osc_clk_div_by1 |
hssi_pldadapt_tx_tx_pld_10g_tx_bitslip_polling_bypass |
disable |
hssi_pldadapt_tx_tx_pld_8g_tx_boundary_sel_polling_bypass |
disable |
hssi_pldadapt_tx_tx_pld_pma_fpll_cnt_sel_polling_bypass |
disable |
hssi_pldadapt_tx_tx_pld_pma_fpll_num_phase_shifts_polling_bypass |
disable |
hssi_pldadapt_tx_tx_usertest_sel |
enable |
hssi_pldadapt_tx_txfifo_empty |
empty_default |
hssi_pldadapt_tx_txfifo_full |
full_pc_sw |
hssi_pldadapt_tx_txfifo_mode |
txphase_comp |
hssi_pldadapt_tx_txfifo_pempty |
2 |
hssi_pldadapt_tx_txfifo_pfull |
24 |
hssi_pldadapt_tx_us_bypass_pipeln |
us_bypass_pipeln_dis |
hssi_pldadapt_tx_us_last_chnl |
us_not_last_chnl |
hssi_pldadapt_tx_us_master |
us_master_en |
hssi_pldadapt_tx_word_align_enable |
disable |
hssi_pldadapt_tx_word_mark |
wm_en |
hssi_pldadapt_tx_silicon_rev |
14nm5 |
hssi_pldadapt_tx_reconfig_settings |
{} |
hssi_ctp_bti_protected |
true |
hssi_ctp_func_mode |
pcie_g4_x16_ep |
hssi_ctp_is_active |
false |
hssi_ctp_is_cvp_enable |
false |
hssi_ctp_is_present |
false |
hssi_ctp_powerdown_mode |
true |
hssi_ctp_sim_mode |
hardware_mode |
hssi_ctp_sup_mode |
user_mode |
hssi_ctp_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch0_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch0_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch0_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch0_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch0_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch0_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch0_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch10_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch10_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch10_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch10_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch10_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch10_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch10_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch11_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch11_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch11_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch11_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch11_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch11_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch11_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch12_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch12_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch12_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch12_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch12_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch12_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch12_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch13_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch13_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch13_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch13_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch13_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch13_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch13_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch14_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch14_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch14_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch14_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch14_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch14_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch14_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch15_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch15_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch15_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch15_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch15_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch15_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch15_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch16_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch16_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch16_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch16_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch16_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch16_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch16_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch17_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch17_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch17_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch17_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch17_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch17_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch17_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch18_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch18_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch18_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch18_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch18_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch18_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch18_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch19_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch19_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch19_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch19_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch19_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch19_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch19_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch1_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch1_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch1_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch1_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch1_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch1_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch1_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch20_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch20_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch20_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch20_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch20_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch20_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch20_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch21_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch21_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch21_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch21_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch21_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch21_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch21_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch22_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch22_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch22_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch22_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch22_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch22_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch22_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch23_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch23_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch23_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch23_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch23_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch23_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch23_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch2_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch2_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch2_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch2_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch2_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch2_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch2_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch3_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch3_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch3_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch3_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch3_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch3_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch3_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch4_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch4_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch4_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch4_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch4_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch4_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch4_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch5_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch5_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch5_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch5_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch5_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch5_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch5_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch6_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch6_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch6_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch6_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch6_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch6_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch6_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch7_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch7_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch7_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch7_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch7_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch7_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch7_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch8_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch8_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch8_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch8_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch8_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch8_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch8_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch9_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch9_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch9_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch9_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch9_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch9_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibadapt_wrap_ch9_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powermode_ac |
pwr_pcie_x16 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powermode_ac_avmm2 |
avmm2_off |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powermode_ac_rx_datapath |
rx_datapath_off |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powermode_ac_sr |
sr_off |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powermode_ac_tx_datapath |
tx_datapath_off |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibcmn_top_powermode_freq_hz |
1000000000 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_clksrc_sel |
sel_pcie |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_ctrl_sel_mode |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_dfd_ctrl_mux_sel |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_dfd_ctrl_src_sel |
pld_src |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_ecc_chnl_sel |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_ecc_enable_mode |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_ecc_mask |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_cfgbox_autoclear_dis |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_cfgbox_msg |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_cfgbox_send_msg |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_rxadpt_rst_ovren |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_rxadpt_rst_ovrval |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_spare0_rsvd |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_spare0_rsvd_prst |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_tx_div2_rst_opt |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_txadpt_rst_ovren |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_txadpt_rst_ovrval |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_usrbox_autoclear_dis |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_usrbox_msg |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set0_usrbox_send_msg |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_cfgbox_autoclear_dis |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_cfgbox_msg |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_cfgbox_send_msg |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_rxadpt_rst_ovren |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_rxadpt_rst_ovrval |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_spare0_rsvd |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_spare0_rsvd_prst |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_tx_div2_rst_opt |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_txadpt_rst_ovren |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_txadpt_rst_ovrval |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_usrbox_autoclear_dis |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_usrbox_msg |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_set1_usrbox_send_msg |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_aib_csr_top_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_adptwrap_dummy_func_mode |
c3adpt_ehip |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_adptwrap_dummy_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_adptwrap_dummy_powermode_ac |
pcie_g4_x16 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_adptwrap_dummy_powermode_dc |
powerdown |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_adptwrap_dummy_powermode_freq_hz |
250 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_adptwrap_dummy_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_adptwrap_dummy_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aioavmm1_op_mode |
aioavmm1_pwr_down |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aioavmm1_powermode_ac |
aioavmm1_avmm1_osc_div1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aioavmm1_powermode_dc |
aioavmm1_powerdown_avmm1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aioavmm2_op_mode |
aioavmm2_pwr_down |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aioavmm2_powermode_ac |
aioavmm2_avmm2_osc_div1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aioavmm2_powermode_dc |
aioavmm2_powerdown_avmm2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aiorx_op_mode |
aiorx_pwr_down |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aiorx_powermode_ac |
aiorx_rxdatapath_low_speed_pwr |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aiorx_powermode_dc |
aiorx_powerdown_rxdatapath |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aiotx_op_mode |
aiotx_pwr_down |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aiotx_powermode_ac |
aiotx_txdatapath_low_speed_pwr |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_aiotx_powermode_dc |
aiotx_powerdown_txdatapath |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_avmm_clk_hz |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aioavmm1_aib_red_avm1_shiften |
chnl0_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aioavmm2_aib_red_rx_shiften |
chnl0_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aioavmm2_aib_red_tx_shiften |
chnl0_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiorx_aib_red_rx_shiften |
chnl0_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_dirclkn_shiften |
chnl0_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_dirclkp_shiften |
chnl0_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_drx_shiften |
chnl0_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_dtx_shiften |
chnl0_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_pinp_shiften |
chnl0_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_rx_shiften |
chnl0_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_tx_shiften |
chnl0_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_txferclkout_shiften |
chnl0_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl0_aiotx_aib_red_txferclkoutn_shiften |
chnl0_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aioavmm1_aib_red_avm1_shiften |
chnl10_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aioavmm2_aib_red_rx_shiften |
chnl10_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aioavmm2_aib_red_tx_shiften |
chnl10_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiorx_aib_red_rx_shiften |
chnl10_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_dirclkn_shiften |
chnl10_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_dirclkp_shiften |
chnl10_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_drx_shiften |
chnl10_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_dtx_shiften |
chnl10_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_pinp_shiften |
chnl10_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_rx_shiften |
chnl10_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_tx_shiften |
chnl10_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_txferclkout_shiften |
chnl10_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl10_aiotx_aib_red_txferclkoutn_shiften |
chnl10_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aioavmm1_aib_red_avm1_shiften |
chnl11_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aioavmm2_aib_red_rx_shiften |
chnl11_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aioavmm2_aib_red_tx_shiften |
chnl11_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiorx_aib_red_rx_shiften |
chnl11_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_dirclkn_shiften |
chnl11_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_dirclkp_shiften |
chnl11_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_drx_shiften |
chnl11_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_dtx_shiften |
chnl11_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_pinp_shiften |
chnl11_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_rx_shiften |
chnl11_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_tx_shiften |
chnl11_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_txferclkout_shiften |
chnl11_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl11_aiotx_aib_red_txferclkoutn_shiften |
chnl11_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aioavmm1_aib_red_avm1_shiften |
chnl12_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aioavmm2_aib_red_rx_shiften |
chnl12_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aioavmm2_aib_red_tx_shiften |
chnl12_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiorx_aib_red_rx_shiften |
chnl12_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_dirclkn_shiften |
chnl12_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_dirclkp_shiften |
chnl12_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_drx_shiften |
chnl12_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_dtx_shiften |
chnl12_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_pinp_shiften |
chnl12_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_rx_shiften |
chnl12_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_tx_shiften |
chnl12_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_txferclkout_shiften |
chnl12_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl12_aiotx_aib_red_txferclkoutn_shiften |
chnl12_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aioavmm1_aib_red_avm1_shiften |
chnl13_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aioavmm2_aib_red_rx_shiften |
chnl13_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aioavmm2_aib_red_tx_shiften |
chnl13_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiorx_aib_red_rx_shiften |
chnl13_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_dirclkn_shiften |
chnl13_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_dirclkp_shiften |
chnl13_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_drx_shiften |
chnl13_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_dtx_shiften |
chnl13_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_pinp_shiften |
chnl13_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_rx_shiften |
chnl13_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_tx_shiften |
chnl13_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_txferclkout_shiften |
chnl13_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl13_aiotx_aib_red_txferclkoutn_shiften |
chnl13_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aioavmm1_aib_red_avm1_shiften |
chnl14_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aioavmm2_aib_red_rx_shiften |
chnl14_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aioavmm2_aib_red_tx_shiften |
chnl14_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiorx_aib_red_rx_shiften |
chnl14_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_dirclkn_shiften |
chnl14_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_dirclkp_shiften |
chnl14_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_drx_shiften |
chnl14_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_dtx_shiften |
chnl14_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_pinp_shiften |
chnl14_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_rx_shiften |
chnl14_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_tx_shiften |
chnl14_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_txferclkout_shiften |
chnl14_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl14_aiotx_aib_red_txferclkoutn_shiften |
chnl14_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aioavmm1_aib_red_avm1_shiften |
chnl15_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aioavmm2_aib_red_rx_shiften |
chnl15_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aioavmm2_aib_red_tx_shiften |
chnl15_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiorx_aib_red_rx_shiften |
chnl15_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_dirclkn_shiften |
chnl15_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_dirclkp_shiften |
chnl15_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_drx_shiften |
chnl15_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_dtx_shiften |
chnl15_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_pinp_shiften |
chnl15_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_rx_shiften |
chnl15_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_tx_shiften |
chnl15_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_txferclkout_shiften |
chnl15_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl15_aiotx_aib_red_txferclkoutn_shiften |
chnl15_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aioavmm1_aib_red_avm1_shiften |
chnl16_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aioavmm2_aib_red_rx_shiften |
chnl16_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aioavmm2_aib_red_tx_shiften |
chnl16_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiorx_aib_red_rx_shiften |
chnl16_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_dirclkn_shiften |
chnl16_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_dirclkp_shiften |
chnl16_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_drx_shiften |
chnl16_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_dtx_shiften |
chnl16_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_pinp_shiften |
chnl16_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_rx_shiften |
chnl16_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_tx_shiften |
chnl16_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_txferclkout_shiften |
chnl16_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl16_aiotx_aib_red_txferclkoutn_shiften |
chnl16_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aioavmm1_aib_red_avm1_shiften |
chnl17_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aioavmm2_aib_red_rx_shiften |
chnl17_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aioavmm2_aib_red_tx_shiften |
chnl17_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiorx_aib_red_rx_shiften |
chnl17_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_dirclkn_shiften |
chnl17_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_dirclkp_shiften |
chnl17_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_drx_shiften |
chnl17_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_dtx_shiften |
chnl17_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_pinp_shiften |
chnl17_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_rx_shiften |
chnl17_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_tx_shiften |
chnl17_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_txferclkout_shiften |
chnl17_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl17_aiotx_aib_red_txferclkoutn_shiften |
chnl17_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aioavmm1_aib_red_avm1_shiften |
chnl18_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aioavmm2_aib_red_rx_shiften |
chnl18_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aioavmm2_aib_red_tx_shiften |
chnl18_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiorx_aib_red_rx_shiften |
chnl18_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_dirclkn_shiften |
chnl18_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_dirclkp_shiften |
chnl18_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_drx_shiften |
chnl18_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_dtx_shiften |
chnl18_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_pinp_shiften |
chnl18_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_rx_shiften |
chnl18_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_tx_shiften |
chnl18_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_txferclkout_shiften |
chnl18_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl18_aiotx_aib_red_txferclkoutn_shiften |
chnl18_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aioavmm1_aib_red_avm1_shiften |
chnl19_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aioavmm2_aib_red_rx_shiften |
chnl19_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aioavmm2_aib_red_tx_shiften |
chnl19_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiorx_aib_red_rx_shiften |
chnl19_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_dirclkn_shiften |
chnl19_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_dirclkp_shiften |
chnl19_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_drx_shiften |
chnl19_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_dtx_shiften |
chnl19_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_pinp_shiften |
chnl19_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_rx_shiften |
chnl19_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_tx_shiften |
chnl19_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_txferclkout_shiften |
chnl19_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl19_aiotx_aib_red_txferclkoutn_shiften |
chnl19_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aioavmm1_aib_red_avm1_shiften |
chnl1_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aioavmm2_aib_red_rx_shiften |
chnl1_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aioavmm2_aib_red_tx_shiften |
chnl1_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiorx_aib_red_rx_shiften |
chnl1_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_dirclkn_shiften |
chnl1_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_dirclkp_shiften |
chnl1_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_drx_shiften |
chnl1_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_dtx_shiften |
chnl1_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_pinp_shiften |
chnl1_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_rx_shiften |
chnl1_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_tx_shiften |
chnl1_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_txferclkout_shiften |
chnl1_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl1_aiotx_aib_red_txferclkoutn_shiften |
chnl1_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aioavmm1_aib_red_avm1_shiften |
chnl20_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aioavmm2_aib_red_rx_shiften |
chnl20_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aioavmm2_aib_red_tx_shiften |
chnl20_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiorx_aib_red_rx_shiften |
chnl20_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_dirclkn_shiften |
chnl20_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_dirclkp_shiften |
chnl20_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_drx_shiften |
chnl20_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_dtx_shiften |
chnl20_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_pinp_shiften |
chnl20_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_rx_shiften |
chnl20_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_tx_shiften |
chnl20_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_txferclkout_shiften |
chnl20_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl20_aiotx_aib_red_txferclkoutn_shiften |
chnl20_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aioavmm1_aib_red_avm1_shiften |
chnl21_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aioavmm2_aib_red_rx_shiften |
chnl21_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aioavmm2_aib_red_tx_shiften |
chnl21_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiorx_aib_red_rx_shiften |
chnl21_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_dirclkn_shiften |
chnl21_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_dirclkp_shiften |
chnl21_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_drx_shiften |
chnl21_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_dtx_shiften |
chnl21_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_pinp_shiften |
chnl21_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_rx_shiften |
chnl21_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_tx_shiften |
chnl21_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_txferclkout_shiften |
chnl21_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl21_aiotx_aib_red_txferclkoutn_shiften |
chnl21_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aioavmm1_aib_red_avm1_shiften |
chnl22_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aioavmm2_aib_red_rx_shiften |
chnl22_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aioavmm2_aib_red_tx_shiften |
chnl22_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiorx_aib_red_rx_shiften |
chnl22_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_dirclkn_shiften |
chnl22_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_dirclkp_shiften |
chnl22_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_drx_shiften |
chnl22_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_dtx_shiften |
chnl22_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_pinp_shiften |
chnl22_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_rx_shiften |
chnl22_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_tx_shiften |
chnl22_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_txferclkout_shiften |
chnl22_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl22_aiotx_aib_red_txferclkoutn_shiften |
chnl22_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aioavmm1_aib_red_avm1_shiften |
chnl23_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aioavmm2_aib_red_rx_shiften |
chnl23_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aioavmm2_aib_red_tx_shiften |
chnl23_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiorx_aib_red_rx_shiften |
chnl23_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_dirclkn_shiften |
chnl23_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_dirclkp_shiften |
chnl23_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_drx_shiften |
chnl23_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_dtx_shiften |
chnl23_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_pinp_shiften |
chnl23_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_rx_shiften |
chnl23_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_tx_shiften |
chnl23_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_txferclkout_shiften |
chnl23_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl23_aiotx_aib_red_txferclkoutn_shiften |
chnl23_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aioavmm1_aib_red_avm1_shiften |
chnl2_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aioavmm2_aib_red_rx_shiften |
chnl2_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aioavmm2_aib_red_tx_shiften |
chnl2_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiorx_aib_red_rx_shiften |
chnl2_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_dirclkn_shiften |
chnl2_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_dirclkp_shiften |
chnl2_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_drx_shiften |
chnl2_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_dtx_shiften |
chnl2_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_pinp_shiften |
chnl2_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_rx_shiften |
chnl2_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_tx_shiften |
chnl2_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_txferclkout_shiften |
chnl2_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl2_aiotx_aib_red_txferclkoutn_shiften |
chnl2_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aioavmm1_aib_red_avm1_shiften |
chnl3_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aioavmm2_aib_red_rx_shiften |
chnl3_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aioavmm2_aib_red_tx_shiften |
chnl3_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiorx_aib_red_rx_shiften |
chnl3_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_dirclkn_shiften |
chnl3_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_dirclkp_shiften |
chnl3_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_drx_shiften |
chnl3_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_dtx_shiften |
chnl3_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_pinp_shiften |
chnl3_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_rx_shiften |
chnl3_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_tx_shiften |
chnl3_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_txferclkout_shiften |
chnl3_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl3_aiotx_aib_red_txferclkoutn_shiften |
chnl3_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aioavmm1_aib_red_avm1_shiften |
chnl4_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aioavmm2_aib_red_rx_shiften |
chnl4_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aioavmm2_aib_red_tx_shiften |
chnl4_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiorx_aib_red_rx_shiften |
chnl4_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_dirclkn_shiften |
chnl4_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_dirclkp_shiften |
chnl4_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_drx_shiften |
chnl4_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_dtx_shiften |
chnl4_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_pinp_shiften |
chnl4_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_rx_shiften |
chnl4_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_tx_shiften |
chnl4_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_txferclkout_shiften |
chnl4_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl4_aiotx_aib_red_txferclkoutn_shiften |
chnl4_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aioavmm1_aib_red_avm1_shiften |
chnl5_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aioavmm2_aib_red_rx_shiften |
chnl5_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aioavmm2_aib_red_tx_shiften |
chnl5_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiorx_aib_red_rx_shiften |
chnl5_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_dirclkn_shiften |
chnl5_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_dirclkp_shiften |
chnl5_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_drx_shiften |
chnl5_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_dtx_shiften |
chnl5_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_pinp_shiften |
chnl5_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_rx_shiften |
chnl5_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_tx_shiften |
chnl5_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_txferclkout_shiften |
chnl5_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl5_aiotx_aib_red_txferclkoutn_shiften |
chnl5_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aioavmm1_aib_red_avm1_shiften |
chnl6_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aioavmm2_aib_red_rx_shiften |
chnl6_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aioavmm2_aib_red_tx_shiften |
chnl6_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiorx_aib_red_rx_shiften |
chnl6_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_dirclkn_shiften |
chnl6_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_dirclkp_shiften |
chnl6_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_drx_shiften |
chnl6_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_dtx_shiften |
chnl6_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_pinp_shiften |
chnl6_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_rx_shiften |
chnl6_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_tx_shiften |
chnl6_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_txferclkout_shiften |
chnl6_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl6_aiotx_aib_red_txferclkoutn_shiften |
chnl6_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aioavmm1_aib_red_avm1_shiften |
chnl7_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aioavmm2_aib_red_rx_shiften |
chnl7_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aioavmm2_aib_red_tx_shiften |
chnl7_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiorx_aib_red_rx_shiften |
chnl7_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_dirclkn_shiften |
chnl7_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_dirclkp_shiften |
chnl7_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_drx_shiften |
chnl7_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_dtx_shiften |
chnl7_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_pinp_shiften |
chnl7_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_rx_shiften |
chnl7_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_tx_shiften |
chnl7_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_txferclkout_shiften |
chnl7_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl7_aiotx_aib_red_txferclkoutn_shiften |
chnl7_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aioavmm1_aib_red_avm1_shiften |
chnl8_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aioavmm2_aib_red_rx_shiften |
chnl8_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aioavmm2_aib_red_tx_shiften |
chnl8_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiorx_aib_red_rx_shiften |
chnl8_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_dirclkn_shiften |
chnl8_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_dirclkp_shiften |
chnl8_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_drx_shiften |
chnl8_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_dtx_shiften |
chnl8_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_pinp_shiften |
chnl8_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_rx_shiften |
chnl8_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_tx_shiften |
chnl8_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_txferclkout_shiften |
chnl8_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl8_aiotx_aib_red_txferclkoutn_shiften |
chnl8_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aioavmm1_aib_red_avm1_shiften |
chnl9_avmm1aib_red_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aioavmm2_aib_red_rx_shiften |
chnl9_avmm2aib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aioavmm2_aib_red_tx_shiften |
chnl9_avmm2aib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiorx_aib_red_rx_shiften |
chnl9_rxaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_dirclkn_shiften |
chnl9_txaib_red_dirclkn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_dirclkp_shiften |
chnl9_txaib_red_dirclkp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_drx_shiften |
chnl9_txaib_red_drx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_dtx_shiften |
chnl9_txaib_red_dtx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_pinp_shiften |
chnl9_txaib_red_pinp_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_rx_shiften |
chnl9_txaib_red_rx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_tx_shiften |
chnl9_txaib_red_tx_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_txferclkout_shiften |
chnl9_txaib_red_txferclkout_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_chnl9_aiotx_aib_red_txferclkoutn_shiften |
chnl9_txaib_red_txferclkoutn_shift_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_dfd_dll_dcc_en |
disable_dfd |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_dft_hssitestip_dll_dcc_en |
disable_dft |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_redundancy_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_rx_transfer_clk_duty_cycle |
rx_trsf_clk_dc_50_50 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_rx_transfer_clk_freq |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_rx_transfer_clk_freq_hz |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_datasel_gr0 |
set0_avmm1aib_datasel0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_datasel_gr1 |
set0_avmm1aib_datasel1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_datasel_gr2 |
set0_avmm1aib_datasel2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_inctrl_gr0 |
set0_avmm1aib_inctrl0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_inctrl_gr1 |
set0_avmm1aib_inctrl1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_inctrl_gr2 |
set0_avmm1aib_inctrl2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_outctrl_gr0 |
set0_avmm1aib_outen0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_outctrl_gr1 |
set0_avmm1aib_outen1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm1_aib_outctrl_gr2 |
set0_avmm1aib_outen2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm2_aib_datasel |
set0_avmm2aib_datasel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm2_aib_inctrl |
set0_avmm2aib_inctrl_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aioavmm2_aib_outctrl |
set0_avmm2aib_outen_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_datasel_gr0 |
set0_rxaib_datasel0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_datasel_gr1 |
set0_rxaib_datasel1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_datasel_gr2 |
set0_rxaib_datasel2_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_ddrctrl_gr0 |
set0_rxaib_ddr0_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_ddrctrl_gr1 |
set0_rxaib_ddr1_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_iinasyncen |
set0_rxaib_inasyncen_setting2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_iinclken |
set0_rxaib_inclken_setting3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_outctrl_gr0 |
set0_rxaib_outen0_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_outctrl_gr1 |
set0_rxaib_outen1_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_outctrl_gr2 |
set0_rxaib_outen2_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_outctrl_gr3 |
set0_rxaib_outen3_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_clkdiv |
set0_rxaib_rx_clkdiv_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_byp |
set0_rxaib_rx_dcc_byp_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_byp_iocsr_unused |
set0_rxaib_rx_dcc_byp_disable_iocsr_unused |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_cont_cal |
set0_rxaib_rx_dcc_cal_single |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_cont_cal_iocsr_unused |
set0_rxaib_rx_dcc_cal_single_iocsr_unused |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_dft |
set0_rxaib_rx_dcc_dft_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_dft_sel |
set0_rxaib_rx_dcc_dft_mode0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_dll_entest |
set0_rxaib_rx_dcc_dll_test_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_dy_ctl_static |
set0_rxaib_rx_dcc_dy_ctl_static_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_dy_ctlsel |
set0_rxaib_rx_dcc_dy_ctlsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_en |
set0_rxaib_rx_dcc_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_en_iocsr_unused |
set0_rxaib_rx_dcc_disable_iocsr_unused |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_manual_dn |
set0_rxaib_rx_dcc_manual_dn0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_manual_up |
set0_rxaib_rx_dcc_manual_up0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_rst_prgmnvrt |
set0_rxaib_rx_dcc_st_rst_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_core_dn_prgmnvrt |
set0_rxaib_rx_dcc_st_core_dn_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_core_up_prgmnvrt |
set0_rxaib_rx_dcc_st_core_up_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_core_updnen |
set0_rxaib_rx_dcc_st_core_updnen_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_dftmuxsel |
set0_rxaib_rx_dcc_st_dftmuxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_dly_pst |
set0_rxaib_rx_dcc_st_dly_pst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_en |
set0_rxaib_rx_dcc_st_en_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_lockreq_muxsel |
set0_rxaib_rx_dcc_st_lockreq_muxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_new_dll |
set0_rxaib_rx_dcc_new_dll_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_new_dll2 |
set0_rxaib_rx_dcc_new_dll2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_st_rst |
set0_rxaib_rx_dcc_st_rst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_dcc_test_clk_pll_en_n |
set0_rxaib_rx_dcc_test_clk_pll_en_n_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_halfcode |
set0_rxaib_rx_halfcode_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiorx_aib_rx_selflock |
set0_rxaib_rx_selflock_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_datasel_gr0 |
set0_txaib_datasel0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_datasel_gr1 |
set0_txaib_datasel1_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_datasel_gr2 |
set0_txaib_datasel2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_clkdiv |
set0_txaib_dllstr_align_clkdiv_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_dcc_dll_dft_sel |
set0_txaib_dllstr_align_dcc_dll_dft_sel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_dft_ch_muxsel |
set0_txaib_dllstr_align_dft_ch_muxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_dly_pst |
set0_txaib_dllstr_align_dly_pst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_dy_ctl_static |
set0_txaib_dllstr_align_dy_ctl_static_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_dy_ctlsel |
set0_txaib_dllstr_align_dy_ctlsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_entest |
set0_txaib_dllstr_align_test_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_halfcode |
set0_txaib_dllstr_align_halfcode_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_selflock |
set0_txaib_dllstr_align_selflock_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_core_dn_prgmnvrt |
set0_txaib_dllstr_align_st_core_dn_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_core_up_prgmnvrt |
set0_txaib_dllstr_align_st_core_up_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_core_updnen |
set0_txaib_dllstr_align_st_core_updnen_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_dftmuxsel |
set0_txaib_dllstr_align_st_dftmuxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_en |
set0_txaib_dllstr_align_st_en_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_lockreq_muxsel |
set0_txaib_dllstr_align_st_lockreq_muxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_new_dll |
set0_txaib_dllstr_align_new_dll_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_new_dll2 |
set0_txaib_dllstr_align_new_dll2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_rst |
set0_txaib_dllstr_align_st_rst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_st_rst_prgmnvrt |
set0_txaib_dllstr_align_st_rst_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_dllstr_align_test_clk_pll_en_n |
set0_txaib_dllstr_align_test_clk_pll_en_n_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_inctrl_gr0 |
set0_txaib_inctrl0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_inctrl_gr1 |
set0_txaib_inctrl1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_inctrl_gr2 |
set0_txaib_inctrl2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_inctrl_gr3 |
set0_txaib_inctrl3_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outctrl_gr0 |
set0_txaib_outen0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outctrl_gr1 |
set0_txaib_outen1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outctrl_gr2 |
set0_txaib_outen2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outndrv_r12 |
set0_txaib_ndrv12_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outndrv_r34 |
set0_txaib_ndrv34_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outndrv_r56 |
set0_txaib_ndrv56_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outndrv_r78 |
set0_txaib_ndrv78_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outpdrv_r12 |
set0_txaib_pdrv12_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outpdrv_r34 |
set0_txaib_pdrv34_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outpdrv_r56 |
set0_txaib_pdrv56_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set0_aiotx_aib_outpdrv_r78 |
set0_txaib_pdrv78_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_datasel_gr0 |
set1_avmm1aib_datasel0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_datasel_gr1 |
set1_avmm1aib_datasel1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_datasel_gr2 |
set1_avmm1aib_datasel2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_inctrl_gr0 |
set1_avmm1aib_inctrl0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_inctrl_gr1 |
set1_avmm1aib_inctrl1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_inctrl_gr2 |
set1_avmm1aib_inctrl2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_outctrl_gr0 |
set1_avmm1aib_outen0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_outctrl_gr1 |
set1_avmm1aib_outen1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm1_aib_outctrl_gr2 |
set1_avmm1aib_outen2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm2_aib_datasel |
set1_avmm2aib_datasel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm2_aib_inctrl |
set1_avmm2aib_inctrl_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aioavmm2_aib_outctrl |
set1_avmm2aib_outen_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_datasel_gr0 |
set1_rxaib_datasel0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_datasel_gr1 |
set1_rxaib_datasel1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_datasel_gr2 |
set1_rxaib_datasel2_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_ddrctrl_gr0 |
set1_rxaib_ddr0_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_ddrctrl_gr1 |
set1_rxaib_ddr1_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_iinasyncen |
set1_rxaib_inasyncen_setting2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_iinclken |
set1_rxaib_inclken_setting3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_outctrl_gr0 |
set1_rxaib_outen0_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_outctrl_gr1 |
set1_rxaib_outen1_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_outctrl_gr2 |
set1_rxaib_outen2_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_outctrl_gr3 |
set1_rxaib_outen3_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_clkdiv |
set1_rxaib_rx_clkdiv_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_byp |
set1_rxaib_rx_dcc_byp_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_byp_iocsr_unused |
set1_rxaib_rx_dcc_byp_disable_iocsr_unused |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_cont_cal |
set1_rxaib_rx_dcc_cal_single |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_cont_cal_iocsr_unused |
set1_rxaib_rx_dcc_cal_single_iocsr_unused |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_dft |
set1_rxaib_rx_dcc_dft_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_dft_sel |
set1_rxaib_rx_dcc_dft_mode0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_dll_entest |
set1_rxaib_rx_dcc_dll_test_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_dy_ctl_static |
set1_rxaib_rx_dcc_dy_ctl_static_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_dy_ctlsel |
set1_rxaib_rx_dcc_dy_ctlsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_en |
set1_rxaib_rx_dcc_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_en_iocsr_unused |
set1_rxaib_rx_dcc_disable_iocsr_unused |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_manual_dn |
set1_rxaib_rx_dcc_manual_dn0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_manual_up |
set1_rxaib_rx_dcc_manual_up0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_rst_prgmnvrt |
set1_rxaib_rx_dcc_st_rst_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_core_dn_prgmnvrt |
set1_rxaib_rx_dcc_st_core_dn_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_core_up_prgmnvrt |
set1_rxaib_rx_dcc_st_core_up_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_core_updnen |
set1_rxaib_rx_dcc_st_core_updnen_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_dftmuxsel |
set1_rxaib_rx_dcc_st_dftmuxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_dly_pst |
set1_rxaib_rx_dcc_st_dly_pst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_en |
set1_rxaib_rx_dcc_st_en_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_lockreq_muxsel |
set1_rxaib_rx_dcc_st_lockreq_muxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_new_dll |
set1_rxaib_rx_dcc_new_dll_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_new_dll2 |
set1_rxaib_rx_dcc_new_dll2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_st_rst |
set1_rxaib_rx_dcc_st_rst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_dcc_test_clk_pll_en_n |
set1_rxaib_rx_dcc_test_clk_pll_en_n_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_halfcode |
set1_rxaib_rx_halfcode_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiorx_aib_rx_selflock |
set1_rxaib_rx_selflock_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_datasel_gr0 |
set1_txaib_datasel0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_datasel_gr1 |
set1_txaib_datasel1_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_datasel_gr2 |
set1_txaib_datasel2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_clkdiv |
set1_txaib_dllstr_align_clkdiv_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_dcc_dll_dft_sel |
set1_txaib_dllstr_align_dcc_dll_dft_sel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_dft_ch_muxsel |
set1_txaib_dllstr_align_dft_ch_muxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_dly_pst |
set1_txaib_dllstr_align_dly_pst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_dy_ctl_static |
set1_txaib_dllstr_align_dy_ctl_static_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_dy_ctlsel |
set1_txaib_dllstr_align_dy_ctlsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_entest |
set1_txaib_dllstr_align_test_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_halfcode |
set1_txaib_dllstr_align_halfcode_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_selflock |
set1_txaib_dllstr_align_selflock_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_core_dn_prgmnvrt |
set1_txaib_dllstr_align_st_core_dn_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_core_up_prgmnvrt |
set1_txaib_dllstr_align_st_core_up_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_core_updnen |
set1_txaib_dllstr_align_st_core_updnen_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_dftmuxsel |
set1_txaib_dllstr_align_st_dftmuxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_en |
set1_txaib_dllstr_align_st_en_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_lockreq_muxsel |
set1_txaib_dllstr_align_st_lockreq_muxsel_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_new_dll |
set1_txaib_dllstr_align_new_dll_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_new_dll2 |
set1_txaib_dllstr_align_new_dll2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_rst |
set1_txaib_dllstr_align_st_rst_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_st_rst_prgmnvrt |
set1_txaib_dllstr_align_st_rst_prgmnvrt_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_dllstr_align_test_clk_pll_en_n |
set1_txaib_dllstr_align_test_clk_pll_en_n_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_inctrl_gr0 |
set1_txaib_inctrl0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_inctrl_gr1 |
set1_txaib_inctrl1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_inctrl_gr2 |
set1_txaib_inctrl2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_inctrl_gr3 |
set1_txaib_inctrl3_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outctrl_gr0 |
set1_txaib_outen0_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outctrl_gr1 |
set1_txaib_outen1_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outctrl_gr2 |
set1_txaib_outen2_setting0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outndrv_r12 |
set1_txaib_ndrv12_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outndrv_r34 |
set1_txaib_ndrv34_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outndrv_r56 |
set1_txaib_ndrv56_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outndrv_r78 |
set1_txaib_ndrv78_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outpdrv_r12 |
set1_txaib_pdrv12_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outpdrv_r34 |
set1_txaib_pdrv34_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outpdrv_r56 |
set1_txaib_pdrv56_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_set1_aiotx_aib_outpdrv_r78 |
set1_txaib_pdrv78_setting1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_tx_transfer_clk_freq |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_tx_transfer_clk_freq_hz |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_40_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_41_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_42_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr10_aib_csr10_ctrl_43_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_44_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_45_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_46_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr11_aib_csr11_ctrl_47_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_48_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_49_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_50_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr12_aib_csr12_ctrl_51_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_52_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr13_aib_csr13_ctrl_53_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr3_aib_csr3_ctrl_13_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr5_aib_csr5_ctrl_22_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr5_aib_csr5_ctrl_22_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr7_aib_csr7_ctrl_28_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr7_aib_csr7_ctrl_28_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr7_aib_csr7_ctrl_31_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr7_aib_csr7_ctrl_31_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr7_aib_csr7_ctrl_31_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr8_aib_csr8_ctrl_32_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr8_aib_csr8_ctrl_32_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr8_aib_csr8_ctrl_32_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr8_aib_csr8_ctrl_33_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr8_aib_csr8_ctrl_33_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr8_aib_csr8_ctrl_33_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr8_aib_csr8_ctrl_35_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_36_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_37_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_37_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_37_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_38_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aib_csr9_aib_csr9_ctrl_39_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio0_aib_dprio0_ctrl_1_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio0_aib_dprio0_ctrl_1_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio0_aib_dprio0_ctrl_1_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio0_aib_dprio0_ctrl_1_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio0_aib_dprio0_ctrl_1_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio0_aib_dprio0_ctrl_3_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio0_aib_dprio0_ctrl_3_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad0_aibdprio1_aib_dprio1_ctrl_4_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_40_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_41_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_42_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr10_aib_csr10_ctrl_43_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_44_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_45_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_46_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr11_aib_csr11_ctrl_47_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_48_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_49_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_50_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr12_aib_csr12_ctrl_51_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_52_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr13_aib_csr13_ctrl_53_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr3_aib_csr3_ctrl_13_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr5_aib_csr5_ctrl_22_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr5_aib_csr5_ctrl_22_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr7_aib_csr7_ctrl_28_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr7_aib_csr7_ctrl_28_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr7_aib_csr7_ctrl_31_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr7_aib_csr7_ctrl_31_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr7_aib_csr7_ctrl_31_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr8_aib_csr8_ctrl_32_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr8_aib_csr8_ctrl_32_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr8_aib_csr8_ctrl_32_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr8_aib_csr8_ctrl_33_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr8_aib_csr8_ctrl_33_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr8_aib_csr8_ctrl_33_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr8_aib_csr8_ctrl_35_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_36_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_37_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_37_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_37_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_38_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aib_csr9_aib_csr9_ctrl_39_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio0_aib_dprio0_ctrl_1_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio0_aib_dprio0_ctrl_1_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio0_aib_dprio0_ctrl_1_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio0_aib_dprio0_ctrl_1_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio0_aib_dprio0_ctrl_1_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio0_aib_dprio0_ctrl_3_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio0_aib_dprio0_ctrl_3_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_0 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_1 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_2 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_3 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_4 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_5 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_6 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_aibio_dummy_unused_r_ad1_aibdprio1_aib_dprio1_ctrl_4_7 |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_avmm_osc_clock_setting |
osc_clk_div_by1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_avmm_clk_dcg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_avmm_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_free_run_div_clk |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_rdfifo_empty |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_rdfifo_full |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_rdfifo_stop_read |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_rdfifo_stop_write |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm1_write_resp_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_avmm_clk_dcg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_avmm_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_free_run_div_clk |
set0_avmm2_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_rdfifo_empty |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_rdfifo_full |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_rdfifo_stop_read |
set0_avmm2_rdfifo_rd_empty |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm2_rdfifo_stop_write |
set0_avmm2_rdfifo_wr_full |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm_hrdrst_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm_spare_rsvd |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm_spare_rsvd_prst |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_avmm_testbus_sel |
set0_avmm2_transfer_testbus |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_hwcfg_adpt_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_hwcfg_aib_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_hwcfg_mode |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set0_sr_test_enable |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_avmm_clk_dcg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_avmm_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_free_run_div_clk |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_rdfifo_empty |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_rdfifo_full |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_rdfifo_stop_read |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_rdfifo_stop_write |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm1_write_resp_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_avmm_clk_dcg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_avmm_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_free_run_div_clk |
set1_avmm2_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_rdfifo_empty |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_rdfifo_full |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_rdfifo_stop_read |
set1_avmm2_rdfifo_rd_empty |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm2_rdfifo_stop_write |
set1_avmm2_rdfifo_wr_full |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm_hrdrst_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm_spare_rsvd |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm_spare_rsvd_prst |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_avmm_testbus_sel |
set1_avmm2_transfer_testbus |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_hwcfg_adpt_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_hwcfg_aib_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_hwcfg_mode |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_set1_sr_test_enable |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_avmm_dummy_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_clock_del_measure_enable |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_fifo_mode |
bypass |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_fifo_width |
fifo_single_width |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_loopback_mode |
loopback_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_pma_aib_rx_clk_expected_setting |
not_used |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_rx_osc_clock_setting |
osc_clk_div_by1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_adapter_lpbk_mode |
set0_loopback_disabled |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_aib_lpbk_mode |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_async_direct_hip_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_datapath_mapping_mode |
set0_map_rx_pmadir_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fifo_double_write |
set0_fifo_double_write_dis |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fifo_rd_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fifo_rd_clk_sel |
set0_fifo_rd_rx_ehip_frd_clk |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fifo_stop_rd |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fifo_stop_wr |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fifo_wr_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fifo_wr_clk_sel |
set0_fifo_wr_ehip_rx_clk |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_free_run_div_clk |
set0_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fsr_pld_10g_rx_crc32_err_rst_val |
set0_reset_to_zero_crc32 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fsr_pld_8g_sigdet_out_rst_val |
set0_reset_to_zero_sigdet |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fsr_pld_ltd_b_rst_val |
set0_reset_to_zero_ltdb |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fsr_pld_ltr_rst_val |
set0_reset_to_zero_ltr |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_fsr_pld_rx_fifo_align_clr_rst_val |
set0_reset_to_zero_alignclr |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_hrdrst_dcd_cal_done_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_hrdrst_rst_sm_dis |
set0_enable_rx_rst_sm |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_hrdrst_rx_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_hrdrst_user_ctl_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk1_sel |
set0_feedthru_clk0_clk1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk1_sel0 |
set0_feedthru_clks_or_txfifowr_post_ct_or_txfiford_pre_or_post_ct_mux_clk1_mux0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk1_sel1 |
set0_feedthru_clks_or_txfiford_pre_or_post_ct_mux_clk1_mux1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk1_sel2 |
set0_pma_clks_or_txfiford_pre_ct_mux_clk1_mux2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk1_sel3 |
set0_pma_clks_clk1_mux3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk2_sel |
set0_feedthru_clk0_clk2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk2_sel0 |
set0_pma_clks_or_set0_rxfiford_post_ct_or_set0_rxfifowr_pre_or_post_ct_mux_clk2_mux0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk2_sel1 |
set0_pma_clks_or_set0_rxfifowr_pre_or_post_ct_mux_clk2_mux1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk2_sel2 |
set0_pma_clks_or_set0_rxfifowr_pre_ct_mux_clk2_mux2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_internal_clk2_sel3 |
set0_pma_clks_clk2_mux3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_msb_pipeline_byp |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_phcomp_rd_del |
set0_phcomp_rd_del2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_pma_coreclkin_sel |
set0_pma_coreclkin_osc_clkdiv2_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_10g_krfec_rx_diag_data_status_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_datapath_tb_sel |
set0_aib_dcc_dll_tb |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_fifo_power_mode |
set0_full_width_full_depth |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_fifo_read_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_fifo_write_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_latency_src_sel |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_parity_sel |
set0_func_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pcs_testbus_sel |
set0_direct_tr_tb_bit0_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pcspma_testbus_sel |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pld_8g_a1a2_k1k2_flag_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pld_8g_wa_boundary_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pld_pma_pcie_sw_done_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pld_pma_reser_in_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pld_pma_testbus_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_pld_test_data_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_rmfflag_stretch_enable |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_rmfflag_stretch_num_stages |
set0_rmfflag_zero_stage |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rx_usertest_sel |
set0_direct_tr_usertest3_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfifo_empty |
set0_empty_default |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfifo_full |
set0_full_sw |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfifo_mode |
set0_rxbypass_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfifo_pempty |
2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfifo_pfull |
24 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfiford_post_ct_sel |
set0_rxfiford_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfiford_to_aib_sel |
set0_rxfiford_sclk_to_aib |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfifowr_post_ct_sel |
set0_rxfifowr_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_rxfifowr_pre_ct_sel |
set0_rxfifowr_sclk_pre_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_stretch_num_stages |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_txfiford_post_ct_sel |
set0_txfiford_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_txfiford_pre_ct_sel |
set0_txfiford_sclk_pre_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_txfifowr_from_aib_sel |
set0_txfifowr_sclk_from_aib |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_txfifowr_post_ct_sel |
set0_txfifowr_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set0_word_mark |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_adapter_lpbk_mode |
set1_loopback_disabled |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_aib_lpbk_mode |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_async_direct_hip_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_datapath_mapping_mode |
set1_map_rx_pmadir_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fifo_double_write |
set1_fifo_double_write_dis |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fifo_rd_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fifo_rd_clk_sel |
set1_fifo_rd_rx_ehip_frd_clk |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fifo_stop_rd |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fifo_stop_wr |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fifo_wr_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fifo_wr_clk_sel |
set1_fifo_wr_ehip_rx_clk |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_free_run_div_clk |
set1_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fsr_pld_10g_rx_crc32_err_rst_val |
set1_reset_to_zero_crc32 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fsr_pld_8g_sigdet_out_rst_val |
set1_reset_to_zero_sigdet |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fsr_pld_ltd_b_rst_val |
set1_reset_to_zero_ltdb |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fsr_pld_ltr_rst_val |
set1_reset_to_zero_ltr |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_fsr_pld_rx_fifo_align_clr_rst_val |
set1_reset_to_zero_alignclr |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_hrdrst_dcd_cal_done_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_hrdrst_rst_sm_dis |
set1_enable_rx_rst_sm |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_hrdrst_rx_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_hrdrst_user_ctl_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk1_sel |
set1_feedthru_clk0_clk1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk1_sel0 |
set1_feedthru_clks_or_txfifowr_post_ct_or_txfiford_pre_or_post_ct_mux_clk1_mux0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk1_sel1 |
set1_feedthru_clks_or_txfiford_pre_or_post_ct_mux_clk1_mux1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk1_sel2 |
set1_pma_clks_or_txfiford_pre_ct_mux_clk1_mux2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk1_sel3 |
set1_pma_clks_clk1_mux3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk2_sel |
set1_feedthru_clk0_clk2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk2_sel0 |
set1_pma_clks_or_set1_rxfiford_post_ct_or_set1_rxfifowr_pre_or_post_ct_mux_clk2_mux0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk2_sel1 |
set1_pma_clks_or_set1_rxfifowr_pre_or_post_ct_mux_clk2_mux1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk2_sel2 |
set1_pma_clks_or_set1_rxfifowr_pre_ct_mux_clk2_mux2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_internal_clk2_sel3 |
set1_pma_clks_clk2_mux3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_msb_pipeline_byp |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_phcomp_rd_del |
set1_phcomp_rd_del2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_pma_coreclkin_sel |
set1_pma_coreclkin_osc_clkdiv2_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_10g_krfec_rx_diag_data_status_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_datapath_tb_sel |
set1_aib_dcc_dll_tb |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_fifo_power_mode |
set1_full_width_full_depth |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_fifo_read_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_fifo_write_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_latency_src_sel |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_parity_sel |
set1_func_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pcs_testbus_sel |
set1_direct_tr_tb_bit0_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pcspma_testbus_sel |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pld_8g_a1a2_k1k2_flag_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pld_8g_wa_boundary_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pld_pma_pcie_sw_done_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pld_pma_reser_in_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pld_pma_testbus_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_pld_test_data_polling_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_rmfflag_stretch_enable |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_rmfflag_stretch_num_stages |
set1_rmfflag_zero_stage |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rx_usertest_sel |
set1_direct_tr_usertest3_sel |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfifo_empty |
set1_empty_default |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfifo_full |
set1_full_sw |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfifo_mode |
set1_rxbypass_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfifo_pempty |
2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfifo_pfull |
24 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfiford_post_ct_sel |
set1_rxfiford_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfiford_to_aib_sel |
set1_rxfiford_sclk_to_aib |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfifowr_post_ct_sel |
set1_rxfifowr_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_rxfifowr_pre_ct_sel |
set1_rxfifowr_sclk_pre_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_stretch_num_stages |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_txfiford_post_ct_sel |
set1_txfiford_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_txfiford_pre_ct_sel |
set1_txfiford_sclk_pre_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_txfifowr_from_aib_sel |
set1_txfifowr_sclk_from_aib |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_txfifowr_post_ct_sel |
set1_txfifowr_sclk_post_ct |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_set1_word_mark |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_rxchnl_dummy_word_align_enable |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set0_sr_free_run_div_clk |
set0_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set0_sr_hip_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set0_sr_osc_clk_div_sel |
set0_non_div |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set0_sr_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set0_sr_parity_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set0_sr_reserved_in_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set0_sr_reserved_out_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set1_sr_free_run_div_clk |
set1_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set1_sr_hip_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set1_sr_osc_clk_div_sel |
set1_non_div |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set1_sr_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set1_sr_parity_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set1_sr_reserved_in_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_set1_sr_reserved_out_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_sr_dummy_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_duplex_mode |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_fifo_mode |
phase_comp |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_fifo_width |
fifo_single_width |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_func_mode |
pcie_mode_0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_loopback_mode |
loopback_disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_datapath_mapping_mode |
set0_map_tx_pmadir |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_dv_gating |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fifo_double_read |
set0_fifo_double_read_dis |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fifo_rd_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fifo_rd_clk_sel |
set0_fifo_rd_transfer_div2_clk |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fifo_stop_rd |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fifo_stop_wr |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fifo_wr_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_free_run_div_clk |
set0_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit0_rst_val |
set0_reset_to_zero_hfsrin0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit1_rst_val |
set0_reset_to_zero_hfsrin1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit2_rst_val |
set0_reset_to_zero_hfsrin2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_in_bit3_rst_val |
set0_reset_to_zero_hfsrin3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit0_rst_val |
set0_reset_to_zero_hfsrout0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit1_rst_val |
set0_reset_to_zero_hfsrout1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit2_rst_val |
set0_reset_to_zero_hfsrout2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_hip_fsr_out_bit3_rst_val |
set0_reset_to_zero_hfsrout3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_mask_tx_pll_rst_val |
set0_reset_to_zero_maskpll |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_fsr_pld_txelecidle_rst_val |
set0_reset_to_zero_txelec |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_hip_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_hrdrst_align_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_hrdrst_dcd_cal_done_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_hrdrst_dll_lock_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_hrdrst_rst_sm_dis |
set0_enable_tx_rst_sm |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_hrdrst_rx_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_hrdrst_user_ctl_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_phcomp_rd_del |
set0_phcomp_rd_del2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_stretch_num_stages |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_tx_datapath_tb_sel |
set0_cp_bond |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_tx_fifo_power_mode |
set0_full_width_full_depth |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_tx_fifo_read_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_tx_fifo_write_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_tx_rev_lpbk |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_tx_usertest_sel |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_txfifo_empty |
set0_empty_default |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_txfifo_full |
set0_full_sw |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_txfifo_pempty |
2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_txfifo_pfull |
24 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set0_word_align |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_datapath_mapping_mode |
set1_map_tx_pmadir |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_dv_gating |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fifo_double_read |
set1_fifo_double_read_dis |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fifo_rd_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fifo_rd_clk_sel |
set1_fifo_rd_transfer_div2_clk |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fifo_stop_rd |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fifo_stop_wr |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fifo_wr_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_free_run_div_clk |
set1_out_of_reset_sync |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit0_rst_val |
set1_reset_to_zero_hfsrin0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit1_rst_val |
set1_reset_to_zero_hfsrin1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit2_rst_val |
set1_reset_to_zero_hfsrin2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_in_bit3_rst_val |
set1_reset_to_zero_hfsrin3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit0_rst_val |
set1_reset_to_zero_hfsrout0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit1_rst_val |
set1_reset_to_zero_hfsrout1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit2_rst_val |
set1_reset_to_zero_hfsrout2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_hip_fsr_out_bit3_rst_val |
set1_reset_to_zero_hfsrout3 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_mask_tx_pll_rst_val |
set1_reset_to_zero_maskpll |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_fsr_pld_txelecidle_rst_val |
set1_reset_to_zero_txelec |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_hip_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_hrdrst_align_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_hrdrst_dcd_cal_done_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_hrdrst_dll_lock_bypass |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_hrdrst_rst_sm_dis |
set1_enable_tx_rst_sm |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_hrdrst_rx_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_hrdrst_user_ctl_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_osc_clk_scg_en |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_phcomp_rd_del |
set1_phcomp_rd_del2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_stretch_num_stages |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_tx_datapath_tb_sel |
set1_cp_bond |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_tx_fifo_power_mode |
set1_full_width_full_depth |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_tx_fifo_read_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_tx_fifo_write_latency_adjust |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_tx_rev_lpbk |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_tx_usertest_sel |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_txfifo_empty |
set1_empty_default |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_txfifo_full |
set1_full_sw |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_txfifo_pempty |
2 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_txfifo_pfull |
24 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_set1_word_align |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_topology |
disabled_system |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_tx_osc_clock_setting |
osc_clk_div_by1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_bcmrbc_txchnl_dummy_word_align_enable |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_bti_protected |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_func_mode |
hrc_enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_disable |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_num_active_ip |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_sel_ip0 |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_sel_ip1 |
4 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_sel_ip2 |
4 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_sel_ip3 |
4 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_sel_ip4 |
4 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_arb_timeslot_interval |
283 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_byp_mode |
nobypass |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_bypass_ctrl_0 |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_bypass_ctrl_1 |
3145728 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_cold_reset_time |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_core_rst_width |
16 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_cpll_ena_warm_reset |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_cpll_lock_time |
4375 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_cpll_post_rls_quiet_time |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_cpll_post_rst_quiet_time |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_cpll_reset_time |
64 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_dfd_sel |
0 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_dis_chk_cpll_lock |
false |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_dis_phystat_chk_4_partial_rst |
false |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_ip_ena_vec |
1 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_irq_mask |
37189495 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_lane_stagger_disable |
enable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_lane_stagger_interval |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_link_req_is_full_rst |
false |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_link_req_is_partial_rst |
false |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_perst_filter_hi_time |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_perst_filter_lo_time |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_phy_lane_rst_width |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_phy_post_creg_quiet_time |
16 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_phy_post_lane_rst_quiet_time |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_phy_post_phy_rst_quiet_time |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_phy_stagger_disable |
disable |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_phy_stagger_interval |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_phy_warm_rst_width |
4 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_pin_perst_is_full_rst |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_post_core_rst_quiet_time |
10 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_topology |
upi |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_hrc_warm_rst_timeout |
128 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_powerdown_mode |
true |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_sup_mode |
user_mode |
hssi_ctp_u_wraib_top_u_wraibcmn_top_u_wraibcmn_hrc_top_topology |
upi_x20 |
hssi_ctp_u_wraib_top_u_wraibcmn_top_whr_mode |
pcie_1g |
hssi_ctp_u_wriopads_corepll_bypass |
corepll_en |
hssi_ctp_u_wriopads_corepll_div_fdbk |
0 |
hssi_ctp_u_wriopads_corepll_div_out |
0 |
hssi_ctp_u_wriopads_corepll_div_ref |
0 |
hssi_ctp_u_wriopads_corepll_fb_src |
corepll_internal |
hssi_ctp_u_wriopads_corepll_filter |
0 |
hssi_ctp_u_wriopads_powerdown_mode |
true |
hssi_ctp_u_wriopads_powermode_ac |
pwr_1g |
hssi_ctp_u_wriopads_powermode_dc |
powerup |
hssi_ctp_u_wriopads_powermode_freq_hz |
5000000 |
hssi_ctp_u_wriopads_sup_mode |
user_mode |
hssi_ctp_u_wriopads_topology |
disabled_block |
hssi_ctp_u_wriopads_whr_mode |
pcie_1g |
hssi_ctp_u_wrpcie_top_ippwrmod_freq |
clk1g |
hssi_ctp_u_wrpcie_top_powermode_ac |
pcie_pwr_g4_x16 |
hssi_ctp_u_wrpcie_top_powermode_dc |
powerdown |
hssi_ctp_u_wrpcie_top_powermode_freq_hz |
1000000000 |
hssi_ctp_u_wrpcie_top_topology |
pcie_x16 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_bad_dllp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_bad_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_blk_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_corrected_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf0_table_size |
261 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf1_start_addr |
320 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf1_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf2_start_addr |
512 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf2_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf3_start_addr |
704 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf3_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf4_start_addr |
896 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf4_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf5_start_addr |
1088 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf5_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf6_start_addr |
1280 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf6_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf7_start_addr |
1472 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dbi_pf7_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core16_cfg_dl_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_ecrc_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_fc_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_mlf_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_ram_ecc_chk_val |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_ram_ecc_gen_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_rcvr_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_rcvr_overflow_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_replay_number_rollover_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_replay_timer_timeout_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_surprise_down_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cfg_uncor_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_clkmod_core_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core16_clrhip_not_rst_sticky |
false |
hssi_ctp_u_wrpcie_top_u_core16_crs_override |
false |
hssi_ctp_u_wrpcie_top_u_core16_crs_override_value |
true |
hssi_ctp_u_wrpcie_top_u_core16_cvp_blocking_dis |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_data_compressed |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_data_encrypted |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_hard_reset_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_hip_clk_sel_default |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_intf_reset_ctl |
2 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_irq_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_jtag0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_jtag1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_jtag2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_jtag3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_mode_default |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_mode_gating_dis |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_update_no_reset |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_user_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_vsec_id |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_vsec_rev |
0 |
hssi_ctp_u_wrpcie_top_u_core16_cvp_warm_rst_ready_force_bit0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_cvp_warm_rst_ready_force_bit1 |
true |
hssi_ctp_u_wrpcie_top_u_core16_cvp_warm_rst_req_ena |
disable |
hssi_ctp_u_wrpcie_top_u_core16_cvp_write_mask_ctl |
3 |
hssi_ctp_u_wrpcie_top_u_core16_dbi_ro_wr_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_device_type |
dev_nep |
hssi_ctp_u_wrpcie_top_u_core16_device_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_disable_ct_ur |
false |
hssi_ctp_u_wrpcie_top_u_core16_disable_msg_ur |
false |
hssi_ctp_u_wrpcie_top_u_core16_disable_ur_nf |
false |
hssi_ctp_u_wrpcie_top_u_core16_ecrc_strip |
true |
hssi_ctp_u_wrpcie_top_u_core16_en_gpio_perst |
false |
hssi_ctp_u_wrpcie_top_u_core16_enable_poison_nf |
false |
hssi_ctp_u_wrpcie_top_u_core16_ep_signal_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_err_tlp_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acs_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_acscap_enable_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf0 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf1 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf2 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf3 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf4 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf5 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf6 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_aricap_nxtptr_pf7 |
624 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_globalinvalidate_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_invalidateqdepth_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf0 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf1 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf2 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf3 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf4 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf5 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf6 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_nxtptr_pf7 |
780 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_ats_pagealignreq_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_atscap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msix_tablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixpba_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_msixtable_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf0 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf1 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf2 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf3 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf4 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf5 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf6 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_pciecap_nxtptr_pf7 |
176 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_revisionid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_subsysid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_devspecificmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_exttphrequester_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_intvecmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf0 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf1 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf2 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf3 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf4 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf5 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf6 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_nxtptr_pf7 |
764 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablelocation_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tph_sttablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_tphcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf0 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf1 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf2 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf3 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf4 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf5 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf6 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_exvf_type0cap_nxtptr_pf7 |
112 |
hssi_ctp_u_wrpcie_top_u_core16_func_mode |
disable |
hssi_ctp_u_wrpcie_top_u_core16_gate_clk_in_reset_dis |
false |
hssi_ctp_u_wrpcie_top_u_core16_gate_radm_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core16_gpio_irq |
0 |
hssi_ctp_u_wrpcie_top_u_core16_intel_marker |
0 |
hssi_ctp_u_wrpcie_top_u_core16_irq_misc_ctrl |
0 |
hssi_ctp_u_wrpcie_top_u_core16_kp |
3 |
hssi_ctp_u_wrpcie_top_u_core16_margining_ready |
false |
hssi_ctp_u_wrpcie_top_u_core16_margining_software_ready |
false |
hssi_ctp_u_wrpcie_top_u_core16_nonsriov_mode |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ack_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 |
782 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 |
783 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_capalities_ctrl_reg_byte0 |
784 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_capalities_ctrl_reg_byte1 |
785 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_adv_err_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
258 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
259 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aer_cap_root_err_status_off_addr_byte0 |
304 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_cap_ari_base_addr_byte2 |
378 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_cap_ari_base_addr_byte3 |
379 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_cap_cap_reg_addr_byte0 |
380 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 |
766 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 |
767 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
768 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_auto_eq_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_auto_eq_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_auto_lane_flip_ctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aux_clk_freq |
10 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aux_clk_freq_off_rsvdp_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar0_mem_io |
pf0_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar0_type |
pf0_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar1_mem_io |
pf0_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar1_type |
pf0_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar2_mem_io |
pf0_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar2_type |
pf0_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar3_mem_io |
pf0_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar3_type |
pf0_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar4_mem_io |
pf0_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar4_type |
pf0_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar5_mem_io |
pf0_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_bar5_type |
pf0_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_common_clk_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_config_limit |
1023 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_config_phy_tx_change |
pf0_full_swing |
hssi_ctp_u_wrpcie_top_u_core16_pf0_config_tx_comp_rx |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_cross_link_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_cross_link_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_d1_support |
pf0_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf0_d2_support |
pf0_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_67 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_68 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_direct_speed_change |
pf0_auto_speed_chg |
hssi_ctp_u_wrpcie_top_u_core16_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_disable_fc_wd_timer |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_disable_scrambler_gen_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_disable_scrambler_gen_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 |
1138 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 |
1139 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dlink_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dlink_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dll_link_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsi |
pf0_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_dsp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_eidle_timer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_eq_eieos_cnt |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_eq_eieos_cnt_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_eq_phase_2_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_eq_phase_2_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_eq_redo |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_eq_redo_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_fast_link_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_fast_training_seq |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen1_ei_inference |
pf0_use_rx_eidle |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen2_ctrl_off_rsvdp_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_dc_balance_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_dc_balance_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_dllp_xmt_delay_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_dllp_xmt_delay_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_control_off_rsvdp_27_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_control_off_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_control_off_rsvdp_7_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_eval_2ms_disable |
pf0_abort |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_eval_2ms_disable_atg4 |
pf0_abort_atg4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fb_mode |
pf0_dir_chg |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fb_mode_atg4 |
pf0_dir_chg_atg4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_max_post_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_max_post_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_max_pre_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_max_pre_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_n_evals |
4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_n_evals_atg4 |
4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_t_min_phase23 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fmdc_t_min_phase23_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fom_inc_initial_eval |
pf0_ignore_init_fom |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_fom_inc_initial_eval_atg4 |
pf0_ignore_init_fom_atg4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_invreq_eva_diff_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_invreq_eva_diff_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_phase23_exit_mode |
pf0_next_rec_speed |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_phase23_exit_mode_atg4 |
pf0_next_rec_speed_atg4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_pset_req_as_coef |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_pset_req_as_coef_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_pset_req_vec |
128 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_eq_pset_req_vec_atg4 |
128 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_equalization_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_equalization_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_lower_rate_eq_redo_enable |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_14_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_19_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_1_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_related_off_rsvdp_26_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_req_send_consec_eieos_for_pset_map |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_zrxdc_noncompl |
pf0_non_compliant |
hssi_ctp_u_wrpcie_top_u_core16_pf0_gen3_zrxdc_noncompl_atg4 |
pf0_non_compliant_atg4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_int_pin |
pf0_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf0_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control01_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control01_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control01_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control01_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1011_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1011_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1011_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1011_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1213_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1213_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1213_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1213_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1415_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1415_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1415_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control1415_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control23_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control23_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control23_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control23_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control45_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control45_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control45_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control45_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control67_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control67_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control67_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control67_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control89_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control89_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control89_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_lane_equalization_control89_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_capable |
pf0_conn_x1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_link_num |
4 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_loopback_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 |
810 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 |
811 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ltr_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ltr_next_offset |
816 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 |
490 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 |
491 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_margin_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_margin_next_offset |
780 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_mask_radm_1 |
8200 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_mask_radm_2 |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_max_func_num |
pf0_one_function |
hssi_ctp_u_wrpcie_top_u_core16_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_misc_control_1_rsvdp_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
81 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
82 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
83 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_pba_offset_reg_addr_byte0 |
184 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_pba_offset_reg_addr_byte1 |
185 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_pba_offset_reg_addr_byte2 |
186 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_pba_offset_reg_addr_byte3 |
187 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_table_offset_reg_addr_byte0 |
180 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_table_offset_reg_addr_byte1 |
181 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_table_offset_reg_addr_byte2 |
182 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_msix_table_offset_reg_addr_byte3 |
183 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
177 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
178 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
179 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2097330 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2097331 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_no_soft_rst |
pf0_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf0_num_of_lanes |
16 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_p2p_err_rpt_ctrl |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_p2p_track_cpl_to_reg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
820 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
821 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
818 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
819 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_multiple_msg_cap |
pf0_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_active_state_link_pm_support |
pf0_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_attention_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_attention_indicator_button |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_clock_power_man |
pf0_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_crs_sw_visibility |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_device_capabilities_reg_addr_byte0 |
116 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_device_capabilities_reg_addr_byte1 |
117 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_device_capabilities_reg_addr_byte3 |
119 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_device_control_device_status_addr_byte1 |
121 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_electromech_interlock |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_en_clk_power_man |
pf0_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_ext_tag_supp |
pf0_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_flr_cap |
pf0_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_hot_plug_capable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_hot_plug_surprise |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_capabilities_reg_addr_byte0 |
124 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_capabilities_reg_addr_byte1 |
125 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_capabilities_reg_addr_byte2 |
126 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_capabilities_reg_addr_byte3 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4194464 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_control_link_status_reg_addr_byte0 |
4194432 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_control_link_status_reg_addr_byte1 |
4194433 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_control_link_status_reg_addr_byte2 |
4194434 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_max_link_speed |
pf0_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_max_link_width |
pf0_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_max_payload_size |
pf0_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_mrl_sensor |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_no_cmd_cpl_support |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
113 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
115 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_phy_slot_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_power_controller |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_power_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_rcb |
pf0_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 |
142 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_sel_deemphasis |
pf0_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2097276 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2097277 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_slot_capabilities_reg_addr_byte0 |
132 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_slot_capabilities_reg_addr_byte1 |
133 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_slot_capabilities_reg_addr_byte2 |
134 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_slot_capabilities_reg_addr_byte3 |
135 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_slot_power_limit_scale |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_slot_power_limit_value |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_target_link_speed |
pf0_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pcie_slot_imp |
pf0_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pipe_loopback |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pipe_loopback_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 |
472 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 |
473 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 |
474 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 |
474 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 |
476 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 |
477 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 |
478 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 |
479 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 |
480 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 |
481 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 |
482 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 |
483 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 |
484 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 |
485 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 |
486 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 |
487 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 |
442 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 |
443 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pl16g_next_offset |
488 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
65 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
66 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
67 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pm_cap_con_status_reg_addr_byte0 |
68 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_link_ctrl_off_rsvdp_4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 |
1805 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 |
1806 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_aux_clk_freq_off_addr_byte0 |
2880 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_aux_clk_freq_off_addr_byte1 |
2881 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_filter_mask_2_off_addr_byte0 |
1824 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_filter_mask_2_off_addr_byte1 |
1825 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_filter_mask_2_off_addr_byte2 |
1826 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_filter_mask_2_off_addr_byte3 |
1827 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen2_ctrl_off_addr_byte0 |
2060 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen2_ctrl_off_addr_byte1 |
2061 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen2_ctrl_off_addr_byte2 |
4196366 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 |
2202 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_atg4_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_atg4_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_atg4_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_gen3_related_off_atg4_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_misc_control_1_off_addr_byte1 |
2237 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_misc_control_1_off_addr_byte2 |
2238 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_pipe_loopback_control_off_addr_byte3 |
2235 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_port_force_off_addr_byte0 |
1800 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_port_link_ctrl_off_addr_byte0 |
1808 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_port_link_ctrl_off_addr_byte2 |
1810 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_queue_status_off_addr_byte2 |
1854 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_queue_status_off_addr_byte3 |
1855 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 |
1820 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 |
1821 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 |
1822 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 |
1823 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 |
1816 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 |
1872 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 |
1873 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 |
1874 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 |
1875 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 |
1868 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 |
1869 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 |
1870 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 |
1864 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 |
1865 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 |
1866 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_pre_det_lane |
pf0_det_all_lanes |
hssi_ctp_u_wrpcie_top_u_core16_pf0_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
794 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
795 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
800 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
801 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
802 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
803 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_queue_status_off_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
825 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
826 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rate_shadow_sel |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rate_shadow_sel_atg4 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved250 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved4 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved8 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_67_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_68_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_reset_assert |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_root_control_root_capabilities_reg_rsvdp_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_root_err_status_off_rsvdp_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rp_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rp_rom_mask |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rxeq_ph01_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rxeq_ph01_en_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rxeq_rgrdless_rxts |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rxeq_rgrdless_rxts_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_rxstatus_value |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_scramble_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sel_deemphasis |
pf0_minus_3db_ctl |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf0_skp_int_val |
640 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 |
364 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 |
365 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 |
366 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 |
367 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 |
368 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 |
369 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 |
370 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 |
371 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_sn_base_addr_byte2 |
362 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_sn_base_addr_byte3 |
363 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 |
404 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 |
405 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 |
406 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 |
407 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 |
424 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 |
425 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 |
426 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 |
427 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 |
428 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 |
429 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 |
430 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 |
431 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 |
432 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 |
433 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 |
434 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 |
435 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 |
409 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 |
410 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 |
411 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 |
412 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 |
413 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 |
414 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 |
415 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 |
416 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 |
417 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 |
418 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 |
419 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 |
420 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 |
421 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 |
422 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 |
423 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 |
394 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 |
395 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_spcie_next_offset |
456 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2097724 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2097725 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2097732 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2097733 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2097734 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2097735 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2097748 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2097749 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2097750 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2097751 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2097753 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2097754 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2097755 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2097756 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2097757 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2097758 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2097759 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2097761 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2097762 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2097763 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2097764 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2097765 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2097766 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2097767 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2097769 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2097770 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2097771 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_base_reg_addr_byte2 |
562 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_base_reg_addr_byte3 |
563 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_initial_vfs_addr_byte0 |
572 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_initial_vfs_addr_byte1 |
573 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 |
580 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 |
581 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 |
582 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 |
583 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 |
588 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 |
589 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 |
590 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 |
591 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_bar0_reg_addr_byte0 |
596 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_bar1_reg_addr_byte0 |
600 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_bar2_reg_addr_byte0 |
604 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_bar3_reg_addr_byte0 |
608 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_bar4_reg_addr_byte0 |
612 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_bar5_reg_addr_byte0 |
616 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_device_id_reg_addr_byte2 |
586 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_cap_vf_device_id_reg_addr_byte3 |
587 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar0_type |
pf0_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar1_type |
pf0_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar2_type |
pf0_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar3_type |
pf0_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar4_type |
pf0_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_bar5_type |
pf0_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_offset_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_target_above_config_limit |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_timer_mod_flow_control |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_timer_mod_flow_control_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
626 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
627 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_addr_byte0 |
628 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_addr_byte1 |
629 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_addr_byte2 |
630 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_addr_byte3 |
631 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2097780 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2097781 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2097782 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2097783 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_st_table_loc_0 |
pf0_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf0_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf0_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar0_mask_reg_addr_byte0 |
2097168 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar0_mask_reg_addr_byte1 |
2097169 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar0_mask_reg_addr_byte2 |
2097170 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar0_mask_reg_addr_byte3 |
2097171 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar0_reg_addr_byte0 |
16 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar1_enable_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar1_mask_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar1_mask_reg_addr_byte1 |
2097173 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar1_mask_reg_addr_byte2 |
2097174 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar1_mask_reg_addr_byte3 |
2097175 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar1_reg_addr_byte0 |
20 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar2_mask_reg_addr_byte0 |
2097176 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar2_mask_reg_addr_byte1 |
2097177 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar2_mask_reg_addr_byte2 |
2097178 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar2_mask_reg_addr_byte3 |
2097179 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar2_reg_addr_byte0 |
24 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar3_enable_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar3_mask_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar3_mask_reg_addr_byte1 |
2097181 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar3_mask_reg_addr_byte2 |
2097182 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar3_mask_reg_addr_byte3 |
2097183 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar3_reg_addr_byte0 |
28 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar4_mask_reg_addr_byte0 |
2097184 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar4_mask_reg_addr_byte1 |
2097185 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar4_mask_reg_addr_byte2 |
2097186 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar4_mask_reg_addr_byte3 |
2097187 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar4_reg_addr_byte0 |
32 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar5_enable_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar5_mask_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar5_mask_reg_addr_byte1 |
2097189 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar5_mask_reg_addr_byte2 |
2097190 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar5_mask_reg_addr_byte3 |
2097191 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bar5_reg_addr_byte0 |
36 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
14 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
40 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
41 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
42 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
43 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_class_code_revision_id_addr_byte0 |
8 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_class_code_revision_id_addr_byte1 |
9 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_class_code_revision_id_addr_byte2 |
10 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_class_code_revision_id_addr_byte3 |
11 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2097200 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2097201 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2097202 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2097203 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
48 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
61 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
52 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 |
2097208 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 |
2097209 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 |
2097210 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 |
2097211 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
44 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
45 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
46 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
47 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_send_8gt_eq_ts2_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_send_8gt_eq_ts2_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_usp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_cpl_data_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_cpl_data_scale |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_cpl_hdr_scale |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_cpl_header_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_cpl_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_np_data_credit |
230 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_np_header_credit |
115 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_np_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_p_data_credit |
750 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_p_header_credit |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc0_p_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc_cap_vc_base_addr_byte2 |
330 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc_cap_vc_base_addr_byte3 |
331 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vc_next_offset |
360 |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vendor_specific_dllp_req |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf0_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_cap_hdr_reg_addr_byte2 |
4878 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_cap_hdr_reg_addr_byte3 |
4879 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_capalities_ctrl_reg_byte0 |
4880 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_capalities_ctrl_reg_byte1 |
4881 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ari_cap_cap_reg_addr_byte0 |
4476 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ats_cap_ats_cap_hdr_reg_addr_byte2 |
4862 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ats_cap_ats_cap_hdr_reg_addr_byte3 |
4863 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
4864 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar0_mem_io |
pf1_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar0_type |
pf1_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar1_mem_io |
pf1_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar1_type |
pf1_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar2_mem_io |
pf1_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar2_type |
pf1_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar3_mem_io |
pf1_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar3_type |
pf1_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar4_mem_io |
pf1_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar4_type |
pf1_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar5_mem_io |
pf1_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_bar5_type |
pf1_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_d1_support |
pf1_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf1_d2_support |
pf1_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_dsi |
pf1_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf1_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_int_pin |
pf1_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf1_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
4177 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
4178 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
4179 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_pba_offset_reg_addr_byte0 |
4280 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_pba_offset_reg_addr_byte1 |
4281 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_pba_offset_reg_addr_byte2 |
4282 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_pba_offset_reg_addr_byte3 |
4283 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_table_offset_reg_addr_byte0 |
4276 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_table_offset_reg_addr_byte1 |
4277 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_table_offset_reg_addr_byte2 |
4278 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_msix_table_offset_reg_addr_byte3 |
4279 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
4273 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
4274 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
4275 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_no_soft_rst |
pf1_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf1_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
4916 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
4917 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
4914 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
4915 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_multiple_msg_cap |
pf1_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_active_state_link_pm_control |
pf1_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_active_state_link_pm_support |
pf1_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_clock_power_man |
pf1_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_device_capabilities_reg_addr_byte0 |
4212 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_device_capabilities_reg_addr_byte1 |
4213 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_device_capabilities_reg_addr_byte3 |
4215 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_en_clk_power_man |
pf1_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_ext_tag_supp |
pf1_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_flr_cap |
pf1_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_capabilities_reg_addr_byte0 |
4220 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_capabilities_reg_addr_byte1 |
4221 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_capabilities_reg_addr_byte2 |
4222 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_capabilities_reg_addr_byte3 |
4223 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4198560 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_control_link_status_reg_addr_byte0 |
4198528 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_control_link_status_reg_addr_byte1 |
4198529 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_control_link_status_reg_addr_byte2 |
4198530 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_max_link_speed |
pf1_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_max_link_width |
pf1_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_max_payload_size |
pf1_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
4209 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
4211 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_rcb |
pf1_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_sel_deemphasis |
pf1_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2101372 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2101373 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_target_link_speed |
pf1_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pcie_slot_imp |
pf1_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
4161 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
4162 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
4163 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pm_cap_con_status_reg_addr_byte0 |
4164 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
4890 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
4891 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
4896 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
4897 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
4898 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
4899 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
4921 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
4922 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2101844 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2101845 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2101846 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2101847 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2101848 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2101849 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2101850 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2101851 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2101852 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2101853 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2101854 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2101855 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2101856 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2101857 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2101858 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2101859 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2101860 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2101861 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2101862 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2101863 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2101864 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2101865 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2101866 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2101867 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2101848 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2101856 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2101864 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_base_reg_addr_byte2 |
4658 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_base_reg_addr_byte3 |
4659 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sup_page_sizes_reg_addr_byte0 |
4684 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sup_page_sizes_reg_addr_byte1 |
4685 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sup_page_sizes_reg_addr_byte2 |
4686 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_sup_page_sizes_reg_addr_byte3 |
4687 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_bar0_reg_addr_byte0 |
4692 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_bar1_reg_addr_byte0 |
4696 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_bar2_reg_addr_byte0 |
4700 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_bar3_reg_addr_byte0 |
4704 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_bar4_reg_addr_byte0 |
4708 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_bar5_reg_addr_byte0 |
4712 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_device_id_reg_addr_byte2 |
4682 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_cap_vf_device_id_reg_addr_byte3 |
4683 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar0_type |
pf1_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar1_type |
pf1_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar2_type |
pf1_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar3_type |
pf1_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar4_type |
pf1_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_bar5_type |
pf1_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
4722 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
4723 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_addr_byte0 |
4724 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_addr_byte1 |
4725 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_addr_byte2 |
4726 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_addr_byte3 |
4727 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101876 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101877 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101878 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101879 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_st_table_loc_0 |
pf1_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf1_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_st_table_loc_1 |
pf1_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf1_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar0_mask_reg_addr_byte0 |
2101264 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar0_mask_reg_addr_byte1 |
2101265 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar0_mask_reg_addr_byte2 |
2101266 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar0_mask_reg_addr_byte3 |
2101267 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar0_reg_addr_byte0 |
4112 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar1_enable_reg_addr_byte0 |
2101268 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar1_mask_reg_addr_byte0 |
2101268 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar1_mask_reg_addr_byte1 |
2101269 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar1_mask_reg_addr_byte2 |
2101270 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar1_mask_reg_addr_byte3 |
2101271 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar1_reg_addr_byte0 |
4116 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar2_mask_reg_addr_byte0 |
2101272 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar2_mask_reg_addr_byte1 |
2101273 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar2_mask_reg_addr_byte2 |
2101274 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar2_mask_reg_addr_byte3 |
2101275 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar2_reg_addr_byte0 |
4120 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar3_enable_reg_addr_byte0 |
2101276 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar3_mask_reg_addr_byte0 |
2101276 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar3_mask_reg_addr_byte1 |
2101277 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar3_mask_reg_addr_byte2 |
2101278 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar3_mask_reg_addr_byte3 |
2101279 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar3_reg_addr_byte0 |
4124 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar4_mask_reg_addr_byte0 |
2101280 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar4_mask_reg_addr_byte1 |
2101281 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar4_mask_reg_addr_byte2 |
2101282 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar4_mask_reg_addr_byte3 |
2101283 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar4_reg_addr_byte0 |
4128 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar5_enable_reg_addr_byte0 |
2101284 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar5_mask_reg_addr_byte0 |
2101284 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar5_mask_reg_addr_byte1 |
2101285 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar5_mask_reg_addr_byte2 |
2101286 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar5_mask_reg_addr_byte3 |
2101287 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bar5_reg_addr_byte0 |
4132 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
4110 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
4136 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
4137 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
4138 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
4139 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
4096 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
4097 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
4098 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
4099 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2101296 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2101297 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2101298 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2101299 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
4144 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
4157 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
4148 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
4140 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
4141 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
4142 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
4143 |
hssi_ctp_u_wrpcie_top_u_core16_pf1_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf1_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_cap_hdr_reg_addr_byte2 |
8974 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_cap_hdr_reg_addr_byte3 |
8975 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_capalities_ctrl_reg_byte0 |
4880 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_capalities_ctrl_reg_byte1 |
4881 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ari_cap_cap_reg_addr_byte0 |
8572 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ats_cap_ats_cap_hdr_reg_addr_byte2 |
8958 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ats_cap_ats_cap_hdr_reg_addr_byte3 |
8959 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
8960 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar0_mem_io |
pf2_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar0_type |
pf2_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar1_mem_io |
pf2_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar1_type |
pf2_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar2_mem_io |
pf2_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar2_type |
pf2_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar3_mem_io |
pf2_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar3_type |
pf2_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar4_mem_io |
pf2_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar4_type |
pf2_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar5_mem_io |
pf2_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_bar5_type |
pf2_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_d1_support |
pf2_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf2_d2_support |
pf2_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_dsi |
pf2_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf2_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_int_pin |
pf2_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf2_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
8273 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
8274 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
8275 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_pba_offset_reg_addr_byte0 |
8376 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_pba_offset_reg_addr_byte1 |
8377 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_pba_offset_reg_addr_byte2 |
8378 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_pba_offset_reg_addr_byte3 |
8379 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_table_offset_reg_addr_byte0 |
8372 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_table_offset_reg_addr_byte1 |
8373 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_table_offset_reg_addr_byte2 |
8374 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_msix_table_offset_reg_addr_byte3 |
8375 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
8369 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
8370 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
8371 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_no_soft_rst |
pf2_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf2_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
9012 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
9013 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
9010 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
9011 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_multiple_msg_cap |
pf2_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_active_state_link_pm_control |
pf2_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_active_state_link_pm_support |
pf2_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_clock_power_man |
pf2_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_device_capabilities_reg_addr_byte0 |
8308 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_device_capabilities_reg_addr_byte1 |
8309 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_device_capabilities_reg_addr_byte3 |
8311 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_en_clk_power_man |
pf2_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_ext_tag_supp |
pf2_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_flr_cap |
pf2_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_capabilities_reg_addr_byte0 |
8316 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_capabilities_reg_addr_byte1 |
8317 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_capabilities_reg_addr_byte2 |
8318 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_capabilities_reg_addr_byte3 |
8319 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4202656 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_control_link_status_reg_addr_byte0 |
4202624 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_control_link_status_reg_addr_byte1 |
4202625 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_control_link_status_reg_addr_byte2 |
4202626 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_max_link_speed |
pf2_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_max_link_width |
pf2_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_max_payload_size |
pf2_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
8305 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
8307 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_rcb |
pf2_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_sel_deemphasis |
pf2_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2105468 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2105469 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_target_link_speed |
pf2_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pcie_slot_imp |
pf2_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
8257 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
8258 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
8259 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pm_cap_con_status_reg_addr_byte0 |
8260 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
8986 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
8987 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
8992 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
8993 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
8994 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
8995 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
9017 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
9018 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2105940 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2105941 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2105942 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2105943 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2105944 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2105945 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2105946 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2105947 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2105948 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2105949 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2105950 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2105951 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2105952 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2105953 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2105954 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2105955 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2105956 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2105957 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2105958 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2105959 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2105960 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2105961 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2105962 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2105963 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2105944 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2105952 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2105960 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_base_reg_addr_byte2 |
8754 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_base_reg_addr_byte3 |
8755 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sup_page_sizes_reg_addr_byte0 |
8780 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sup_page_sizes_reg_addr_byte1 |
8781 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sup_page_sizes_reg_addr_byte2 |
8782 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_sup_page_sizes_reg_addr_byte3 |
8783 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_bar0_reg_addr_byte0 |
8788 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_bar1_reg_addr_byte0 |
8792 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_bar2_reg_addr_byte0 |
8796 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_bar3_reg_addr_byte0 |
8800 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_bar4_reg_addr_byte0 |
8804 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_bar5_reg_addr_byte0 |
8808 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_device_id_reg_addr_byte2 |
8778 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_cap_vf_device_id_reg_addr_byte3 |
8779 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar0_type |
pf2_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar1_type |
pf2_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar2_type |
pf2_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar3_type |
pf2_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar4_type |
pf2_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_bar5_type |
pf2_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
8818 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
8819 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_addr_byte0 |
8820 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_addr_byte1 |
8821 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_addr_byte2 |
8822 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_addr_byte3 |
8823 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101876 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101877 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101878 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101879 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_st_table_loc_0 |
pf2_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf2_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_st_table_loc_1 |
pf2_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf2_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar0_mask_reg_addr_byte0 |
2105360 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar0_mask_reg_addr_byte1 |
2105361 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar0_mask_reg_addr_byte2 |
2105362 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar0_mask_reg_addr_byte3 |
2105363 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar0_reg_addr_byte0 |
8208 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar1_enable_reg_addr_byte0 |
2105364 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar1_mask_reg_addr_byte0 |
2105364 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar1_mask_reg_addr_byte1 |
2105365 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar1_mask_reg_addr_byte2 |
2105366 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar1_mask_reg_addr_byte3 |
2105367 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar1_reg_addr_byte0 |
8212 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar2_mask_reg_addr_byte0 |
2105368 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar2_mask_reg_addr_byte1 |
2105369 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar2_mask_reg_addr_byte2 |
2105370 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar2_mask_reg_addr_byte3 |
2105371 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar2_reg_addr_byte0 |
8216 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar3_enable_reg_addr_byte0 |
2105372 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar3_mask_reg_addr_byte0 |
2105372 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar3_mask_reg_addr_byte1 |
2105373 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar3_mask_reg_addr_byte2 |
2105374 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar3_mask_reg_addr_byte3 |
2105375 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar3_reg_addr_byte0 |
8220 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar4_mask_reg_addr_byte0 |
2105376 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar4_mask_reg_addr_byte1 |
2105377 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar4_mask_reg_addr_byte2 |
2105378 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar4_mask_reg_addr_byte3 |
2105379 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar4_reg_addr_byte0 |
8224 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar5_enable_reg_addr_byte0 |
2105380 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar5_mask_reg_addr_byte0 |
2105380 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar5_mask_reg_addr_byte1 |
2105381 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar5_mask_reg_addr_byte2 |
2105382 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar5_mask_reg_addr_byte3 |
2105383 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bar5_reg_addr_byte0 |
8228 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
8206 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
8232 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
8233 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
8234 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
8235 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
8192 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
8193 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
8194 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
8195 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2105392 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2105393 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2105394 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2105395 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
8240 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
8253 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
8244 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
8236 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
8237 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
8238 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
8239 |
hssi_ctp_u_wrpcie_top_u_core16_pf2_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf2_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_cap_hdr_reg_addr_byte2 |
13070 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_cap_hdr_reg_addr_byte3 |
13071 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_capalities_ctrl_reg_byte0 |
4880 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_capalities_ctrl_reg_byte1 |
4881 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ari_cap_cap_reg_addr_byte0 |
12668 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ats_cap_ats_cap_hdr_reg_addr_byte2 |
13054 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ats_cap_ats_cap_hdr_reg_addr_byte3 |
13055 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
13056 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar0_mem_io |
pf3_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar0_type |
pf3_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar1_mem_io |
pf3_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar1_type |
pf3_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar2_mem_io |
pf3_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar2_type |
pf3_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar3_mem_io |
pf3_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar3_type |
pf3_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar4_mem_io |
pf3_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar4_type |
pf3_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar5_mem_io |
pf3_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_bar5_type |
pf3_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_d1_support |
pf3_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf3_d2_support |
pf3_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_dsi |
pf3_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf3_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_int_pin |
pf3_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf3_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
12369 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
12370 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
12371 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_pba_offset_reg_addr_byte0 |
12472 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_pba_offset_reg_addr_byte1 |
12473 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_pba_offset_reg_addr_byte2 |
12474 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_pba_offset_reg_addr_byte3 |
12475 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_table_offset_reg_addr_byte0 |
12468 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_table_offset_reg_addr_byte1 |
12469 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_table_offset_reg_addr_byte2 |
12470 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_msix_table_offset_reg_addr_byte3 |
12471 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
12465 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
12466 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
12467 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_no_soft_rst |
pf3_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf3_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
13108 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
13109 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
13106 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
13107 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_multiple_msg_cap |
pf3_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_active_state_link_pm_control |
pf3_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_active_state_link_pm_support |
pf3_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_clock_power_man |
pf3_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_device_capabilities_reg_addr_byte0 |
12404 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_device_capabilities_reg_addr_byte1 |
12405 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_device_capabilities_reg_addr_byte3 |
12407 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_en_clk_power_man |
pf3_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_ext_tag_supp |
pf3_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_flr_cap |
pf3_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_capabilities_reg_addr_byte0 |
12412 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_capabilities_reg_addr_byte1 |
12413 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_capabilities_reg_addr_byte2 |
12414 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_capabilities_reg_addr_byte3 |
12415 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4206752 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_control_link_status_reg_addr_byte0 |
4206720 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_control_link_status_reg_addr_byte1 |
4206721 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_control_link_status_reg_addr_byte2 |
4206722 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_max_link_speed |
pf3_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_max_link_width |
pf3_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_max_payload_size |
pf3_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
12401 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
12403 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_rcb |
pf3_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_sel_deemphasis |
pf3_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2109564 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2109565 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_target_link_speed |
pf3_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pcie_slot_imp |
pf3_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
12353 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
12354 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
12355 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pm_cap_con_status_reg_addr_byte0 |
12356 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
13082 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
13083 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
13088 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
13089 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
13090 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
13091 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
13113 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
13114 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2110036 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2110037 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2110038 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2110039 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2110040 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2110041 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2110042 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2110043 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2110044 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2110045 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2110046 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2110047 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2110048 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2110049 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2110050 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2110051 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2110052 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2110053 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2110054 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2110055 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2110056 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2110057 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2110058 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2110059 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2110040 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2110048 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2110056 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_base_reg_addr_byte2 |
12850 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_base_reg_addr_byte3 |
12851 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sup_page_sizes_reg_addr_byte0 |
12876 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sup_page_sizes_reg_addr_byte1 |
12877 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sup_page_sizes_reg_addr_byte2 |
12878 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_sup_page_sizes_reg_addr_byte3 |
12879 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_bar0_reg_addr_byte0 |
12884 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_bar1_reg_addr_byte0 |
12888 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_bar2_reg_addr_byte0 |
12892 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_bar3_reg_addr_byte0 |
12896 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_bar4_reg_addr_byte0 |
12900 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_bar5_reg_addr_byte0 |
12904 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_device_id_reg_addr_byte2 |
12874 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_cap_vf_device_id_reg_addr_byte3 |
12875 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar0_type |
pf3_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar1_type |
pf3_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar2_type |
pf3_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar3_type |
pf3_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar4_type |
pf3_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_bar5_type |
pf3_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
12914 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
12915 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_addr_byte0 |
12916 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_addr_byte1 |
12917 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_addr_byte2 |
12918 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_addr_byte3 |
12919 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101876 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101877 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101878 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101879 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_st_table_loc_0 |
pf3_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf3_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_st_table_loc_1 |
pf3_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf3_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar0_mask_reg_addr_byte0 |
2109456 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar0_mask_reg_addr_byte1 |
2109457 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar0_mask_reg_addr_byte2 |
2109458 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar0_mask_reg_addr_byte3 |
2109459 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar0_reg_addr_byte0 |
12304 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar1_enable_reg_addr_byte0 |
2109460 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar1_mask_reg_addr_byte0 |
2109460 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar1_mask_reg_addr_byte1 |
2109461 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar1_mask_reg_addr_byte2 |
2109462 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar1_mask_reg_addr_byte3 |
2109463 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar1_reg_addr_byte0 |
12308 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar2_mask_reg_addr_byte0 |
2109464 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar2_mask_reg_addr_byte1 |
2109465 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar2_mask_reg_addr_byte2 |
2109466 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar2_mask_reg_addr_byte3 |
2109467 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar2_reg_addr_byte0 |
12312 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar3_enable_reg_addr_byte0 |
2109468 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar3_mask_reg_addr_byte0 |
2109468 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar3_mask_reg_addr_byte1 |
2109469 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar3_mask_reg_addr_byte2 |
2109470 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar3_mask_reg_addr_byte3 |
2109471 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar3_reg_addr_byte0 |
12316 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar4_mask_reg_addr_byte0 |
2109472 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar4_mask_reg_addr_byte1 |
2109473 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar4_mask_reg_addr_byte2 |
2109474 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar4_mask_reg_addr_byte3 |
2109475 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar4_reg_addr_byte0 |
12320 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar5_enable_reg_addr_byte0 |
2109476 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar5_mask_reg_addr_byte0 |
2109476 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar5_mask_reg_addr_byte1 |
2109477 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar5_mask_reg_addr_byte2 |
2109478 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar5_mask_reg_addr_byte3 |
2109479 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bar5_reg_addr_byte0 |
12324 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
12302 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
12328 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
12329 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
12330 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
12331 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
12288 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
12289 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
12290 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
12291 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2109488 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2109489 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2109490 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2109491 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
12336 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
12349 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
12340 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
12332 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
12333 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
12334 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
12335 |
hssi_ctp_u_wrpcie_top_u_core16_pf3_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf3_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_cap_hdr_reg_addr_byte2 |
17166 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_cap_hdr_reg_addr_byte3 |
17167 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_capalities_ctrl_reg_byte0 |
4880 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_capalities_ctrl_reg_byte1 |
4881 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ari_cap_cap_reg_addr_byte0 |
16764 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ats_cap_ats_cap_hdr_reg_addr_byte2 |
17150 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ats_cap_ats_cap_hdr_reg_addr_byte3 |
17151 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
17152 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar0_mem_io |
pf4_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar0_type |
pf4_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar1_mem_io |
pf4_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar1_type |
pf4_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar2_mem_io |
pf4_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar2_type |
pf4_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar3_mem_io |
pf4_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar3_type |
pf4_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar4_mem_io |
pf4_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar4_type |
pf4_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar5_mem_io |
pf4_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_bar5_type |
pf4_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_d1_support |
pf4_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf4_d2_support |
pf4_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_dsi |
pf4_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf4_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_int_pin |
pf4_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf4_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
16465 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
16466 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
16467 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_pba_offset_reg_addr_byte0 |
16568 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_pba_offset_reg_addr_byte1 |
16569 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_pba_offset_reg_addr_byte2 |
16570 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_pba_offset_reg_addr_byte3 |
16571 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_table_offset_reg_addr_byte0 |
16564 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_table_offset_reg_addr_byte1 |
16565 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_table_offset_reg_addr_byte2 |
16566 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_msix_table_offset_reg_addr_byte3 |
16567 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
16561 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
16562 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
16563 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_no_soft_rst |
pf4_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf4_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
17204 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
17205 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
17202 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
17203 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_multiple_msg_cap |
pf4_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_active_state_link_pm_control |
pf4_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_active_state_link_pm_support |
pf4_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_clock_power_man |
pf4_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_device_capabilities_reg_addr_byte0 |
16500 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_device_capabilities_reg_addr_byte1 |
16501 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_device_capabilities_reg_addr_byte3 |
16503 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_en_clk_power_man |
pf4_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_ext_tag_supp |
pf4_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_flr_cap |
pf4_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_capabilities_reg_addr_byte0 |
16508 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_capabilities_reg_addr_byte1 |
16509 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_capabilities_reg_addr_byte2 |
16510 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_capabilities_reg_addr_byte3 |
16511 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4210848 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_control_link_status_reg_addr_byte0 |
4210816 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_control_link_status_reg_addr_byte1 |
4210817 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_control_link_status_reg_addr_byte2 |
4210818 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_max_link_speed |
pf4_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_max_link_width |
pf4_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_max_payload_size |
pf4_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
16497 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
16499 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_rcb |
pf4_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_sel_deemphasis |
pf4_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2113660 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2113661 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_target_link_speed |
pf4_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pcie_slot_imp |
pf4_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
16449 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
16450 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
16451 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pm_cap_con_status_reg_addr_byte0 |
16452 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
17178 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
17179 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
17184 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
17185 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
17186 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
17187 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
17209 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
17210 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2114132 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2114133 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2114134 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2114135 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2114136 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2114137 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2114138 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2114139 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2114140 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2114141 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2114142 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2114143 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2114144 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2114145 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2114146 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2114147 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2114148 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2114149 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2114150 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2114151 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2114152 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2114153 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2114154 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2114155 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2114136 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2114144 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2114152 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_base_reg_addr_byte2 |
16946 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_base_reg_addr_byte3 |
16947 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sup_page_sizes_reg_addr_byte0 |
16972 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sup_page_sizes_reg_addr_byte1 |
16973 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sup_page_sizes_reg_addr_byte2 |
16974 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_sup_page_sizes_reg_addr_byte3 |
16975 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_bar0_reg_addr_byte0 |
16980 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_bar1_reg_addr_byte0 |
16984 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_bar2_reg_addr_byte0 |
16988 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_bar3_reg_addr_byte0 |
16992 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_bar4_reg_addr_byte0 |
16996 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_bar5_reg_addr_byte0 |
17000 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_device_id_reg_addr_byte2 |
16970 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_cap_vf_device_id_reg_addr_byte3 |
16971 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar0_type |
pf4_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar1_type |
pf4_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar2_type |
pf4_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar3_type |
pf4_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar4_type |
pf4_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_bar5_type |
pf4_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
17010 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
17011 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_addr_byte0 |
17012 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_addr_byte1 |
17013 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_addr_byte2 |
17014 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_addr_byte3 |
17015 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101876 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101877 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101878 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101879 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_st_table_loc_0 |
pf4_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf4_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_st_table_loc_1 |
pf4_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf4_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar0_mask_reg_addr_byte0 |
2113552 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar0_mask_reg_addr_byte1 |
2113553 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar0_mask_reg_addr_byte2 |
2113554 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar0_mask_reg_addr_byte3 |
2113555 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar0_reg_addr_byte0 |
16400 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar1_enable_reg_addr_byte0 |
2113556 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar1_mask_reg_addr_byte0 |
2113556 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar1_mask_reg_addr_byte1 |
2113557 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar1_mask_reg_addr_byte2 |
2113558 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar1_mask_reg_addr_byte3 |
2113559 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar1_reg_addr_byte0 |
16404 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar2_mask_reg_addr_byte0 |
2113560 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar2_mask_reg_addr_byte1 |
2113561 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar2_mask_reg_addr_byte2 |
2113562 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar2_mask_reg_addr_byte3 |
2113563 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar2_reg_addr_byte0 |
16408 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar3_enable_reg_addr_byte0 |
2113564 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar3_mask_reg_addr_byte0 |
2113564 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar3_mask_reg_addr_byte1 |
2113565 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar3_mask_reg_addr_byte2 |
2113566 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar3_mask_reg_addr_byte3 |
2113567 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar3_reg_addr_byte0 |
16412 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar4_mask_reg_addr_byte0 |
2113568 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar4_mask_reg_addr_byte1 |
2113569 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar4_mask_reg_addr_byte2 |
2113570 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar4_mask_reg_addr_byte3 |
2113571 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar4_reg_addr_byte0 |
16416 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar5_enable_reg_addr_byte0 |
2113572 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar5_mask_reg_addr_byte0 |
2113572 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar5_mask_reg_addr_byte1 |
2113573 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar5_mask_reg_addr_byte2 |
2113574 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar5_mask_reg_addr_byte3 |
2113575 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bar5_reg_addr_byte0 |
16420 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
16398 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
16424 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
16425 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
16426 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
16427 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
16384 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
16385 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
16386 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
16387 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2113584 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2113585 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2113586 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2113587 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
16432 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
16445 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
16436 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
16428 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
16429 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
16430 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
16431 |
hssi_ctp_u_wrpcie_top_u_core16_pf4_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf4_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_cap_hdr_reg_addr_byte2 |
21262 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_cap_hdr_reg_addr_byte3 |
21263 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_capalities_ctrl_reg_byte0 |
4880 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_capalities_ctrl_reg_byte1 |
4881 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ari_cap_cap_reg_addr_byte0 |
20860 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ats_cap_ats_cap_hdr_reg_addr_byte2 |
21246 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ats_cap_ats_cap_hdr_reg_addr_byte3 |
21247 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
21248 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar0_mem_io |
pf5_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar0_type |
pf5_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar1_mem_io |
pf5_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar1_type |
pf5_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar2_mem_io |
pf5_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar2_type |
pf5_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar3_mem_io |
pf5_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar3_type |
pf5_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar4_mem_io |
pf5_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar4_type |
pf5_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar5_mem_io |
pf5_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_bar5_type |
pf5_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_d1_support |
pf5_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf5_d2_support |
pf5_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_dsi |
pf5_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf5_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_int_pin |
pf5_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf5_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
20561 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
20562 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
20563 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_pba_offset_reg_addr_byte0 |
20664 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_pba_offset_reg_addr_byte1 |
20665 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_pba_offset_reg_addr_byte2 |
20666 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_pba_offset_reg_addr_byte3 |
20667 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_table_offset_reg_addr_byte0 |
20660 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_table_offset_reg_addr_byte1 |
20661 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_table_offset_reg_addr_byte2 |
20662 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_msix_table_offset_reg_addr_byte3 |
20663 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
20657 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
20658 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
20659 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_no_soft_rst |
pf5_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf5_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
21300 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
21301 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
21298 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
21299 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_multiple_msg_cap |
pf5_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_active_state_link_pm_control |
pf5_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_active_state_link_pm_support |
pf5_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_clock_power_man |
pf5_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_device_capabilities_reg_addr_byte0 |
20596 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_device_capabilities_reg_addr_byte1 |
20597 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_device_capabilities_reg_addr_byte3 |
20599 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_en_clk_power_man |
pf5_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_ext_tag_supp |
pf5_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_flr_cap |
pf5_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_capabilities_reg_addr_byte0 |
20604 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_capabilities_reg_addr_byte1 |
20605 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_capabilities_reg_addr_byte2 |
20606 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_capabilities_reg_addr_byte3 |
20607 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4214944 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_control_link_status_reg_addr_byte0 |
4214912 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_control_link_status_reg_addr_byte1 |
4214913 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_control_link_status_reg_addr_byte2 |
4214914 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_max_link_speed |
pf5_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_max_link_width |
pf5_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_max_payload_size |
pf5_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
20593 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
20595 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_rcb |
pf5_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_sel_deemphasis |
pf5_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2117756 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2117757 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_target_link_speed |
pf5_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pcie_slot_imp |
pf5_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
20545 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
20546 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
20547 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pm_cap_con_status_reg_addr_byte0 |
20548 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
21274 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
21275 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
21280 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
21281 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
21282 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
21283 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
21305 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
21306 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2118228 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2118229 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2118230 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2118231 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2118232 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2118233 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2118234 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2118235 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2118236 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2118237 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2118238 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2118239 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2118240 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2118241 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2118242 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2118243 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2118244 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2118245 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2118246 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2118247 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2118248 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2118249 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2118250 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2118251 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2118232 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2118240 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2118248 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_base_reg_addr_byte2 |
21042 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_base_reg_addr_byte3 |
21043 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sup_page_sizes_reg_addr_byte0 |
21068 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sup_page_sizes_reg_addr_byte1 |
21069 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sup_page_sizes_reg_addr_byte2 |
21070 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_sup_page_sizes_reg_addr_byte3 |
21071 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_bar0_reg_addr_byte0 |
21076 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_bar1_reg_addr_byte0 |
21080 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_bar2_reg_addr_byte0 |
21084 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_bar3_reg_addr_byte0 |
21088 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_bar4_reg_addr_byte0 |
21092 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_bar5_reg_addr_byte0 |
21096 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_device_id_reg_addr_byte2 |
21066 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_cap_vf_device_id_reg_addr_byte3 |
21067 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar0_type |
pf5_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar1_type |
pf5_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar2_type |
pf5_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar3_type |
pf5_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar4_type |
pf5_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_bar5_type |
pf5_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
21106 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
21107 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_addr_byte0 |
21108 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_addr_byte1 |
21109 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_addr_byte2 |
21110 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_addr_byte3 |
21111 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101876 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101877 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101878 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101879 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_st_table_loc_0 |
pf5_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf5_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_st_table_loc_1 |
pf5_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf5_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar0_mask_reg_addr_byte0 |
2117648 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar0_mask_reg_addr_byte1 |
2117649 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar0_mask_reg_addr_byte2 |
2117650 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar0_mask_reg_addr_byte3 |
2117651 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar0_reg_addr_byte0 |
20496 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar1_enable_reg_addr_byte0 |
2117652 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar1_mask_reg_addr_byte0 |
2117652 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar1_mask_reg_addr_byte1 |
2117653 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar1_mask_reg_addr_byte2 |
2117654 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar1_mask_reg_addr_byte3 |
2117655 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar1_reg_addr_byte0 |
20500 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar2_mask_reg_addr_byte0 |
2117656 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar2_mask_reg_addr_byte1 |
2117657 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar2_mask_reg_addr_byte2 |
2117658 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar2_mask_reg_addr_byte3 |
2117659 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar2_reg_addr_byte0 |
20504 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar3_enable_reg_addr_byte0 |
2117660 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar3_mask_reg_addr_byte0 |
2117660 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar3_mask_reg_addr_byte1 |
2117661 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar3_mask_reg_addr_byte2 |
2117662 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar3_mask_reg_addr_byte3 |
2117663 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar3_reg_addr_byte0 |
20508 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar4_mask_reg_addr_byte0 |
2117664 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar4_mask_reg_addr_byte1 |
2117665 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar4_mask_reg_addr_byte2 |
2117666 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar4_mask_reg_addr_byte3 |
2117667 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar4_reg_addr_byte0 |
20512 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar5_enable_reg_addr_byte0 |
2117668 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar5_mask_reg_addr_byte0 |
2117668 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar5_mask_reg_addr_byte1 |
2117669 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar5_mask_reg_addr_byte2 |
2117670 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar5_mask_reg_addr_byte3 |
2117671 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bar5_reg_addr_byte0 |
20516 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
20494 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
20520 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
20521 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
20522 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
20523 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
20480 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
20481 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
20482 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
20483 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2117680 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2117681 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2117682 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2117683 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
20528 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
20541 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
20532 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
20524 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
20525 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
20526 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
20527 |
hssi_ctp_u_wrpcie_top_u_core16_pf5_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf5_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_cap_hdr_reg_addr_byte2 |
25358 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_cap_hdr_reg_addr_byte3 |
25359 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_capalities_ctrl_reg_byte0 |
4880 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_capalities_ctrl_reg_byte1 |
4881 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ari_cap_cap_reg_addr_byte0 |
24956 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ats_cap_ats_cap_hdr_reg_addr_byte2 |
25342 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ats_cap_ats_cap_hdr_reg_addr_byte3 |
25343 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
25344 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar0_mem_io |
pf6_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar0_type |
pf6_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar1_mem_io |
pf6_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar1_type |
pf6_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar2_mem_io |
pf6_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar2_type |
pf6_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar3_mem_io |
pf6_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar3_type |
pf6_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar4_mem_io |
pf6_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar4_type |
pf6_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar5_mem_io |
pf6_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_bar5_type |
pf6_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_d1_support |
pf6_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf6_d2_support |
pf6_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_dsi |
pf6_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf6_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_int_pin |
pf6_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf6_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
24657 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
24658 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
24659 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_pba_offset_reg_addr_byte0 |
24760 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_pba_offset_reg_addr_byte1 |
24761 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_pba_offset_reg_addr_byte2 |
24762 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_pba_offset_reg_addr_byte3 |
24763 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_table_offset_reg_addr_byte0 |
24756 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_table_offset_reg_addr_byte1 |
24757 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_table_offset_reg_addr_byte2 |
24758 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_msix_table_offset_reg_addr_byte3 |
24759 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
24753 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
24754 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
24755 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_no_soft_rst |
pf6_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf6_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
25396 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
25397 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
25394 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
25395 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_multiple_msg_cap |
pf6_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_active_state_link_pm_control |
pf6_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_active_state_link_pm_support |
pf6_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_clock_power_man |
pf6_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_device_capabilities_reg_addr_byte0 |
24692 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_device_capabilities_reg_addr_byte1 |
24693 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_device_capabilities_reg_addr_byte3 |
24695 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_en_clk_power_man |
pf6_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_ext_tag_supp |
pf6_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_flr_cap |
pf6_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_capabilities_reg_addr_byte0 |
24700 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_capabilities_reg_addr_byte1 |
24701 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_capabilities_reg_addr_byte2 |
24702 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_capabilities_reg_addr_byte3 |
24703 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4219040 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_control_link_status_reg_addr_byte0 |
4219008 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_control_link_status_reg_addr_byte1 |
4219009 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_control_link_status_reg_addr_byte2 |
4219010 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_max_link_speed |
pf6_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_max_link_width |
pf6_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_max_payload_size |
pf6_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
24689 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
24691 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_rcb |
pf6_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_sel_deemphasis |
pf6_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2121852 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2121853 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_target_link_speed |
pf6_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pcie_slot_imp |
pf6_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
24641 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
24642 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
24643 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pm_cap_con_status_reg_addr_byte0 |
24644 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
25370 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
25371 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
25376 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
25377 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
25378 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
25379 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
25401 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
25402 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2122324 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2122325 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2122326 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2122327 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2122328 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2122329 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2122330 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2122331 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2122332 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2122333 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2122334 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2122335 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2122336 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2122337 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2122338 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2122339 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2122340 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2122341 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2122342 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2122343 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2122344 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2122345 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2122346 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2122347 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2122328 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2122336 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2122344 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_base_reg_addr_byte2 |
25138 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_base_reg_addr_byte3 |
25139 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sup_page_sizes_reg_addr_byte0 |
25164 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sup_page_sizes_reg_addr_byte1 |
25165 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sup_page_sizes_reg_addr_byte2 |
25166 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_sup_page_sizes_reg_addr_byte3 |
25167 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_bar0_reg_addr_byte0 |
25172 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_bar1_reg_addr_byte0 |
25176 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_bar2_reg_addr_byte0 |
25180 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_bar3_reg_addr_byte0 |
25184 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_bar4_reg_addr_byte0 |
25188 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_bar5_reg_addr_byte0 |
25192 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_device_id_reg_addr_byte2 |
25162 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_cap_vf_device_id_reg_addr_byte3 |
25163 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar0_type |
pf6_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar1_type |
pf6_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar2_type |
pf6_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar3_type |
pf6_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar4_type |
pf6_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_bar5_type |
pf6_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
25202 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
25203 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_addr_byte0 |
25204 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_addr_byte1 |
25205 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_addr_byte2 |
25206 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_addr_byte3 |
25207 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101876 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101877 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101878 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101879 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_st_table_loc_0 |
pf6_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf6_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_st_table_loc_1 |
pf6_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf6_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar0_mask_reg_addr_byte0 |
2121744 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar0_mask_reg_addr_byte1 |
2121745 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar0_mask_reg_addr_byte2 |
2121746 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar0_mask_reg_addr_byte3 |
2121747 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar0_reg_addr_byte0 |
24592 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar1_enable_reg_addr_byte0 |
2121748 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar1_mask_reg_addr_byte0 |
2121748 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar1_mask_reg_addr_byte1 |
2121749 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar1_mask_reg_addr_byte2 |
2121750 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar1_mask_reg_addr_byte3 |
2121751 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar1_reg_addr_byte0 |
24596 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar2_mask_reg_addr_byte0 |
2121752 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar2_mask_reg_addr_byte1 |
2121753 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar2_mask_reg_addr_byte2 |
2121754 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar2_mask_reg_addr_byte3 |
2121755 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar2_reg_addr_byte0 |
24600 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar3_enable_reg_addr_byte0 |
2121756 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar3_mask_reg_addr_byte0 |
2121756 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar3_mask_reg_addr_byte1 |
2121757 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar3_mask_reg_addr_byte2 |
2121758 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar3_mask_reg_addr_byte3 |
2121759 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar3_reg_addr_byte0 |
24604 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar4_mask_reg_addr_byte0 |
2121760 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar4_mask_reg_addr_byte1 |
2121761 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar4_mask_reg_addr_byte2 |
2121762 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar4_mask_reg_addr_byte3 |
2121763 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar4_reg_addr_byte0 |
24608 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar5_enable_reg_addr_byte0 |
2121764 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar5_mask_reg_addr_byte0 |
2121764 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar5_mask_reg_addr_byte1 |
2121765 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar5_mask_reg_addr_byte2 |
2121766 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar5_mask_reg_addr_byte3 |
2121767 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bar5_reg_addr_byte0 |
24612 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
24590 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
24616 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
24617 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
24618 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
24619 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
24576 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
24577 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
24578 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
24579 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2121776 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2121777 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2121778 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2121779 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
24624 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
24637 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
24628 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
24620 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
24621 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
24622 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
24623 |
hssi_ctp_u_wrpcie_top_u_core16_pf6_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf6_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_cap_hdr_reg_addr_byte2 |
29454 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_cap_hdr_reg_addr_byte3 |
29455 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_capalities_ctrl_reg_byte0 |
4880 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_capalities_ctrl_reg_byte1 |
4881 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ari_cap_cap_reg_addr_byte0 |
29052 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ats_cap_ats_cap_hdr_reg_addr_byte2 |
29438 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ats_cap_ats_cap_hdr_reg_addr_byte3 |
29439 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
29440 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar0_mem_io |
pf7_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar0_type |
pf7_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar1_mem_io |
pf7_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar1_type |
pf7_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar2_mem_io |
pf7_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar2_type |
pf7_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar3_mem_io |
pf7_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar3_type |
pf7_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar4_mem_io |
pf7_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar4_type |
pf7_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar5_mem_io |
pf7_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_bar5_type |
pf7_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_d1_support |
pf7_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf7_d2_support |
pf7_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_dsi |
pf7_not_required |
hssi_ctp_u_wrpcie_top_u_core16_pf7_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_int_pin |
pf7_inta |
hssi_ctp_u_wrpcie_top_u_core16_pf7_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
28753 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
28754 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
28755 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_pba_offset_reg_addr_byte0 |
28856 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_pba_offset_reg_addr_byte1 |
28857 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_pba_offset_reg_addr_byte2 |
28858 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_pba_offset_reg_addr_byte3 |
28859 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_table_offset_reg_addr_byte0 |
28852 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_table_offset_reg_addr_byte1 |
28853 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_table_offset_reg_addr_byte2 |
28854 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_msix_table_offset_reg_addr_byte3 |
28855 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
28849 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
28850 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
28851 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_no_soft_rst |
pf7_internally_reset |
hssi_ctp_u_wrpcie_top_u_core16_pf7_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
29492 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
29493 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
29490 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
29491 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_multiple_msg_cap |
pf7_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_active_state_link_pm_control |
pf7_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_active_state_link_pm_support |
pf7_no_aspm |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_clock_power_man |
pf7_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_device_capabilities_reg_addr_byte0 |
28788 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_device_capabilities_reg_addr_byte1 |
28789 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_device_capabilities_reg_addr_byte3 |
28791 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_en_clk_power_man |
pf7_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_ext_tag_supp |
pf7_supported |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_flr_cap |
pf7_capable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_capabilities_reg_addr_byte0 |
28796 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_capabilities_reg_addr_byte1 |
28797 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_capabilities_reg_addr_byte2 |
28798 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_capabilities_reg_addr_byte3 |
28799 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4223136 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_control_link_status_reg_addr_byte0 |
4223104 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_control_link_status_reg_addr_byte1 |
4223105 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_control_link_status_reg_addr_byte2 |
4223106 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_max_link_speed |
pf7_max_8gts |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_max_link_width |
pf7_x16 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_max_payload_size |
pf7_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
28785 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
28787 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_rcb |
pf7_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_sel_deemphasis |
pf7_minus_6db |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2125948 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2125949 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_target_link_speed |
pf7_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pcie_slot_imp |
pf7_not_implemented |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
28737 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
28738 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
28739 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pm_cap_con_status_reg_addr_byte0 |
28740 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
29466 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
29467 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
29472 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
29473 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
29474 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
29475 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
29497 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
29498 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2126420 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2126421 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2126422 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2126423 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2126424 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2126425 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2126426 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2126427 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2126428 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2126429 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2126430 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2126431 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2126432 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2126433 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2126434 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2126435 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2126436 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2126437 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2126438 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2126439 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2126440 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2126441 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2126442 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2126443 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2126424 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2126432 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2126440 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_base_reg_addr_byte2 |
29234 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_base_reg_addr_byte3 |
29235 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sup_page_sizes_reg_addr_byte0 |
29260 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sup_page_sizes_reg_addr_byte1 |
29261 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sup_page_sizes_reg_addr_byte2 |
29262 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_sup_page_sizes_reg_addr_byte3 |
29263 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_bar0_reg_addr_byte0 |
29268 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_bar1_reg_addr_byte0 |
29272 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_bar2_reg_addr_byte0 |
29276 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_bar3_reg_addr_byte0 |
29280 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_bar4_reg_addr_byte0 |
29284 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_bar5_reg_addr_byte0 |
29288 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_device_id_reg_addr_byte2 |
29258 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_cap_vf_device_id_reg_addr_byte3 |
29259 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar0_type |
pf7_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar1_type |
pf7_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar2_type |
pf7_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar3_type |
pf7_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar4_type |
pf7_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_bar5_type |
pf7_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
29298 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
29299 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_addr_byte0 |
29300 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_addr_byte1 |
29301 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_addr_byte2 |
29302 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_addr_byte3 |
29303 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101876 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101877 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101878 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101879 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_st_table_loc_0 |
pf7_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf7_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_st_table_loc_1 |
pf7_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf7_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar0_mask_reg_addr_byte0 |
2125840 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar0_mask_reg_addr_byte1 |
2125841 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar0_mask_reg_addr_byte2 |
2125842 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar0_mask_reg_addr_byte3 |
2125843 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar0_reg_addr_byte0 |
28688 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar1_enable_reg_addr_byte0 |
2125844 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar1_mask_reg_addr_byte0 |
2125844 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar1_mask_reg_addr_byte1 |
2125845 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar1_mask_reg_addr_byte2 |
2125846 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar1_mask_reg_addr_byte3 |
2125847 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar1_reg_addr_byte0 |
28692 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar2_mask_reg_addr_byte0 |
2125848 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar2_mask_reg_addr_byte1 |
2125849 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar2_mask_reg_addr_byte2 |
2125850 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar2_mask_reg_addr_byte3 |
2125851 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar2_reg_addr_byte0 |
28696 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar3_enable_reg_addr_byte0 |
2125852 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar3_mask_reg_addr_byte0 |
2125852 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar3_mask_reg_addr_byte1 |
2125853 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar3_mask_reg_addr_byte2 |
2125854 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar3_mask_reg_addr_byte3 |
2125855 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar3_reg_addr_byte0 |
28700 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar4_mask_reg_addr_byte0 |
2125856 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar4_mask_reg_addr_byte1 |
2125857 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar4_mask_reg_addr_byte2 |
2125858 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar4_mask_reg_addr_byte3 |
2125859 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar4_reg_addr_byte0 |
28704 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar5_enable_reg_addr_byte0 |
2125860 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar5_mask_reg_addr_byte0 |
2125860 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar5_mask_reg_addr_byte1 |
2125861 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar5_mask_reg_addr_byte2 |
2125862 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar5_mask_reg_addr_byte3 |
2125863 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bar5_reg_addr_byte0 |
28708 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
28686 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
28712 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
28713 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
28714 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
28715 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
28672 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
28673 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
28674 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
28675 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2125872 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2125873 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2125874 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2125875 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
28720 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
28733 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
28724 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
28716 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
28717 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
28718 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
28719 |
hssi_ctp_u_wrpcie_top_u_core16_pf7_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pf7_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core16_pld_aib_loopback_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pld_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core16_pld_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_pld_tx_fifo_dyn_empty_dis |
false |
hssi_ctp_u_wrpcie_top_u_core16_powerdown_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_powermode_ac |
pcie_g4_x16 |
hssi_ctp_u_wrpcie_top_u_core16_powermode_dc |
powerdown |
hssi_ctp_u_wrpcie_top_u_core16_powermode_freq_hz |
1000000000 |
hssi_ctp_u_wrpcie_top_u_core16_rct |
1 |
hssi_ctp_u_wrpcie_top_u_core16_rstctl_timer_a |
0 |
hssi_ctp_u_wrpcie_top_u_core16_rstctl_timer_b |
0 |
hssi_ctp_u_wrpcie_top_u_core16_rtsel |
1 |
hssi_ctp_u_wrpcie_top_u_core16_rx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_rxbuf_limit_bypass |
0 |
hssi_ctp_u_wrpcie_top_u_core16_rxbuf_limit_init |
false |
hssi_ctp_u_wrpcie_top_u_core16_rxbuf_pfull_th |
22 |
hssi_ctp_u_wrpcie_top_u_core16_scratch_pad0_31_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core16_sd_cfg |
false |
hssi_ctp_u_wrpcie_top_u_core16_sd_dwip |
false |
hssi_ctp_u_wrpcie_top_u_core16_shadow_select |
false |
hssi_ctp_u_wrpcie_top_u_core16_sim_mode |
enable |
hssi_ctp_u_wrpcie_top_u_core16_sriov_clk_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_sris_mode |
false |
hssi_ctp_u_wrpcie_top_u_core16_sup_mode |
user_mode |
hssi_ctp_u_wrpcie_top_u_core16_test_in_high |
0 |
hssi_ctp_u_wrpcie_top_u_core16_test_in_lo |
0 |
hssi_ctp_u_wrpcie_top_u_core16_test_in_override |
false |
hssi_ctp_u_wrpcie_top_u_core16_tx_cdts_rst |
false |
hssi_ctp_u_wrpcie_top_u_core16_tx_fifo_empty_threshold_1 |
3 |
hssi_ctp_u_wrpcie_top_u_core16_tx_fifo_empty_threshold_2 |
12 |
hssi_ctp_u_wrpcie_top_u_core16_tx_fifo_empty_threshold_3 |
15 |
hssi_ctp_u_wrpcie_top_u_core16_tx_fifo_empty_threshold_4 |
2 |
hssi_ctp_u_wrpcie_top_u_core16_tx_fifo_full_threshold |
40 |
hssi_ctp_u_wrpcie_top_u_core16_tx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core16_user_mode_del_count |
0 |
hssi_ctp_u_wrpcie_top_u_core16_vf |
0 |
hssi_ctp_u_wrpcie_top_u_core16_vf_select |
false |
hssi_ctp_u_wrpcie_top_u_core16_virtual_drop_vendor0_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_virtual_drop_vendor1_msg |
false |
hssi_ctp_u_wrpcie_top_u_core16_virtual_ep_native |
native |
hssi_ctp_u_wrpcie_top_u_core16_virtual_gen2_pma_pll_usage |
not_applicable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_hrdrstctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_ip_port_num |
pcie_port0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_link_rate |
gen3 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_link_width |
x16 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_maxpayload_size |
max_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_num_of_lanes |
num_16 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_dlink_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_io_decode |
io32 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_ltr_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_margin_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_pl16g_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_prefetch_decode |
pref64 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf0_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf1_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf2_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf3_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf4_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf5_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf6_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pf7_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_phase23_txpreset |
preset7 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_phase23_txpreset_atg4 |
gen4_preset7 |
hssi_ctp_u_wrpcie_top_u_core16_virtual_pldclk_rate |
fast |
hssi_ctp_u_wrpcie_top_u_core16_virtual_rp_ep_mode |
ep |
hssi_ctp_u_wrpcie_top_u_core16_virtual_tlp_bypass_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_txeq_mode |
eq_disable |
hssi_ctp_u_wrpcie_top_u_core16_virtual_uc_calibration_en |
enable |
hssi_ctp_u_wrpcie_top_u_core16_vsec_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core16_vsec_select |
false |
hssi_ctp_u_wrpcie_top_u_core16_wait_pld_warm_rst_rdy |
false |
hssi_ctp_u_wrpcie_top_u_core16_wct |
1 |
hssi_ctp_u_wrpcie_top_u_core16_wtsel |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_bad_dllp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_bad_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_blk_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_corrected_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf0_table_size |
261 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf1_start_addr |
320 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf1_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf2_start_addr |
512 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf2_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf3_start_addr |
704 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf3_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf4_start_addr |
896 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf4_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf5_start_addr |
1088 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf5_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf6_start_addr |
1280 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf6_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf7_start_addr |
1472 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dbi_pf7_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_dl_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_ecrc_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_fc_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_mlf_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_ram_ecc_chk_val |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_ram_ecc_gen_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_rcvr_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_rcvr_overflow_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_replay_number_rollover_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_replay_timer_timeout_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_surprise_down_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cfg_uncor_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_clkmod_core_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_clrhip_not_rst_sticky |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_crs_override |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_crs_override_value |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_blocking_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_data_compressed |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_data_encrypted |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_hard_reset_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_hip_clk_sel_default |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_intf_reset_ctl |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_irq_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_jtag0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_jtag1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_jtag2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_jtag3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_mode_default |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_mode_gating_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_update_no_reset |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_user_id |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_vsec_id |
4466 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_vsec_rev |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_warm_rst_ready_force_bit0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_warm_rst_ready_force_bit1 |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_warm_rst_req_ena |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_cvp_write_mask_ctl |
3 |
hssi_ctp_u_wrpcie_top_u_core4_0_dbi_ro_wr_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_device_type |
dev_nep |
hssi_ctp_u_wrpcie_top_u_core4_0_device_width |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_disable_ct_ur |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_disable_msg_ur |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_disable_ur_nf |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_ecrc_strip |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_en_gpio_perst |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_enable_poison_nf |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_ep_signal_mask |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_err_tlp_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acs_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_acscap_enable_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf0 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf1 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf2 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf3 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf4 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf5 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf6 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_aricap_nxtptr_pf7 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_globalinvalidate_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_invalidateqdepth_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf0 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf1 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf2 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf3 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf4 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf5 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf6 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_nxtptr_pf7 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_ats_pagealignreq_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_atscap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msix_tablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixpba_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_msixtable_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf0 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf1 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf2 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf3 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf4 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf5 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf6 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_pciecap_nxtptr_pf7 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_revisionid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_subsysid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_devspecificmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_exttphrequester_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_intvecmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf0 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf1 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf2 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf3 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf4 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf5 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf6 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_nxtptr_pf7 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablelocation_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tph_sttablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_tphcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf0 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf1 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf2 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf3 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf4 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf5 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf6 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_exvf_type0cap_nxtptr_pf7 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_func_mode |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_gate_clk_in_reset_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_gate_radm_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_gpio_irq |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_intel_marker |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_irq_misc_ctrl |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_kp |
3 |
hssi_ctp_u_wrpcie_top_u_core4_0_margining_ready |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_margining_software_ready |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_nonsriov_mode |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ack_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 |
642 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 |
643 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_capalities_ctrl_reg_byte0 |
644 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_capalities_ctrl_reg_byte1 |
645 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_adv_err_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
258 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
259 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aer_cap_root_err_status_off_addr_byte0 |
304 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_cap_ari_base_addr_byte2 |
378 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_cap_ari_base_addr_byte3 |
379 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_cap_cap_reg_addr_byte0 |
380 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 |
626 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 |
627 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
628 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_auto_eq_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_auto_eq_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_auto_lane_flip_ctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aux_clk_freq |
10 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aux_clk_freq_off_rsvdp_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar0_mem_io |
pf0_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar0_type |
pf0_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar1_mem_io |
pf0_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar1_type |
pf0_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar2_mem_io |
pf0_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar2_type |
pf0_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar3_mem_io |
pf0_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar3_type |
pf0_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar4_mem_io |
pf0_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar4_type |
pf0_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar5_mem_io |
pf0_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_bar5_type |
pf0_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_common_clk_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_config_limit |
1023 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_config_phy_tx_change |
pf0_full_swing |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_config_tx_comp_rx |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_cross_link_active |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_cross_link_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_d1_support |
pf0_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_d2_support |
pf0_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_67 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_68 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_direct_speed_change |
pf0_auto_speed_chg |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_disable_fc_wd_timer |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_disable_scrambler_gen_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_disable_scrambler_gen_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 |
998 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 |
999 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dlink_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dlink_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dll_link_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsi |
pf0_not_required |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_dsp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_eidle_timer |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_eq_eieos_cnt |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_eq_eieos_cnt_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_eq_phase_2_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_eq_phase_2_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_eq_redo |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_eq_redo_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_fast_link_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_fast_training_seq |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen1_ei_inference |
pf0_use_rx_eidle |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen2_ctrl_off_rsvdp_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_dc_balance_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_dc_balance_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_dllp_xmt_delay_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_dllp_xmt_delay_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_control_off_rsvdp_27_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_control_off_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_control_off_rsvdp_7_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_eval_2ms_disable |
pf0_abort |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_eval_2ms_disable_atg4 |
pf0_abort_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fb_mode |
pf0_dir_chg |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fb_mode_atg4 |
pf0_dir_chg_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_max_post_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_max_post_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_max_pre_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_max_pre_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_n_evals |
4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_n_evals_atg4 |
4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_t_min_phase23 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fmdc_t_min_phase23_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fom_inc_initial_eval |
pf0_ignore_init_fom |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_fom_inc_initial_eval_atg4 |
pf0_ignore_init_fom_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_invreq_eva_diff_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_invreq_eva_diff_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_phase23_exit_mode |
pf0_next_rec_speed |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_phase23_exit_mode_atg4 |
pf0_next_rec_speed_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_pset_req_as_coef |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_pset_req_as_coef_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_pset_req_vec |
128 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_eq_pset_req_vec_atg4 |
128 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_equalization_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_equalization_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_lower_rate_eq_redo_enable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_14_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_19_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_1_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_related_off_rsvdp_26_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_req_send_consec_eieos_for_pset_map |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_zrxdc_noncompl |
pf0_non_compliant |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_gen3_zrxdc_noncompl_atg4 |
pf0_non_compliant_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_int_pin |
pf0_inta |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control01_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control01_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control01_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control01_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1011_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1011_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1011_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1011_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1213_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1213_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1213_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1213_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1415_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1415_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1415_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control1415_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control23_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control23_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control23_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control23_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control45_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control45_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control45_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control45_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control67_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control67_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control67_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control67_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control89_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control89_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control89_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_lane_equalization_control89_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_capable |
pf0_conn_x1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_link_num |
4 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_loopback_enable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 |
670 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 |
671 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ltr_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ltr_next_offset |
816 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 |
462 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 |
463 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_margin_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_margin_next_offset |
780 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_mask_radm_1 |
8200 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_mask_radm_2 |
3 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_max_func_num |
pf0_one_function |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_misc_control_1_rsvdp_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
81 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
82 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
83 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_pba_offset_reg_addr_byte0 |
184 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_pba_offset_reg_addr_byte1 |
185 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_pba_offset_reg_addr_byte2 |
186 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_pba_offset_reg_addr_byte3 |
187 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_table_offset_reg_addr_byte0 |
180 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_table_offset_reg_addr_byte1 |
181 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_table_offset_reg_addr_byte2 |
182 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_msix_table_offset_reg_addr_byte3 |
183 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
177 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
178 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
179 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2097330 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2097331 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_no_soft_rst |
pf0_internally_reset |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_num_of_lanes |
16 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_p2p_err_rpt_ctrl |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_p2p_track_cpl_to_reg |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
680 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
681 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
678 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
679 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_multiple_msg_cap |
pf0_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_active_state_link_pm_support |
pf0_no_aspm |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_attention_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_attention_indicator_button |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_clock_power_man |
pf0_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_crs_sw_visibility |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_device_capabilities_reg_addr_byte0 |
116 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_device_capabilities_reg_addr_byte1 |
117 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_device_capabilities_reg_addr_byte3 |
119 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_device_control_device_status_addr_byte1 |
121 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_electromech_interlock |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_en_clk_power_man |
pf0_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_ext_tag_supp |
pf0_supported |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_flr_cap |
pf0_capable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_hot_plug_capable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_hot_plug_surprise |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_capabilities_reg_addr_byte0 |
124 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_capabilities_reg_addr_byte1 |
125 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_capabilities_reg_addr_byte2 |
126 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_capabilities_reg_addr_byte3 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4194464 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_control_link_status_reg_addr_byte0 |
4194432 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_control_link_status_reg_addr_byte1 |
4194433 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_control_link_status_reg_addr_byte2 |
4194434 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_max_link_speed |
pf0_max_8gts |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_max_link_width |
pf0_x16 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_max_payload_size |
pf0_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_mrl_sensor |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_no_cmd_cpl_support |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
113 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
115 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_phy_slot_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_power_controller |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_power_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_rcb |
pf0_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 |
142 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_sel_deemphasis |
pf0_minus_6db |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2097276 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2097277 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_slot_capabilities_reg_addr_byte0 |
132 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_slot_capabilities_reg_addr_byte1 |
133 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_slot_capabilities_reg_addr_byte2 |
134 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_slot_capabilities_reg_addr_byte3 |
135 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_slot_power_limit_scale |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_slot_power_limit_value |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_target_link_speed |
pf0_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pcie_slot_imp |
pf0_not_implemented |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pipe_loopback |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pipe_loopback_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 |
456 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 |
457 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 |
458 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 |
458 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 |
460 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 |
461 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 |
462 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 |
463 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 |
464 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 |
465 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 |
466 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 |
467 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 |
468 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 |
469 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 |
470 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 |
471 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 |
426 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 |
427 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pl16g_next_offset |
488 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
65 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
66 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
67 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pm_cap_con_status_reg_addr_byte0 |
68 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_link_ctrl_off_rsvdp_4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 |
1805 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 |
1806 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_aux_clk_freq_off_addr_byte0 |
2880 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_aux_clk_freq_off_addr_byte1 |
2881 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_filter_mask_2_off_addr_byte0 |
1824 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_filter_mask_2_off_addr_byte1 |
1825 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_filter_mask_2_off_addr_byte2 |
1826 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_filter_mask_2_off_addr_byte3 |
1827 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen2_ctrl_off_addr_byte0 |
2060 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen2_ctrl_off_addr_byte1 |
2061 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen2_ctrl_off_addr_byte2 |
4196366 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 |
2202 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_atg4_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_atg4_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_atg4_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_gen3_related_off_atg4_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_misc_control_1_off_addr_byte1 |
2237 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_misc_control_1_off_addr_byte2 |
2238 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_pipe_loopback_control_off_addr_byte3 |
2235 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_port_force_off_addr_byte0 |
1800 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_port_link_ctrl_off_addr_byte0 |
1808 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_port_link_ctrl_off_addr_byte2 |
1810 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_queue_status_off_addr_byte2 |
1854 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_queue_status_off_addr_byte3 |
1855 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 |
1820 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 |
1821 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 |
1822 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 |
1823 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 |
1816 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 |
1872 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 |
1873 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 |
1874 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 |
1875 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 |
1868 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 |
1869 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 |
1870 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 |
1864 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 |
1865 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 |
1866 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_pre_det_lane |
pf0_det_all_lanes |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
654 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
655 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
800 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
801 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
802 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
803 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_queue_status_off_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
685 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
686 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rate_shadow_sel |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rate_shadow_sel_atg4 |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved250 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved8 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_67_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_68_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_reset_assert |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_root_control_root_capabilities_reg_rsvdp_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_root_err_status_off_rsvdp_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rp_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rp_rom_mask |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rxeq_ph01_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rxeq_ph01_en_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rxeq_rgrdless_rxts |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rxeq_rgrdless_rxts_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_rxstatus_value |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_scramble_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sel_deemphasis |
pf0_minus_3db_ctl |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_skp_int_val |
640 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 |
364 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 |
365 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 |
366 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 |
367 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 |
368 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 |
369 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 |
370 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 |
371 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_sn_base_addr_byte2 |
362 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_sn_base_addr_byte3 |
363 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 |
404 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 |
405 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 |
406 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 |
407 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 |
424 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 |
425 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 |
426 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 |
427 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 |
428 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 |
429 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 |
430 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 |
431 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 |
432 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 |
433 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 |
434 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 |
435 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 |
408 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 |
409 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 |
410 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 |
411 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 |
412 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 |
413 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 |
414 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 |
415 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 |
416 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 |
417 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 |
418 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 |
419 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 |
420 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 |
421 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 |
422 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 |
423 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 |
394 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 |
395 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_spcie_next_offset |
456 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2097724 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2097725 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2097732 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2097733 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2097734 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2097735 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2097748 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2097749 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2097750 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2097751 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2097753 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2097754 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2097755 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2097756 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2097757 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2097758 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2097759 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2097761 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2097762 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2097763 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2097764 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2097765 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2097766 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2097767 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2097769 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2097770 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2097771 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_base_reg_addr_byte2 |
562 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_base_reg_addr_byte3 |
563 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_initial_vfs_addr_byte0 |
572 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_initial_vfs_addr_byte1 |
573 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 |
580 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 |
581 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 |
582 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 |
583 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 |
588 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 |
589 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 |
590 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 |
591 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_bar0_reg_addr_byte0 |
596 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_bar1_reg_addr_byte0 |
600 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_bar2_reg_addr_byte0 |
604 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_bar3_reg_addr_byte0 |
608 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_bar4_reg_addr_byte0 |
612 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_bar5_reg_addr_byte0 |
616 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_device_id_reg_addr_byte2 |
586 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_cap_vf_device_id_reg_addr_byte3 |
587 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar0_type |
pf0_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar1_type |
pf0_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar2_type |
pf0_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar3_type |
pf0_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar4_type |
pf0_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_bar5_type |
pf0_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_offset_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_target_above_config_limit |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_timer_mod_flow_control |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_timer_mod_flow_control_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
486 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
487 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_addr_byte0 |
488 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_addr_byte1 |
489 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_addr_byte2 |
490 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_addr_byte3 |
491 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2097640 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2097641 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2097642 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2097643 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_st_table_loc_0 |
pf0_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf0_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf0_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar0_mask_reg_addr_byte0 |
2097168 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar0_mask_reg_addr_byte1 |
2097169 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar0_mask_reg_addr_byte2 |
2097170 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar0_mask_reg_addr_byte3 |
2097171 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar0_reg_addr_byte0 |
16 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar1_enable_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar1_mask_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar1_mask_reg_addr_byte1 |
2097173 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar1_mask_reg_addr_byte2 |
2097174 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar1_mask_reg_addr_byte3 |
2097175 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar1_reg_addr_byte0 |
20 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar2_mask_reg_addr_byte0 |
2097176 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar2_mask_reg_addr_byte1 |
2097177 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar2_mask_reg_addr_byte2 |
2097178 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar2_mask_reg_addr_byte3 |
2097179 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar2_reg_addr_byte0 |
24 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar3_enable_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar3_mask_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar3_mask_reg_addr_byte1 |
2097181 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar3_mask_reg_addr_byte2 |
2097182 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar3_mask_reg_addr_byte3 |
2097183 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar3_reg_addr_byte0 |
28 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar4_mask_reg_addr_byte0 |
2097184 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar4_mask_reg_addr_byte1 |
2097185 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar4_mask_reg_addr_byte2 |
2097186 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar4_mask_reg_addr_byte3 |
2097187 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar4_reg_addr_byte0 |
32 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar5_enable_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar5_mask_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar5_mask_reg_addr_byte1 |
2097189 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar5_mask_reg_addr_byte2 |
2097190 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar5_mask_reg_addr_byte3 |
2097191 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bar5_reg_addr_byte0 |
36 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
14 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
40 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
41 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
42 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
43 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_class_code_revision_id_addr_byte0 |
8 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_class_code_revision_id_addr_byte1 |
9 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_class_code_revision_id_addr_byte2 |
10 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_class_code_revision_id_addr_byte3 |
11 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
3 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2097200 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2097201 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2097202 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2097203 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
48 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
61 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
52 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 |
2097208 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 |
2097209 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 |
2097210 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 |
2097211 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
44 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
45 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
46 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
47 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_send_8gt_eq_ts2_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_send_8gt_eq_ts2_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_usp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_cpl_data_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_cpl_data_scale |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_cpl_hdr_scale |
3 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_cpl_header_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_cpl_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_np_data_credit |
230 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_np_header_credit |
115 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_np_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_p_data_credit |
750 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_p_header_credit |
127 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc0_p_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc_cap_vc_base_addr_byte2 |
330 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc_cap_vc_base_addr_byte3 |
331 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vc_next_offset |
360 |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vendor_specific_dllp_req |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pf0_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pld_aib_loopback_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pld_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pld_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_pld_tx_fifo_dyn_empty_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_powerdown_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_powermode_ac |
pcie_g4_x16 |
hssi_ctp_u_wrpcie_top_u_core4_0_powermode_dc |
powerdown |
hssi_ctp_u_wrpcie_top_u_core4_0_powermode_freq_hz |
1000000000 |
hssi_ctp_u_wrpcie_top_u_core4_0_rct |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_rstctl_timer_a |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_rstctl_timer_b |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_rtsel |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_rx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_rxbuf_limit_bypass |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_rxbuf_limit_init |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_rxbuf_pfull_th |
22 |
hssi_ctp_u_wrpcie_top_u_core4_0_scratch_pad0_31_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_sd_cfg |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_sd_dwip |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_shadow_select |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_sim_mode |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_sriov_clk_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_sris_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_sup_mode |
user_mode |
hssi_ctp_u_wrpcie_top_u_core4_0_test_in_high |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_test_in_lo |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_test_in_override |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_tx_cdts_rst |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_tx_fifo_empty_threshold_1 |
3 |
hssi_ctp_u_wrpcie_top_u_core4_0_tx_fifo_empty_threshold_2 |
12 |
hssi_ctp_u_wrpcie_top_u_core4_0_tx_fifo_empty_threshold_3 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_0_tx_fifo_empty_threshold_4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_0_tx_fifo_full_threshold |
40 |
hssi_ctp_u_wrpcie_top_u_core4_0_tx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_user_mode_del_count |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_vf |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_vf_select |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_drop_vendor0_msg |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_drop_vendor1_msg |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_ep_native |
native |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_gen2_pma_pll_usage |
not_applicable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_hrdrstctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_ip_port_num |
pcie_port0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_link_rate |
gen3 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_link_width |
x16 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_maxpayload_size |
max_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_num_of_lanes |
num_16 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_dlink_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_io_decode |
io32 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_ltr_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_margin_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_pl16g_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_prefetch_decode |
pref64 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf0_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf1_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf2_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf3_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf4_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf5_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf6_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pf7_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_phase23_txpreset |
preset7 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_phase23_txpreset_atg4 |
gen4_preset7 |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_pldclk_rate |
fast |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_rp_ep_mode |
ep |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_tlp_bypass_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_txeq_mode |
eq_disable |
hssi_ctp_u_wrpcie_top_u_core4_0_virtual_uc_calibration_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_0_vsec_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_0_vsec_select |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_wait_pld_warm_rst_rdy |
false |
hssi_ctp_u_wrpcie_top_u_core4_0_wct |
1 |
hssi_ctp_u_wrpcie_top_u_core4_0_wtsel |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_bad_dllp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_bad_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_blk_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_corrected_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf0_table_size |
261 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf1_start_addr |
320 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf1_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf2_start_addr |
512 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf2_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf3_start_addr |
704 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf3_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf4_start_addr |
896 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf4_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf5_start_addr |
1088 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf5_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf6_start_addr |
1280 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf6_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf7_start_addr |
1472 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dbi_pf7_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_dl_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_ecrc_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_fc_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_mlf_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_ram_ecc_chk_val |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_ram_ecc_gen_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_rcvr_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_rcvr_overflow_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_replay_number_rollover_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_replay_timer_timeout_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_surprise_down_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cfg_uncor_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_clkmod_core_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_clrhip_not_rst_sticky |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_crs_override |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_crs_override_value |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_blocking_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_data_compressed |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_data_encrypted |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_hard_reset_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_hip_clk_sel_default |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_intf_reset_ctl |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_irq_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_jtag0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_jtag1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_jtag2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_jtag3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_mode_default |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_mode_gating_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_update_no_reset |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_user_id |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_vsec_id |
4466 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_vsec_rev |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_warm_rst_ready_force_bit0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_warm_rst_ready_force_bit1 |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_warm_rst_req_ena |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_cvp_write_mask_ctl |
3 |
hssi_ctp_u_wrpcie_top_u_core4_1_dbi_ro_wr_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_device_type |
dev_nep |
hssi_ctp_u_wrpcie_top_u_core4_1_device_width |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_disable_ct_ur |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_disable_msg_ur |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_disable_ur_nf |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_ecrc_strip |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_en_gpio_perst |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_enable_poison_nf |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_ep_signal_mask |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_err_tlp_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acs_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_acscap_enable_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf0 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf1 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf2 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf3 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf4 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf5 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf6 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_aricap_nxtptr_pf7 |
624 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_globalinvalidate_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_invalidateqdepth_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf0 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf1 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf2 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf3 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf4 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf5 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf6 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_nxtptr_pf7 |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_ats_pagealignreq_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_atscap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msix_tablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixpba_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_msixtable_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf0 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf1 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf2 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf3 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf4 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf5 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf6 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_pciecap_nxtptr_pf7 |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_revisionid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_subsysid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_devspecificmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_exttphrequester_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_intvecmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf0 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf1 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf2 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf3 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf4 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf5 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf6 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_nxtptr_pf7 |
764 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablelocation_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tph_sttablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_tphcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf0 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf1 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf2 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf3 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf4 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf5 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf6 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_exvf_type0cap_nxtptr_pf7 |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_func_mode |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_gate_clk_in_reset_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_gate_radm_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_gpio_irq |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_intel_marker |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_irq_misc_ctrl |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_kp |
3 |
hssi_ctp_u_wrpcie_top_u_core4_1_margining_ready |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_margining_software_ready |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_nonsriov_mode |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ack_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 |
642 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 |
643 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_capalities_ctrl_reg_byte0 |
644 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_capalities_ctrl_reg_byte1 |
645 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_adv_err_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
258 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
259 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aer_cap_root_err_status_off_addr_byte0 |
304 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_cap_ari_base_addr_byte2 |
378 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_cap_ari_base_addr_byte3 |
379 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_cap_cap_reg_addr_byte0 |
380 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 |
626 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 |
627 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
628 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_auto_eq_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_auto_eq_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_auto_lane_flip_ctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aux_clk_freq |
10 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aux_clk_freq_off_rsvdp_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar0_mem_io |
pf0_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar0_type |
pf0_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar1_mem_io |
pf0_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar1_type |
pf0_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar2_mem_io |
pf0_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar2_type |
pf0_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar3_mem_io |
pf0_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar3_type |
pf0_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar4_mem_io |
pf0_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar4_type |
pf0_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar5_mem_io |
pf0_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_bar5_type |
pf0_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_common_clk_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_config_limit |
1023 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_config_phy_tx_change |
pf0_full_swing |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_config_tx_comp_rx |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_cross_link_active |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_cross_link_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_d1_support |
pf0_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_d2_support |
pf0_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_67 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_68 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_direct_speed_change |
pf0_auto_speed_chg |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_disable_fc_wd_timer |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_disable_scrambler_gen_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_disable_scrambler_gen_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 |
998 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 |
999 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dlink_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dlink_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dll_link_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsi |
pf0_not_required |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_dsp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_eidle_timer |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_eq_eieos_cnt |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_eq_eieos_cnt_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_eq_phase_2_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_eq_phase_2_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_eq_redo |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_eq_redo_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_fast_link_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_fast_training_seq |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen1_ei_inference |
pf0_use_rx_eidle |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen2_ctrl_off_rsvdp_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_dc_balance_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_dc_balance_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_dllp_xmt_delay_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_dllp_xmt_delay_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_control_off_rsvdp_27_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_control_off_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_control_off_rsvdp_7_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_eval_2ms_disable |
pf0_abort |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_eval_2ms_disable_atg4 |
pf0_abort_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fb_mode |
pf0_dir_chg |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fb_mode_atg4 |
pf0_dir_chg_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_max_post_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_max_post_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_max_pre_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_max_pre_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_n_evals |
4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_n_evals_atg4 |
4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_t_min_phase23 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fmdc_t_min_phase23_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fom_inc_initial_eval |
pf0_ignore_init_fom |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_fom_inc_initial_eval_atg4 |
pf0_ignore_init_fom_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_invreq_eva_diff_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_invreq_eva_diff_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_phase23_exit_mode |
pf0_next_rec_speed |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_phase23_exit_mode_atg4 |
pf0_next_rec_speed_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_pset_req_as_coef |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_pset_req_as_coef_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_pset_req_vec |
128 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_eq_pset_req_vec_atg4 |
128 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_equalization_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_equalization_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_lower_rate_eq_redo_enable |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_14_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_19_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_1_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_related_off_rsvdp_26_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_req_send_consec_eieos_for_pset_map |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_zrxdc_noncompl |
pf0_non_compliant |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_gen3_zrxdc_noncompl_atg4 |
pf0_non_compliant_atg4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_int_pin |
pf0_inta |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control01_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control01_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control01_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control01_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1011_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1011_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1011_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1011_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1213_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1213_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1213_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1213_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1415_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1415_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1415_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control1415_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control23_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control23_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control23_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control23_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control45_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control45_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control45_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control45_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control67_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control67_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control67_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control67_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control89_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control89_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control89_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_lane_equalization_control89_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_capable |
pf0_conn_x1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_link_num |
4 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_loopback_enable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 |
670 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 |
671 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ltr_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ltr_next_offset |
816 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 |
462 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 |
463 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_margin_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_margin_next_offset |
780 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_mask_radm_1 |
8200 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_mask_radm_2 |
3 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_max_func_num |
pf0_one_function |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_misc_control_1_rsvdp_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
81 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
82 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
83 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_pba_offset_reg_addr_byte0 |
184 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_pba_offset_reg_addr_byte1 |
185 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_pba_offset_reg_addr_byte2 |
186 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_pba_offset_reg_addr_byte3 |
187 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_table_offset_reg_addr_byte0 |
180 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_table_offset_reg_addr_byte1 |
181 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_table_offset_reg_addr_byte2 |
182 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_msix_table_offset_reg_addr_byte3 |
183 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
177 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
178 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
179 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2097330 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2097331 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_no_soft_rst |
pf0_internally_reset |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_num_of_lanes |
16 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_p2p_err_rpt_ctrl |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_p2p_track_cpl_to_reg |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
680 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
681 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
678 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
679 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_multiple_msg_cap |
pf0_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_active_state_link_pm_support |
pf0_no_aspm |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_attention_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_attention_indicator_button |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_clock_power_man |
pf0_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_crs_sw_visibility |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_device_capabilities_reg_addr_byte0 |
116 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_device_capabilities_reg_addr_byte1 |
117 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_device_capabilities_reg_addr_byte3 |
119 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_device_control_device_status_addr_byte1 |
121 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_electromech_interlock |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_en_clk_power_man |
pf0_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_ext_tag_supp |
pf0_supported |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_flr_cap |
pf0_capable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_hot_plug_capable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_hot_plug_surprise |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_capabilities_reg_addr_byte0 |
124 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_capabilities_reg_addr_byte1 |
125 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_capabilities_reg_addr_byte2 |
126 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_capabilities_reg_addr_byte3 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4194464 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_control_link_status_reg_addr_byte0 |
4194432 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_control_link_status_reg_addr_byte1 |
4194433 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_control_link_status_reg_addr_byte2 |
4194434 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_max_link_speed |
pf0_max_8gts |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_max_link_width |
pf0_x16 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_max_payload_size |
pf0_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_mrl_sensor |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_no_cmd_cpl_support |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
113 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
115 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_phy_slot_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_power_controller |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_power_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_rcb |
pf0_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 |
142 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_sel_deemphasis |
pf0_minus_6db |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2097276 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2097277 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_slot_capabilities_reg_addr_byte0 |
132 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_slot_capabilities_reg_addr_byte1 |
133 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_slot_capabilities_reg_addr_byte2 |
134 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_slot_capabilities_reg_addr_byte3 |
135 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_slot_power_limit_scale |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_slot_power_limit_value |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_target_link_speed |
pf0_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pcie_slot_imp |
pf0_not_implemented |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pipe_loopback |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pipe_loopback_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 |
456 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 |
457 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 |
458 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 |
458 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 |
460 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 |
461 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 |
462 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 |
463 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 |
464 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 |
465 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 |
466 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 |
467 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 |
468 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 |
469 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 |
470 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 |
471 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 |
426 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 |
427 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pl16g_next_offset |
488 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
65 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
66 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
67 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pm_cap_con_status_reg_addr_byte0 |
68 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_link_ctrl_off_rsvdp_4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 |
1805 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 |
1806 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_aux_clk_freq_off_addr_byte0 |
2880 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_aux_clk_freq_off_addr_byte1 |
2881 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_filter_mask_2_off_addr_byte0 |
1824 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_filter_mask_2_off_addr_byte1 |
1825 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_filter_mask_2_off_addr_byte2 |
1826 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_filter_mask_2_off_addr_byte3 |
1827 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen2_ctrl_off_addr_byte0 |
2060 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen2_ctrl_off_addr_byte1 |
2061 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen2_ctrl_off_addr_byte2 |
4196366 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 |
2202 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_atg4_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_atg4_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_atg4_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_gen3_related_off_atg4_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_misc_control_1_off_addr_byte1 |
2237 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_misc_control_1_off_addr_byte2 |
2238 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_pipe_loopback_control_off_addr_byte3 |
2235 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_port_force_off_addr_byte0 |
1800 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_port_link_ctrl_off_addr_byte0 |
1808 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_port_link_ctrl_off_addr_byte2 |
1810 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_queue_status_off_addr_byte2 |
1854 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_queue_status_off_addr_byte3 |
1855 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 |
1820 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 |
1821 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 |
1822 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 |
1823 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 |
1816 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 |
1872 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 |
1873 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 |
1874 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 |
1875 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 |
1868 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 |
1869 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 |
1870 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 |
1864 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 |
1865 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 |
1866 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_pre_det_lane |
pf0_det_all_lanes |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
654 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
655 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
800 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
801 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
802 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
803 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_queue_status_off_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
685 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
686 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rate_shadow_sel |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rate_shadow_sel_atg4 |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved250 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved4 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved6 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved8 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_67_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_68_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_reset_assert |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_root_control_root_capabilities_reg_rsvdp_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_root_err_status_off_rsvdp_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rp_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rp_rom_mask |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rxeq_ph01_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rxeq_ph01_en_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rxeq_rgrdless_rxts |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rxeq_rgrdless_rxts_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_rxstatus_value |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_scramble_disable |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sel_deemphasis |
pf0_minus_3db_ctl |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_skp_int_val |
640 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 |
364 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 |
365 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 |
366 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 |
367 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 |
368 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 |
369 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 |
370 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 |
371 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_sn_base_addr_byte2 |
362 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_sn_base_addr_byte3 |
363 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 |
404 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 |
405 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 |
406 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 |
407 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 |
424 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 |
425 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 |
426 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 |
427 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 |
428 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 |
429 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 |
430 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 |
431 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 |
432 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 |
433 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 |
434 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 |
435 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 |
408 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 |
409 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 |
410 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 |
411 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 |
412 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 |
413 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 |
414 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 |
415 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 |
416 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 |
417 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 |
418 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 |
419 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 |
420 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 |
421 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 |
422 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 |
423 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 |
394 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 |
395 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_spcie_next_offset |
456 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2097724 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2097725 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2097732 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2097733 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2097734 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2097735 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2097748 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2097749 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2097750 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2097751 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2097753 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2097754 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2097755 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2097756 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2097757 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2097758 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2097759 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2097761 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2097762 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2097763 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2097764 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2097765 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2097766 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2097767 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2097769 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2097770 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2097771 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_base_reg_addr_byte2 |
562 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_base_reg_addr_byte3 |
563 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_initial_vfs_addr_byte0 |
572 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_initial_vfs_addr_byte1 |
573 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 |
580 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 |
581 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 |
582 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 |
583 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 |
588 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 |
589 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 |
590 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 |
591 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_bar0_reg_addr_byte0 |
596 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_bar1_reg_addr_byte0 |
600 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_bar2_reg_addr_byte0 |
604 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_bar3_reg_addr_byte0 |
608 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_bar4_reg_addr_byte0 |
612 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_bar5_reg_addr_byte0 |
616 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_device_id_reg_addr_byte2 |
586 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_cap_vf_device_id_reg_addr_byte3 |
587 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar0_type |
pf0_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar1_type |
pf0_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar2_type |
pf0_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar3_type |
pf0_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar4_type |
pf0_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_bar5_type |
pf0_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_offset_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_target_above_config_limit |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_timer_mod_flow_control |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_timer_mod_flow_control_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
486 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
487 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_addr_byte0 |
488 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_addr_byte1 |
489 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_addr_byte2 |
490 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_addr_byte3 |
491 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2097640 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2097641 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2097642 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2097643 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_st_table_loc_0 |
pf0_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf0_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf0_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar0_mask_reg_addr_byte0 |
2097168 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar0_mask_reg_addr_byte1 |
2097169 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar0_mask_reg_addr_byte2 |
2097170 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar0_mask_reg_addr_byte3 |
2097171 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar0_reg_addr_byte0 |
16 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar1_enable_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar1_mask_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar1_mask_reg_addr_byte1 |
2097173 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar1_mask_reg_addr_byte2 |
2097174 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar1_mask_reg_addr_byte3 |
2097175 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar1_reg_addr_byte0 |
20 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar2_mask_reg_addr_byte0 |
2097176 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar2_mask_reg_addr_byte1 |
2097177 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar2_mask_reg_addr_byte2 |
2097178 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar2_mask_reg_addr_byte3 |
2097179 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar2_reg_addr_byte0 |
24 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar3_enable_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar3_mask_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar3_mask_reg_addr_byte1 |
2097181 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar3_mask_reg_addr_byte2 |
2097182 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar3_mask_reg_addr_byte3 |
2097183 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar3_reg_addr_byte0 |
28 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar4_mask_reg_addr_byte0 |
2097184 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar4_mask_reg_addr_byte1 |
2097185 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar4_mask_reg_addr_byte2 |
2097186 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar4_mask_reg_addr_byte3 |
2097187 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar4_reg_addr_byte0 |
32 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar5_enable_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar5_mask_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar5_mask_reg_addr_byte1 |
2097189 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar5_mask_reg_addr_byte2 |
2097190 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar5_mask_reg_addr_byte3 |
2097191 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bar5_reg_addr_byte0 |
36 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
14 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
40 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
41 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
42 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
43 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_class_code_revision_id_addr_byte0 |
8 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_class_code_revision_id_addr_byte1 |
9 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_class_code_revision_id_addr_byte2 |
10 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_class_code_revision_id_addr_byte3 |
11 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
3 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2097200 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2097201 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2097202 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2097203 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
48 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
61 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
52 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 |
2097208 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 |
2097209 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 |
2097210 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 |
2097211 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
44 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
45 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
46 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
47 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_send_8gt_eq_ts2_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_send_8gt_eq_ts2_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_usp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_cpl_data_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_cpl_data_scale |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_cpl_hdr_scale |
3 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_cpl_header_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_cpl_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_np_data_credit |
230 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_np_header_credit |
115 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_np_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_p_data_credit |
750 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_p_header_credit |
127 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc0_p_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc_cap_vc_base_addr_byte2 |
330 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc_cap_vc_base_addr_byte3 |
331 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vc_next_offset |
360 |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vendor_specific_dllp_req |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pf0_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pld_aib_loopback_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pld_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pld_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_pld_tx_fifo_dyn_empty_dis |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_powerdown_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_powermode_ac |
pcie_g4_x16 |
hssi_ctp_u_wrpcie_top_u_core4_1_powermode_dc |
powerdown |
hssi_ctp_u_wrpcie_top_u_core4_1_powermode_freq_hz |
1000000000 |
hssi_ctp_u_wrpcie_top_u_core4_1_rct |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_rstctl_timer_a |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_rstctl_timer_b |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_rtsel |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_rx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_rxbuf_limit_bypass |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_rxbuf_limit_init |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_rxbuf_pfull_th |
22 |
hssi_ctp_u_wrpcie_top_u_core4_1_scratch_pad0_31_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_sd_cfg |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_sd_dwip |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_shadow_select |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_sim_mode |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_sriov_clk_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_sris_mode |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_sup_mode |
user_mode |
hssi_ctp_u_wrpcie_top_u_core4_1_test_in_high |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_test_in_lo |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_test_in_override |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_tx_cdts_rst |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_tx_fifo_empty_threshold_1 |
3 |
hssi_ctp_u_wrpcie_top_u_core4_1_tx_fifo_empty_threshold_2 |
12 |
hssi_ctp_u_wrpcie_top_u_core4_1_tx_fifo_empty_threshold_3 |
15 |
hssi_ctp_u_wrpcie_top_u_core4_1_tx_fifo_empty_threshold_4 |
2 |
hssi_ctp_u_wrpcie_top_u_core4_1_tx_fifo_full_threshold |
40 |
hssi_ctp_u_wrpcie_top_u_core4_1_tx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_user_mode_del_count |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_vf |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_vf_select |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_drop_vendor0_msg |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_drop_vendor1_msg |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_ep_native |
native |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_gen2_pma_pll_usage |
not_applicable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_hrdrstctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_ip_port_num |
pcie_port0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_link_rate |
gen3 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_link_width |
x16 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_maxpayload_size |
max_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_num_of_lanes |
num_16 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_dlink_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_io_decode |
io32 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_ltr_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_margin_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_pl16g_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_prefetch_decode |
pref64 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf0_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf1_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf2_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf3_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf4_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf5_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf6_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pf7_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_phase23_txpreset |
preset7 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_phase23_txpreset_atg4 |
gen4_preset7 |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_pldclk_rate |
fast |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_rp_ep_mode |
ep |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_tlp_bypass_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_txeq_mode |
eq_disable |
hssi_ctp_u_wrpcie_top_u_core4_1_virtual_uc_calibration_en |
enable |
hssi_ctp_u_wrpcie_top_u_core4_1_vsec_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core4_1_vsec_select |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_wait_pld_warm_rst_rdy |
false |
hssi_ctp_u_wrpcie_top_u_core4_1_wct |
1 |
hssi_ctp_u_wrpcie_top_u_core4_1_wtsel |
0 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_bad_dllp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_bad_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_blk_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_corrected_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf0_table_size |
261 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf1_start_addr |
320 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf1_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf2_start_addr |
512 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf2_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf3_start_addr |
704 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf3_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf4_start_addr |
896 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf4_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf5_start_addr |
1088 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf5_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf6_start_addr |
1280 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf6_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf7_start_addr |
1472 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dbi_pf7_table_size |
171 |
hssi_ctp_u_wrpcie_top_u_core8_cfg_dl_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_ecrc_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_fc_protocol_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_mlf_tlp_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_ram_ecc_chk_val |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_ram_ecc_gen_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_rcvr_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_rcvr_overflow_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_replay_number_rollover_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_replay_timer_timeout_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_surprise_down_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cfg_uncor_internal_err_sts_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_clkmod_core_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core8_clrhip_not_rst_sticky |
false |
hssi_ctp_u_wrpcie_top_u_core8_crs_override |
false |
hssi_ctp_u_wrpcie_top_u_core8_crs_override_value |
true |
hssi_ctp_u_wrpcie_top_u_core8_cvp_blocking_dis |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_data_compressed |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_data_encrypted |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_hard_reset_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_hip_clk_sel_default |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_intf_reset_ctl |
2 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_irq_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_jtag0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_jtag1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_jtag2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_jtag3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_mode_default |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_mode_gating_dis |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_update_no_reset |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_user_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_vsec_id |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_vsec_rev |
0 |
hssi_ctp_u_wrpcie_top_u_core8_cvp_warm_rst_ready_force_bit0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_cvp_warm_rst_ready_force_bit1 |
true |
hssi_ctp_u_wrpcie_top_u_core8_cvp_warm_rst_req_ena |
disable |
hssi_ctp_u_wrpcie_top_u_core8_cvp_write_mask_ctl |
3 |
hssi_ctp_u_wrpcie_top_u_core8_dbi_ro_wr_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_device_type |
dev_nep |
hssi_ctp_u_wrpcie_top_u_core8_device_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_disable_ct_ur |
false |
hssi_ctp_u_wrpcie_top_u_core8_disable_msg_ur |
false |
hssi_ctp_u_wrpcie_top_u_core8_disable_ur_nf |
false |
hssi_ctp_u_wrpcie_top_u_core8_ecrc_strip |
true |
hssi_ctp_u_wrpcie_top_u_core8_en_gpio_perst |
false |
hssi_ctp_u_wrpcie_top_u_core8_enable_poison_nf |
false |
hssi_ctp_u_wrpcie_top_u_core8_ep_signal_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_err_tlp_bypass |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acs_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_acscap_enable_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf0 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf1 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf2 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf3 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf4 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf5 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf6 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_aricap_nxtptr_pf7 |
624 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_globalinvalidate_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_invalidateqdepth_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf0 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf1 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf2 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf3 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf4 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf5 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf6 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_nxtptr_pf7 |
780 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_ats_pagealignreq_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_atscap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_nxtptr_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msix_tablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixpba_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_bir_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_msixtable_offset_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf0 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf1 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf2 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf3 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf4 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf5 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf6 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_pciecap_nxtptr_pf7 |
176 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_revisionid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_subsysid_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_devspecificmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_exttphrequester_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf3 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf5 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_intvecmode_pf7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf0 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf1 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf2 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf3 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf4 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf5 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf6 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_nxtptr_pf7 |
764 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablelocation_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tph_sttablesize_pf7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_tphcap_enable |
255 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf0 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf1 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf2 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf3 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf4 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf5 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf6 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_exvf_type0cap_nxtptr_pf7 |
112 |
hssi_ctp_u_wrpcie_top_u_core8_func_mode |
disable |
hssi_ctp_u_wrpcie_top_u_core8_gate_clk_in_reset_dis |
false |
hssi_ctp_u_wrpcie_top_u_core8_gate_radm_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core8_gpio_irq |
0 |
hssi_ctp_u_wrpcie_top_u_core8_intel_marker |
0 |
hssi_ctp_u_wrpcie_top_u_core8_irq_misc_ctrl |
0 |
hssi_ctp_u_wrpcie_top_u_core8_kp |
3 |
hssi_ctp_u_wrpcie_top_u_core8_margining_ready |
false |
hssi_ctp_u_wrpcie_top_u_core8_margining_software_ready |
false |
hssi_ctp_u_wrpcie_top_u_core8_nonsriov_mode |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ack_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_cap_hdr_reg_addr_byte2 |
726 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_cap_hdr_reg_addr_byte3 |
727 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_capalities_ctrl_reg_byte0 |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_capalities_ctrl_reg_byte1 |
729 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_adv_err_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
258 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
259 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aer_cap_root_err_status_off_addr_byte0 |
304 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_cap_ari_base_addr_byte2 |
378 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_cap_ari_base_addr_byte3 |
379 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_cap_cap_reg_addr_byte0 |
380 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ats_cap_ats_cap_hdr_reg_addr_byte2 |
766 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ats_cap_ats_cap_hdr_reg_addr_byte3 |
767 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
768 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_auto_eq_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_auto_eq_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_auto_lane_flip_ctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aux_clk_freq |
10 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aux_clk_freq_off_rsvdp_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar0_mem_io |
pf0_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar0_type |
pf0_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar1_mem_io |
pf0_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar1_type |
pf0_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar2_mem_io |
pf0_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar2_type |
pf0_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar3_mem_io |
pf0_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar3_type |
pf0_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar4_mem_io |
pf0_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar4_type |
pf0_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar5_mem_io |
pf0_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_bar5_type |
pf0_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_common_clk_n_fts |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_config_limit |
1023 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_config_phy_tx_change |
pf0_full_swing |
hssi_ctp_u_wrpcie_top_u_core8_pf0_config_tx_comp_rx |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_cross_link_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_cross_link_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_d1_support |
pf0_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf0_d2_support |
pf0_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_67 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_68 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_direct_speed_change |
pf0_auto_speed_chg |
hssi_ctp_u_wrpcie_top_u_core8_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_disable_fc_wd_timer |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_disable_scrambler_gen_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_disable_scrambler_gen_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte2 |
1082 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dlink_cap_dlink_fea_ext_hdr_off_addr_byte3 |
1083 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dlink_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dlink_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dll_link_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsi |
pf0_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_dsp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_eidle_timer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_eq_eieos_cnt |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_eq_eieos_cnt_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_eq_phase_2_3 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_eq_phase_2_3_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_eq_redo |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_eq_redo_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_fast_link_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_fast_training_seq |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen1_ei_inference |
pf0_use_rx_eidle |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen2_ctrl_off_rsvdp_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_dc_balance_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_dc_balance_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_dllp_xmt_delay_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_dllp_xmt_delay_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_control_off_rsvdp_27_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_control_off_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_control_off_rsvdp_7_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_eval_2ms_disable |
pf0_abort |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_eval_2ms_disable_atg4 |
pf0_abort_atg4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fb_mode |
pf0_dir_chg |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fb_mode_atg4 |
pf0_dir_chg_atg4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fb_mode_dir_change_off_rsvdp_18_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_max_post_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_max_post_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_max_pre_cusror_delta |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_max_pre_cusror_delta_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_n_evals |
4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_n_evals_atg4 |
4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_t_min_phase23 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fmdc_t_min_phase23_atg4 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fom_inc_initial_eval |
pf0_ignore_init_fom |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_fom_inc_initial_eval_atg4 |
pf0_ignore_init_fom_atg4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_invreq_eva_diff_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_invreq_eva_diff_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_phase23_exit_mode |
pf0_next_rec_speed |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_phase23_exit_mode_atg4 |
pf0_next_rec_speed_atg4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_pset_req_as_coef |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_pset_req_as_coef_atg4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_pset_req_vec |
128 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_eq_pset_req_vec_atg4 |
128 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_equalization_disable |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_equalization_disable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_lower_rate_eq_redo_enable |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_lower_rate_eq_redo_enable_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_14_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_19_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_1_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_related_off_rsvdp_26_atg4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_req_send_consec_eieos_for_pset_map |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_req_send_consec_eieos_for_pset_map_atg4 |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_zrxdc_noncompl |
pf0_non_compliant |
hssi_ctp_u_wrpcie_top_u_core8_pf0_gen3_zrxdc_noncompl_atg4 |
pf0_non_compliant_atg4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_int_pin |
pf0_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf0_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control01_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control01_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control01_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control01_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1011_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1011_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1011_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1011_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1213_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1213_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1213_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1213_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1415_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1415_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1415_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control1415_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control23_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control23_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control23_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control23_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control45_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control45_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control45_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control45_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control67_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control67_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control67_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control67_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control89_reg_rsvdp_15 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control89_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control89_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_lane_equalization_control89_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_capable |
pf0_conn_x1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_link_num |
4 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_loopback_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte2 |
810 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ltr_cap_ltr_cap_hdr_reg_addr_byte3 |
811 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ltr_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ltr_next_offset |
816 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte2 |
490 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_margin_cap_margin_ext_cap_hdr_reg_addr_byte3 |
491 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_margin_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_margin_next_offset |
780 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_mask_radm_1 |
8200 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_mask_radm_2 |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_max_func_num |
pf0_one_function |
hssi_ctp_u_wrpcie_top_u_core8_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_misc_control_1_rsvdp_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
81 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
82 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
83 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_pba_offset_reg_addr_byte0 |
184 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_pba_offset_reg_addr_byte1 |
185 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_pba_offset_reg_addr_byte2 |
186 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_pba_offset_reg_addr_byte3 |
187 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_table_offset_reg_addr_byte0 |
180 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_table_offset_reg_addr_byte1 |
181 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_table_offset_reg_addr_byte2 |
182 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_msix_table_offset_reg_addr_byte3 |
183 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
177 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
178 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
179 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2097330 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2097331 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_no_soft_rst |
pf0_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf0_num_of_lanes |
16 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_p2p_err_rpt_ctrl |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_p2p_track_cpl_to_reg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
820 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
821 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
818 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
819 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_multiple_msg_cap |
pf0_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_active_state_link_pm_control |
pf0_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_active_state_link_pm_support |
pf0_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_attention_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_attention_indicator_button |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_clock_power_man |
pf0_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_crs_sw_visibility |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_device_capabilities_reg_addr_byte0 |
116 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_device_capabilities_reg_addr_byte1 |
117 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_device_capabilities_reg_addr_byte3 |
119 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_device_control_device_status_addr_byte1 |
121 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_electromech_interlock |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_en_clk_power_man |
pf0_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_ext_tag_supp |
pf0_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_flr_cap |
pf0_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_hot_plug_capable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_hot_plug_surprise |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_capabilities_reg_addr_byte0 |
124 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_capabilities_reg_addr_byte1 |
125 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_capabilities_reg_addr_byte2 |
126 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_capabilities_reg_addr_byte3 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4194464 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_control_link_status_reg_addr_byte0 |
4194432 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_control_link_status_reg_addr_byte1 |
4194433 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_control_link_status_reg_addr_byte2 |
4194434 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_max_link_speed |
pf0_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_max_link_width |
pf0_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_max_payload_size |
pf0_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_mrl_sensor |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_no_cmd_cpl_support |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
113 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
115 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_phy_slot_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_power_controller |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_power_indicator |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_rcb |
pf0_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_root_control_root_capabilities_reg_addr_byte2 |
142 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_sel_deemphasis |
pf0_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2097276 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2097277 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_slot_capabilities_reg_addr_byte0 |
132 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_slot_capabilities_reg_addr_byte1 |
133 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_slot_capabilities_reg_addr_byte2 |
134 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_slot_capabilities_reg_addr_byte3 |
135 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_slot_power_limit_scale |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_slot_power_limit_value |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_target_link_speed |
pf0_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pcie_slot_imp |
pf0_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pipe_loopback |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pipe_loopback_control_off_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte0 |
456 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte1 |
457 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte2 |
458 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_20h_reg_addr_byte3 |
458 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte0 |
460 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte1 |
461 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte2 |
462 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_24h_reg_addr_byte3 |
463 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte0 |
464 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte1 |
465 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte2 |
466 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_28h_reg_addr_byte3 |
467 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte0 |
468 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte1 |
469 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte2 |
470 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_cap_off_2ch_reg_addr_byte3 |
471 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte2 |
426 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_pl16g_ext_cap_hdr_reg_addr_byte3 |
427 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pl16g_next_offset |
488 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
65 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
66 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
67 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pm_cap_con_status_reg_addr_byte0 |
68 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_link_ctrl_off_rsvdp_4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte1 |
1805 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_ack_f_aspm_ctrl_off_addr_byte2 |
1806 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_aux_clk_freq_off_addr_byte0 |
2880 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_aux_clk_freq_off_addr_byte1 |
2881 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_filter_mask_2_off_addr_byte0 |
1824 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_filter_mask_2_off_addr_byte1 |
1825 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_filter_mask_2_off_addr_byte2 |
1826 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_filter_mask_2_off_addr_byte3 |
1827 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen2_ctrl_off_addr_byte0 |
2060 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen2_ctrl_off_addr_byte1 |
2061 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen2_ctrl_off_addr_byte2 |
4196366 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte0 |
2216 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte1 |
2217 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte2 |
2218 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_control_off_atg4_addr_byte3 |
2219 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte0 |
2220 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte1 |
2221 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_fb_mode_dir_change_off_atg4_addr_byte2 |
2222 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_eq_local_fs_lf_off_addr_byte1 |
2202 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_atg4_addr_byte0 |
2192 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_atg4_addr_byte1 |
2193 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_atg4_addr_byte2 |
2194 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_gen3_related_off_atg4_addr_byte3 |
2195 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_misc_control_1_off_addr_byte1 |
2237 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_misc_control_1_off_addr_byte2 |
2238 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_pipe_loopback_control_off_addr_byte3 |
2235 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_port_force_off_addr_byte0 |
1800 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_port_link_ctrl_off_addr_byte0 |
1808 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_port_link_ctrl_off_addr_byte2 |
1810 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_queue_status_off_addr_byte2 |
1854 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_queue_status_off_addr_byte3 |
1855 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_symbol_timer_filter_1_off_addr_byte0 |
1820 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_symbol_timer_filter_1_off_addr_byte1 |
1821 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_symbol_timer_filter_1_off_addr_byte2 |
1822 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_symbol_timer_filter_1_off_addr_byte3 |
1823 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_timer_ctrl_max_func_num_off_addr_byte0 |
1816 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte0 |
1872 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte1 |
1873 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte2 |
1874 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_cpl_rx_q_ctrl_off_addr_byte3 |
1875 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte0 |
1868 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte1 |
1869 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_np_rx_q_ctrl_off_addr_byte2 |
1870 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte0 |
1864 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte1 |
1865 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_port_logic_vc0_p_rx_q_ctrl_off_addr_byte2 |
1866 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_pre_det_lane |
pf0_det_all_lanes |
hssi_ctp_u_wrpcie_top_u_core8_pf0_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
738 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
795 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
800 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
801 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
802 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
803 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_queue_status_off_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
769 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
770 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rate_shadow_sel |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rate_shadow_sel_atg4 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved250 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved4 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved8 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_67_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_68_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_reset_assert |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_root_control_root_capabilities_reg_rsvdp_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_root_err_status_off_rsvdp_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rp_exp_rom_bar_mask_reg_rp_rom_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rp_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rp_rom_mask |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rxeq_ph01_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rxeq_ph01_en_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rxeq_rgrdless_rxts |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rxeq_rgrdless_rxts_atg4 |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_rxstatus_value |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_scramble_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sel_deemphasis |
pf0_minus_3db_ctl |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf0_skp_int_val |
640 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_1_addr_byte0 |
364 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_1_addr_byte1 |
365 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_1_addr_byte2 |
366 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_1_addr_byte3 |
367 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_2_addr_byte0 |
368 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_2_addr_byte1 |
369 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_2_addr_byte2 |
370 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_ser_num_reg_dw_2_addr_byte3 |
371 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_sn_base_addr_byte2 |
362 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_sn_base_addr_byte3 |
363 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte0 |
404 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte1 |
405 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte2 |
406 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control01_reg_addr_byte3 |
407 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte0 |
424 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte1 |
425 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte2 |
426 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1011_reg_addr_byte3 |
427 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte0 |
428 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte1 |
429 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte2 |
430 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1213_reg_addr_byte3 |
431 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte0 |
432 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte1 |
433 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte2 |
434 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control1415_reg_addr_byte3 |
435 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte0 |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte1 |
409 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte2 |
410 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control23_reg_addr_byte3 |
411 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte0 |
412 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte1 |
413 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte2 |
414 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control45_reg_addr_byte3 |
415 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte0 |
416 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte1 |
417 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte2 |
418 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control67_reg_addr_byte3 |
419 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte0 |
420 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte1 |
421 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte2 |
422 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_lane_equalization_control89_reg_addr_byte3 |
423 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_spcie_cap_header_reg_addr_byte2 |
394 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_spcie_cap_header_reg_addr_byte3 |
395 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_spcie_next_offset |
456 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2097724 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2097725 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2097732 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2097733 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2097734 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2097735 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2097748 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2097749 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2097750 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2097751 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2097753 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2097754 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2097755 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2097756 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2097757 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2097758 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2097759 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2097761 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2097762 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2097763 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2097764 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2097765 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2097766 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2097767 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2097769 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2097770 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2097771 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2097752 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2097760 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2097768 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_base_reg_addr_byte2 |
562 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_base_reg_addr_byte3 |
563 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_initial_vfs_addr_byte0 |
572 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_initial_vfs_addr_byte1 |
573 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_vf_offset_position_addr_byte0 |
580 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_vf_offset_position_addr_byte1 |
581 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_vf_offset_position_addr_byte2 |
582 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sriov_vf_offset_position_addr_byte3 |
583 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sup_page_sizes_reg_addr_byte0 |
588 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sup_page_sizes_reg_addr_byte1 |
589 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sup_page_sizes_reg_addr_byte2 |
590 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_sup_page_sizes_reg_addr_byte3 |
591 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_bar0_reg_addr_byte0 |
596 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_bar1_reg_addr_byte0 |
600 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_bar2_reg_addr_byte0 |
604 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_bar3_reg_addr_byte0 |
608 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_bar4_reg_addr_byte0 |
612 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_bar5_reg_addr_byte0 |
616 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_device_id_reg_addr_byte2 |
586 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_cap_vf_device_id_reg_addr_byte3 |
587 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar0_type |
pf0_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar1_type |
pf0_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar2_type |
pf0_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar3_type |
pf0_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar4_type |
pf0_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_bar5_type |
pf0_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_offset_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_target_above_config_limit |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_timer_mod_flow_control |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_timer_mod_flow_control_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
570 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
571 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_addr_byte0 |
572 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_addr_byte1 |
573 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_addr_byte2 |
574 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_addr_byte3 |
575 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2097724 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2097725 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2097726 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2097727 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_st_table_loc_0 |
pf0_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf0_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_st_table_loc_1 |
pf0_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf0_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar0_mask_reg_addr_byte0 |
2097168 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar0_mask_reg_addr_byte1 |
2097169 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar0_mask_reg_addr_byte2 |
2097170 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar0_mask_reg_addr_byte3 |
2097171 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar0_reg_addr_byte0 |
16 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar1_enable_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar1_mask_reg_addr_byte0 |
2097172 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar1_mask_reg_addr_byte1 |
2097173 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar1_mask_reg_addr_byte2 |
2097174 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar1_mask_reg_addr_byte3 |
2097175 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar1_reg_addr_byte0 |
20 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar2_mask_reg_addr_byte0 |
2097176 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar2_mask_reg_addr_byte1 |
2097177 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar2_mask_reg_addr_byte2 |
2097178 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar2_mask_reg_addr_byte3 |
2097179 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar2_reg_addr_byte0 |
24 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar3_enable_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar3_mask_reg_addr_byte0 |
2097180 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar3_mask_reg_addr_byte1 |
2097181 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar3_mask_reg_addr_byte2 |
2097182 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar3_mask_reg_addr_byte3 |
2097183 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar3_reg_addr_byte0 |
28 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar4_mask_reg_addr_byte0 |
2097184 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar4_mask_reg_addr_byte1 |
2097185 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar4_mask_reg_addr_byte2 |
2097186 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar4_mask_reg_addr_byte3 |
2097187 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar4_reg_addr_byte0 |
32 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar5_enable_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar5_mask_reg_addr_byte0 |
2097188 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar5_mask_reg_addr_byte1 |
2097189 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar5_mask_reg_addr_byte2 |
2097190 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar5_mask_reg_addr_byte3 |
2097191 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bar5_reg_addr_byte0 |
36 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
14 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
40 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
41 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
42 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
43 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_class_code_revision_id_addr_byte0 |
8 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_class_code_revision_id_addr_byte1 |
9 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_class_code_revision_id_addr_byte2 |
10 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_class_code_revision_id_addr_byte3 |
11 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2097200 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2097201 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2097202 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2097203 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
48 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
61 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
52 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte0 |
2097208 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte1 |
2097209 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte2 |
2097210 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_rp_exp_rom_bar_mask_reg_addr_byte3 |
2097211 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
44 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
45 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
46 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
47 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset0 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_16g_tx_preset9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint0 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint1 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint10 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint11 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint12 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint13 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint14 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint15 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint3 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint4 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint5 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint6 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint7 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint8 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_rx_preset_hint9 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_send_8gt_eq_ts2_disable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_send_8gt_eq_ts2_disable_atg4 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset0 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset1 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset10 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset11 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset12 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset13 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset14 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset15 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset2 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset3 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset4 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset5 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset6 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset7 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset8 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_usp_tx_preset9 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_cpl_data_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_cpl_data_scale |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_cpl_hdr_scale |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_cpl_header_credit |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_cpl_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_np_data_credit |
230 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_np_header_credit |
115 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_np_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_p_data_credit |
750 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_p_header_credit |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc0_p_tlp_q_mode |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc_cap_vc_base_addr_byte2 |
330 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc_cap_vc_base_addr_byte3 |
331 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vc_next_offset |
360 |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vendor_specific_dllp_req |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf0_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_cap_hdr_reg_addr_byte2 |
4822 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_cap_hdr_reg_addr_byte3 |
4823 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_capalities_ctrl_reg_byte0 |
4824 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_capalities_ctrl_reg_byte1 |
4825 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ari_cap_cap_reg_addr_byte0 |
4476 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ats_cap_ats_cap_hdr_reg_addr_byte2 |
4862 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ats_cap_ats_cap_hdr_reg_addr_byte3 |
4863 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
4864 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar0_mem_io |
pf1_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar0_type |
pf1_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar1_mem_io |
pf1_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar1_type |
pf1_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar2_mem_io |
pf1_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar2_type |
pf1_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar3_mem_io |
pf1_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar3_type |
pf1_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar4_mem_io |
pf1_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar4_type |
pf1_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar5_mem_io |
pf1_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_bar5_type |
pf1_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_d1_support |
pf1_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf1_d2_support |
pf1_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_dsi |
pf1_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf1_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_int_pin |
pf1_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf1_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
4177 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
4178 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
4179 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_pba_offset_reg_addr_byte0 |
4280 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_pba_offset_reg_addr_byte1 |
4281 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_pba_offset_reg_addr_byte2 |
4282 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_pba_offset_reg_addr_byte3 |
4283 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_table_offset_reg_addr_byte0 |
4276 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_table_offset_reg_addr_byte1 |
4277 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_table_offset_reg_addr_byte2 |
4278 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_msix_table_offset_reg_addr_byte3 |
4279 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
4273 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
4274 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
4275 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_no_soft_rst |
pf1_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf1_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
4916 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
4917 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
4914 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
4915 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_multiple_msg_cap |
pf1_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_active_state_link_pm_control |
pf1_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_active_state_link_pm_support |
pf1_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_clock_power_man |
pf1_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_device_capabilities_reg_addr_byte0 |
4212 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_device_capabilities_reg_addr_byte1 |
4213 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_device_capabilities_reg_addr_byte3 |
4215 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_en_clk_power_man |
pf1_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_ext_tag_supp |
pf1_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_flr_cap |
pf1_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_capabilities_reg_addr_byte0 |
4220 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_capabilities_reg_addr_byte1 |
4221 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_capabilities_reg_addr_byte2 |
4222 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_capabilities_reg_addr_byte3 |
4223 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4198560 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_control_link_status_reg_addr_byte0 |
4198528 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_control_link_status_reg_addr_byte1 |
4198529 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_control_link_status_reg_addr_byte2 |
4198530 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_max_link_speed |
pf1_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_max_link_width |
pf1_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_max_payload_size |
pf1_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
4209 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
4211 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_rcb |
pf1_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_sel_deemphasis |
pf1_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2101372 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2101373 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_target_link_speed |
pf1_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pcie_slot_imp |
pf1_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
4161 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
4162 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
4163 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pm_cap_con_status_reg_addr_byte0 |
4164 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
4834 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
4891 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
4896 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
4897 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
4898 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
4899 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
4865 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
4866 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2101844 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2101845 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2101846 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2101847 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2101848 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2101849 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2101850 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2101851 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2101852 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2101853 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2101854 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2101855 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2101856 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2101857 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2101858 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2101859 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2101860 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2101861 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2101862 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2101863 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2101864 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2101865 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2101866 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2101867 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2101848 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2101856 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2101864 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_base_reg_addr_byte2 |
4658 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_base_reg_addr_byte3 |
4659 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sup_page_sizes_reg_addr_byte0 |
4684 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sup_page_sizes_reg_addr_byte1 |
4685 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sup_page_sizes_reg_addr_byte2 |
4686 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_sup_page_sizes_reg_addr_byte3 |
4687 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_bar0_reg_addr_byte0 |
4692 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_bar1_reg_addr_byte0 |
4696 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_bar2_reg_addr_byte0 |
4700 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_bar3_reg_addr_byte0 |
4704 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_bar4_reg_addr_byte0 |
4708 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_bar5_reg_addr_byte0 |
4712 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_device_id_reg_addr_byte2 |
4682 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_cap_vf_device_id_reg_addr_byte3 |
4683 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar0_type |
pf1_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar1_type |
pf1_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar2_type |
pf1_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar3_type |
pf1_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar4_type |
pf1_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_bar5_type |
pf1_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
4666 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
4667 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_addr_byte2 |
4670 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_addr_byte3 |
4671 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101822 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101823 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_st_table_loc_0 |
pf1_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf1_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_st_table_loc_1 |
pf1_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf1_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar0_mask_reg_addr_byte0 |
2101264 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar0_mask_reg_addr_byte1 |
2101265 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar0_mask_reg_addr_byte2 |
2101266 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar0_mask_reg_addr_byte3 |
2101267 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar0_reg_addr_byte0 |
4112 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar1_enable_reg_addr_byte0 |
2101268 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar1_mask_reg_addr_byte0 |
2101268 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar1_mask_reg_addr_byte1 |
2101269 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar1_mask_reg_addr_byte2 |
2101270 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar1_mask_reg_addr_byte3 |
2101271 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar1_reg_addr_byte0 |
4116 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar2_mask_reg_addr_byte0 |
2101272 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar2_mask_reg_addr_byte1 |
2101273 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar2_mask_reg_addr_byte2 |
2101274 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar2_mask_reg_addr_byte3 |
2101275 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar2_reg_addr_byte0 |
4120 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar3_enable_reg_addr_byte0 |
2101276 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar3_mask_reg_addr_byte0 |
2101276 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar3_mask_reg_addr_byte1 |
2101277 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar3_mask_reg_addr_byte2 |
2101278 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar3_mask_reg_addr_byte3 |
2101279 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar3_reg_addr_byte0 |
4124 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar4_mask_reg_addr_byte0 |
2101280 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar4_mask_reg_addr_byte1 |
2101281 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar4_mask_reg_addr_byte2 |
2101282 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar4_mask_reg_addr_byte3 |
2101283 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar4_reg_addr_byte0 |
4128 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar5_enable_reg_addr_byte0 |
2101284 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar5_mask_reg_addr_byte0 |
2101284 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar5_mask_reg_addr_byte1 |
2101285 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar5_mask_reg_addr_byte2 |
2101286 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar5_mask_reg_addr_byte3 |
2101287 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bar5_reg_addr_byte0 |
4132 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
4110 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
4136 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
4137 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
4138 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
4139 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
4096 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
4097 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
4098 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
4099 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2101296 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2101297 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2101298 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2101299 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
4144 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
4157 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
4148 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
4140 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
4141 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
4142 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
4143 |
hssi_ctp_u_wrpcie_top_u_core8_pf1_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf1_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_cap_hdr_reg_addr_byte2 |
8918 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_cap_hdr_reg_addr_byte3 |
8919 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_capalities_ctrl_reg_byte0 |
4824 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_capalities_ctrl_reg_byte1 |
4825 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ari_cap_cap_reg_addr_byte0 |
8572 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ats_cap_ats_cap_hdr_reg_addr_byte2 |
8958 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ats_cap_ats_cap_hdr_reg_addr_byte3 |
8959 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
8960 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar0_mem_io |
pf2_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar0_type |
pf2_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar1_mem_io |
pf2_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar1_type |
pf2_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar2_mem_io |
pf2_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar2_type |
pf2_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar3_mem_io |
pf2_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar3_type |
pf2_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar4_mem_io |
pf2_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar4_type |
pf2_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar5_mem_io |
pf2_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_bar5_type |
pf2_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_d1_support |
pf2_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf2_d2_support |
pf2_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_dsi |
pf2_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf2_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_int_pin |
pf2_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf2_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
8273 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
8274 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
8275 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_pba_offset_reg_addr_byte0 |
8376 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_pba_offset_reg_addr_byte1 |
8377 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_pba_offset_reg_addr_byte2 |
8378 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_pba_offset_reg_addr_byte3 |
8379 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_table_offset_reg_addr_byte0 |
8372 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_table_offset_reg_addr_byte1 |
8373 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_table_offset_reg_addr_byte2 |
8374 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_msix_table_offset_reg_addr_byte3 |
8375 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
8369 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
8370 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
8371 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_no_soft_rst |
pf2_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf2_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
9012 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
9013 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
9010 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
9011 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_multiple_msg_cap |
pf2_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_active_state_link_pm_control |
pf2_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_active_state_link_pm_support |
pf2_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_clock_power_man |
pf2_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_device_capabilities_reg_addr_byte0 |
8308 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_device_capabilities_reg_addr_byte1 |
8309 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_device_capabilities_reg_addr_byte3 |
8311 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_en_clk_power_man |
pf2_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_ext_tag_supp |
pf2_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_flr_cap |
pf2_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_capabilities_reg_addr_byte0 |
8316 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_capabilities_reg_addr_byte1 |
8317 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_capabilities_reg_addr_byte2 |
8318 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_capabilities_reg_addr_byte3 |
8319 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4202656 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_control_link_status_reg_addr_byte0 |
4202624 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_control_link_status_reg_addr_byte1 |
4202625 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_control_link_status_reg_addr_byte2 |
4202626 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_max_link_speed |
pf2_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_max_link_width |
pf2_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_max_payload_size |
pf2_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
8305 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
8307 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_rcb |
pf2_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_sel_deemphasis |
pf2_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2105468 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2105469 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_target_link_speed |
pf2_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pcie_slot_imp |
pf2_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
8257 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
8258 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
8259 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pm_cap_con_status_reg_addr_byte0 |
8260 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
8930 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
8987 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
8992 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
8993 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
8994 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
8995 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
8961 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
8962 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2105940 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2105941 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2105942 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2105943 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2105944 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2105945 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2105946 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2105947 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2105948 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2105949 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2105950 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2105951 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2105952 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2105953 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2105954 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2105955 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2105956 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2105957 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2105958 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2105959 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2105960 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2105961 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2105962 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2105963 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2105944 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2105952 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2105960 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_base_reg_addr_byte2 |
8754 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_base_reg_addr_byte3 |
8755 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sup_page_sizes_reg_addr_byte0 |
8780 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sup_page_sizes_reg_addr_byte1 |
8781 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sup_page_sizes_reg_addr_byte2 |
8782 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_sup_page_sizes_reg_addr_byte3 |
8783 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_bar0_reg_addr_byte0 |
8788 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_bar1_reg_addr_byte0 |
8792 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_bar2_reg_addr_byte0 |
8796 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_bar3_reg_addr_byte0 |
8800 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_bar4_reg_addr_byte0 |
8804 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_bar5_reg_addr_byte0 |
8808 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_device_id_reg_addr_byte2 |
8778 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_cap_vf_device_id_reg_addr_byte3 |
8779 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar0_type |
pf2_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar1_type |
pf2_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar2_type |
pf2_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar3_type |
pf2_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar4_type |
pf2_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_bar5_type |
pf2_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
8762 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
8763 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_addr_byte0 |
8764 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_addr_byte1 |
8765 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_addr_byte2 |
8766 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_addr_byte3 |
8767 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101822 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101823 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_st_table_loc_0 |
pf2_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf2_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_st_table_loc_1 |
pf2_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf2_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar0_mask_reg_addr_byte0 |
2105360 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar0_mask_reg_addr_byte1 |
2105361 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar0_mask_reg_addr_byte2 |
2105362 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar0_mask_reg_addr_byte3 |
2105363 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar0_reg_addr_byte0 |
8208 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar1_enable_reg_addr_byte0 |
2105364 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar1_mask_reg_addr_byte0 |
2105364 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar1_mask_reg_addr_byte1 |
2105365 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar1_mask_reg_addr_byte2 |
2105366 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar1_mask_reg_addr_byte3 |
2105367 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar1_reg_addr_byte0 |
8212 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar2_mask_reg_addr_byte0 |
2105368 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar2_mask_reg_addr_byte1 |
2105369 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar2_mask_reg_addr_byte2 |
2105370 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar2_mask_reg_addr_byte3 |
2105371 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar2_reg_addr_byte0 |
8216 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar3_enable_reg_addr_byte0 |
2105372 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar3_mask_reg_addr_byte0 |
2105372 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar3_mask_reg_addr_byte1 |
2105373 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar3_mask_reg_addr_byte2 |
2105374 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar3_mask_reg_addr_byte3 |
2105375 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar3_reg_addr_byte0 |
8220 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar4_mask_reg_addr_byte0 |
2105376 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar4_mask_reg_addr_byte1 |
2105377 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar4_mask_reg_addr_byte2 |
2105378 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar4_mask_reg_addr_byte3 |
2105379 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar4_reg_addr_byte0 |
8224 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar5_enable_reg_addr_byte0 |
2105380 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar5_mask_reg_addr_byte0 |
2105380 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar5_mask_reg_addr_byte1 |
2105381 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar5_mask_reg_addr_byte2 |
2105382 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar5_mask_reg_addr_byte3 |
2105383 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bar5_reg_addr_byte0 |
8228 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
8206 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
8232 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
8233 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
8234 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
8235 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
8192 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
8193 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
8194 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
8195 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2105392 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2105393 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2105394 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2105395 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
8240 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
8253 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
8244 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
8236 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
8237 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
8238 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
8239 |
hssi_ctp_u_wrpcie_top_u_core8_pf2_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf2_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_cap_hdr_reg_addr_byte2 |
13014 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_cap_hdr_reg_addr_byte3 |
13015 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_capalities_ctrl_reg_byte0 |
4824 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_capalities_ctrl_reg_byte1 |
4825 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ari_cap_cap_reg_addr_byte0 |
12668 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ats_cap_ats_cap_hdr_reg_addr_byte2 |
13054 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ats_cap_ats_cap_hdr_reg_addr_byte3 |
13055 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
13056 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar0_mem_io |
pf3_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar0_type |
pf3_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar1_mem_io |
pf3_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar1_type |
pf3_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar2_mem_io |
pf3_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar2_type |
pf3_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar3_mem_io |
pf3_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar3_type |
pf3_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar4_mem_io |
pf3_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar4_type |
pf3_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar5_mem_io |
pf3_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_bar5_type |
pf3_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_d1_support |
pf3_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf3_d2_support |
pf3_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_dsi |
pf3_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf3_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_int_pin |
pf3_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf3_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
12369 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
12370 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
12371 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_pba_offset_reg_addr_byte0 |
12472 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_pba_offset_reg_addr_byte1 |
12473 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_pba_offset_reg_addr_byte2 |
12474 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_pba_offset_reg_addr_byte3 |
12475 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_table_offset_reg_addr_byte0 |
12468 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_table_offset_reg_addr_byte1 |
12469 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_table_offset_reg_addr_byte2 |
12470 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_msix_table_offset_reg_addr_byte3 |
12471 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
12465 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
12466 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
12467 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_no_soft_rst |
pf3_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf3_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
13108 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
13109 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
13106 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
13107 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_multiple_msg_cap |
pf3_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_active_state_link_pm_control |
pf3_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_active_state_link_pm_support |
pf3_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_clock_power_man |
pf3_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_device_capabilities_reg_addr_byte0 |
12404 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_device_capabilities_reg_addr_byte1 |
12405 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_device_capabilities_reg_addr_byte3 |
12407 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_en_clk_power_man |
pf3_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_ext_tag_supp |
pf3_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_flr_cap |
pf3_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_capabilities_reg_addr_byte0 |
12412 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_capabilities_reg_addr_byte1 |
12413 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_capabilities_reg_addr_byte2 |
12414 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_capabilities_reg_addr_byte3 |
12415 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4206752 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_control_link_status_reg_addr_byte0 |
4206720 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_control_link_status_reg_addr_byte1 |
4206721 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_control_link_status_reg_addr_byte2 |
4206722 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_max_link_speed |
pf3_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_max_link_width |
pf3_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_max_payload_size |
pf3_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
12401 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
12403 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_rcb |
pf3_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_sel_deemphasis |
pf3_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2109564 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2109565 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_target_link_speed |
pf3_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pcie_slot_imp |
pf3_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
12353 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
12354 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
12355 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pm_cap_con_status_reg_addr_byte0 |
12356 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
13026 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
13083 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
13088 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
13089 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
13090 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
13091 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
13057 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
13058 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2110036 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2110037 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2110038 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2110039 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2110040 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2110041 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2110042 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2110043 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2110044 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2110045 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2110046 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2110047 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2110048 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2110049 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2110050 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2110051 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2110052 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2110053 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2110054 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2110055 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2110056 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2110057 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2110058 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2110059 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2110040 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2110048 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2110056 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_base_reg_addr_byte2 |
12850 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_base_reg_addr_byte3 |
12851 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sup_page_sizes_reg_addr_byte0 |
12876 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sup_page_sizes_reg_addr_byte1 |
12877 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sup_page_sizes_reg_addr_byte2 |
12878 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_sup_page_sizes_reg_addr_byte3 |
12879 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_bar0_reg_addr_byte0 |
12884 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_bar1_reg_addr_byte0 |
12888 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_bar2_reg_addr_byte0 |
12892 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_bar3_reg_addr_byte0 |
12896 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_bar4_reg_addr_byte0 |
12900 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_bar5_reg_addr_byte0 |
12904 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_device_id_reg_addr_byte2 |
12874 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_cap_vf_device_id_reg_addr_byte3 |
12875 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar0_type |
pf3_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar1_type |
pf3_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar2_type |
pf3_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar3_type |
pf3_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar4_type |
pf3_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_bar5_type |
pf3_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
12858 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
12859 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_addr_byte0 |
12860 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_addr_byte1 |
12861 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_addr_byte2 |
12862 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_addr_byte3 |
12863 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101822 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101823 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_st_table_loc_0 |
pf3_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf3_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_st_table_loc_1 |
pf3_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf3_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar0_mask_reg_addr_byte0 |
2109456 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar0_mask_reg_addr_byte1 |
2109457 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar0_mask_reg_addr_byte2 |
2109458 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar0_mask_reg_addr_byte3 |
2109459 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar0_reg_addr_byte0 |
12304 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar1_enable_reg_addr_byte0 |
2109460 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar1_mask_reg_addr_byte0 |
2109460 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar1_mask_reg_addr_byte1 |
2109461 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar1_mask_reg_addr_byte2 |
2109462 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar1_mask_reg_addr_byte3 |
2109463 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar1_reg_addr_byte0 |
12308 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar2_mask_reg_addr_byte0 |
2109464 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar2_mask_reg_addr_byte1 |
2109465 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar2_mask_reg_addr_byte2 |
2109466 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar2_mask_reg_addr_byte3 |
2109467 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar2_reg_addr_byte0 |
12312 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar3_enable_reg_addr_byte0 |
2109468 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar3_mask_reg_addr_byte0 |
2109468 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar3_mask_reg_addr_byte1 |
2109469 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar3_mask_reg_addr_byte2 |
2109470 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar3_mask_reg_addr_byte3 |
2109471 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar3_reg_addr_byte0 |
12316 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar4_mask_reg_addr_byte0 |
2109472 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar4_mask_reg_addr_byte1 |
2109473 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar4_mask_reg_addr_byte2 |
2109474 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar4_mask_reg_addr_byte3 |
2109475 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar4_reg_addr_byte0 |
12320 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar5_enable_reg_addr_byte0 |
2109476 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar5_mask_reg_addr_byte0 |
2109476 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar5_mask_reg_addr_byte1 |
2109477 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar5_mask_reg_addr_byte2 |
2109478 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar5_mask_reg_addr_byte3 |
2109479 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bar5_reg_addr_byte0 |
12324 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
12302 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
12328 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
12329 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
12330 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
12331 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
12288 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
12289 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
12290 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
12291 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2109488 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2109489 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2109490 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2109491 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
12336 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
12349 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
12340 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
12332 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
12333 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
12334 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
12335 |
hssi_ctp_u_wrpcie_top_u_core8_pf3_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf3_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_cap_hdr_reg_addr_byte2 |
17110 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_cap_hdr_reg_addr_byte3 |
17111 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_capalities_ctrl_reg_byte0 |
4824 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_capalities_ctrl_reg_byte1 |
4825 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ari_cap_cap_reg_addr_byte0 |
16764 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ats_cap_ats_cap_hdr_reg_addr_byte2 |
17150 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ats_cap_ats_cap_hdr_reg_addr_byte3 |
17151 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
17152 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar0_mem_io |
pf4_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar0_type |
pf4_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar1_mem_io |
pf4_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar1_type |
pf4_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar2_mem_io |
pf4_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar2_type |
pf4_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar3_mem_io |
pf4_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar3_type |
pf4_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar4_mem_io |
pf4_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar4_type |
pf4_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar5_mem_io |
pf4_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_bar5_type |
pf4_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_d1_support |
pf4_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf4_d2_support |
pf4_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_dsi |
pf4_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf4_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_int_pin |
pf4_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf4_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
16465 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
16466 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
16467 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_pba_offset_reg_addr_byte0 |
16568 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_pba_offset_reg_addr_byte1 |
16569 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_pba_offset_reg_addr_byte2 |
16570 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_pba_offset_reg_addr_byte3 |
16571 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_table_offset_reg_addr_byte0 |
16564 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_table_offset_reg_addr_byte1 |
16565 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_table_offset_reg_addr_byte2 |
16566 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_msix_table_offset_reg_addr_byte3 |
16567 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
16561 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
16562 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
16563 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_no_soft_rst |
pf4_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf4_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
17204 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
17205 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
17202 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
17203 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_multiple_msg_cap |
pf4_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_active_state_link_pm_control |
pf4_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_active_state_link_pm_support |
pf4_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_clock_power_man |
pf4_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_device_capabilities_reg_addr_byte0 |
16500 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_device_capabilities_reg_addr_byte1 |
16501 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_device_capabilities_reg_addr_byte3 |
16503 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_en_clk_power_man |
pf4_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_ext_tag_supp |
pf4_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_flr_cap |
pf4_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_capabilities_reg_addr_byte0 |
16508 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_capabilities_reg_addr_byte1 |
16509 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_capabilities_reg_addr_byte2 |
16510 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_capabilities_reg_addr_byte3 |
16511 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4210848 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_control_link_status_reg_addr_byte0 |
4210816 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_control_link_status_reg_addr_byte1 |
4210817 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_control_link_status_reg_addr_byte2 |
4210818 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_max_link_speed |
pf4_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_max_link_width |
pf4_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_max_payload_size |
pf4_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
16497 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
16499 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_rcb |
pf4_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_sel_deemphasis |
pf4_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2113660 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2113661 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_target_link_speed |
pf4_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pcie_slot_imp |
pf4_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
16449 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
16450 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
16451 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pm_cap_con_status_reg_addr_byte0 |
16452 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
17122 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
17179 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
17184 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
17185 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
17186 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
17187 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
17153 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
17154 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2114132 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2114133 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2114134 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2114135 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2114136 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2114137 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2114138 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2114139 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2114140 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2114141 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2114142 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2114143 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2114144 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2114145 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2114146 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2114147 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2114148 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2114149 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2114150 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2114151 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2114152 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2114153 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2114154 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2114155 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2114136 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2114144 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2114152 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_base_reg_addr_byte2 |
16946 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_base_reg_addr_byte3 |
16947 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sup_page_sizes_reg_addr_byte0 |
16972 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sup_page_sizes_reg_addr_byte1 |
16973 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sup_page_sizes_reg_addr_byte2 |
16974 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_sup_page_sizes_reg_addr_byte3 |
16975 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_bar0_reg_addr_byte0 |
16980 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_bar1_reg_addr_byte0 |
16984 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_bar2_reg_addr_byte0 |
16988 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_bar3_reg_addr_byte0 |
16992 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_bar4_reg_addr_byte0 |
16996 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_bar5_reg_addr_byte0 |
17000 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_device_id_reg_addr_byte2 |
16970 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_cap_vf_device_id_reg_addr_byte3 |
16971 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar0_type |
pf4_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar1_type |
pf4_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar2_type |
pf4_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar3_type |
pf4_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar4_type |
pf4_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_bar5_type |
pf4_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
16954 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
16955 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_addr_byte0 |
16956 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_addr_byte1 |
16957 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_addr_byte2 |
16958 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_addr_byte3 |
16959 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101822 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101823 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_st_table_loc_0 |
pf4_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf4_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_st_table_loc_1 |
pf4_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf4_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar0_mask_reg_addr_byte0 |
2113552 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar0_mask_reg_addr_byte1 |
2113553 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar0_mask_reg_addr_byte2 |
2113554 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar0_mask_reg_addr_byte3 |
2113555 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar0_reg_addr_byte0 |
16400 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar1_enable_reg_addr_byte0 |
2113556 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar1_mask_reg_addr_byte0 |
2113556 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar1_mask_reg_addr_byte1 |
2113557 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar1_mask_reg_addr_byte2 |
2113558 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar1_mask_reg_addr_byte3 |
2113559 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar1_reg_addr_byte0 |
16404 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar2_mask_reg_addr_byte0 |
2113560 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar2_mask_reg_addr_byte1 |
2113561 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar2_mask_reg_addr_byte2 |
2113562 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar2_mask_reg_addr_byte3 |
2113563 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar2_reg_addr_byte0 |
16408 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar3_enable_reg_addr_byte0 |
2113564 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar3_mask_reg_addr_byte0 |
2113564 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar3_mask_reg_addr_byte1 |
2113565 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar3_mask_reg_addr_byte2 |
2113566 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar3_mask_reg_addr_byte3 |
2113567 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar3_reg_addr_byte0 |
16412 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar4_mask_reg_addr_byte0 |
2113568 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar4_mask_reg_addr_byte1 |
2113569 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar4_mask_reg_addr_byte2 |
2113570 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar4_mask_reg_addr_byte3 |
2113571 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar4_reg_addr_byte0 |
16416 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar5_enable_reg_addr_byte0 |
2113572 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar5_mask_reg_addr_byte0 |
2113572 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar5_mask_reg_addr_byte1 |
2113573 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar5_mask_reg_addr_byte2 |
2113574 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar5_mask_reg_addr_byte3 |
2113575 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bar5_reg_addr_byte0 |
16420 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
16398 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
16424 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
16425 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
16426 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
16427 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
16384 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
16385 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
16386 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
16387 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2113584 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2113585 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2113586 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2113587 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
16432 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
16445 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
16436 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
16428 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
16429 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
16430 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
16431 |
hssi_ctp_u_wrpcie_top_u_core8_pf4_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf4_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_cap_hdr_reg_addr_byte2 |
21206 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_cap_hdr_reg_addr_byte3 |
21207 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_capalities_ctrl_reg_byte0 |
4824 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_capalities_ctrl_reg_byte1 |
4825 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ari_cap_cap_reg_addr_byte0 |
20860 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ats_cap_ats_cap_hdr_reg_addr_byte2 |
21246 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ats_cap_ats_cap_hdr_reg_addr_byte3 |
21247 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
21248 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar0_mem_io |
pf5_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar0_type |
pf5_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar1_mem_io |
pf5_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar1_type |
pf5_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar2_mem_io |
pf5_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar2_type |
pf5_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar3_mem_io |
pf5_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar3_type |
pf5_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar4_mem_io |
pf5_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar4_type |
pf5_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar5_mem_io |
pf5_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_bar5_type |
pf5_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_d1_support |
pf5_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf5_d2_support |
pf5_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_dsi |
pf5_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf5_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_int_pin |
pf5_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf5_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
20561 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
20562 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
20563 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_pba_offset_reg_addr_byte0 |
20664 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_pba_offset_reg_addr_byte1 |
20665 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_pba_offset_reg_addr_byte2 |
20666 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_pba_offset_reg_addr_byte3 |
20667 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_table_offset_reg_addr_byte0 |
20660 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_table_offset_reg_addr_byte1 |
20661 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_table_offset_reg_addr_byte2 |
20662 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_msix_table_offset_reg_addr_byte3 |
20663 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
20657 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
20658 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
20659 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_no_soft_rst |
pf5_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf5_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
21300 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
21301 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
21298 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
21299 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_multiple_msg_cap |
pf5_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_active_state_link_pm_control |
pf5_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_active_state_link_pm_support |
pf5_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_clock_power_man |
pf5_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_device_capabilities_reg_addr_byte0 |
20596 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_device_capabilities_reg_addr_byte1 |
20597 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_device_capabilities_reg_addr_byte3 |
20599 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_en_clk_power_man |
pf5_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_ext_tag_supp |
pf5_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_flr_cap |
pf5_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_capabilities_reg_addr_byte0 |
20604 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_capabilities_reg_addr_byte1 |
20605 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_capabilities_reg_addr_byte2 |
20606 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_capabilities_reg_addr_byte3 |
20607 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4214944 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_control_link_status_reg_addr_byte0 |
4214912 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_control_link_status_reg_addr_byte1 |
4214913 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_control_link_status_reg_addr_byte2 |
4214914 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_max_link_speed |
pf5_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_max_link_width |
pf5_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_max_payload_size |
pf5_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
20593 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
20595 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_rcb |
pf5_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_sel_deemphasis |
pf5_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2117756 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2117757 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_target_link_speed |
pf5_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pcie_slot_imp |
pf5_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
20545 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
20546 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
20547 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pm_cap_con_status_reg_addr_byte0 |
20548 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
21218 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
21275 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
21280 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
21281 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
21282 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
21283 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
21249 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
21250 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2118228 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2118229 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2118230 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2118231 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2118232 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2118233 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2118234 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2118235 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2118236 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2118237 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2118238 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2118239 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2118240 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2118241 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2118242 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2118243 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2118244 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2118245 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2118246 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2118247 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2118248 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2118249 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2118250 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2118251 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2118232 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2118240 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2118248 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_base_reg_addr_byte2 |
21042 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_base_reg_addr_byte3 |
21043 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sup_page_sizes_reg_addr_byte0 |
21068 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sup_page_sizes_reg_addr_byte1 |
21069 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sup_page_sizes_reg_addr_byte2 |
21070 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_sup_page_sizes_reg_addr_byte3 |
21071 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_bar0_reg_addr_byte0 |
21076 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_bar1_reg_addr_byte0 |
21080 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_bar2_reg_addr_byte0 |
21084 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_bar3_reg_addr_byte0 |
21088 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_bar4_reg_addr_byte0 |
21092 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_bar5_reg_addr_byte0 |
21096 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_device_id_reg_addr_byte2 |
21066 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_cap_vf_device_id_reg_addr_byte3 |
21067 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar0_type |
pf5_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar1_type |
pf5_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar2_type |
pf5_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar3_type |
pf5_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar4_type |
pf5_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_bar5_type |
pf5_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
21050 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
21051 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_addr_byte0 |
21052 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_addr_byte1 |
21053 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_addr_byte2 |
21054 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_addr_byte3 |
21055 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101822 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101823 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_st_table_loc_0 |
pf5_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf5_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_st_table_loc_1 |
pf5_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf5_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar0_mask_reg_addr_byte0 |
2117648 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar0_mask_reg_addr_byte1 |
2117649 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar0_mask_reg_addr_byte2 |
2117650 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar0_mask_reg_addr_byte3 |
2117651 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar0_reg_addr_byte0 |
20496 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar1_enable_reg_addr_byte0 |
2117652 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar1_mask_reg_addr_byte0 |
2117652 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar1_mask_reg_addr_byte1 |
2117653 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar1_mask_reg_addr_byte2 |
2117654 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar1_mask_reg_addr_byte3 |
2117655 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar1_reg_addr_byte0 |
20500 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar2_mask_reg_addr_byte0 |
2117656 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar2_mask_reg_addr_byte1 |
2117657 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar2_mask_reg_addr_byte2 |
2117658 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar2_mask_reg_addr_byte3 |
2117659 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar2_reg_addr_byte0 |
20504 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar3_enable_reg_addr_byte0 |
2117660 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar3_mask_reg_addr_byte0 |
2117660 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar3_mask_reg_addr_byte1 |
2117661 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar3_mask_reg_addr_byte2 |
2117662 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar3_mask_reg_addr_byte3 |
2117663 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar3_reg_addr_byte0 |
20508 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar4_mask_reg_addr_byte0 |
2117664 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar4_mask_reg_addr_byte1 |
2117665 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar4_mask_reg_addr_byte2 |
2117666 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar4_mask_reg_addr_byte3 |
2117667 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar4_reg_addr_byte0 |
20512 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar5_enable_reg_addr_byte0 |
2117668 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar5_mask_reg_addr_byte0 |
2117668 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar5_mask_reg_addr_byte1 |
2117669 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar5_mask_reg_addr_byte2 |
2117670 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar5_mask_reg_addr_byte3 |
2117671 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bar5_reg_addr_byte0 |
20516 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
20494 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
20520 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
20521 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
20522 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
20523 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
20480 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
20481 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
20482 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
20483 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2117680 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2117681 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2117682 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2117683 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
20528 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
20541 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
20532 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
20524 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
20525 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
20526 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
20527 |
hssi_ctp_u_wrpcie_top_u_core8_pf5_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf5_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_cap_hdr_reg_addr_byte2 |
25302 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_cap_hdr_reg_addr_byte3 |
25303 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_capalities_ctrl_reg_byte0 |
4824 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_capalities_ctrl_reg_byte1 |
4825 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ari_cap_cap_reg_addr_byte0 |
24956 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ats_cap_ats_cap_hdr_reg_addr_byte2 |
25342 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ats_cap_ats_cap_hdr_reg_addr_byte3 |
25343 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
25344 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar0_mem_io |
pf6_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar0_type |
pf6_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar1_mem_io |
pf6_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar1_type |
pf6_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar2_mem_io |
pf6_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar2_type |
pf6_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar3_mem_io |
pf6_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar3_type |
pf6_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar4_mem_io |
pf6_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar4_type |
pf6_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar5_mem_io |
pf6_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_bar5_type |
pf6_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_d1_support |
pf6_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf6_d2_support |
pf6_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_dsi |
pf6_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf6_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_int_pin |
pf6_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf6_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
24657 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
24658 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
24659 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_pba_offset_reg_addr_byte0 |
24760 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_pba_offset_reg_addr_byte1 |
24761 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_pba_offset_reg_addr_byte2 |
24762 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_pba_offset_reg_addr_byte3 |
24763 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_table_offset_reg_addr_byte0 |
24756 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_table_offset_reg_addr_byte1 |
24757 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_table_offset_reg_addr_byte2 |
24758 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_msix_table_offset_reg_addr_byte3 |
24759 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
24753 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
24754 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
24755 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_no_soft_rst |
pf6_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf6_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
25396 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
25397 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
25394 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
25395 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_multiple_msg_cap |
pf6_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_active_state_link_pm_control |
pf6_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_active_state_link_pm_support |
pf6_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_clock_power_man |
pf6_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_device_capabilities_reg_addr_byte0 |
24692 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_device_capabilities_reg_addr_byte1 |
24693 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_device_capabilities_reg_addr_byte3 |
24695 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_en_clk_power_man |
pf6_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_ext_tag_supp |
pf6_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_flr_cap |
pf6_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_capabilities_reg_addr_byte0 |
24700 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_capabilities_reg_addr_byte1 |
24701 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_capabilities_reg_addr_byte2 |
24702 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_capabilities_reg_addr_byte3 |
24703 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4219040 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_control_link_status_reg_addr_byte0 |
4219008 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_control_link_status_reg_addr_byte1 |
4219009 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_control_link_status_reg_addr_byte2 |
4219010 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_max_link_speed |
pf6_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_max_link_width |
pf6_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_max_payload_size |
pf6_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
24689 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
24691 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_rcb |
pf6_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_sel_deemphasis |
pf6_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2121852 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2121853 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_target_link_speed |
pf6_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pcie_slot_imp |
pf6_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
24641 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
24642 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
24643 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pm_cap_con_status_reg_addr_byte0 |
24644 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
25314 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
25371 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
25376 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
25377 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
25378 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
25379 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
25345 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
25346 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2122324 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2122325 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2122326 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2122327 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2122328 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2122329 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2122330 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2122331 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2122332 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2122333 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2122334 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2122335 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2122336 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2122337 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2122338 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2122339 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2122340 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2122341 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2122342 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2122343 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2122344 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2122345 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2122346 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2122347 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2122328 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2122336 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2122344 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_base_reg_addr_byte2 |
25138 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_base_reg_addr_byte3 |
25139 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sup_page_sizes_reg_addr_byte0 |
25164 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sup_page_sizes_reg_addr_byte1 |
25165 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sup_page_sizes_reg_addr_byte2 |
25166 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_sup_page_sizes_reg_addr_byte3 |
25167 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_bar0_reg_addr_byte0 |
25172 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_bar1_reg_addr_byte0 |
25176 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_bar2_reg_addr_byte0 |
25180 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_bar3_reg_addr_byte0 |
25184 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_bar4_reg_addr_byte0 |
25188 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_bar5_reg_addr_byte0 |
25192 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_device_id_reg_addr_byte2 |
25162 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_cap_vf_device_id_reg_addr_byte3 |
25163 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar0_type |
pf6_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar1_type |
pf6_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar2_type |
pf6_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar3_type |
pf6_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar4_type |
pf6_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_bar5_type |
pf6_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
25146 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
25147 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_addr_byte0 |
25148 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_addr_byte1 |
25149 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_addr_byte2 |
25150 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_addr_byte3 |
25151 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101822 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101823 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_st_table_loc_0 |
pf6_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf6_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_st_table_loc_1 |
pf6_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf6_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar0_mask_reg_addr_byte0 |
2121744 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar0_mask_reg_addr_byte1 |
2121745 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar0_mask_reg_addr_byte2 |
2121746 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar0_mask_reg_addr_byte3 |
2121747 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar0_reg_addr_byte0 |
24592 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar1_enable_reg_addr_byte0 |
2121748 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar1_mask_reg_addr_byte0 |
2121748 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar1_mask_reg_addr_byte1 |
2121749 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar1_mask_reg_addr_byte2 |
2121750 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar1_mask_reg_addr_byte3 |
2121751 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar1_reg_addr_byte0 |
24596 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar2_mask_reg_addr_byte0 |
2121752 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar2_mask_reg_addr_byte1 |
2121753 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar2_mask_reg_addr_byte2 |
2121754 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar2_mask_reg_addr_byte3 |
2121755 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar2_reg_addr_byte0 |
24600 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar3_enable_reg_addr_byte0 |
2121756 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar3_mask_reg_addr_byte0 |
2121756 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar3_mask_reg_addr_byte1 |
2121757 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar3_mask_reg_addr_byte2 |
2121758 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar3_mask_reg_addr_byte3 |
2121759 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar3_reg_addr_byte0 |
24604 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar4_mask_reg_addr_byte0 |
2121760 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar4_mask_reg_addr_byte1 |
2121761 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar4_mask_reg_addr_byte2 |
2121762 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar4_mask_reg_addr_byte3 |
2121763 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar4_reg_addr_byte0 |
24608 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar5_enable_reg_addr_byte0 |
2121764 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar5_mask_reg_addr_byte0 |
2121764 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar5_mask_reg_addr_byte1 |
2121765 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar5_mask_reg_addr_byte2 |
2121766 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar5_mask_reg_addr_byte3 |
2121767 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bar5_reg_addr_byte0 |
24612 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
24590 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
24616 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
24617 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
24618 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
24619 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
24576 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
24577 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
24578 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
24579 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2121776 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2121777 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2121778 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2121779 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
24624 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
24637 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
24628 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
24620 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
24621 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
24622 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
24623 |
hssi_ctp_u_wrpcie_top_u_core8_pf6_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf6_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_at_block |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_cap_hdr_reg_addr_byte2 |
29398 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_cap_hdr_reg_addr_byte3 |
29399 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_capalities_ctrl_reg_byte0 |
4824 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_capalities_ctrl_reg_byte1 |
4825 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_direct_translated_p2p |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_egress_ctrl_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_p2p_cpl_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_p2p_egress_control |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_p2p_req_redirect |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_src_valid |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_acs_usp_forwarding |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_rsvdp_7 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_acs_next_offset |
792 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte2 |
4354 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_aer_cap_aer_ext_cap_hdr_off_addr_byte3 |
4355 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_aer_cap_version |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_aer_next_offset |
328 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ari_acs_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ari_cap_ari_base_addr_byte2 |
4474 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ari_cap_ari_base_addr_byte3 |
4475 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ari_cap_cap_reg_addr_byte0 |
29052 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ari_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ari_mfvc_fun_grp_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ari_next_offset |
408 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ats_cap_ats_cap_hdr_reg_addr_byte2 |
29438 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ats_cap_ats_cap_hdr_reg_addr_byte3 |
29439 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ats_cap_ats_capabilities_ctrl_reg_addr_byte0 |
29440 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ats_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ats_capabilities_ctrl_reg_rsvdp_7 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ats_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_aux_curr |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar0_mem_io |
pf7_bar0_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar0_type |
pf7_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar1_mem_io |
pf7_bar1_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar1_type |
pf7_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar2_mem_io |
pf7_bar2_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar2_type |
pf7_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar3_mem_io |
pf7_bar3_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar3_type |
pf7_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar4_mem_io |
pf7_bar4_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar4_type |
pf7_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar5_mem_io |
pf7_bar5_mem |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_bar5_type |
pf7_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_base_class_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_cap_id_nxt_ptr_reg_rsvdp_20 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_cap_pointer |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_cardbus_cis_pointer |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_con_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_con_status_reg_rsvdp_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_d1_support |
pf7_d1_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf7_d2_support |
pf7_d2_not_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_14 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_15 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_17 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_18 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_19 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_20 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_21 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_22 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_23 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_24 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_26 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_28 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_30 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_31 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_32 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_33 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_34 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_35 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_36 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_37 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_38 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_39 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_4 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_40 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_41 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_42 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_43 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_44 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_45 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_46 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_47 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_48 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_49 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_5 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_50 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_51 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_52 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_53 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_54 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_55 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_56 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_57 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_58 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_59 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_6 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_60 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_61 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_62 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_63 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_64 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_65 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_66 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_7 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_8 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dbi_reserved_9 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_device_capabilities_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_device_capabilities_reg_rsvdp_16 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_device_capabilities_reg_rsvdp_29 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_dsi |
pf7_not_required |
hssi_ctp_u_wrpcie_top_u_core8_pf7_exp_rom_bar_mask_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_exp_rom_base_addr_reg_rsvdp_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_global_inval_spprtd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_header_type |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_int_pin |
pf7_inta |
hssi_ctp_u_wrpcie_top_u_core8_pf7_invalidate_q_depth |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_link_capabilities_reg_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_link_control_link_status_reg_rsvdp_12 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_link_control_link_status_reg_rsvdp_2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_link_control_link_status_reg_rsvdp_25 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_link_control_link_status_reg_rsvdp_9 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte1 |
28753 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte2 |
28754 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msi_cap_pci_msi_cap_id_next_ctrl_reg_addr_byte3 |
28755 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_pba_offset_reg_addr_byte0 |
28856 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_pba_offset_reg_addr_byte1 |
28857 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_pba_offset_reg_addr_byte2 |
28858 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_pba_offset_reg_addr_byte3 |
28859 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_table_offset_reg_addr_byte0 |
28852 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_table_offset_reg_addr_byte1 |
28853 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_table_offset_reg_addr_byte2 |
28854 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_msix_table_offset_reg_addr_byte3 |
28855 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte1 |
28849 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte2 |
28850 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_addr_byte3 |
28851 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte2 |
2101426 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_msix_cap_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_addr_byte3 |
2101427 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_multi_func |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_no_soft_rst |
pf7_internally_reset |
hssi_ctp_u_wrpcie_top_u_core8_pf7_page_aligned_req |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_execute_permission_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_max_pasid_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte0 |
29492 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_pasid_cap_cntrl_reg_addr_byte1 |
29493 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte2 |
29490 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_pasid_ext_hdr_reg_addr_byte3 |
29491 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_privileged_mode_supported |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_rsvdp_0 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_rsvpd_13 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pasid_next_offset |
824 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_64_bit_addr_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_cap_next_offset |
112 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_ext_data_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_ext_data_en |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_multiple_msg_cap |
pf7_msi_vec_32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_multiple_msg_en |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msi_pvm_sup_cap |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_bir |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_cap_id_next_ctrl_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_cap_id_next_ctrl_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_cap_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_enable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_enable_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_function_mask |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_function_mask_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_pba |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_pba_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_table_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_table_size |
255 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_msix_table_size_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar0_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar2_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar4_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pci_type0_vendor_id |
5827 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_active_state_link_pm_control |
pf7_aspm_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_active_state_link_pm_support |
pf7_no_aspm |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_aspm_opt_compliance |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_aux_power_pm_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_clock_power_man |
pf7_refclk_remove_not_ok |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_common_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_device_capabilities_reg_addr_byte0 |
28788 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_device_capabilities_reg_addr_byte1 |
28789 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_device_capabilities_reg_addr_byte3 |
28791 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_device_control_device_status_addr_byte1 |
4217 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_dll_active |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_en_clk_power_man |
pf7_clkreq_dis |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_en_no_snoop |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_enter_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_ep_l0s_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_ep_l1_accpt_latency |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_ext_tag_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_ext_tag_supp |
pf7_supported |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_extended_synch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_flr_cap |
pf7_capable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_hw_auto_speed_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvd |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_rsvdp_31 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_initiate_flr |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_l0s_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_l0s_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_l1_exit_latency_commclk_dis |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_l1_exit_latency_commclk_ena_cs2 |
7 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_auto_bw_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_auto_bw_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_bw_man_int_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_bw_man_status |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_capabilities_reg_addr_byte0 |
28796 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_capabilities_reg_addr_byte1 |
28797 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_capabilities_reg_addr_byte2 |
28798 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_capabilities_reg_addr_byte3 |
28799 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_control2_link_status2_reg_addr_byte0 |
4223136 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_control_link_status_reg_addr_byte0 |
4223104 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_control_link_status_reg_addr_byte1 |
4223105 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_control_link_status_reg_addr_byte2 |
4223106 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_disable |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_link_training |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_max_link_speed |
pf7_max_8gts |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_max_link_width |
pf7_x16 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_max_payload_size |
pf7_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_max_read_req_size |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_nego_link_width |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_next_ptr |
176 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte1 |
28785 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_pcie_cap_id_pcie_next_cap_ptr_pcie_cap_reg_addr_byte3 |
28787 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_phantom_func_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_phantom_func_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_port_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_rcb |
pf7_rcb_64 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_retrain_link |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_role_based_err_report |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_sel_deemphasis |
pf7_minus_6db |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_shadow_link_capabilities_reg_addr_byte0 |
2125948 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_shadow_link_capabilities_reg_addr_byte1 |
2125949 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_slot_clk_config |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_target_link_speed |
pf7_trgt_gen3 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_cap_tx_margin |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_int_msg_num |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pcie_slot_imp |
pf7_not_implemented |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_ari_device_number |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_dbi_ro_wr_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_default_target |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_disable_auto_ltr_clr_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_mask_ur_ca_4_trgt1 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_misc_control_1_off_rsvdp_6 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_port_logic_misc_control_1_off_addr_byte0 |
2236 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_simplified_replay_timer |
true |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pf0_tlp_bypass_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte1 |
28737 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte2 |
28738 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pm_cap_cap_id_nxt_ptr_reg_addr_byte3 |
28739 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pm_cap_con_status_reg_addr_byte0 |
28740 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pm_next_pointer |
80 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pm_spec_ver |
3 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pme_clk |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_pme_support |
27 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_power_state |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_program_interface |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte2 |
29410 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_cap_prs_ext_cap_hdr_reg_addr_byte3 |
29467 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte0 |
29472 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte1 |
29473 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte2 |
29474 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_cap_prs_req_capacity_reg_addr_byte3 |
29475 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_ext_next_offset |
808 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_prs_outstanding_capacity |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ras_des_cap_ras_des_hdr_reg_addr_byte2 |
29441 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ras_des_cap_ras_des_hdr_reg_addr_byte3 |
29442 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ras_des_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_ras_des_next_offset |
1136 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved10 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_10_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_11_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_12_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_13_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_14_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_15_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_16_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_17_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_18_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_19_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_20_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_21_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_22_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_23_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_24_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_25_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_26_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_27_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_28_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_29_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_2_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_30_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_31_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_32_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_33_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_34_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_35_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_36_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_37_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_38_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_39_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_3_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_40_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_41_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_42_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_43_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_44_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_45_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_46_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_47_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_48_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_49_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_4_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_50_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_51_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_52_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_53_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_54_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_55_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_56_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_57_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_58_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_59_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_5_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_60_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_61_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_62_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_63_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_64_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_65_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_66_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_6_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_7_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_8_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_reserved_9_addr |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_revision_id |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_rom_bar_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_rom_bar_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_link_capabilities_reg_shadow_rsvdp_23 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_pcie_cap_active_state_link_pm_support |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_pcie_cap_aspm_opt_compliance |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_pcie_cap_clock_power_man |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_pcie_cap_dll_active_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_pcie_cap_link_bw_not_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_pcie_cap_max_link_width |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_pcie_cap_surprise_down_err_rep_cap |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_shadow_sriov_vf_stride_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_1_addr_byte0 |
4460 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_1_addr_byte1 |
4461 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_1_addr_byte2 |
4462 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_1_addr_byte3 |
4463 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_2_addr_byte0 |
4464 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_2_addr_byte1 |
4465 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_2_addr_byte2 |
4466 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_ser_num_reg_dw_2_addr_byte3 |
4467 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_sn_base_addr_byte2 |
4458 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_sn_base_addr_byte3 |
4459 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_next_offset |
376 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_ser_num_reg_1_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sn_ser_num_reg_2_dw |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_sriov_initial_vfs_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte0 |
2101828 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte1 |
2101829 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte2 |
2101830 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_sriov_vf_offset_position_addr_byte3 |
2101831 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte0 |
2126420 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte1 |
2126421 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte2 |
2126422 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar0_reg_addr_byte3 |
2126423 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte0 |
2126424 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte1 |
2126425 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte2 |
2126426 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar1_reg_addr_byte3 |
2126427 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte0 |
2126428 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte1 |
2126429 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte2 |
2126430 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar2_reg_addr_byte3 |
2126431 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte0 |
2126432 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte1 |
2126433 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte2 |
2126434 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar3_reg_addr_byte3 |
2126435 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte0 |
2126436 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte1 |
2126437 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte2 |
2126438 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar4_reg_addr_byte3 |
2126439 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte0 |
2126440 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte1 |
2126441 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte2 |
2126442 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_shadow_vf_bar5_reg_addr_byte3 |
2126443 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_bar1_enable_reg_addr_byte0 |
2126424 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_bar3_enable_reg_addr_byte0 |
2126432 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_bar5_enable_reg_addr_byte0 |
2126440 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_base_reg_addr_byte2 |
29234 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_base_reg_addr_byte3 |
29235 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_initial_vfs_addr_byte0 |
4668 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_initial_vfs_addr_byte1 |
4669 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_vf_offset_position_addr_byte0 |
4676 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_vf_offset_position_addr_byte1 |
4677 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_vf_offset_position_addr_byte2 |
4678 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sriov_vf_offset_position_addr_byte3 |
4679 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sup_page_sizes_reg_addr_byte0 |
29260 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sup_page_sizes_reg_addr_byte1 |
29261 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sup_page_sizes_reg_addr_byte2 |
29262 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_sup_page_sizes_reg_addr_byte3 |
29263 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_version |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_bar0_reg_addr_byte0 |
29268 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_bar1_reg_addr_byte0 |
29272 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_bar2_reg_addr_byte0 |
29276 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_bar3_reg_addr_byte0 |
29280 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_bar4_reg_addr_byte0 |
29284 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_bar5_reg_addr_byte0 |
29288 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_device_id_reg_addr_byte2 |
29258 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_cap_vf_device_id_reg_addr_byte3 |
29259 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_initial_vfs_ari_cs2 |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_initial_vfs_nonari |
64 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_next_offset |
632 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_sup_page_size |
1363 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar0_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar0_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar0_type |
pf7_sriov_vf_bar0_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar1_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar1_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar1_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar1_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar1_type |
pf7_sriov_vf_bar1_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar2_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar2_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar2_type |
pf7_sriov_vf_bar2_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar3_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar3_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar3_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar3_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar3_type |
pf7_sriov_vf_bar3_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar4_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar4_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar4_type |
pf7_sriov_vf_bar4_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar5_dummy_mask_7_1 |
127 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar5_enabled |
enable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar5_prefetch |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar5_start |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_bar5_type |
pf7_sriov_vf_bar5_mem32 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_device_id |
43981 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_offset_ari_cs2 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_offset_position_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_sriov_vf_stride_nonari |
256 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_subclass_code |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_subsys_dev_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_subsys_vendor_id |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte2 |
29242 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_ext_cap_hdr_reg_addr_byte3 |
29243 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_addr_byte0 |
29244 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_addr_byte1 |
29245 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_addr_byte2 |
29246 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_addr_byte3 |
29247 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte0 |
2101820 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte1 |
2101821 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte2 |
2101822 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_cap_tph_req_cap_reg_vfcomm_cs2_addr_byte3 |
2101823 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_int_vec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_int_vec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_reg_rsvdp_11 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_reg_rsvdp_27 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_reg_rsvdp_3 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_11_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_27_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_reg_vfcomm_cs2_rsvdp_3_vfcomm_cs2 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_st_table_loc_0 |
pf7_in_tph_struct |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 |
pf7_in_tph_struct_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_st_table_loc_1 |
pf7_not_in_msix_table |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 |
pf7_not_in_msix_table_vf |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_st_table_size |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_st_table_size_vfcomm_cs2 |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_cap_ver |
1 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_device_spec |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_device_spec_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_extended_tph |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_extended_tph_vfcomm_cs2 |
disable |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_next_ptr |
728 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_no_st_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_tph_req_no_st_mode_vfcomm_cs2 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar0_mask_reg_addr_byte0 |
2125840 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar0_mask_reg_addr_byte1 |
2125841 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar0_mask_reg_addr_byte2 |
2125842 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar0_mask_reg_addr_byte3 |
2125843 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar0_reg_addr_byte0 |
28688 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar1_enable_reg_addr_byte0 |
2125844 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar1_mask_reg_addr_byte0 |
2125844 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar1_mask_reg_addr_byte1 |
2125845 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar1_mask_reg_addr_byte2 |
2125846 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar1_mask_reg_addr_byte3 |
2125847 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar1_reg_addr_byte0 |
28692 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar2_mask_reg_addr_byte0 |
2125848 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar2_mask_reg_addr_byte1 |
2125849 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar2_mask_reg_addr_byte2 |
2125850 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar2_mask_reg_addr_byte3 |
2125851 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar2_reg_addr_byte0 |
28696 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar3_enable_reg_addr_byte0 |
2125852 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar3_mask_reg_addr_byte0 |
2125852 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar3_mask_reg_addr_byte1 |
2125853 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar3_mask_reg_addr_byte2 |
2125854 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar3_mask_reg_addr_byte3 |
2125855 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar3_reg_addr_byte0 |
28700 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar4_mask_reg_addr_byte0 |
2125856 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar4_mask_reg_addr_byte1 |
2125857 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar4_mask_reg_addr_byte2 |
2125858 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar4_mask_reg_addr_byte3 |
2125859 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar4_reg_addr_byte0 |
28704 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar5_enable_reg_addr_byte0 |
2125860 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar5_mask_reg_addr_byte0 |
2125860 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar5_mask_reg_addr_byte1 |
2125861 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar5_mask_reg_addr_byte2 |
2125862 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar5_mask_reg_addr_byte3 |
2125863 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bar5_reg_addr_byte0 |
28708 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_bist_header_type_latency_cache_line_size_reg_addr_byte2 |
28686 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte0 |
28712 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte1 |
28713 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte2 |
28714 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_cardbus_cis_ptr_reg_addr_byte3 |
28715 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_class_code_revision_id_addr_byte0 |
4104 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_class_code_revision_id_addr_byte1 |
4105 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_class_code_revision_id_addr_byte2 |
4106 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_class_code_revision_id_addr_byte3 |
4107 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte0 |
28672 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte1 |
28673 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte2 |
28674 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_device_id_vendor_id_reg_addr_byte3 |
28675 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte0 |
2125872 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte1 |
2125873 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte2 |
2125874 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_exp_rom_bar_mask_reg_addr_byte3 |
2125875 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_exp_rom_base_addr_reg_addr_byte0 |
28720 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_max_latency_min_grant_interrupt_pin_interrupt_line_reg_addr_byte1 |
28733 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_pci_cap_ptr_reg_addr_byte0 |
28724 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte0 |
28716 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte1 |
28717 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte2 |
28718 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_type0_hdr_subsystem_id_subsystem_vendor_id_reg_addr_byte3 |
28719 |
hssi_ctp_u_wrpcie_top_u_core8_pf7_vf_bar0_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_vf_bar1_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_vf_bar2_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_vf_bar3_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_vf_bar4_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pf7_vf_bar5_reg_rsvdp_0 |
false |
hssi_ctp_u_wrpcie_top_u_core8_pld_aib_loopback_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pld_clk_dis |
false |
hssi_ctp_u_wrpcie_top_u_core8_pld_crs_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_pld_tx_fifo_dyn_empty_dis |
false |
hssi_ctp_u_wrpcie_top_u_core8_powerdown_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_powermode_ac |
pcie_g4_x16 |
hssi_ctp_u_wrpcie_top_u_core8_powermode_dc |
powerdown |
hssi_ctp_u_wrpcie_top_u_core8_powermode_freq_hz |
1000000000 |
hssi_ctp_u_wrpcie_top_u_core8_rct |
1 |
hssi_ctp_u_wrpcie_top_u_core8_rstctl_timer_a |
0 |
hssi_ctp_u_wrpcie_top_u_core8_rstctl_timer_b |
0 |
hssi_ctp_u_wrpcie_top_u_core8_rtsel |
1 |
hssi_ctp_u_wrpcie_top_u_core8_rx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_rxbuf_limit_bypass |
0 |
hssi_ctp_u_wrpcie_top_u_core8_rxbuf_limit_init |
false |
hssi_ctp_u_wrpcie_top_u_core8_rxbuf_pfull_th |
22 |
hssi_ctp_u_wrpcie_top_u_core8_scratch_pad0_31_1 |
0 |
hssi_ctp_u_wrpcie_top_u_core8_sd_cfg |
false |
hssi_ctp_u_wrpcie_top_u_core8_sd_dwip |
false |
hssi_ctp_u_wrpcie_top_u_core8_shadow_select |
false |
hssi_ctp_u_wrpcie_top_u_core8_sim_mode |
enable |
hssi_ctp_u_wrpcie_top_u_core8_sriov_clk_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_sris_mode |
false |
hssi_ctp_u_wrpcie_top_u_core8_sup_mode |
user_mode |
hssi_ctp_u_wrpcie_top_u_core8_test_in_high |
0 |
hssi_ctp_u_wrpcie_top_u_core8_test_in_lo |
0 |
hssi_ctp_u_wrpcie_top_u_core8_test_in_override |
false |
hssi_ctp_u_wrpcie_top_u_core8_tx_cdts_rst |
false |
hssi_ctp_u_wrpcie_top_u_core8_tx_fifo_empty_threshold_1 |
3 |
hssi_ctp_u_wrpcie_top_u_core8_tx_fifo_empty_threshold_2 |
12 |
hssi_ctp_u_wrpcie_top_u_core8_tx_fifo_empty_threshold_3 |
15 |
hssi_ctp_u_wrpcie_top_u_core8_tx_fifo_empty_threshold_4 |
2 |
hssi_ctp_u_wrpcie_top_u_core8_tx_fifo_full_threshold |
40 |
hssi_ctp_u_wrpcie_top_u_core8_tx_lane_flip_en |
false |
hssi_ctp_u_wrpcie_top_u_core8_user_mode_del_count |
0 |
hssi_ctp_u_wrpcie_top_u_core8_vf |
0 |
hssi_ctp_u_wrpcie_top_u_core8_vf_select |
false |
hssi_ctp_u_wrpcie_top_u_core8_virtual_drop_vendor0_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_virtual_drop_vendor1_msg |
false |
hssi_ctp_u_wrpcie_top_u_core8_virtual_ep_native |
native |
hssi_ctp_u_wrpcie_top_u_core8_virtual_gen2_pma_pll_usage |
not_applicable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_hrdrstctrl_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_ip_port_num |
pcie_port0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_link_rate |
gen3 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_link_width |
x16 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_maxpayload_size |
max_payload_1024 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_num_of_lanes |
num_16 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_dlink_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_io_decode |
io32 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_ltr_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_margin_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_pl16g_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_prefetch_decode |
pref64 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf0_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf1_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf2_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf3_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf4_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf5_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf6_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_exvf_acs_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_exvf_aricap_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_exvf_ats_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_exvf_msix_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_exvf_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_exvf_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_msi_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_msix_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_pasid_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_pb_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_prs_ext_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_ras_des_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sn_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_num_vf_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_num_vf_non_ari |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_vf_bar0_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_vf_bar1_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_vf_bar2_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_vf_bar3_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_vf_bar4_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_sriov_vf_bar5_enabled |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_tph_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_user_vsec_cap_enable |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_user_vsec_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pf7_virtio_en |
disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_phase23_txpreset |
preset7 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_phase23_txpreset_atg4 |
gen4_preset7 |
hssi_ctp_u_wrpcie_top_u_core8_virtual_pldclk_rate |
fast |
hssi_ctp_u_wrpcie_top_u_core8_virtual_rp_ep_mode |
ep |
hssi_ctp_u_wrpcie_top_u_core8_virtual_tlp_bypass_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_txeq_mode |
eq_disable |
hssi_ctp_u_wrpcie_top_u_core8_virtual_uc_calibration_en |
enable |
hssi_ctp_u_wrpcie_top_u_core8_vsec_next_offset |
0 |
hssi_ctp_u_wrpcie_top_u_core8_vsec_select |
false |
hssi_ctp_u_wrpcie_top_u_core8_wait_pld_warm_rst_rdy |
false |
hssi_ctp_u_wrpcie_top_u_core8_wct |
1 |
hssi_ctp_u_wrpcie_top_u_core8_wtsel |
0 |
hssi_ctp_u_wrpcie_top_virtual_cfg_func_mode |
func_disable |
hssi_ctp_u_wrpcie_top_virtual_port_type |
ep |
hssi_ctp_u_wrpcie_top_virtual_powerdown_mode |
false |
hssi_ctp_u_wrpcie_top_virtual_sim_mode |
enable |
hssi_ctp_u_wrpcie_top_virtual_sris_enable |
disable |
hssi_ctp_u_wrpcie_top_virtual_sup_mode |
user_mode |
hssi_ctp_u_wrpcie_top_virtual_tlp_bypass_en |
bypass_disable |
hssi_ctp_u_wrphy_top_pcs_func_mode |
phy_disabled |
hssi_ctp_u_wrphy_top_pcs_powerdown_mode |
true |
hssi_ctp_u_wrphy_top_pcs_powermode_ac |
disabled |
hssi_ctp_u_wrphy_top_pcs_powermode_dc |
powerdown |
hssi_ctp_u_wrphy_top_pcs_powermode_freq_hz |
0 |
hssi_ctp_u_wrphy_top_pcs_sup_mode |
user_mode |
hssi_ctp_u_wrphy_top_pcs_topology |
disabled_block |
hssi_ctp_u_wrphy_top_pma_top_0_avmm_sel |
cfg_avmm_mode |
hssi_ctp_u_wrphy_top_pma_top_0_bs_mode |
bs_ac_mode |
hssi_ctp_u_wrphy_top_pma_top_0_bs_rx_bigswing |
dis_rx_bigswing |
hssi_ctp_u_wrphy_top_pma_top_0_bs_rx_level |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_bs_tx_lowswing |
dis_tx_lowswing |
hssi_ctp_u_wrphy_top_pma_top_0_bti_protected |
true |
hssi_ctp_u_wrphy_top_pma_top_0_cfg_phy_reset |
phy_reset_off |
hssi_ctp_u_wrphy_top_pma_top_0_cfg_phy_reset_ovrd |
phy_reset_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_0_cfg_pma_ovrd |
pma_hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_0_cfg_ref_clk_en |
ref_clk_en |
hssi_ctp_u_wrphy_top_pma_top_0_cfg_ref_clk_en_ovrd |
ref_clk_en_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_0_cr_access_en |
clr_cr_access |
hssi_ctp_u_wrphy_top_pma_top_0_cr_para_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_cr_para_sel |
cr_jtag_intf_en |
hssi_ctp_u_wrphy_top_pma_top_0_cr_para_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_cr_wr_rd_n |
cr_rd_access |
hssi_ctp_u_wrphy_top_pma_top_0_dfd_ctrl |
csr_mode |
hssi_ctp_u_wrphy_top_pma_top_0_dfd_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_enable_rom_sram_wr |
dis_boot_rom_sram_wr |
hssi_ctp_u_wrphy_top_pma_top_0_es_mode |
standard |
hssi_ctp_u_wrphy_top_pma_top_0_ext_pclk_req |
always_on |
hssi_ctp_u_wrphy_top_pma_top_0_func_mode |
phy_disabled |
hssi_ctp_u_wrphy_top_pma_top_0_lane_off_disable |
lane_off_dis |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_div10_clk_en |
dis_mplla_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_div16p5_clk_en |
dis_mplla_div16p5_clk |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_div8_clk_en |
dis_mplla_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_div_clk_en |
dis_mplla_div_clk |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_force_en |
mplla_force_en |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_init_cal_disable |
en_mplla_init_cal |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_recal_bank_sel_ovrd_en |
dis_mplla_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_ssc_clk_sel |
mplla_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_ssc_en |
dis_mplla_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_ssc_up_spread |
mplla_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_0_mplla_tx_clk_div |
mplla_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_div10_clk_en |
dis_mpllb_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_div8_clk_en |
dis_mpllb_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_div_clk_en |
dis_mpllb_div_clk |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_force_en |
mpllb_force_en |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_recal_bank_sel_ovrd_en |
dis_mpllb_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_ssc_clk_sel |
mpllb_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_ssc_en |
dis_mpllb_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_ssc_up_spread |
mpllb_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_0_mpllb_tx_clk_div |
mpllb_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_0_phy_ext_ctrl_sel |
hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_0_phy_sram_ext_ld_done |
clr_sram_ext_ld_done |
hssi_ctp_u_wrphy_top_pma_top_0_phy_src_sel |
mst_clk_src_phy0 |
hssi_ctp_u_wrphy_top_pma_top_0_phytop_misc_spare_control |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_powerdown_mode |
true |
hssi_ctp_u_wrphy_top_pma_top_0_powermode_ac |
disabled |
hssi_ctp_u_wrphy_top_pma_top_0_powermode_dc |
powerdown |
hssi_ctp_u_wrphy_top_pma_top_0_powermode_freq_hz |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_ppm_threshold |
13 |
hssi_ctp_u_wrphy_top_pma_top_0_quad_num |
phy_quad0 |
hssi_ctp_u_wrphy_top_pma_top_0_ref_clk_div2_en |
dis_refclk_div2 |
hssi_ctp_u_wrphy_top_pma_top_0_ref_clk_en_mode |
pcs_ctrl |
hssi_ctp_u_wrphy_top_pma_top_0_ref_clk_mode |
ref_clk_common |
hssi_ctp_u_wrphy_top_pma_top_0_ref_clk_mplla_div2_en |
dis_mplla_div2 |
hssi_ctp_u_wrphy_top_pma_top_0_ref_clk_mpllb_div2_en |
dis_mpllb_div2 |
hssi_ctp_u_wrphy_top_pma_top_0_ref_clkdet_en |
ref_clkdet_dis |
hssi_ctp_u_wrphy_top_pma_top_0_ref_range |
3 |
hssi_ctp_u_wrphy_top_pma_top_0_rtune_req |
rtune_off |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_cont |
en_adapt_cont |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_mode_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_mode_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_mode_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_mode_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_sel_g1 |
rx_adapt_g1_sel0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_sel_g2 |
rx_adapt_g2_sel0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_sel_g3 |
rx_adapt_g3_sel0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_adapt_sel_g4 |
rx_adapt_g4_sel0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_ppm_max_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_ppm_max_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_ppm_max_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_ppm_max_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_freqband_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_freqband_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_freqband_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_freqband_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_step_ctrl_g1 |
g1_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_step_ctrl_g2 |
g2_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_step_ctrl_g3 |
g3_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_step_ctrl_g4 |
g4_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_temp_comp_en_g1 |
dis_rx_vco_temp_comp_g1 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_temp_comp_en_g2 |
dis_rx_vco_temp_comp_g2 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_temp_comp_en_g3 |
dis_rx_vco_temp_comp_g3 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_cdr_vco_temp_comp_en_g4 |
dis_rx_vco_temp_comp_g4 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_delta_iq_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_delta_iq_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_delta_iq_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_delta_iq_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_dfe_bypass_g1 |
en_dfe_bypass_g1 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_dfe_bypass_g2 |
en_dfe_bypass_g2 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_dfe_bypass_g3 |
en_dfe_bypass_g3 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_dfe_bypass_g4 |
en_dfe_bypass_g4 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_att_lvl_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_att_lvl_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_att_lvl_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_att_lvl_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_boost_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_boost_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_boost_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_boost_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_pole_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_pole_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_pole_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_ctle_pole_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_dfe_tap1_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_dfe_tap1_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_dfe_tap1_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_dfe_tap1_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga1_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga1_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga1_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga1_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga2_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga2_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga2_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_eq_vga2_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_los_lfps_en |
dis_los_lfps |
hssi_ctp_u_wrphy_top_pma_top_0_rx_los_threshold |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_margin_iq |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_offcan_cont |
en_offcan_cont |
hssi_ctp_u_wrphy_top_pma_top_0_rx_ref_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_ref_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_ref_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_ref_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_spare_bits |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_sris_mode_en |
dis_rx_sris_mode |
hssi_ctp_u_wrphy_top_pma_top_0_rx_term_acdc |
rx_term_ac |
hssi_ctp_u_wrphy_top_pma_top_0_rx_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_vco_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_vco_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_vco_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_vco_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_rx_vref_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_sim_mode |
sim_mode_dis |
hssi_ctp_u_wrphy_top_pma_top_0_sram_access_en |
clr_sram_access |
hssi_ctp_u_wrphy_top_pma_top_0_sram_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_sram_bypass |
sram_bypass_mode |
hssi_ctp_u_wrphy_top_pma_top_0_sram_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_sram_wr_rd_n |
sram_rd_access |
hssi_ctp_u_wrphy_top_pma_top_0_sup_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_sup_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_sup_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_sup_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_sup_misc_ovrd_en |
dis_sup_misc_ovrd |
hssi_ctp_u_wrphy_top_pma_top_0_sup_mode |
user_mode |
hssi_ctp_u_wrphy_top_pma_top_0_test_burnin |
burnin_off |
hssi_ctp_u_wrphy_top_pma_top_0_topology |
disabled_block |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_main_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_main_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_main_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_main_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_ovrd_g1 |
dis_g1_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_ovrd_g2 |
dis_g2_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_ovrd_g3 |
dis_g3_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_ovrd_g4 |
dis_g4_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_post_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_post_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_post_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_post_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_pre_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_pre_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_pre_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_eq_pre_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_iboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_tx_vboost_en |
en_vboost |
hssi_ctp_u_wrphy_top_pma_top_0_tx_vboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_txdn_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_0_txup_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_avmm_sel |
cfg_avmm_mode |
hssi_ctp_u_wrphy_top_pma_top_1_bs_mode |
bs_ac_mode |
hssi_ctp_u_wrphy_top_pma_top_1_bs_rx_bigswing |
dis_rx_bigswing |
hssi_ctp_u_wrphy_top_pma_top_1_bs_rx_level |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_bs_tx_lowswing |
dis_tx_lowswing |
hssi_ctp_u_wrphy_top_pma_top_1_bti_protected |
true |
hssi_ctp_u_wrphy_top_pma_top_1_cfg_phy_reset |
phy_reset_off |
hssi_ctp_u_wrphy_top_pma_top_1_cfg_phy_reset_ovrd |
phy_reset_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_1_cfg_pma_ovrd |
pma_hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_1_cfg_ref_clk_en |
ref_clk_en |
hssi_ctp_u_wrphy_top_pma_top_1_cfg_ref_clk_en_ovrd |
ref_clk_en_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_1_cr_access_en |
clr_cr_access |
hssi_ctp_u_wrphy_top_pma_top_1_cr_para_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_cr_para_sel |
cr_jtag_intf_en |
hssi_ctp_u_wrphy_top_pma_top_1_cr_para_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_cr_wr_rd_n |
cr_rd_access |
hssi_ctp_u_wrphy_top_pma_top_1_dfd_ctrl |
csr_mode |
hssi_ctp_u_wrphy_top_pma_top_1_dfd_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_enable_rom_sram_wr |
dis_boot_rom_sram_wr |
hssi_ctp_u_wrphy_top_pma_top_1_es_mode |
standard |
hssi_ctp_u_wrphy_top_pma_top_1_ext_pclk_req |
always_on |
hssi_ctp_u_wrphy_top_pma_top_1_func_mode |
phy_disabled |
hssi_ctp_u_wrphy_top_pma_top_1_lane_off_disable |
lane_off_dis |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_div10_clk_en |
dis_mplla_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_div16p5_clk_en |
dis_mplla_div16p5_clk |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_div8_clk_en |
dis_mplla_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_div_clk_en |
dis_mplla_div_clk |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_force_en |
mplla_force_en |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_init_cal_disable |
en_mplla_init_cal |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_recal_bank_sel_ovrd_en |
dis_mplla_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_ssc_clk_sel |
mplla_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_ssc_en |
dis_mplla_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_ssc_up_spread |
mplla_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_1_mplla_tx_clk_div |
mplla_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_div10_clk_en |
dis_mpllb_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_div8_clk_en |
dis_mpllb_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_div_clk_en |
dis_mpllb_div_clk |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_force_en |
mpllb_force_en |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_recal_bank_sel_ovrd_en |
dis_mpllb_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_ssc_clk_sel |
mpllb_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_ssc_en |
dis_mpllb_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_ssc_up_spread |
mpllb_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_1_mpllb_tx_clk_div |
mpllb_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_1_phy_ext_ctrl_sel |
hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_1_phy_sram_ext_ld_done |
clr_sram_ext_ld_done |
hssi_ctp_u_wrphy_top_pma_top_1_phy_src_sel |
mst_clk_src_phy0 |
hssi_ctp_u_wrphy_top_pma_top_1_phytop_misc_spare_control |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_powerdown_mode |
true |
hssi_ctp_u_wrphy_top_pma_top_1_powermode_ac |
disabled |
hssi_ctp_u_wrphy_top_pma_top_1_powermode_dc |
powerdown |
hssi_ctp_u_wrphy_top_pma_top_1_powermode_freq_hz |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_ppm_threshold |
13 |
hssi_ctp_u_wrphy_top_pma_top_1_quad_num |
phy_quad0 |
hssi_ctp_u_wrphy_top_pma_top_1_ref_clk_div2_en |
dis_refclk_div2 |
hssi_ctp_u_wrphy_top_pma_top_1_ref_clk_en_mode |
pcs_ctrl |
hssi_ctp_u_wrphy_top_pma_top_1_ref_clk_mode |
ref_clk_common |
hssi_ctp_u_wrphy_top_pma_top_1_ref_clk_mplla_div2_en |
dis_mplla_div2 |
hssi_ctp_u_wrphy_top_pma_top_1_ref_clk_mpllb_div2_en |
dis_mpllb_div2 |
hssi_ctp_u_wrphy_top_pma_top_1_ref_clkdet_en |
ref_clkdet_dis |
hssi_ctp_u_wrphy_top_pma_top_1_ref_range |
3 |
hssi_ctp_u_wrphy_top_pma_top_1_rtune_req |
rtune_off |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_cont |
en_adapt_cont |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_mode_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_mode_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_mode_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_mode_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_sel_g1 |
rx_adapt_g1_sel0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_sel_g2 |
rx_adapt_g2_sel0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_sel_g3 |
rx_adapt_g3_sel0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_adapt_sel_g4 |
rx_adapt_g4_sel0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_ppm_max_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_ppm_max_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_ppm_max_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_ppm_max_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_freqband_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_freqband_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_freqband_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_freqband_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_step_ctrl_g1 |
g1_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_step_ctrl_g2 |
g2_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_step_ctrl_g3 |
g3_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_step_ctrl_g4 |
g4_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_temp_comp_en_g1 |
dis_rx_vco_temp_comp_g1 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_temp_comp_en_g2 |
dis_rx_vco_temp_comp_g2 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_temp_comp_en_g3 |
dis_rx_vco_temp_comp_g3 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_cdr_vco_temp_comp_en_g4 |
dis_rx_vco_temp_comp_g4 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_delta_iq_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_delta_iq_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_delta_iq_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_delta_iq_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_dfe_bypass_g1 |
en_dfe_bypass_g1 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_dfe_bypass_g2 |
en_dfe_bypass_g2 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_dfe_bypass_g3 |
en_dfe_bypass_g3 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_dfe_bypass_g4 |
en_dfe_bypass_g4 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_att_lvl_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_att_lvl_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_att_lvl_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_att_lvl_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_boost_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_boost_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_boost_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_boost_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_pole_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_pole_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_pole_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_ctle_pole_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_dfe_tap1_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_dfe_tap1_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_dfe_tap1_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_dfe_tap1_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga1_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga1_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga1_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga1_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga2_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga2_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga2_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_eq_vga2_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_los_lfps_en |
dis_los_lfps |
hssi_ctp_u_wrphy_top_pma_top_1_rx_los_threshold |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_margin_iq |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_offcan_cont |
en_offcan_cont |
hssi_ctp_u_wrphy_top_pma_top_1_rx_ref_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_ref_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_ref_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_ref_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_spare_bits |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_sris_mode_en |
dis_rx_sris_mode |
hssi_ctp_u_wrphy_top_pma_top_1_rx_term_acdc |
rx_term_ac |
hssi_ctp_u_wrphy_top_pma_top_1_rx_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_vco_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_vco_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_vco_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_vco_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_rx_vref_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_sim_mode |
sim_mode_dis |
hssi_ctp_u_wrphy_top_pma_top_1_sram_access_en |
clr_sram_access |
hssi_ctp_u_wrphy_top_pma_top_1_sram_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_sram_bypass |
sram_bypass_mode |
hssi_ctp_u_wrphy_top_pma_top_1_sram_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_sram_wr_rd_n |
sram_rd_access |
hssi_ctp_u_wrphy_top_pma_top_1_sup_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_sup_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_sup_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_sup_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_sup_misc_ovrd_en |
dis_sup_misc_ovrd |
hssi_ctp_u_wrphy_top_pma_top_1_sup_mode |
user_mode |
hssi_ctp_u_wrphy_top_pma_top_1_test_burnin |
burnin_off |
hssi_ctp_u_wrphy_top_pma_top_1_topology |
disabled_block |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_main_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_main_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_main_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_main_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_ovrd_g1 |
dis_g1_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_ovrd_g2 |
dis_g2_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_ovrd_g3 |
dis_g3_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_ovrd_g4 |
dis_g4_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_post_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_post_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_post_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_post_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_pre_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_pre_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_pre_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_eq_pre_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_iboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_tx_vboost_en |
en_vboost |
hssi_ctp_u_wrphy_top_pma_top_1_tx_vboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_txdn_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_1_txup_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_avmm_sel |
cfg_avmm_mode |
hssi_ctp_u_wrphy_top_pma_top_2_bs_mode |
bs_ac_mode |
hssi_ctp_u_wrphy_top_pma_top_2_bs_rx_bigswing |
dis_rx_bigswing |
hssi_ctp_u_wrphy_top_pma_top_2_bs_rx_level |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_bs_tx_lowswing |
dis_tx_lowswing |
hssi_ctp_u_wrphy_top_pma_top_2_bti_protected |
true |
hssi_ctp_u_wrphy_top_pma_top_2_cfg_phy_reset |
phy_reset_off |
hssi_ctp_u_wrphy_top_pma_top_2_cfg_phy_reset_ovrd |
phy_reset_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_2_cfg_pma_ovrd |
pma_hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_2_cfg_ref_clk_en |
ref_clk_en |
hssi_ctp_u_wrphy_top_pma_top_2_cfg_ref_clk_en_ovrd |
ref_clk_en_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_2_cr_access_en |
clr_cr_access |
hssi_ctp_u_wrphy_top_pma_top_2_cr_para_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_cr_para_sel |
cr_jtag_intf_en |
hssi_ctp_u_wrphy_top_pma_top_2_cr_para_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_cr_wr_rd_n |
cr_rd_access |
hssi_ctp_u_wrphy_top_pma_top_2_dfd_ctrl |
csr_mode |
hssi_ctp_u_wrphy_top_pma_top_2_dfd_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_enable_rom_sram_wr |
dis_boot_rom_sram_wr |
hssi_ctp_u_wrphy_top_pma_top_2_es_mode |
standard |
hssi_ctp_u_wrphy_top_pma_top_2_ext_pclk_req |
always_on |
hssi_ctp_u_wrphy_top_pma_top_2_func_mode |
phy_disabled |
hssi_ctp_u_wrphy_top_pma_top_2_lane_off_disable |
lane_off_dis |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_div10_clk_en |
dis_mplla_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_div16p5_clk_en |
dis_mplla_div16p5_clk |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_div8_clk_en |
dis_mplla_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_div_clk_en |
dis_mplla_div_clk |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_force_en |
mplla_force_en |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_init_cal_disable |
en_mplla_init_cal |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_recal_bank_sel_ovrd_en |
dis_mplla_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_ssc_clk_sel |
mplla_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_ssc_en |
dis_mplla_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_ssc_up_spread |
mplla_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_2_mplla_tx_clk_div |
mplla_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_div10_clk_en |
dis_mpllb_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_div8_clk_en |
dis_mpllb_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_div_clk_en |
dis_mpllb_div_clk |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_force_en |
mpllb_force_en |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_recal_bank_sel_ovrd_en |
dis_mpllb_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_ssc_clk_sel |
mpllb_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_ssc_en |
dis_mpllb_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_ssc_up_spread |
mpllb_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_2_mpllb_tx_clk_div |
mpllb_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_2_phy_ext_ctrl_sel |
hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_2_phy_sram_ext_ld_done |
clr_sram_ext_ld_done |
hssi_ctp_u_wrphy_top_pma_top_2_phy_src_sel |
mst_clk_src_phy0 |
hssi_ctp_u_wrphy_top_pma_top_2_phytop_misc_spare_control |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_powerdown_mode |
true |
hssi_ctp_u_wrphy_top_pma_top_2_powermode_ac |
disabled |
hssi_ctp_u_wrphy_top_pma_top_2_powermode_dc |
powerdown |
hssi_ctp_u_wrphy_top_pma_top_2_powermode_freq_hz |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_ppm_threshold |
13 |
hssi_ctp_u_wrphy_top_pma_top_2_quad_num |
phy_quad0 |
hssi_ctp_u_wrphy_top_pma_top_2_ref_clk_div2_en |
dis_refclk_div2 |
hssi_ctp_u_wrphy_top_pma_top_2_ref_clk_en_mode |
pcs_ctrl |
hssi_ctp_u_wrphy_top_pma_top_2_ref_clk_mode |
ref_clk_common |
hssi_ctp_u_wrphy_top_pma_top_2_ref_clk_mplla_div2_en |
dis_mplla_div2 |
hssi_ctp_u_wrphy_top_pma_top_2_ref_clk_mpllb_div2_en |
dis_mpllb_div2 |
hssi_ctp_u_wrphy_top_pma_top_2_ref_clkdet_en |
ref_clkdet_dis |
hssi_ctp_u_wrphy_top_pma_top_2_ref_range |
3 |
hssi_ctp_u_wrphy_top_pma_top_2_rtune_req |
rtune_off |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_cont |
en_adapt_cont |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_mode_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_mode_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_mode_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_mode_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_sel_g1 |
rx_adapt_g1_sel0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_sel_g2 |
rx_adapt_g2_sel0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_sel_g3 |
rx_adapt_g3_sel0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_adapt_sel_g4 |
rx_adapt_g4_sel0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_ppm_max_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_ppm_max_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_ppm_max_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_ppm_max_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_freqband_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_freqband_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_freqband_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_freqband_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_step_ctrl_g1 |
g1_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_step_ctrl_g2 |
g2_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_step_ctrl_g3 |
g3_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_step_ctrl_g4 |
g4_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_temp_comp_en_g1 |
dis_rx_vco_temp_comp_g1 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_temp_comp_en_g2 |
dis_rx_vco_temp_comp_g2 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_temp_comp_en_g3 |
dis_rx_vco_temp_comp_g3 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_cdr_vco_temp_comp_en_g4 |
dis_rx_vco_temp_comp_g4 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_delta_iq_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_delta_iq_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_delta_iq_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_delta_iq_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_dfe_bypass_g1 |
en_dfe_bypass_g1 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_dfe_bypass_g2 |
en_dfe_bypass_g2 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_dfe_bypass_g3 |
en_dfe_bypass_g3 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_dfe_bypass_g4 |
en_dfe_bypass_g4 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_att_lvl_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_att_lvl_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_att_lvl_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_att_lvl_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_boost_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_boost_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_boost_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_boost_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_pole_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_pole_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_pole_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_ctle_pole_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_dfe_tap1_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_dfe_tap1_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_dfe_tap1_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_dfe_tap1_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga1_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga1_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga1_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga1_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga2_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga2_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga2_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_eq_vga2_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_los_lfps_en |
dis_los_lfps |
hssi_ctp_u_wrphy_top_pma_top_2_rx_los_threshold |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_margin_iq |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_offcan_cont |
en_offcan_cont |
hssi_ctp_u_wrphy_top_pma_top_2_rx_ref_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_ref_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_ref_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_ref_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_spare_bits |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_sris_mode_en |
dis_rx_sris_mode |
hssi_ctp_u_wrphy_top_pma_top_2_rx_term_acdc |
rx_term_ac |
hssi_ctp_u_wrphy_top_pma_top_2_rx_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_vco_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_vco_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_vco_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_vco_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_rx_vref_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_sim_mode |
sim_mode_dis |
hssi_ctp_u_wrphy_top_pma_top_2_sram_access_en |
clr_sram_access |
hssi_ctp_u_wrphy_top_pma_top_2_sram_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_sram_bypass |
sram_bypass_mode |
hssi_ctp_u_wrphy_top_pma_top_2_sram_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_sram_wr_rd_n |
sram_rd_access |
hssi_ctp_u_wrphy_top_pma_top_2_sup_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_sup_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_sup_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_sup_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_sup_misc_ovrd_en |
dis_sup_misc_ovrd |
hssi_ctp_u_wrphy_top_pma_top_2_sup_mode |
user_mode |
hssi_ctp_u_wrphy_top_pma_top_2_test_burnin |
burnin_off |
hssi_ctp_u_wrphy_top_pma_top_2_topology |
disabled_block |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_main_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_main_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_main_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_main_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_ovrd_g1 |
dis_g1_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_ovrd_g2 |
dis_g2_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_ovrd_g3 |
dis_g3_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_ovrd_g4 |
dis_g4_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_post_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_post_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_post_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_post_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_pre_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_pre_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_pre_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_eq_pre_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_iboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_tx_vboost_en |
en_vboost |
hssi_ctp_u_wrphy_top_pma_top_2_tx_vboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_txdn_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_2_txup_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_avmm_sel |
cfg_avmm_mode |
hssi_ctp_u_wrphy_top_pma_top_3_bs_mode |
bs_ac_mode |
hssi_ctp_u_wrphy_top_pma_top_3_bs_rx_bigswing |
dis_rx_bigswing |
hssi_ctp_u_wrphy_top_pma_top_3_bs_rx_level |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_bs_tx_lowswing |
dis_tx_lowswing |
hssi_ctp_u_wrphy_top_pma_top_3_bti_protected |
true |
hssi_ctp_u_wrphy_top_pma_top_3_cfg_phy_reset |
phy_reset_off |
hssi_ctp_u_wrphy_top_pma_top_3_cfg_phy_reset_ovrd |
phy_reset_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_3_cfg_pma_ovrd |
pma_hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_3_cfg_ref_clk_en |
ref_clk_en |
hssi_ctp_u_wrphy_top_pma_top_3_cfg_ref_clk_en_ovrd |
ref_clk_en_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_3_cr_access_en |
clr_cr_access |
hssi_ctp_u_wrphy_top_pma_top_3_cr_para_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_cr_para_sel |
cr_jtag_intf_en |
hssi_ctp_u_wrphy_top_pma_top_3_cr_para_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_cr_wr_rd_n |
cr_rd_access |
hssi_ctp_u_wrphy_top_pma_top_3_dfd_ctrl |
csr_mode |
hssi_ctp_u_wrphy_top_pma_top_3_dfd_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_enable_rom_sram_wr |
dis_boot_rom_sram_wr |
hssi_ctp_u_wrphy_top_pma_top_3_es_mode |
standard |
hssi_ctp_u_wrphy_top_pma_top_3_ext_pclk_req |
always_on |
hssi_ctp_u_wrphy_top_pma_top_3_func_mode |
phy_disabled |
hssi_ctp_u_wrphy_top_pma_top_3_lane_off_disable |
lane_off_dis |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_div10_clk_en |
dis_mplla_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_div16p5_clk_en |
dis_mplla_div16p5_clk |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_div8_clk_en |
dis_mplla_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_div_clk_en |
dis_mplla_div_clk |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_force_en |
mplla_force_en |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_init_cal_disable |
en_mplla_init_cal |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_recal_bank_sel_ovrd_en |
dis_mplla_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_ssc_clk_sel |
mplla_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_ssc_en |
dis_mplla_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_ssc_up_spread |
mplla_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_3_mplla_tx_clk_div |
mplla_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_div10_clk_en |
dis_mpllb_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_div8_clk_en |
dis_mpllb_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_div_clk_en |
dis_mpllb_div_clk |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_force_en |
mpllb_force_en |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_recal_bank_sel_ovrd_en |
dis_mpllb_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_ssc_clk_sel |
mpllb_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_ssc_en |
dis_mpllb_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_ssc_up_spread |
mpllb_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_3_mpllb_tx_clk_div |
mpllb_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_3_phy_ext_ctrl_sel |
hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_3_phy_sram_ext_ld_done |
clr_sram_ext_ld_done |
hssi_ctp_u_wrphy_top_pma_top_3_phy_src_sel |
mst_clk_src_phy0 |
hssi_ctp_u_wrphy_top_pma_top_3_phytop_misc_spare_control |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_powerdown_mode |
true |
hssi_ctp_u_wrphy_top_pma_top_3_powermode_ac |
disabled |
hssi_ctp_u_wrphy_top_pma_top_3_powermode_dc |
powerdown |
hssi_ctp_u_wrphy_top_pma_top_3_powermode_freq_hz |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_ppm_threshold |
13 |
hssi_ctp_u_wrphy_top_pma_top_3_quad_num |
phy_quad0 |
hssi_ctp_u_wrphy_top_pma_top_3_ref_clk_div2_en |
dis_refclk_div2 |
hssi_ctp_u_wrphy_top_pma_top_3_ref_clk_en_mode |
pcs_ctrl |
hssi_ctp_u_wrphy_top_pma_top_3_ref_clk_mode |
ref_clk_common |
hssi_ctp_u_wrphy_top_pma_top_3_ref_clk_mplla_div2_en |
dis_mplla_div2 |
hssi_ctp_u_wrphy_top_pma_top_3_ref_clk_mpllb_div2_en |
dis_mpllb_div2 |
hssi_ctp_u_wrphy_top_pma_top_3_ref_clkdet_en |
ref_clkdet_dis |
hssi_ctp_u_wrphy_top_pma_top_3_ref_range |
3 |
hssi_ctp_u_wrphy_top_pma_top_3_rtune_req |
rtune_off |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_cont |
en_adapt_cont |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_mode_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_mode_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_mode_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_mode_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_sel_g1 |
rx_adapt_g1_sel0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_sel_g2 |
rx_adapt_g2_sel0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_sel_g3 |
rx_adapt_g3_sel0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_adapt_sel_g4 |
rx_adapt_g4_sel0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_ppm_max_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_ppm_max_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_ppm_max_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_ppm_max_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_freqband_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_freqband_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_freqband_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_freqband_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_step_ctrl_g1 |
g1_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_step_ctrl_g2 |
g2_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_step_ctrl_g3 |
g3_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_step_ctrl_g4 |
g4_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_temp_comp_en_g1 |
dis_rx_vco_temp_comp_g1 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_temp_comp_en_g2 |
dis_rx_vco_temp_comp_g2 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_temp_comp_en_g3 |
dis_rx_vco_temp_comp_g3 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_cdr_vco_temp_comp_en_g4 |
dis_rx_vco_temp_comp_g4 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_delta_iq_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_delta_iq_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_delta_iq_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_delta_iq_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_dfe_bypass_g1 |
en_dfe_bypass_g1 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_dfe_bypass_g2 |
en_dfe_bypass_g2 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_dfe_bypass_g3 |
en_dfe_bypass_g3 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_dfe_bypass_g4 |
en_dfe_bypass_g4 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_att_lvl_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_att_lvl_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_att_lvl_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_att_lvl_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_boost_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_boost_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_boost_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_boost_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_pole_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_pole_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_pole_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_ctle_pole_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_dfe_tap1_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_dfe_tap1_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_dfe_tap1_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_dfe_tap1_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga1_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga1_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga1_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga1_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga2_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga2_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga2_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_eq_vga2_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_los_lfps_en |
dis_los_lfps |
hssi_ctp_u_wrphy_top_pma_top_3_rx_los_threshold |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_margin_iq |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_offcan_cont |
en_offcan_cont |
hssi_ctp_u_wrphy_top_pma_top_3_rx_ref_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_ref_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_ref_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_ref_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_spare_bits |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_sris_mode_en |
dis_rx_sris_mode |
hssi_ctp_u_wrphy_top_pma_top_3_rx_term_acdc |
rx_term_ac |
hssi_ctp_u_wrphy_top_pma_top_3_rx_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_vco_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_vco_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_vco_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_vco_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_rx_vref_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_sim_mode |
sim_mode_dis |
hssi_ctp_u_wrphy_top_pma_top_3_sram_access_en |
clr_sram_access |
hssi_ctp_u_wrphy_top_pma_top_3_sram_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_sram_bypass |
sram_bypass_mode |
hssi_ctp_u_wrphy_top_pma_top_3_sram_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_sram_wr_rd_n |
sram_rd_access |
hssi_ctp_u_wrphy_top_pma_top_3_sup_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_sup_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_sup_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_sup_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_sup_misc_ovrd_en |
dis_sup_misc_ovrd |
hssi_ctp_u_wrphy_top_pma_top_3_sup_mode |
user_mode |
hssi_ctp_u_wrphy_top_pma_top_3_test_burnin |
burnin_off |
hssi_ctp_u_wrphy_top_pma_top_3_topology |
disabled_block |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_main_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_main_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_main_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_main_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_ovrd_g1 |
dis_g1_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_ovrd_g2 |
dis_g2_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_ovrd_g3 |
dis_g3_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_ovrd_g4 |
dis_g4_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_post_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_post_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_post_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_post_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_pre_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_pre_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_pre_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_eq_pre_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_iboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_tx_vboost_en |
en_vboost |
hssi_ctp_u_wrphy_top_pma_top_3_tx_vboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_txdn_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_3_txup_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_avmm_sel |
cfg_avmm_mode |
hssi_ctp_u_wrphy_top_pma_top_4_bs_mode |
bs_ac_mode |
hssi_ctp_u_wrphy_top_pma_top_4_bs_rx_bigswing |
dis_rx_bigswing |
hssi_ctp_u_wrphy_top_pma_top_4_bs_rx_level |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_bs_tx_lowswing |
dis_tx_lowswing |
hssi_ctp_u_wrphy_top_pma_top_4_bti_protected |
true |
hssi_ctp_u_wrphy_top_pma_top_4_cfg_phy_reset |
phy_reset_off |
hssi_ctp_u_wrphy_top_pma_top_4_cfg_phy_reset_ovrd |
phy_reset_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_4_cfg_pma_ovrd |
pma_hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_4_cfg_ref_clk_en |
ref_clk_en |
hssi_ctp_u_wrphy_top_pma_top_4_cfg_ref_clk_en_ovrd |
ref_clk_en_ovrd_dis |
hssi_ctp_u_wrphy_top_pma_top_4_cr_access_en |
clr_cr_access |
hssi_ctp_u_wrphy_top_pma_top_4_cr_para_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_cr_para_sel |
cr_jtag_intf_en |
hssi_ctp_u_wrphy_top_pma_top_4_cr_para_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_cr_wr_rd_n |
cr_rd_access |
hssi_ctp_u_wrphy_top_pma_top_4_dfd_ctrl |
csr_mode |
hssi_ctp_u_wrphy_top_pma_top_4_dfd_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_enable_rom_sram_wr |
dis_boot_rom_sram_wr |
hssi_ctp_u_wrphy_top_pma_top_4_es_mode |
standard |
hssi_ctp_u_wrphy_top_pma_top_4_ext_pclk_req |
always_on |
hssi_ctp_u_wrphy_top_pma_top_4_func_mode |
phy_disabled |
hssi_ctp_u_wrphy_top_pma_top_4_lane_off_disable |
lane_off_dis |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_div10_clk_en |
dis_mplla_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_div16p5_clk_en |
dis_mplla_div16p5_clk |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_div8_clk_en |
dis_mplla_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_div_clk_en |
dis_mplla_div_clk |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_force_en |
mplla_force_en |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_init_cal_disable |
en_mplla_init_cal |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_recal_bank_sel_ovrd_en |
dis_mplla_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_ssc_clk_sel |
mplla_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_ssc_en |
dis_mplla_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_ssc_up_spread |
mplla_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_4_mplla_tx_clk_div |
mplla_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_bandwidth |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_div10_clk_en |
dis_mpllb_div10_clk |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_div8_clk_en |
dis_mpllb_div8_clk |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_div_clk_en |
dis_mpllb_div_clk |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_div_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_force_en |
mpllb_force_en |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_fracn_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_multiplier |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_recal_bank_sel |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_recal_bank_sel_ovrd_en |
dis_mpllb_recal_bank_sel_ovrd |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_ssc_clk_sel |
mpllb_ssc_clk_sel0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_ssc_en |
dis_mpllb_ssc_mode |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_ssc_freq_cnt_init |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_ssc_freq_cnt_peak |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_ssc_up_spread |
mpllb_ssc_spread_down |
hssi_ctp_u_wrphy_top_pma_top_4_mpllb_tx_clk_div |
mpllb_tx_clk_div1 |
hssi_ctp_u_wrphy_top_pma_top_4_phy_ext_ctrl_sel |
hw_ctl_mode |
hssi_ctp_u_wrphy_top_pma_top_4_phy_sram_ext_ld_done |
clr_sram_ext_ld_done |
hssi_ctp_u_wrphy_top_pma_top_4_phy_src_sel |
mst_clk_src_phy0 |
hssi_ctp_u_wrphy_top_pma_top_4_phytop_misc_spare_control |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_powerdown_mode |
true |
hssi_ctp_u_wrphy_top_pma_top_4_powermode_ac |
disabled |
hssi_ctp_u_wrphy_top_pma_top_4_powermode_dc |
powerdown |
hssi_ctp_u_wrphy_top_pma_top_4_powermode_freq_hz |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_ppm_threshold |
13 |
hssi_ctp_u_wrphy_top_pma_top_4_quad_num |
phy_quad0 |
hssi_ctp_u_wrphy_top_pma_top_4_ref_clk_div2_en |
dis_refclk_div2 |
hssi_ctp_u_wrphy_top_pma_top_4_ref_clk_en_mode |
pcs_ctrl |
hssi_ctp_u_wrphy_top_pma_top_4_ref_clk_mode |
ref_clk_common |
hssi_ctp_u_wrphy_top_pma_top_4_ref_clk_mplla_div2_en |
dis_mplla_div2 |
hssi_ctp_u_wrphy_top_pma_top_4_ref_clk_mpllb_div2_en |
dis_mpllb_div2 |
hssi_ctp_u_wrphy_top_pma_top_4_ref_clkdet_en |
ref_clkdet_dis |
hssi_ctp_u_wrphy_top_pma_top_4_ref_range |
3 |
hssi_ctp_u_wrphy_top_pma_top_4_rtune_req |
rtune_off |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_cont |
en_adapt_cont |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_mode_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_mode_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_mode_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_mode_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_sel_g1 |
rx_adapt_g1_sel0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_sel_g2 |
rx_adapt_g2_sel0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_sel_g3 |
rx_adapt_g3_sel0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_adapt_sel_g4 |
rx_adapt_g4_sel0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_ppm_max_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_ppm_max_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_ppm_max_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_ppm_max_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_freqband_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_freqband_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_freqband_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_freqband_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_step_ctrl_g1 |
g1_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_step_ctrl_g2 |
g2_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_step_ctrl_g3 |
g3_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_step_ctrl_g4 |
g4_rx_vco_step_val0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_temp_comp_en_g1 |
dis_rx_vco_temp_comp_g1 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_temp_comp_en_g2 |
dis_rx_vco_temp_comp_g2 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_temp_comp_en_g3 |
dis_rx_vco_temp_comp_g3 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_cdr_vco_temp_comp_en_g4 |
dis_rx_vco_temp_comp_g4 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_delta_iq_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_delta_iq_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_delta_iq_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_delta_iq_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_dfe_bypass_g1 |
en_dfe_bypass_g1 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_dfe_bypass_g2 |
en_dfe_bypass_g2 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_dfe_bypass_g3 |
en_dfe_bypass_g3 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_dfe_bypass_g4 |
en_dfe_bypass_g4 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_att_lvl_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_att_lvl_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_att_lvl_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_att_lvl_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_boost_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_boost_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_boost_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_boost_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_pole_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_pole_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_pole_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_ctle_pole_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_dfe_tap1_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_dfe_tap1_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_dfe_tap1_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_dfe_tap1_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga1_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga1_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga1_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga1_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga2_gain_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga2_gain_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga2_gain_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_eq_vga2_gain_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_los_lfps_en |
dis_los_lfps |
hssi_ctp_u_wrphy_top_pma_top_4_rx_los_threshold |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_margin_iq |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_offcan_cont |
en_offcan_cont |
hssi_ctp_u_wrphy_top_pma_top_4_rx_ref_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_ref_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_ref_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_ref_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_spare_bits |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_sris_mode_en |
dis_rx_sris_mode |
hssi_ctp_u_wrphy_top_pma_top_4_rx_term_acdc |
rx_term_ac |
hssi_ctp_u_wrphy_top_pma_top_4_rx_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_vco_ld_val_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_vco_ld_val_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_vco_ld_val_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_vco_ld_val_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_rx_vref_ctrl |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_sim_mode |
sim_mode_dis |
hssi_ctp_u_wrphy_top_pma_top_4_sram_access_en |
clr_sram_access |
hssi_ctp_u_wrphy_top_pma_top_4_sram_addr |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_sram_bypass |
sram_bypass_mode |
hssi_ctp_u_wrphy_top_pma_top_4_sram_wr_data |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_sram_wr_rd_n |
sram_rd_access |
hssi_ctp_u_wrphy_top_pma_top_4_sup_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_sup_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_sup_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_sup_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_sup_misc_ovrd_en |
dis_sup_misc_ovrd |
hssi_ctp_u_wrphy_top_pma_top_4_sup_mode |
user_mode |
hssi_ctp_u_wrphy_top_pma_top_4_test_burnin |
burnin_off |
hssi_ctp_u_wrphy_top_pma_top_4_topology |
disabled_block |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_main_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_main_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_main_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_main_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_ovrd_g1 |
dis_g1_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_ovrd_g2 |
dis_g2_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_ovrd_g3 |
dis_g3_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_ovrd_g4 |
dis_g4_eq_ovrd |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_post_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_post_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_post_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_post_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_pre_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_pre_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_pre_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_eq_pre_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_iboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_misc_g1 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_misc_g2 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_misc_g3 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_misc_g4 |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_tx_vboost_en |
en_vboost |
hssi_ctp_u_wrphy_top_pma_top_4_tx_vboost_lvl |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_txdn_term_offset |
0 |
hssi_ctp_u_wrphy_top_pma_top_4_txup_term_offset |
0 |
hssi_ctp_u_wrtilectrl_cfg_ip_sec |
no_access |
hssi_ctp_u_wrtilectrl_corepll_hw_mode_bypass |
hw_mode_bypass_dis |
hssi_ctp_u_wrtilectrl_func_mode |
pcie_g4_x16_ep |
hssi_ctp_u_wrtilectrl_hrc_clk_sel |
hrc_sel_div4 |
hssi_ctp_u_wrtilectrl_hw_mode_decode |
disabled |
hssi_ctp_u_wrtilectrl_hw_mode_enable |
hw_mode_disable |
hssi_ctp_u_wrtilectrl_op_mode |
pwr_down |
hssi_ctp_u_wrtilectrl_pcie_cvp_src_clk_sel |
pcie_cvp_src_sel_div1 |
hssi_ctp_u_wrtilectrl_powerdown_mode |
true |
hssi_ctp_u_wrtilectrl_powermode_ac |
powerdown_ac |
hssi_ctp_u_wrtilectrl_powermode_dc |
powerdown_dc |
hssi_ctp_u_wrtilectrl_powermode_freq_hz |
250000000 |
hssi_ctp_u_wrtilectrl_pvt_div_cnt_threshold |
pvt_div_40 |
hssi_ctp_u_wrtilectrl_sup_mode |
user_mode |
hssi_ctp_u_wrtilectrl_topology |
disabled_block |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_actreden |
aibaux_actreden_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_asyn_rxen |
aibaux_asyn_rxen_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_asyn_txen |
aibaux_asyn_txen_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_cndn_cken |
aibaux_cndn_cken_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_cndn_rxen |
aibaux_cndn_rxen_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_cnup_txen |
aibaux_cnup_txen_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_dll_osc_cr_dftsel |
aibaux_dll_osc_cr_dftsel_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_dly_ovrd_cnocdn |
aibaux_dly_ovrd_cnocdn_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_dly_ovrd_cnocup |
aibaux_dly_ovrd_cnocup_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_dly_ovrden_cnocdn |
aibaux_dly_ovrden_cnocdn_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_dly_ovrden_cnocup |
aibaux_dly_ovrden_cnocup_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_iocsr_sel |
aibaux_iocsrsel_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_jtag_bypass |
aibaux_jtagbyp_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_ndrv |
aibaux_ndrv_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_atbmuxsel |
aibaux_osc_atbmuxsel_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_bypclken |
aibaux_osc_bypclken_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_cr_dftcounter |
aibaux_osc_cr_dftcounter_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_cr_ld_cntr |
aibaux_osc_cr_ld_cntr_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_cr_pdb |
aibaux_osc_cr_pdb_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_cr_spare |
aibaux_osc_cr_spare_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_cr_trim |
aibaux_osc_cr_trim_setting3 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_cr_vccdreg_vsel |
aibaux_osc_cr_vccdreg_vsel_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_cr_vreg_rdy |
aibaux_osc_cr_vreg_rdy_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_monitoren |
aibaux_osc_monitoren_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_osc_reserved |
aibaux_osc_reserved_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_pdrv |
aibaux_pdrv_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_pred_rxen |
aibaux_pred_rxen_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_pred_txen |
aibaux_pred_txen_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_spare0_bus0 |
aibaux_spare0_bus0_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_spare0_bus1 |
aibaux_spare0_bus1_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_spare0_bus2 |
aibaux_spare0_bus2_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_spare1_bus0 |
aibaux_spare1_bus0_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_aibaux_spare1_bus2 |
aibaux_spare1_bus2_setting0 |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_dft_aux_en |
disable_dft |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_dft_dll_osc_dftsel |
disable_dll_osc_dftsel |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_dft_osc_dftcounter |
disable_osc_dftcounter |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_op_mode |
pwr_down |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_powermode_ac |
disable_pwr |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_powermode_dc |
powerdown |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_redundancy_en |
disable |
hssi_ctp_u_wrtilectrl_u_aibwraux_top_wrp_sup_mode |
user_mode |
hssi_ctp_u_wrupi_top_powerdown_mode |
true |
hssi_ctp_u_wrupi_top_powermode_ac |
disabled |
hssi_ctp_u_wrupi_top_powermode_dc |
powerdown |
hssi_ctp_u_wrupi_top_powermode_freq_hz |
250 |
hssi_ctp_u_wrupi_top_u_upi_core_func_mode |
disabled |
hssi_ctp_u_wrupi_top_u_upi_core_lpbk_mode |
lpbk_disable |
hssi_ctp_u_wrupi_top_u_upi_core_powerdown_mode |
true |
hssi_ctp_u_wrupi_top_u_upi_core_sim_mode |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_sup_mode |
user_mode |
hssi_ctp_u_wrupi_top_u_upi_core_topology |
disabled_block |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_ack_rtrn_use_slot2_thre |
8 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_aib_dbg_ll_phy_sel |
send_ll_dbg |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_aib_dbg_sync_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_cache_ch_intrv_bit_l |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_cache_ch_intrv_bit_u |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_clk_en |
disable_clk |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_clr_rx_dbg_cnt |
dis_clr_rx_dbg_cnt |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_clr_tx_dbg_cnt |
dis_clr_tx_dbg_cnt |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_crd_setting |
crd_setting1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_debug_en |
disable_dbg_flit |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_deskew_rx_vld |
rx_dsk_vld |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_dfd_ll_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_dfd_sel |
from_dfd_ctrl |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_dis_phy_dbg_b4_ll_init |
en_phy_dbg |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_eco_0 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_eco_1 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_eco_2 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_eco_3 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_force_dsk_vld |
no_force_dsk_vld |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_force_unfreeze_sr_avmm |
no_force_unfreeze_sr_avmm |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_force_unfreeze_tx_rx_sync |
no_force_unfreeze_tx_rx |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_fpga_bus_num |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_fpga_bus_num_valid |
invalid_bus_num |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_func0_cfg_en |
func0_csr_unlock |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_func1_cfg_en |
func1_csr_unlock |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_func_mode |
disable_func_mode |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_inband_en |
enable_inband |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_inband_no_wait_fpga |
inband_wait_fpga |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_init_stall |
disable_init_stall |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_ll_rst |
disable_ll_rst |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_ll_rst_phy_en |
enable_phy_rst |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_lrsm_wait_tx_normal_op |
no_wait_tx_normal_op |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_max_phy_abort |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_max_retry |
15 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_node_id_csr |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_node_id_sel |
from_strap_pin |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_pld_avmm_en |
enable_pld_avmm |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_pld_avmm_snapshot_err_en |
dis_pld_avmm_snapshot_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_pll_lock_lost_en |
en_pll_lock_lost |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_poison_rcvd_en |
dis_poison_rcvd |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_powerdown_mode |
true |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_retry_timeout |
disable_retry_to |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rtry_buf_ok_llcrd_thre |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rtry_buf_ok_thre |
8 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_crc_err_en |
dis_rx_crc_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_crc_err_inj_mode |
dis_rx_crc_err_inj |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ctrl_p1_en |
en_rx_p1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ctrl_p2_en |
dis_rx_p2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ctrl_p3_en |
dis_rx_p3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ctrl_p4_en |
dis_rx_p4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ctrl_p5_en |
dis_rx_p5 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_dsk_pulse_per_2x |
rx_dsk_pulse_64 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ecc_enc_en |
bypass_rx_ecc |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_flit_static_err_en |
en_rx_flit_static_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_halt_upon_fatal |
en_rx_halt |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_illegal_llctrl_slot12_err_en |
en_rx_illegal_llctrl_slot12_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_illegal_vn0_flit_err_en |
en_rx_illegal_vn0_flit_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_llctrl_dbg_err_en |
dis_rx_llctrl_dbg_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_llctrl_err_en |
dis_rx_llctrl_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncb_be_orun_en |
en_rx_ncb_be_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncb_be_par_en |
en_rx_ncb_be_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncb_be_urun_en |
en_rx_ncb_be_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbd_orun_en |
en_rx_ncbd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbd_par_0_en |
en_rx_ncbd_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbd_par_1_en |
en_rx_ncbd_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbd_par_2_en |
en_rx_ncbd_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbd_urun_en |
en_rx_ncbd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbh_orun_en |
en_rx_ncbh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbh_par_en |
en_rx_ncbh_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncbh_urun_en |
en_rx_ncbh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncs_be_orun_en |
en_rx_ncs_be_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncs_be_par_en |
en_rx_ncs_be_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncs_be_urun_en |
en_rx_ncs_be_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsd_orun_en |
en_rx_ncsd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsd_par_0_en |
en_rx_ncsd_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsd_par_1_en |
en_rx_ncsd_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsd_par_2_en |
en_rx_ncsd_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsd_urun_en |
en_rx_ncsd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsh_orun_en |
en_rx_ncsh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsh_par_0_en |
en_rx_ncsh_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsh_par_1_en |
en_rx_ncsh_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_ncsh_urun_en |
en_rx_ncsh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_nonzero_rsvd_field_err_en |
en_rx_nonzero_rsvd_field_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rcvd_rsvd_op |
en_rx_rcvd_rsvd_op |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_req_orun_en |
en_rx_req_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_req_par_0_en |
en_rx_req_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_req_par_1_en |
en_rx_req_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_req_par_2_en |
en_rx_req_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_req_par_3_en |
en_rx_req_par_3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_req_urun_en |
en_rx_req_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspcd_orun_en |
en_rx_rspcd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspcd_par_en |
en_rx_rspcd_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspcd_urun_en |
en_rx_rspcd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspch_orun_en |
en_rx_rspch_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspch_par_en |
en_rx_rspch_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspch_urun_en |
en_rx_rspch_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspod_orun_en |
en_rx_rspod_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspod_par_0_en |
en_rx_rspod_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspod_par_1_en |
en_rx_rspod_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspod_par_2_en |
en_rx_rspod_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspod_urun_en |
en_rx_rspod_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspoh_orun_en |
en_rx_rspoh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspoh_par_0_en |
en_rx_rspoh_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspoh_par_1_en |
en_rx_rspoh_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspoh_urun_en |
en_rx_rspoh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspu_orun_en |
en_rx_rspu_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspu_urun_en |
en_rx_rspu_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspuh_par_0_en |
en_rx_rspuh_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspuh_par_1_en |
en_rx_rspuh_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspuh_par_2_en |
en_rx_rspuh_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rspuh_par_3_en |
en_rx_rspuh_par_3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_rtry_abort_err_en |
en_rx_rtry_abort_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_snp_orun_en |
en_rx_snp_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_snp_par_0_en |
en_rx_snp_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_snp_par_1_en |
en_rx_snp_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_snp_urun_en |
en_rx_snp_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_unexpected_poison_err_en |
en_rx_unexpected_poison_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_unexpected_rtry_ack_err_en |
en_rx_unexpected_rtry_ack_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_viral_rcvd_en |
dis_rx_viral_rcvd |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_vn01_crd_err_en |
en_rx_vn01_crd_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_vn0_err_en |
en_rx_vn0_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_vn1_err_en |
en_rx_vn1_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_vna_err_en |
en_rx_vna_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wb_be_orun_en |
en_rx_wb_be_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wb_be_par_en |
en_rx_wb_be_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wb_be_urun_en |
en_rx_wb_be_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbd_orun_en |
en_rx_wbd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbd_par_0_en |
en_rx_wbd_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbd_par_1_en |
en_rx_wbd_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbd_par_2_en |
en_rx_wbd_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbd_urun_en |
en_rx_wbd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbh_orun_en |
en_rx_wbh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbh_par_0_en |
en_rx_wbh_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbh_par_1_en |
en_rx_wbh_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_rx_wbh_urun_en |
en_rx_wbh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_dbg_cnt_clr |
no_clr_sa_dbg_cnt |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_en |
dis_sa |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_full_thre |
224 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_halt_upon_fatal |
en_sa_halt |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_mode |
sa_use_fpga_ad |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_page_size |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt0_cnt_orun_en |
en_sa_pt0_cnt_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt0_cnt_urun_en |
en_sa_pt0_cnt_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt0_orun_en |
en_sa_pt0_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt0_par_en |
en_sa_pt0_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt1_cnt_orun_en |
en_sa_pt1_cnt_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt1_cnt_urun_en |
en_sa_pt1_cnt_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt1_orun_en |
en_sa_pt1_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt1_par_en |
en_sa_pt1_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt2_cnt_orun_en |
en_sa_pt2_cnt_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt2_cnt_urun_en |
en_sa_pt2_cnt_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt2_orun_en |
en_sa_pt2_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt2_par_en |
en_sa_pt2_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt3_cnt_orun_en |
en_sa_pt3_cnt_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt3_cnt_urun_en |
en_sa_pt3_cnt_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt3_orun_en |
en_sa_pt3_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_pt3_par_en |
en_sa_pt3_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_rsvd_fpga_ad_op_en |
en_sa_rsvd_fpga_ad_op |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_rsvd_sw_ad_op_en |
en_sa_rsvd_sw_ad_op |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_sad_src |
sad_from_csr |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_snp0_sad_en |
en_sa_snp0_sad |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_snp1_sad_en |
en_sa_snp1_sad |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_buf_full_thre |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_rsp_orun_en |
en_sa_tx_rsp_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_rsp_par_0_en |
en_sa_tx_rsp_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_rsp_par_1_en |
en_sa_tx_rsp_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_rsp_urun_en |
en_sa_tx_rsp_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_snp_orun_en |
en_sa_tx_snp_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_snp_par_0_en |
en_sa_tx_snp_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_snp_par_1_en |
en_sa_tx_snp_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sa_tx_snp_urun_en |
en_sa_tx_snp_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_send_flit_over_aib |
dis_send_flit_over_aib |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_send_tx_rx_flit |
send_tx_flit |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_slot0_data_msg_over_nondata |
slot0_data_same_nondata |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_slot1_dis |
en_slot1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_slot2_dis |
en_slot2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_snapshot_en |
enable_snapshot |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_sup_mode |
user_mode |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_topology |
disabled_block |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p0_data_0_en |
dis_tx_1becc_p0_data_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p0_data_1_en |
dis_tx_1becc_p0_data_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p0_data_2_en |
dis_tx_1becc_p0_data_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p0_data_3_en |
dis_tx_1becc_p0_data_3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p0_header_en |
dis_tx_1becc_p0_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p1_header_en |
dis_tx_1becc_p1_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p2_header_en |
dis_tx_1becc_p2_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p3_header_en |
dis_tx_1becc_p3_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p4_header_en |
dis_tx_1becc_p4_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_1becc_p5_header_en |
dis_tx_1becc_p5_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p0_data_0_en |
dis_tx_2becc_p0_data_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p0_data_1_en |
dis_tx_2becc_p0_data_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p0_data_2_en |
dis_tx_2becc_p0_data_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p0_data_3_en |
dis_tx_2becc_p0_data_3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p0_header_en |
dis_tx_2becc_p0_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p1_header_en |
dis_tx_2becc_p1_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p2_header_en |
dis_tx_2becc_p2_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p3_header_en |
dis_tx_2becc_p3_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p4_header_en |
dis_tx_2becc_p4_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_2becc_p5_header_en |
dis_tx_2becc_p5_header |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_buf_full_thre |
32 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_crc_err_inj_mode |
dis_tx_crc_err_inj |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_deskew_lock_err_en |
en_tx_deskew_lock_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_dsk_clr |
tx_dsk_clr_invld |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ecc_dec_en |
bypass_tx_ecc |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_halt_upon_fatal |
en_tx_halt |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_hold_crd |
disable_tx_hold_crd |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_init_rsvd_after_init_done_err_en |
en_tx_init_rsvd_after_init_done_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ll_lp0_fw_agent |
fw_agent_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ll_lp0_lt_agent |
lt_agent_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ll_lp0_port_num |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ll_lp0_sku_type |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ll_lp0_upi_ver |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncb_be_orun_en |
en_tx_ncb_be_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncb_be_par_en |
en_tx_ncb_be_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncb_be_urun_en |
en_tx_ncb_be_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbd_orun_en |
en_tx_ncbd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbd_par_0_en |
en_tx_ncbd_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbd_par_1_en |
en_tx_ncbd_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbd_par_2_en |
en_tx_ncbd_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbd_urun_en |
en_tx_ncbd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbh_orun_en |
en_tx_ncbh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbh_par_en |
en_tx_ncbh_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncbh_urun_en |
en_tx_ncbh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncs_be_orun_en |
en_tx_ncs_be_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncs_be_par_en |
en_tx_ncs_be_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncs_be_urun_en |
en_tx_ncs_be_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsd_orun_en |
en_tx_ncsd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsd_par_0_en |
en_tx_ncsd_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsd_par_1_en |
en_tx_ncsd_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsd_par_2_en |
en_tx_ncsd_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsd_urun_en |
en_tx_ncsd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsh_orun_en |
en_tx_ncsh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsh_par_en |
en_tx_ncsh_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_ncsh_urun_en |
en_tx_ncsh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_poison_en |
en_tx_poison |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_req_orun_en |
en_tx_req_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_req_par_0_en |
en_tx_req_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_req_par_1_en |
en_tx_req_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_req_par_2_en |
en_tx_req_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_req_par_3_en |
en_tx_req_par_3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_req_urun_en |
en_tx_req_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspcd_orun_en |
en_tx_rspcd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspcd_par_0_en |
en_tx_rspcd_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspcd_par_1_en |
en_tx_rspcd_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspcd_par_2_en |
en_tx_rspcd_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspcd_urun_en |
en_tx_rspcd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspch_orun_en |
en_tx_rspch_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspch_par_en |
en_tx_rspch_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspch_urun_en |
en_tx_rspch_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspod_orun_en |
en_tx_rspod_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspod_par_0_en |
en_tx_rspod_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspod_par_1_en |
en_tx_rspod_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspod_par_2_en |
en_tx_rspod_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspod_urun_en |
en_tx_rspod_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspoh_orun_en |
en_tx_rspoh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspoh_par_en |
en_tx_rspoh_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspoh_urun_en |
en_tx_rspoh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspu_orun_en |
en_tx_rspu_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspu_par_0_en |
en_tx_rspu_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspu_par_1_en |
en_tx_rspu_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspu_par_2_en |
en_tx_rspu_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspu_par_3_en |
en_tx_rspu_par_3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rspu_urun_en |
en_tx_rspu_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rtry_err_en |
en_tx_rtry_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rtry_orun_en |
en_tx_rtry_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rtry_par_0_en |
en_tx_rtry_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rtry_par_1_en |
en_tx_rtry_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_rtry_urun_en |
en_tx_rtry_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_snp_orun_en |
en_tx_snp_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_snp_par_0_en |
en_tx_snp_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_snp_par_1_en |
en_tx_snp_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_snp_urun_en |
en_tx_snp_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_vld_flit_rsvd_b4init_done_err_en |
en_tx_vld_flit_rsvd_b4init_done_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_vn0_crd_err_en |
en_tx_vn0_crd_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_vna_crd_err_en |
en_tx_vna_crd_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_vna_ok_thre |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wb_be_orun_en |
en_tx_wb_be_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wb_be_par_en |
en_tx_wb_be_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wb_be_urun_en |
en_tx_wb_be_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbd_orun_en |
en_tx_wbd_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbd_par_0_en |
en_tx_wbd_par_0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbd_par_1_en |
en_tx_wbd_par_1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbd_par_2_en |
en_tx_wbd_par_2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbd_urun_en |
en_tx_wbd_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbh_orun_en |
en_tx_wbh_orun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbh_par_en |
en_tx_wbh_par |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_tx_wbh_urun_en |
en_tx_wbh_urun |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vn0_crd_rtrn_op_en |
en_vn0_crd_rtrn_op |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vn0_ncb_stall |
enable_vn0_ncb_refund |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vn0_ncs_stall |
enable_vn0_ncs_refund |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vn0_req_stall |
enable_vn0_req_refund |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vn0_rsp_stall |
enable_vn0_rsp_refund |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vn0_snp_stall |
enable_vn0_snp_refund |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vn0_wb_stall |
enable_vn0_wb_refund |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vna_rtrn_use_slot2_thre |
8 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_vna_stall |
enable_vna_refund |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_wait_count_2x |
rtry_wait_cnt_16 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upilink_agent_wait_proc_init |
no_wait_proc_init |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_cis_spdetect |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_cis_sprxcalib |
true |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_cis_spsshold |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_cis_sptxcalib |
true |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_cis_spusebackchannel |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_cls_sl1rerr |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_cls_spdriftalarm |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cate |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_ccompbypen |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cdeten |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cdetslave |
detmst |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cenablephyresetd |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cenablephyresetw |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cenhqualen |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cfailoveren |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cfia |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cinit |
init_l0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cinitbegin |
no_blockexit_resetc |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cl0pen |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cl1en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_claloaddisable |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_clatfixen |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cnuminit |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_copspeed |
cslow |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_cpreset |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_crctermsoff |
off |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_creinitprbs |
noreinit |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_crxresetdis |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr1_csinglestep |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr2_csbbackchannel |
slow_backch |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr2_ctxadapten |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr2_ctxadaptpat |
l0prbs |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ctr2_ctxadaptsettings |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_func_mode |
upi_x20_11p2g |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ldc_cdriftalarmthreshold |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ldc_cdriftdepth |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ldc_ctargetlatency |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_loopback_mode |
lpbk_disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_sinitcountp |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_sinitfailp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_slinkupp |
no_linkup |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_sopspeedp |
sslow |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_spdetectp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_sprxcalibp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_spssholdp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_sptxadaptp |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_sptxcalibp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_spusebackchannelp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_sremotelbmp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_srxlanerevp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pis_swakedetectedp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_sdriftalarmlaneaddressp |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_sl0pefailp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_sl0pelataddp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_sl0pelatsubp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_sl1npendp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_sl1rerrp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_sl1routp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_smml0cp |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_spdriftalarmp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_srcvdl0cp |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_srstrcvdp |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pls_ssentl0cp |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_powerdown_mode |
true |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pss_sclmp |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pss_srxstatep |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_pss_stxstatep |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_rdc_crxdatalanedisable |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_sim_mode |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_slow_mode |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_sup_mode |
user_mode |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tdc_ctxdatalanedisable |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tec_claneaddress |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0c_op_tl0c |
33 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0c_op_tl0cq |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0c_op_tl1reissuedelay |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0c_sl_tl0c |
33 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0c_sl_tl0cq |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0c_sl_tl1reissuedelay |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0centry_op_tieo |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0centry_sl_tieo |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentryrx_tl0prxenter2block |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentryrx_tl0prxenter2tran |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentryrx_tl0prxtran2done |
100 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentryrx_tl0prxtran2unblock |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentrytx_tl0ptxenter2null |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentrytx_tl0ptxenter2tran |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentrytx_tl0ptxnullstart2nullstop |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pentrytx_tl0ptxtran2done |
100 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexitrx_tl0pest |
39 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexitrx_tl0prxnullsexitsq |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexitrx_tl0prxnullswidthchg |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexitrx_tl0prxsds2widthchg |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxact_tl0ptxexitend2l0c |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxact_tl0ptxnullsexitsq |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxact_tl0ptxnullsexittran |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxact_tl0ptxsqend2sds |
30 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxidl_tl0ptxexit2next |
32 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxidl_tl0ptxnull2firston |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxidl_tl0ptxpat |
38 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxidl_tl0ptxsbpa |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl0pexittxidl_tl0ptxsds2widthchg |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl1entry_tl1minres |
74 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl1entry_tl1txenter2firstoff |
15 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tl1entry_tl1txfirstoff2lastoff |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_topology |
disabled_system |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_op_ntdr |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_op_ntdt |
12 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_op_trc |
11 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_op_trdb |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_op_trs |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_op_ttc |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_sl_ntdr |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_sl_ntdt |
12 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_sl_trc |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_sl_trdb |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_sl_trs |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tpri_sl_ttc |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_tcfst |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_tclst |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_tlmst |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_tplst |
10 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_trcst |
10 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_trdst |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_ttcst |
9 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_op_ttdst |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_tcfst |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_tclst |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_tlmst |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_tplst |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_trcst |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_trdst |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_ttcst |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tsec_sl_ttdst |
4 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttddc_txdcdatalanecontrol |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttlcs_srxloopcount |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttleo_rxlaneerroverflowstatus |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpcc_exterrcntalllanes |
perlane |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpcc_exterrcntrlaneassign |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpcc_rxerrcntrlanesel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpcc_selerrchckinterval |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpcc_selerrchckstart |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpcc_tinitialcheckmask |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpg2s_laneselpatbuffer2 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgb_patgenbuffer |
2863311530 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_autoinvrotateen |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_cerrorcountinhibit |
normal_err |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_cincludedroppedlanes |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_cloopcount |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_cpstarttest |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_cpstoptest |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_cstoptestonerror |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_drdc0insteadof1 |
drive1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_ignoreremoteparam |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_lpcntrinhibit |
normal_pat |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_patbufselection |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_polyselect |
spec |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_pseudorandomen1 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_pseudorandomen2 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpgc_rotatepatbufsel |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttpis_patterninvert |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttppg_creinitlfsr |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttrec_rxlaneerrcheckdisable |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttres_rxlaneerrstatus |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttsnl_loopback_path |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tttec_cpstarttest |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tttec_cpstoptest |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tttec_startdelayselindex_ph_ttted |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_ttted_ttestdelayctrl0 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_tttls_stxloopcount |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_adapt_deemph_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_adapt_deemph_wr |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_adapt_rxeqeval |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_adapt_tx_deemph |
2140 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_clm_unsup |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_clm_unsup_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_init_abort_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_l0c_biterr_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_l0c_mismatch_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_l0c_unsup_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_l0p_exiterr_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_phy_err_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_rst_lw_change_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_rst_lw_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_rxfifo_ecc_cor_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_en_txfifo_ecc_cor_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_init_abort |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_l0c_biterr |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_l0c_mismatch |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_l0c_unsup |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_l0p_exiterr |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_phy_err |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_rst_lw |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_rst_lw_change |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_rxfifo_ecc_cor |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ce_int_txfifo_ecc_cor |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_driftbuffer_ll |
13 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_driftbuffer_ul |
2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_intreset_drift |
fifo |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_intreset_los |
intrst_all |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_rxdetect_sel |
sigdetect_rx |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_rxfifo_latency |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_sigdet_b2b_cnt |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_smhysteresis |
31 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_smrxlockuicnt |
qual1kui |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_smuitoggle |
det8x |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_txdetect_sel |
cdrlock_tx |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_txdetect_sel_sl |
eyelock |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctr_wordlock_pass |
det3tslock |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr10 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr11 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr12 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr13 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr14 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr15 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr16 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr17 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr18 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr19 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr2 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr20 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr21 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr22 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr23 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr24 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr25 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr26 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr27 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr28 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr29 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr3 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr30 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr31 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr4 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr5 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr6 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr7 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr8 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_ctovr9 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ctrovr_deskew_limit |
limit64ui |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_errcnt0_en_errcnt0_en |
155 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_errcnt0_sts_errcnt0 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_errcnt0_sts_errcnt0_ovf |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_errcnt1_en_errcnt1_en |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_errcnt1_sts_errcnt1 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_errcnt1_sts_errcnt1_ovf |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_pcie_func0_0_did |
48322 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_pcie_func1_0_did |
48323 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_phylane_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_phyovr_wr |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_powerdown_ovr |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_powerdown_ovren |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_rx_lpd_ovr |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_rx_lpd_ovren |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_rx_standby_ovr |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_rx_standby_ovren |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_rx_termination_ovr |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_rx_termination_ovren |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_tx_elecidle_ovr |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_tx_elecidle_ovren |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_tx_lpd_ovr |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phovr_tx_lpd_ovren |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx0_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx10_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx11_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx12_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx13_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx14_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx15_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx16_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx17_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx18_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx19_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx1_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx2_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx3_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx4_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx5_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx6_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx7_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx8_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_phystat_rx9_phystat |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx0_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx10_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx11_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx12_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx13_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx14_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx15_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx16_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx17_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx18_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx19_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx1_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx2_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx3_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx4_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx5_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx6_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx7_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx8_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmcnt_sts_rx9_ppmcnt |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppm_threshold |
3800 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmdetect_dis |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmdetect_sel |
eyelock_asrt |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr15 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr18 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr19 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr20 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr21 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr22 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr23 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr24 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr25 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmovr27 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmtrack_dis |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmctr_ppmtrack_limit |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmlane_ppmlane_sel0 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmlane_ppmlane_sel1 |
1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmlane_ppmlane_spare |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx0_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx10_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx11_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx12_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx13_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx14_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx15_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx16_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx17_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx18_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx19_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx1_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx2_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx3_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx4_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx5_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx6_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx7_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx8_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ppmtrack_sts_rx9_ppmtrack |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx0_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx10_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx11_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx12_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx13_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx14_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx15_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx16_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx17_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx18_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx19_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx1_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx2_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx3_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx4_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx5_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx6_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx7_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx8_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxeiosrcvd_rx9_eiosrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx0_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx10_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx11_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx12_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx13_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx14_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx15_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx16_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx17_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx18_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx19_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx1_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx2_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx3_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx4_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx5_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx6_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx7_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx8_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxsdsrcvd_rx9_sdsrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx0_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx10_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx11_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx12_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx13_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx14_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx15_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx16_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx17_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx18_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx19_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx1_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx2_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx3_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx4_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx5_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx6_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx7_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx8_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts1_ackrcvd_rx9_ts1ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx0_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx10_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx11_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx12_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx13_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx14_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx15_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx16_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx17_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx18_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx19_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx1_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx2_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx3_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx4_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx5_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx6_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx7_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx8_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_rxts2_ackrcvd_rx9_ts2ackrcvd |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_sec_region_lock |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_block_newoffset |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smedgedet_mode |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smhysteresis_ppm |
20 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smignore_err_ppm |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr13 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr21 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr22 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr23 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr24 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr25 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr26 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr27 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr28 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr29 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr30 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr31 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr5 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smovr9 |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smrxlockuicnt_ppm |
6 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smuitoggle_ppm |
2 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_smctr_smzero_ppm |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_topology_func_mode |
3 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_ctrl_debug_en |
output0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_ctrl_dfd_csr_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_ctrl_l0xbar_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_ctrl_l1xbar_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_ctrl_trig0_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_ctrl_trig1_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw0_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw1_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw2_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw3_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw4_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw5_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw6_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_0_l0dw7_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw10_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw11_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw12_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw13_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw14_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw15_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw8_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_1_l0dw9_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw16_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw17_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw18_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw19_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw20_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw21_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw22_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_2_l0dw23_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_3_l0dw24_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_3_l0dw25_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_3_l0dw26_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l0mux_3_l0dw27_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l1mux_0_l1w0_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l1mux_0_l1w1_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l1mux_0_l1w2_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l1mux_0_l1w3_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l1mux_1_l1w4_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l1mux_1_l1w5_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttdfd_l1mux_1_l1w6_sel |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_dlbskew_l0 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_dlbskew_l1 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_dlbskew_l2 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_dlbskew_l3 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_f1_cdrlock |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_f1_sigdet |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_lb_rdlatency |
read_1cyc |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_0_3_lbmode |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l12 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l13 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l14 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l15 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l16 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l17 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l18 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_12_19_dlbskew_l19 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l10 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l11 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l4 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l5 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l6 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l7 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l8 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlb_4_11_dlbskew_l9 |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlmon_ctr_lmon_start |
stop |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlmon_ctr_lmon_stop |
cond1 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ttlmon_ctr_maxbin_limit |
0 |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_txts_sent_tx0_ts1naksent |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_txts_sent_tx1_ts1acksent |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_txts_sent_tx2_ts2naksent |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_txts_sent_tx3_ts2acksent |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_deskew_err |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_driftbuffer_alarm |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_deskew_err_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_driftbuffer_alarm_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_ibist_err_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_initcnt_exceed_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_ppm_exceed_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_rxfifo_ecc_uncor_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_rxfifo_ovrwr_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_skew_exceed_en |
enable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_txfifo_ecc_uncor_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_en_txfifo_ovrwr_en |
disable |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_ibist_err |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_initcnt_exceed |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_ppm_exceed |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_rxfifo_ecc_uncor |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_rxfifo_ovrwr |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_skew_exceed |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_txfifo_ecc_uncor |
false |
hssi_ctp_u_wrupi_top_u_upi_core_u_upiphy_agent_whr_ue_int_txfifo_ovrwr |
false |
hssi_ctp_silicon_rev |
14nm4awhra |
core16_use_ast_parity_hwtcl |
0 |
core16_enable_external_dma_hwtcl |
0 |
core16_read_mover_address_width_hwtcl |
64 |
core16_write_mover_address_width_hwtcl |
64 |
core16_enable_advanced_interrupt_hwtcl |
0 |
core16_bursting_master_address_width_hwtcl |
64 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |