2022.07.20.10:13:28 |
Datasheet |
Overview
Memory Map
BAR_INTERPRETER
intel_pcie_bri v19.1
dut
|
p0_bam_master |
BAR_INTERPRETER |
bri_slave |
p0_app_clk |
clk |
p0_bam_conduit |
bri_conduit |
p0_app_reset_status_n |
reset |
|
|
bri_master |
DMA_CONTROLLER
|
|
|
dma_msix_slave |
|
|
bri_master |
|
|
dma_slave |
|
|
|
bri_master |
mm_bridge_bar4
|
|
|
s0 |
Software Assignments(none) |
DMA_CONTROLLER
intel_pcie_dma v19.1
BAR_INTERPRETER
|
bri_master |
DMA_CONTROLLER |
dma_msix_slave |
bri_master |
dma_slave |
|
mm_bridge_dma_controller
|
m0 |
dma_slave |
|
dut
|
p0_rddm_tx |
rddm_tx |
p0_wrdm_tx |
wrdm_tx |
p0_app_clk |
clk |
p0_rddm_conduit |
rddm_conduit |
p0_wrdm_conduit |
wrdm_conduit |
p0_app_reset_status_n |
reset |
|
|
rddm_desc |
dut
|
|
|
p0_rddm_desc |
|
|
rddm_prio |
|
|
p0_rddm_prio |
|
|
wrdm_desc |
|
|
p0_wrdm_desc |
|
|
wrdm_prio |
|
|
p0_wrdm_prio |
Software Assignments(none) |
dut
intel_pcie_ptile_avmm v4.0.0
DMA_CONTROLLER
|
rddm_desc |
dut |
p0_rddm_desc |
rddm_prio |
p0_rddm_prio |
wrdm_desc |
p0_wrdm_desc |
wrdm_prio |
p0_wrdm_prio |
|
resetIP
|
ninit_done |
ninit_done |
|
|
p0_bam_master |
BAR_INTERPRETER
|
|
|
bri_slave |
|
|
p0_app_clk |
|
|
clk |
|
|
p0_bam_conduit |
|
|
bri_conduit |
|
|
p0_app_reset_status_n |
|
|
reset |
|
|
|
p0_rddm_master |
mm_bridge_dma_controller
|
|
|
s0 |
|
|
p0_app_clk |
|
|
clk |
|
|
p0_app_reset_status_n |
|
|
reset |
|
|
|
p0_rddm_master |
mm_bridge_onchip_mem
|
|
|
s0 |
|
|
p0_app_clk |
|
|
clk |
|
|
p0_app_reset_status_n |
|
|
reset |
|
|
|
p0_wrdm_master |
mem
|
|
|
s1 |
|
|
p0_app_clk |
|
|
clk1 |
|
|
p0_app_reset_status_n |
|
|
reset1 |
|
|
|
p0_rddm_tx |
DMA_CONTROLLER
|
|
|
rddm_tx |
|
|
p0_wrdm_tx |
|
|
wrdm_tx |
|
|
p0_app_clk |
|
|
clk |
|
|
p0_rddm_conduit |
|
|
rddm_conduit |
|
|
p0_wrdm_conduit |
|
|
wrdm_conduit |
|
|
p0_app_reset_status_n |
|
|
reset |
|
|
|
p0_app_clk |
pio_led
|
|
|
clk |
|
|
p0_app_reset_status_n |
|
|
reset |
|
|
|
p0_app_clk |
pio_button
|
|
|
clk |
|
|
p0_app_reset_status_n |
|
|
reset |
|
|
|
p0_app_clk |
mm_bridge_bar4
|
|
|
clk |
|
|
p0_app_reset_status_n |
|
|
reset |
Software Assignments(none) |
mem
altera_avalon_onchip_memory2 v19.3.0
Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR |
0 |
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE |
0 |
CONTENTS_INFO |
"" |
DUAL_PORT |
1 |
GUI_RAM_BLOCK_TYPE |
AUTO |
INIT_CONTENTS_FILE |
onchip_memory2_onchip_memory2 |
INIT_MEM_CONTENT |
0 |
INSTANCE_ID |
NONE |
NON_DEFAULT_INIT_FILE_ENABLED |
0 |
RAM_BLOCK_TYPE |
AUTO |
READ_DURING_WRITE_MODE |
DONT_CARE |
SINGLE_CLOCK_OP |
1 |
SIZE_MULTIPLE |
1 |
SIZE_VALUE |
524288 |
WRITABLE |
1 |
|
mm_bridge_bar4
altera_avalon_mm_bridge v20.0.1
Software Assignments(none) |
mm_bridge_dma_controller
altera_avalon_mm_bridge v20.0.1
dut
|
p0_rddm_master |
mm_bridge_dma_controller |
s0 |
p0_app_clk |
clk |
p0_app_reset_status_n |
reset |
|
|
m0 |
DMA_CONTROLLER
|
|
|
dma_slave |
Software Assignments(none) |
mm_bridge_onchip_mem
altera_avalon_mm_bridge v20.0.1
dut
|
p0_rddm_master |
mm_bridge_onchip_mem |
s0 |
p0_app_clk |
clk |
p0_app_reset_status_n |
reset |
|
|
m0 |
mem
|
|
|
s2 |
Software Assignments(none) |
pio_button
altera_avalon_pio v19.1.3
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
2 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
0 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
pio_led
altera_avalon_pio v19.1.3
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
2 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
0 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
resetIP
altera_s10_user_rst_clkgate v19.3.2
Software Assignments(none) |
generation took 0.00 seconds |
rendering took 0.02 seconds |