Parameters
| DEVICE_FAMILY |
Stratix 10 |
| TARGET_TILE_gui |
2 |
| SPEED_CONFIG |
40 |
| EXT_TX_PLL |
0 |
| SYNOPT_SYNC_E |
0 |
| SYNOPT_TXCRC_INS |
1 |
| SYNOPT_LINK_FAULT |
0 |
| SYNOPT_PREAMBLE_PASS |
0 |
| SYNOPT_MAC_STATS |
1 |
| SYNOPT_STRICT_SOP |
0 |
| SYNOPT_FLOW_CONTROL |
0 |
| SYNOPT_NUMPRIORITY |
1 |
| SYNOPT_READY_LATENCY |
0 |
| ENABLE_ADME |
0 |
| PHY_REFCLK |
1 |
| ENABLE_KR4 |
0 |
| STATUS_CLK_MHZ |
100.0 |
| SYNTH_AN |
0 |
| LINK_TIMER_KR |
504 |
| AN_40GCR |
0 |
| AN_CHAN |
1 |
| AN_PAUSE_C0 |
0 |
| AN_PAUSE_C1 |
0 |
| SYNTH_LT |
0 |
| BERWIDTH |
9 |
| TRNWTWIDTH |
7 |
| VMAXRULE |
30 |
| VMINRULE |
6 |
| VODMINRULE |
14 |
| VPOSTRULE |
25 |
| VPRERULE |
16 |
| PREMAINVAL |
30 |
| PREPOSTVAL |
0 |
| PREPREVAL |
0 |
| INITMAINVAL |
25 |
| INITPOSTVAL |
13 |
| INITPREVAL |
3 |
| SYNTH_FEC |
0 |
| CAPABLE_FEC |
0 |
| ENABLE_FEC |
0 |
| PHY_ANALOG_VOLTAGE |
1_0V |
| EXAMPLE_DESIGN |
1 |
| GEN_SIM |
0 |
| GEN_SYNTH |
0 |
| HDL_FORMAT |
1 |
| DEV_BOARD |
0 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |
|