2020.09.02.11:38:53 |
Datasheet |
Overview
Memory Map
color_depth_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
2 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
cpu
altera_nios2_gen2 v19.1.0
Software Assignments
BIG_ENDIAN |
0 |
BREAK_ADDR |
0x00041820 |
CPU_ARCH_NIOS2_R1 |
|
CPU_FREQ |
100000000u |
CPU_ID_SIZE |
1 |
CPU_ID_VALUE |
0x00000000 |
CPU_IMPLEMENTATION |
"tiny" |
DATA_ADDR_WIDTH |
19 |
DCACHE_LINE_SIZE |
0 |
DCACHE_LINE_SIZE_LOG2 |
0 |
DCACHE_SIZE |
0 |
EXCEPTION_ADDR |
0x00020020 |
FLASH_ACCELERATOR_LINES |
0 |
FLASH_ACCELERATOR_LINE_SIZE |
0 |
FLUSHDA_SUPPORTED |
|
HARDWARE_DIVIDE_PRESENT |
0 |
HARDWARE_MULTIPLY_PRESENT |
0 |
HARDWARE_MULX_PRESENT |
0 |
HAS_DEBUG_CORE |
1 |
HAS_DEBUG_STUB |
|
HAS_ILLEGAL_INSTRUCTION_EXCEPTION |
|
HAS_JMPI_INSTRUCTION |
|
ICACHE_LINE_SIZE |
0 |
ICACHE_LINE_SIZE_LOG2 |
0 |
ICACHE_SIZE |
0 |
INST_ADDR_WIDTH |
19 |
OCI_VERSION |
1 |
RESET_ADDR |
0x00020000 |
|
cpu_clk
altera_clock_bridge v19.2.0
Software Assignments(none) |
cpu_ram
altera_avalon_onchip_memory2 v19.2.0
cpu
|
data_master |
cpu_ram |
s1 |
instruction_master |
s1 |
|
cpu_clk
|
out_clk |
clk1 |
|
cpu_reset
|
out_reset |
reset1 |
Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR |
0 |
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE |
0 |
CONTENTS_INFO |
"" |
DUAL_PORT |
0 |
GUI_RAM_BLOCK_TYPE |
AUTO |
INIT_CONTENTS_FILE |
nios_cpu_ram_cpu_ram |
INIT_MEM_CONTENT |
1 |
INSTANCE_ID |
NONE |
NON_DEFAULT_INIT_FILE_ENABLED |
0 |
RAM_BLOCK_TYPE |
AUTO |
READ_DURING_WRITE_MODE |
DONT_CARE |
SINGLE_CLOCK_OP |
0 |
SIZE_MULTIPLE |
1 |
SIZE_VALUE |
120000 |
WRITABLE |
1 |
|
cpu_reset
altera_reset_bridge v19.2.0
Software Assignments(none) |
edid_ram_access_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
edid_ram_slave_translator
altera_merlin_slave_translator v19.1
cpu
|
data_master |
edid_ram_slave_translator |
avalon_universal_slave_0 |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments(none) |
i2c_master
altera_avalon_i2c v19.2.0
cpu
|
data_master |
i2c_master |
csr |
irq |
interrupt_sender |
|
cpu_clk
|
out_clk |
clock |
|
cpu_reset
|
out_reset |
reset_sink |
Software Assignments
FIFO_DEPTH |
32 |
FREQ |
100000000 |
USE_AV_ST |
0 |
|
i2c_master_ti
altera_avalon_i2c v19.2.0
cpu
|
data_master |
i2c_master_ti |
csr |
irq |
interrupt_sender |
|
cpu_clk
|
out_clk |
clock |
|
cpu_reset
|
out_reset |
reset_sink |
Software Assignments
FIFO_DEPTH |
32 |
FREQ |
100000000 |
USE_AV_ST |
0 |
|
jtag_uart_0
altera_avalon_jtag_uart v19.1.0
cpu
|
data_master |
jtag_uart_0 |
avalon_jtag_slave |
irq |
irq |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments
READ_DEPTH |
1024 |
READ_THRESHOLD |
1 |
WRITE_DEPTH |
1024 |
WRITE_THRESHOLD |
1 |
|
measure_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
24 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
measure_valid_ack
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
measure_valid_req
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
sysid_qsys_0
altera_avalon_sysid_qsys v19.1.0
tmds_bit_clock_ratio_pio
altera_avalon_pio v19.1.0
cpu
|
data_master |
tmds_bit_clock_ratio_pio |
s1 |
irq |
irq |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
tx_hpd_ack_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
tx_hpd_req_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
tx_iopll_rcfg_mgmt_translator
altera_merlin_slave_translator v19.1
cpu
|
data_master |
tx_iopll_rcfg_mgmt_translator |
avalon_universal_slave_0 |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments(none) |
tx_iopll_waitrequest_pio
altera_avalon_pio v19.1.0
cpu
|
data_master |
tx_iopll_waitrequest_pio |
s1 |
irq |
irq |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
tx_os_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
2 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
tx_pll_rcfg_mgmt_translator
altera_merlin_slave_translator v19.1
cpu
|
data_master |
tx_pll_rcfg_mgmt_translator |
avalon_universal_slave_0 |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments(none) |
tx_pll_waitrequest_pio
altera_avalon_pio v19.1.0
cpu
|
data_master |
tx_pll_waitrequest_pio |
s1 |
irq |
irq |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
tx_pma_cal_busy_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
tx_pma_ch
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
2 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
tx_pma_rcfg_mgmt_translator
altera_merlin_slave_translator v19.1
cpu
|
data_master |
tx_pma_rcfg_mgmt_translator |
avalon_universal_slave_0 |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments(none) |
tx_pma_waitrequest_pio
altera_avalon_pio v19.1.0
cpu
|
data_master |
tx_pma_waitrequest_pio |
s1 |
irq |
irq |
|
cpu_clk
|
out_clk |
clk |
|
cpu_reset
|
out_reset |
reset |
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
1 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
1 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
1 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
ANY |
FREQ |
100000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
EDGE |
RESET_VALUE |
0 |
|
tx_rcfg_en_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
tx_rst_pll_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
tx_rst_xcvr_pio
altera_avalon_pio v19.1.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
1 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
100000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
wd_timer
altera_avalon_timer v19.1.0
Software Assignments
ALWAYS_RUN |
0 |
COUNTER_SIZE |
32 |
FIXED_PERIOD |
1 |
FREQ |
100000000 |
LOAD_VALUE |
59999999 |
MULT |
0.001 |
PERIOD |
600 |
PERIOD_UNITS |
ms |
RESET_OUTPUT |
1 |
SNAPSHOT |
0 |
TICKS_PER_SEC |
1 |
TIMEOUT_PULSE_OUTPUT |
0 |
|
generation took 0.00 seconds |
rendering took 0.03 seconds |