nios

2020.09.02.11:38:53 Datasheet
Overview
Processor
   cpu Nios II 19.1.0
All Components
   color_depth_pio altera_avalon_pio 19.1.0
   cpu altera_nios2_gen2 19.1.0
   cpu_ram altera_avalon_onchip_memory2 19.2.0
   edid_ram_access_pio altera_avalon_pio 19.1.0
   edid_ram_slave_translator altera_merlin_slave_translator 19.1
   i2c_master altera_avalon_i2c 19.2.0
   i2c_master_ti altera_avalon_i2c 19.2.0
   jtag_uart_0 altera_avalon_jtag_uart 19.1.0
   measure_pio altera_avalon_pio 19.1.0
   measure_valid_ack altera_avalon_pio 19.1.0
   measure_valid_req altera_avalon_pio 19.1.0
   sysid_qsys_0 altera_avalon_sysid_qsys 19.1.0
   tmds_bit_clock_ratio_pio altera_avalon_pio 19.1.0
   tx_hpd_ack_pio altera_avalon_pio 19.1.0
   tx_hpd_req_pio altera_avalon_pio 19.1.0
   tx_iopll_rcfg_mgmt_translator altera_merlin_slave_translator 19.1
   tx_iopll_waitrequest_pio altera_avalon_pio 19.1.0
   tx_os_pio altera_avalon_pio 19.1.0
   tx_pll_rcfg_mgmt_translator altera_merlin_slave_translator 19.1
   tx_pll_waitrequest_pio altera_avalon_pio 19.1.0
   tx_pma_cal_busy_pio altera_avalon_pio 19.1.0
   tx_pma_ch altera_avalon_pio 19.1.0
   tx_pma_rcfg_mgmt_translator altera_merlin_slave_translator 19.1
   tx_pma_waitrequest_pio altera_avalon_pio 19.1.0
   tx_rcfg_en_pio altera_avalon_pio 19.1.0
   tx_rst_pll_pio altera_avalon_pio 19.1.0
   tx_rst_xcvr_pio altera_avalon_pio 19.1.0
   wd_timer altera_avalon_timer 19.1.0
Memory Map
cpu edid_ram_slave_translator tx_iopll_rcfg_mgmt_translator tx_pll_rcfg_mgmt_translator tx_pma_rcfg_mgmt_translator
 data_master  instruction_master  avalon_anti_slave_0  avalon_anti_slave_0  avalon_anti_slave_0  avalon_anti_slave_0
  color_depth_pio
s1  0x00042840
  cpu
debug_mem_slave  0x00041800 0x00041800
  cpu_ram
s1  0x00020000 0x00020000
  edid_ram_access_pio
s1  0x00043000
  edid_ram_slave_translator
avalon_universal_slave_0  0x00042c00
  i2c_master
csr  0x00043300
  i2c_master_ti
csr  0x00043340
  jtag_uart_0
avalon_jtag_slave  0x000428f8
  measure_pio
s1  0x000428e0
  measure_valid_ack
s1  0x00042940
  measure_valid_req
s1  0x000428c0
  sysid_qsys_0
control_slave  0x000428f0
  tmds_bit_clock_ratio_pio
s1  0x00042890
  tx_hpd_ack_pio
s1  0x00042850
  tx_hpd_req_pio
s1  0x00042860
  tx_iopll_rcfg_mgmt_translator
avalon_universal_slave_0  0x00044000
  tx_iopll_waitrequest_pio
s1  0x00042880
  tx_os_pio
s1  0x000428d0
  tx_pll_rcfg_mgmt_translator
avalon_universal_slave_0  0x00010000
  tx_pll_waitrequest_pio
s1  0x00042870
  tx_pma_cal_busy_pio
s1  0x00042920
  tx_pma_ch
s1  0x00042930
  tx_pma_rcfg_mgmt_translator
avalon_universal_slave_0  0x00048000
  tx_pma_waitrequest_pio
s1  0x00042910
  tx_rcfg_en_pio
s1  0x00042900
  tx_rst_pll_pio
s1  0x000428b0
  tx_rst_xcvr_pio
s1  0x000428a0
  wd_timer
s1  0x00042800

color_depth_pio

altera_avalon_pio v19.1.0
cpu data_master   color_depth_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

cpu

altera_nios2_gen2 v19.1.0
cpu_clk out_clk   cpu
  clk
cpu_reset out_reset  
  reset
data_master   jtag_uart_0
  avalon_jtag_slave
irq  
  irq
data_master   edid_ram_slave_translator
  avalon_universal_slave_0
data_master   tx_iopll_rcfg_mgmt_translator
  avalon_universal_slave_0
data_master   tx_pll_rcfg_mgmt_translator
  avalon_universal_slave_0
data_master   tx_pma_rcfg_mgmt_translator
  avalon_universal_slave_0
data_master   sysid_qsys_0
  control_slave
data_master   i2c_master
  csr
irq  
  interrupt_sender
data_master   i2c_master_ti
  csr
irq  
  interrupt_sender
data_master   color_depth_pio
  s1
irq  
  irq
data_master   cpu_ram
  s1
instruction_master  
  s1
data_master   edid_ram_access_pio
  s1
data_master   measure_pio
  s1
irq  
  irq
data_master   measure_valid_ack
  s1
data_master   measure_valid_req
  s1
irq  
  irq
data_master   tmds_bit_clock_ratio_pio
  s1
irq  
  irq
data_master   tx_hpd_ack_pio
  s1
data_master   tx_hpd_req_pio
  s1
irq  
  irq
data_master   tx_iopll_waitrequest_pio
  s1
irq  
  irq
data_master   tx_os_pio
  s1
data_master   tx_pll_waitrequest_pio
  s1
irq  
  irq
data_master   tx_pma_cal_busy_pio
  s1
irq  
  irq
data_master   tx_pma_ch
  s1
data_master   tx_pma_waitrequest_pio
  s1
irq  
  irq
data_master   tx_rcfg_en_pio
  s1
data_master   tx_rst_pll_pio
  s1
data_master   tx_rst_xcvr_pio
  s1
data_master   wd_timer
  s1
irq  
  irq


Parameters

generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x00041820
CPU_ARCH_NIOS2_R1
CPU_FREQ 100000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "tiny"
DATA_ADDR_WIDTH 19
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
EXCEPTION_ADDR 0x00020020
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 0
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
INST_ADDR_WIDTH 19
OCI_VERSION 1
RESET_ADDR 0x00020000

cpu_clk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

cpu_ram

altera_avalon_onchip_memory2 v19.2.0
cpu data_master   cpu_ram
  s1
instruction_master  
  s1
cpu_clk out_clk  
  clk1
cpu_reset out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE nios_cpu_ram_cpu_ram
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 120000
WRITABLE 1

cpu_reset

altera_reset_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

edid_ram_access_pio

altera_avalon_pio v19.1.0
cpu data_master   edid_ram_access_pio
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

edid_ram_slave_translator

altera_merlin_slave_translator v19.1
cpu data_master   edid_ram_slave_translator
  avalon_universal_slave_0
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

i2c_master

altera_avalon_i2c v19.2.0
cpu data_master   i2c_master
  csr
irq  
  interrupt_sender
cpu_clk out_clk  
  clock
cpu_reset out_reset  
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

FIFO_DEPTH 32
FREQ 100000000
USE_AV_ST 0

i2c_master_ti

altera_avalon_i2c v19.2.0
cpu data_master   i2c_master_ti
  csr
irq  
  interrupt_sender
cpu_clk out_clk  
  clock
cpu_reset out_reset  
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

FIFO_DEPTH 32
FREQ 100000000
USE_AV_ST 0

jtag_uart_0

altera_avalon_jtag_uart v19.1.0
cpu data_master   jtag_uart_0
  avalon_jtag_slave
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 1024
READ_THRESHOLD 1
WRITE_DEPTH 1024
WRITE_THRESHOLD 1

measure_pio

altera_avalon_pio v19.1.0
cpu data_master   measure_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 24
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

measure_valid_ack

altera_avalon_pio v19.1.0
cpu data_master   measure_valid_ack
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

measure_valid_req

altera_avalon_pio v19.1.0
cpu data_master   measure_valid_req
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

sysid_qsys_0

altera_avalon_sysid_qsys v19.1.0
cpu data_master   sysid_qsys_0
  control_slave
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

tmds_bit_clock_ratio_pio

altera_avalon_pio v19.1.0
cpu data_master   tmds_bit_clock_ratio_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

tx_hpd_ack_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_hpd_ack_pio
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

tx_hpd_req_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_hpd_req_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

tx_iopll_rcfg_mgmt_translator

altera_merlin_slave_translator v19.1
cpu data_master   tx_iopll_rcfg_mgmt_translator
  avalon_universal_slave_0
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

tx_iopll_waitrequest_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_iopll_waitrequest_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

tx_os_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_os_pio
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

tx_pll_rcfg_mgmt_translator

altera_merlin_slave_translator v19.1
cpu data_master   tx_pll_rcfg_mgmt_translator
  avalon_universal_slave_0
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

tx_pll_waitrequest_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_pll_waitrequest_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

tx_pma_cal_busy_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_pma_cal_busy_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

tx_pma_ch

altera_avalon_pio v19.1.0
cpu data_master   tx_pma_ch
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

tx_pma_rcfg_mgmt_translator

altera_merlin_slave_translator v19.1
cpu data_master   tx_pma_rcfg_mgmt_translator
  avalon_universal_slave_0
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

tx_pma_waitrequest_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_pma_waitrequest_pio
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

tx_rcfg_en_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_rcfg_en_pio
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

tx_rst_pll_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_rst_pll_pio
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

tx_rst_xcvr_pio

altera_avalon_pio v19.1.0
cpu data_master   tx_rst_xcvr_pio
  s1
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

wd_timer

altera_avalon_timer v19.1.0
cpu data_master   wd_timer
  s1
irq  
  irq
cpu_clk out_clk  
  clk
cpu_reset out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 1
FREQ 100000000
LOAD_VALUE 59999999
MULT 0.001
PERIOD 600
PERIOD_UNITS ms
RESET_OUTPUT 1
SNAPSHOT 0
TICKS_PER_SEC 1
TIMEOUT_PULSE_OUTPUT 0
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