ep_g3x8_avmmdma256_integrated |
|
2020.04.22.15:04:51 |
Datasheet |
Overview
Memory Map
|
DUT
|
dma_rd_master |
rd_dcm_master |
dma_wr_master |
wr_dcm_master |
rxm_bar4 |
DUT
|
|
|
|
|
|
rd_dts_slave |
0x80000000 |
|
0x80000000 |
|
|
wr_dts_slave |
0x80002000 |
|
0x80002000 |
|
|
txs |
|
0x00000000 |
|
0x00000000 |
|
MEM
|
|
|
|
|
|
s1 |
0x00000000 |
|
0x00000000 |
|
|
s2 |
|
|
|
|
0x00000000 |
emif_s10_ddr4a
|
|
|
|
|
|
ctrl_amm_0 |
0x0000001000000000 |
|
0x0000001000000000 |
|
|
emif_s10_ddr4b
|
|
|
|
|
|
ctrl_amm_0 |
0x0000001800000000 |
|
0x0000001800000000 |
|
|
pio_button
|
|
|
|
|
|
s1 |
|
|
|
|
0x04000020 |
pio_led
|
|
|
|
|
|
s1 |
|
|
|
|
0x04000010 |
DUT
altera_pcie_s10_hip_avmm_bridge v20.0.0
Software Assignments(none) |
MEM
altera_avalon_onchip_memory2 v19.2.0
dma_rd_wr_pipe
|
m0 |
MEM |
s1 |
|
DUT
|
rxm_bar4 |
s2 |
coreclkout_hip |
clk1 |
app_nreset_status |
reset1 |
Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR |
0 |
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE |
0 |
CONTENTS_INFO |
"" |
DUAL_PORT |
1 |
GUI_RAM_BLOCK_TYPE |
AUTO |
INIT_CONTENTS_FILE |
ep_g3x8_avmmdma256_integrated_MEM_MEM |
INIT_MEM_CONTENT |
1 |
INSTANCE_ID |
NONE |
NON_DEFAULT_INIT_FILE_ENABLED |
0 |
RAM_BLOCK_TYPE |
AUTO |
READ_DURING_WRITE_MODE |
DONT_CARE |
SINGLE_CLOCK_OP |
1 |
SIZE_MULTIPLE |
1 |
SIZE_VALUE |
524288 |
WRITABLE |
1 |
|
ddr4_clock_crossing_bridge_ddr4a
altera_avalon_mm_clock_crossing_bridge v19.1
Software Assignments(none) |
ddr4_clock_crossing_bridge_ddr4b
altera_avalon_mm_clock_crossing_bridge v19.1
Software Assignments(none) |
ddr4_pipe_ddr4a_0
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
ddr4_pipe_ddr4a_1
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
ddr4_pipe_ddr4b_0
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
ddr4_pipe_ddr4b_1
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
dma_rd_pipe
altera_avalon_mm_bridge v19.1
DUT
|
dma_rd_master |
dma_rd_pipe |
s0 |
coreclkout_hip |
clk |
app_nreset_status |
reset |
|
|
m0 |
dma_rd_wr_pipe
|
|
|
s0 |
Software Assignments(none) |
dma_rd_wr_512_pipe
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
dma_rd_wr_512_pipe_ddr4a
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
dma_rd_wr_512_pipe_ddr4b
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
dma_rd_wr_pipe
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
dma_rd_wr_pipe_0
altera_avalon_mm_bridge v19.1
Software Assignments(none) |
dts_pipe
altera_avalon_mm_bridge v19.1
dma_rd_wr_pipe
|
m0 |
dts_pipe |
s0 |
|
DUT
|
coreclkout_hip |
clk |
app_nreset_status |
reset |
|
|
m0 |
DUT
|
|
|
rd_dts_slave |
|
|
m0 |
|
|
wr_dts_slave |
Software Assignments(none) |
emif_s10_ddr4a
altera_emif_s10 v19.1.0
Software Assignments(none) |
emif_s10_ddr4b
altera_emif_s10 v19.1.0
Software Assignments(none) |
pio_button
altera_avalon_pio v19.1
DUT
|
rxm_bar4 |
pio_button |
s1 |
coreclkout_hip |
clk |
app_nreset_status |
reset |
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
4 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
125000000 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
pio_led
altera_avalon_pio v19.1
DUT
|
rxm_bar4 |
pio_led |
s1 |
coreclkout_hip |
clk |
app_nreset_status |
reset |
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
4 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
125000000 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
generation took 0.02 seconds |
rendering took 0.35 seconds |