rcfg_enable |
1 |
rcfg_jtag_enable |
0 |
rcfg_separate_avmm_busy |
0 |
set_capability_reg_enable |
0 |
set_user_identifier |
0 |
set_csr_soft_logic_enable |
0 |
rcfg_file_prefix |
altera_xcvr_rcfg_10 |
rcfg_sv_file_enable |
0 |
rcfg_h_file_enable |
0 |
rcfg_mif_file_enable |
0 |
rcfg_multi_enable |
0 |
set_rcfg_emb_strm_enable |
0 |
rcfg_reduced_files_enable |
0 |
rcfg_profile_cnt |
2 |
rcfg_profile_select |
1 |
rcfg_profile_data0 |
|
rcfg_profile_data1 |
|
rcfg_profile_data2 |
|
rcfg_profile_data3 |
|
rcfg_profile_data4 |
|
rcfg_profile_data5 |
|
rcfg_profile_data6 |
|
rcfg_profile_data7 |
|
message_level |
error |
reduced_reset_sim_time |
0 |
channel_type |
GX |
protocol_mode |
basic_std |
pma_mode |
basic |
duplex_mode |
rx |
channels |
3 |
set_data_rate |
6000 |
rcfg_iface_enable |
0 |
enable_simple_interface |
1 |
enable_split_interface |
0 |
enable_double_rate_transfer |
0 |
cdr_refclk_cnt |
1 |
cdr_refclk_select |
0 |
set_cdr_refclk_freq |
150.000000 |
rx_ppm_detect_threshold |
1000 |
enable_port_rx_pma_iqtxrx_clkout |
0 |
enable_port_rx_pma_clkslip |
0 |
enable_port_rx_is_lockedtodata |
1 |
enable_port_rx_is_lockedtoref |
1 |
enable_ports_rx_manual_cdr_mode |
1 |
enable_ports_rx_prbs |
0 |
enable_port_rx_seriallpbken |
0 |
std_pcs_pma_width |
20 |
display_std_rx_pld_adapt_width |
20 |
std_low_latency_bypass_enable |
0 |
std_rx_byte_deser_mode |
Disabled |
std_rx_8b10b_enable |
0 |
std_rx_rmfifo_mode |
disabled |
std_rx_rmfifo_pattern_n |
0 |
std_rx_rmfifo_pattern_p |
0 |
enable_port_rx_std_rmfifo_full |
0 |
enable_port_rx_std_rmfifo_empty |
0 |
pcie_rate_match |
Bypass |
std_rx_word_aligner_mode |
synchronous state machine |
std_rx_word_aligner_pattern_len |
20 |
std_rx_word_aligner_pattern |
699050 |
std_rx_word_aligner_rknumber |
8 |
std_rx_word_aligner_renumber |
0 |
std_rx_word_aligner_rgnumber |
3 |
std_rx_word_aligner_fast_sync_status_enable |
0 |
enable_port_rx_std_wa_patternalign |
1 |
enable_port_rx_std_wa_a1a2size |
0 |
enable_port_rx_std_bitslipboundarysel |
1 |
enable_port_rx_std_bitslip |
0 |
std_rx_bitrev_enable |
0 |
enable_port_rx_std_bitrev_ena |
0 |
std_rx_byterev_enable |
0 |
enable_port_rx_std_byterev_ena |
0 |
std_rx_polinv_enable |
1 |
enable_port_rx_polinv |
1 |
enable_port_rx_std_signaldetect |
0 |
enable_ports_pipe_rx_elecidle |
0 |
enable_debug_ports |
0 |
rx_fifo_mode |
Phase compensation |
rx_fifo_pfull |
5 |
rx_fifo_pempty |
2 |
rx_fifo_align_del |
0 |
rx_fifo_control_del |
0 |
enable_port_rx_data_valid |
0 |
enable_port_rx_fifo_full |
0 |
enable_port_rx_fifo_empty |
0 |
enable_port_rx_fifo_pfull |
0 |
enable_port_rx_fifo_pempty |
0 |
enable_port_rx_fifo_del |
0 |
enable_port_rx_fifo_insert |
0 |
enable_port_rx_fifo_rd_en |
0 |
enable_port_rx_fifo_align_clr |
0 |
rx_clkout_sel |
pcs_clkout |
enable_port_rx_clkout2 |
0 |
rx_clkout2_sel |
pcs_clkout |
rx_pma_div_clkout_divider |
0 |
rx_coreclkin_clock_network |
dedicated |
enable_port_latency_measurement |
0 |
generate_docs |
1 |
enable_tx_coreclkin2 |
0 |
rcfg_shared |
0 |
rcfg_use_clk_reset_only |
0 |
set_prbs_soft_logic_enable |
0 |
enable_rcfg_tx_digitalreset_release_ctrl |
0 |
tx_pll_type |
ATX |
tx_pll_refclk |
125.0 |
use_tx_clkout2 |
0 |
use_rx_clkout2 |
0 |
enable_fast_sim |
0 |
design_example_filename |
top |
anlg_voltage |
1_0V |
anlg_link |
lr |
qsf_assignments_enable |
0 |
qsf_assignments_list |
|
rx_pma_analog_mode |
user_custom |
rx_pma_optimal_settings |
1 |
rx_pma_adapt_mode |
manual |
rx_pma_term_sel |
r_r2 |
rx_ctle_ac_gain |
0 |
rx_ctle_eq_gain |
0 |
rx_vga_dc_gain |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |