TR4_QSYS | TR4_QSYS 1.0

2011.12.15.17:21:54 | Generation Report

Output Directory | D:/SVN/tr4/daughter_card/TR4_AHA/
Files | D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/TR4_QSYS.v (433893 bytes VERILOG) D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3.v (11834 bytes VERILOG) D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_c0.v (19487 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd.v (25980 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v (51432 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v (19238 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v (10002 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v (16552 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_odt_gen.v (14757 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v (46253 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_arbiter.v (50108 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_burst_gen.v (64113 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_cmd_gen.v (121966 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_csr.v (53869 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_buffer.v (4779 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_buffer_manager.v (8991 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_burst_tracking.v (4707 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_dataid_manager.v (33821 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_fifo.v (8340 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_list.v (8754 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rdata_path.v (51877 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_wdata_path.v (44528 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_define.iv (2237 bytes VERILOG_INCLUDE)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v (13702 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v (32973 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v (59259 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v (10730 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v (14064 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v (22231 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v (49920 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_input_if.v (10699 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rank_timer.v (116132 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_sideband.v (57384 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_tbp.v (175785 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_timing_param.v (52437 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_controller.v (161675 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_controller_st_top.v (90484 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv (27695 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v (6961 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_clock_pair_generator.v (3520 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pll_memphy.v (23388 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_dll_memphy.v (6001 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_oct_control.v (3791 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_controller_phy.sv (16472 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_memphy_top.sv (25134 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_valid_selector.v (2379 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_datapath.v (6482 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset.v (4421 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_pads.v (13237 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_memphy.v (45568 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset_sync.v (1978 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_afi_mux.v (6280 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_new_io_pads.v (12210 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_fr_cycle_shifter.v (3943 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_datapath.v (26511 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_write_datapath.v (4314 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_hr_to_fr.v (1348 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_mux_bridge.sv (18324 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_phy_csr.sv (6105 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_iss_probe.v (1784 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_flop_mem.v (2755 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_nios_sequencer.sv (11285 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sv (13621 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_altdqdqs.v (5562 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altdq_dqs2_ddio_3reg_stratixiv.sv (53994 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/software/sequencer.c (131340 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/software/sequencer.h (10140 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer.v (352922 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v (32198 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv (9448 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10392 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv (8662 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv (16415 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv (17560 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv (15976 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv (13743 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_no_ifdef_params.v (10403 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_reg.v (1478 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_bitcheck.v (2624 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_core.sv (16455 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_datamux.v (1733 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_data_broadcast.v (2347 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_data_decoder.v (2892 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_ddr3.v (7707 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer.v (10123 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer_wrap.v (2076 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_dm_decoder.v (1735 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_generic.sv (7209 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_no_ifdef_params.v (10442 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_reg.v (1504 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_jumplogic.v (3333 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_lfsr12.v (1438 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_lfsr36.v (2097 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_lfsr72.v (1381 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_pattern_fifo.v (10125 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_ram.v (1317 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_ram_csr.v (2442 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_read_datapath.v (3610 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rw_manager_write_decoder.v (2858 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/sequencer_data_mgr.sv (3779 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/sequencer_phy_mgr.sv (13764 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/sequencer_ptr_mgr.sv (3133 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/sequencer_scc_mgr.sv (17682 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/sequencer_scc_phase_decode.v (13160 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/sequencer_scc_reg_file.v (2631 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_addr_router.sv (6409 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_addr_router_001.sv (8029 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cmd_xbar_demux.sv (4169 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cmd_xbar_demux_001.sv (7987 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cmd_xbar_mux.sv (12302 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst.sdc (5808 bytes SDC)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst.v (208383 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk.v (7838 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck.v (9544 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper.v (12055 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_ociram_default_contents.mif (5878 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_oci_test_bench.v (1713 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_rf_ram_a.mif (600 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_rf_ram_b.mif (600 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_test_bench.v (32285 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_id_router.sv (5987 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_id_router_002.sv (5918 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_irq_mapper.sv (1714 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_demux.sv (4163 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_demux_002.sv (3539 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_mux.sv (12268 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_mux_001.sv (17364 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_sequencer_ram.v (4415 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_sequencer_rom.hex (86029 bytes HEX)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_sequencer_rom.v (4563 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_rom.hex (86046 bytes HEX)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_AC_ROM.hex (1357 bytes HEX)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_inst_ROM.hex (2445 bytes HEX)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.ppf (59549 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sdc (29418 bytes SDC)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_timing.tcl (5726 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing.tcl (17168 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing_core.tcl (81477 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_map.tcl (78709 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_assignments.tcl (18913 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_parameters.tcl (3111 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_cpu.sdc (796 bytes SDC)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TERASIC_CAMERA.v (3344 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/CAMERA_RGB.v (1519 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/CAMERA_Bayer.v (1975 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/Bayer2RGB.v (5185 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/Bayer_LineBuffer.v (4595 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/rgb_fifo.v (7134 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/add2.v (3980 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/add4.v (4428 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_alt_vip_vfb_0.ocp (584 bytes unknown type)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_alt_vip_vfb_0_vfb_writer_vfb_writer.trace (463295 bytes unknown type)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_alt_vip_vfb_0_vfb_reader_vfb_reader.trace (284216 bytes unknown type)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_alt_vip_vfb_0.vhd (471424 bytes VHDL_ENCRYPT)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_alt_vip_vfb_0_tb.vhd (8626 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_muxbin2.vhd (862 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd (158228 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_au.vhd (5638 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_addsubcarry.vhd (11784 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_reg.vhd (2232 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_muxhot16.vhd (2866 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_avalon_st_input.vhd (12742 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_muxfast4.vhd (11574 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_avalon_st_output.vhd (5616 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_atlantic_reporter.vhd (3769 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_avalon_mm_bursting_master_fifo.vhd (36260 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_fifo.vhd (8942 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_fifo_usedw_calculator.vhd (14003 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_general_fifo.vhd (13672 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_gray_clock_crosser.vhd (3963 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_logic_fifo.vhd (5161 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_one_bit_delay.vhd (2313 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_ram_fifo.vhd (8174 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_std_logic_vector_delay.vhd (2610 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_pulling_width_adapter.vhd (6216 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_pushing_width_adapter.vhd (4878 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_pc.vhd (36289 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_cmp.vhd (3083 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_clock_reset.vhd (1791 bytes VHDL)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid.v (43072 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_sync_compare.v (7112 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_calculate_mode.v (3850 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_control.v (5232 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_mode_banks.v (26347 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_statemachine.v (9489 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_fifo.v (2533 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_generic_count.v (1843 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_to_binary.v (1208 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_sync.v (994 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_trigger_sync.v (1430 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_sync_generation.v (4203 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_frame_counter.v (2390 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_sample_counter.v (1606 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_vipitc110_cvo.sdc (6266 bytes SDC)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.ocp (848 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.sdc (3743 bytes SDC)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.v (435744 bytes VERILOG_ENCRYPT)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_bht_ram.mif (2392 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_dc_tag_ram.mif (792 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_ic_tag_ram.mif (1625 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_sysclk.v (7033 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_tck.v (8319 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_wrapper.v (10163 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_mult_cell.v (4773 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_ociram_default_contents.mif (5878 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_oci_test_bench.v (1468 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_rf_ram_a.mif (600 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_rf_ram_b.mif (600 bytes MIF)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_test_bench.v (31415 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_mem.hex (537613 bytes HEX)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_mem.v (3858 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_camera_sda.v (2787 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_camera_scl.v (2269 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart.v (23819 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_input_mutex.dat (3 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_input_stream.dat (10 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_output_stream.dat (0 bytes OTHER)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_sw.v (1879 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_timer_0.v (6931 bytes VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router.sv (6001 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router.sv (5906 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_002.sv (6347 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_003.sv (7955 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_001.sv (5909 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_003.sv (5828 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux.sv (3471 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_mux.sv (11013 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux.sv (4103 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_002.sv (4117 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_003.sv (7927 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_mux_001.sv (11021 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux_001.sv (4111 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux_003.sv (3479 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux_002.sv (12216 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux_003.sv (17304 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_width_adapter.sv (36187 bytes SYSTEM_VERILOG)
D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/TR4_QSYS_irq_mapper.sv (1824 bytes SYSTEM_VERILOG)
Instantiations |

TR4_QSYS TR4_QSYS v1.0 | TR4_QSYS_uniphy_ddr3 as uniphy_ddr3 TERASIC_CAMERA as TERASIC_CAMERA_0 TR4_QSYS_alt_vip_vfb_0 as alt_vip_vfb_0 alt_vipitc110_IS2Vid as alt_vip_itc_0 TR4_QSYS_cpu as cpu
TR4_QSYS_mem as mem
TR4_QSYS_camera_sda as camera_sda
TR4_QSYS_camera_scl as camera_scl, camera_reset_n
TR4_QSYS_jtag_uart as jtag_uart
TR4_QSYS_sw as sw
TR4_QSYS_timer_0 as timer_0
altera_merlin_master_translator as alt_vip_vfb_0_write_master_translator, alt_vip_vfb_0_read_master_translator, cpu_instruction_master_translator, cpu_data_master_translator
altera_merlin_slave_translator as uniphy_ddr3_avl_translator, cpu_jtag_debug_module_translator, mem_s1_translator, camera_sda_s1_translator, camera_scl_s1_translator, camera_reset_n_s1_translator, jtag_uart_avalon_jtag_slave_translator, sw_s1_translator, timer_0_s1_translator
altera_merlin_master_agent as alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent, alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent, cpu_instruction_master_translator_avalon_universal_master_0_agent, cpu_data_master_translator_avalon_universal_master_0_agent
altera_merlin_slave_agent as uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent, mem_s1_translator_avalon_universal_slave_0_agent, camera_sda_s1_translator_avalon_universal_slave_0_agent, camera_scl_s1_translator_avalon_universal_slave_0_agent, camera_reset_n_s1_translator_avalon_universal_slave_0_agent, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent, sw_s1_translator_avalon_universal_slave_0_agent, timer_0_s1_translator_avalon_universal_slave_0_agent
altera_avalon_sc_fifo as uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo, mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, camera_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, camera_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, camera_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
TR4_QSYS_addr_router as addr_router, addr_router_001
TR4_QSYS_id_router as id_router
TR4_QSYS_addr_router_002 as addr_router_002
TR4_QSYS_addr_router_003 as addr_router_003
TR4_QSYS_id_router_001 as id_router_001, id_router_002
TR4_QSYS_id_router_003 as id_router_003, id_router_004, id_router_005, id_router_006, id_router_007, id_router_008
altera_merlin_traffic_limiter as limiter, limiter_001
altera_reset_controller as rst_controller, rst_controller_001, rst_controller_002
TR4_QSYS_cmd_xbar_demux as cmd_xbar_demux, cmd_xbar_demux_001
TR4_QSYS_cmd_xbar_mux as cmd_xbar_mux
TR4_QSYS_rsp_xbar_demux as rsp_xbar_demux
TR4_QSYS_cmd_xbar_demux_002 as cmd_xbar_demux_002
TR4_QSYS_cmd_xbar_demux_003 as cmd_xbar_demux_003
TR4_QSYS_cmd_xbar_mux_001 as cmd_xbar_mux_001, cmd_xbar_mux_002
TR4_QSYS_rsp_xbar_demux_001 as rsp_xbar_demux_001, rsp_xbar_demux_002
TR4_QSYS_rsp_xbar_demux_003 as rsp_xbar_demux_003, rsp_xbar_demux_004, rsp_xbar_demux_005, rsp_xbar_demux_006, rsp_xbar_demux_007, rsp_xbar_demux_008
TR4_QSYS_rsp_xbar_mux_002 as rsp_xbar_mux_002
TR4_QSYS_rsp_xbar_mux_003 as rsp_xbar_mux_003
altera_merlin_width_adapter as width_adapter, width_adapter_001
TR4_QSYS_irq_mapper as irq_mapper
TR4_QSYS_uniphy_ddr3 altera_mem_if_ddr3_emif v11.0 | TR4_QSYS_uniphy_ddr3_c0 as c0 TR4_QSYS_uniphy_ddr3_p0 as p0
TERASIC_CAMERA TERASIC_CAMERA v1.0 |
TR4_QSYS_alt_vip_vfb_0 alt_vip_vfb v11.0 | alt_cusp110_muxbin2 as vfb_writer_packet_write_address_au_l_muxinst, vfb_writer_packet_write_address_au_sload_muxinst, vfb_writer_first_packet_id_au_enable_muxinst, vfb_writer_first_packet_id_au_sload_muxinst, vfb_writer_next_to_last_packet_id_au_enable_muxinst, vfb_writer_overflow_trigger_au_sload_muxinst, vfb_writer_overflow_flag_reg_enable_muxinst, vfb_writer_word_counter_trigger_au_sload_muxinst, vfb_writer_field_interlace_reg_d_muxinst, vfb_writer_field_interlace_reg_enable_muxinst, vfb_check_samples_width_au_l_muxinst, vfb_check_samples_width_au_enable_muxinst, vfb_check_samples_width_au_sload_muxinst, vfb_check_field_height_au_a_muxinst, vfb_check_field_height_au_enable_muxinst, vfb_writer_write_address_au_l_muxinst, sizemismatch_reg_enable_muxinst, vfb_reader_current_packet_id_au_l_muxinst, read_master_renable_trigger_muxinst, read_master_addr_muxinst, read_master_len_be_muxinst, write_master_len_be_muxinst, write_master_push_input_muxinst, vfb_writer_packets_sample_length_reg_d_muxinst, vfb_writer_packets_sample_length_reg_enable_muxinst, vfb_writer_packets_sample_length_reg_1_d_muxinst, vfb_writer_packets_sample_length_reg_1_enable_muxinst, vfb_writer_packets_word_length_reg_d_muxinst, vfb_writer_packets_word_length_reg_enable_muxinst, vfb_writer_packets_word_length_reg_1_d_muxinst, vfb_writer_packets_word_length_reg_1_enable_muxinst, packetdimensions_reg_d_muxinst, packetdimensions_reg_137_d_muxinst, packetdimensions_reg_1372_d_muxinst, packetdimensions_reg_1373_d_muxinst, output_reg_d_muxinst, output_reg_174_d_muxinst, output_reg_1742_d_muxinst, output_reg_1743_d_muxinst, output_reg_1744_d_muxinst, output_reg_1745_d_muxinst, msg_buffer_reply_id_3500_line154_d_muxinst, msg_buffer_id_3505_line162_d_muxinst, msg_field_width_id_3509_line164_d_muxinst, msg_field_height_id_3513_line166_d_muxinst, msg_field_interlace_id_3517_line168_d_muxinst, msg_samples_in_field_id_3521_line170_d_muxinst, msg_words_in_field_id_3525_line172_d_muxinst, msg_first_packet_id_3529_line214_d_muxinst, msg_next_to_last_packet_id_3533_line215_d_muxinst, reader_packets_sample_length_id_3591_line870_d_muxinst, reader_packets_word_length_id_3595_line872_d_muxinst, vfb_reader_length_cnt_id_3610_line889_a_muxinst, vfb_reader_length_cnt_id_3619_line889_a_muxinst
alt_cusp110_au as vfb_writer_packet_write_address_au, vfb_writer_first_packet_id_au, vfb_writer_next_to_last_packet_id_au, vfb_writer_overflow_trigger_au, vfb_writer_length_counter_au, vfb_writer_word_counter_au, vfb_writer_word_counter_trigger_au, vfb_check_samples_width_au, vfb_check_field_height_au, vfb_writer_write_address_au, vfb_reader_read_address_au, vfb_reader_packet_read_address_au, vfb_reader_current_packet_id_au, wrap_packet_id_id_3601_line1069, vfb_reader_length_cnt_4_id_3608_line889, vfb_reader_length_cnt_id_3610_line889, vfb_reader_length_cnt_id_3619_line889, fu_id_6560_line519_89
alt_cusp110_reg as vfb_writer_overflow_flag_reg, vfb_writer_field_width_reg, vfb_writer_field_height_reg, vfb_writer_field_interlace_reg, vfb_writer_just_read_reg, sizemismatch_reg, vfb_writer_packets_sample_length_reg, vfb_writer_packets_sample_length_reg_1, vfb_writer_packets_word_length_reg, vfb_writer_packets_word_length_reg_1, msg_packets_sample_length_reg, msg_packets_sample_length_reg_1, msg_packets_word_length_reg, msg_packets_word_length_reg_1, packetdimensions_reg, packetdimensions_reg_137, packetdimensions_reg_1372, packetdimensions_reg_1373, output_reg, output_reg_174, output_reg_1742, output_reg_1743, output_reg_1744, output_reg_1745, output_reg_1746, output_reg_1747, output_reg_1748, msg_buffer_reply_id_3500_line154, msg_buffer_id_3505_line162, msg_field_width_id_3509_line164, msg_field_height_id_3513_line166, msg_field_interlace_id_3517_line168, msg_samples_in_field_id_3521_line170, msg_words_in_field_id_3525_line172, msg_first_packet_id_3529_line214, msg_next_to_last_packet_id_3533_line215, vfb_writer_buffer_id_3537_line220, write_to_read_buf_id_3540_line145, write_to_read_ack_id_3543_line156, vfb_writer_packet_base_address_0_id_3546_line196, isnotimagedata_0_id_3548_line144, iscontrolpacket_0_id_3550_line202, no_last_burst_0_id_3552_line301, vfb_samples_width_0_id_3556_line247, no_last_burst_0_id_3558_line577, cond580_0_id_3560, drop_0_id_3562_line337, loop_repeat_0_id_3564_line359, burst_trigger_0_id_3566_line555, cond560_0_id_3568, vfb_reader_buffer_id_3570_line857, read_to_write_ack_id_3573_line148, read_to_write_buf_id_3576_line152, vfb_reader_field_width_0_id_3579_line765, vfb_reader_samples_in_field_0_id_3581_line881, vfb_reader_field_height_0_id_3583_line767, vfb_reader_words_in_field_0_id_3585_line883, vfb_reader_field_interlace_0_id_3587_line769, vfb_reader_next_to_last_packet_id_0_id_3589_line868, reader_packets_sample_length_id_3591_line870, reader_packets_word_length_id_3595_line872, vfb_reader_packet_base_address_0_id_3599_line865, vfb_reader_length_cnt_3_id_3604_line889, vfb_reader_word_cnt_0_id_3606_line890, repeat_0_id_3613_line1132, loop_repeat_0_id_3615_line1140, cond1195_0_id_3617, cond1105_0_id_3622, ispreviousendpacket_0_comb_id_8923, justreadqueue_1_1_comb_id_8926, justreadqueue_2_1_comb_id_8929, justreadqueue_1_2_comb_id_8932, ispreviousendpacket_1_comb_id_8935, justreadaccesswire_3_comb_id_8938, justreadaccesswire_4_comb_id_8941, justreadqueue_1_4_comb_id_8944, justreadqueue_2_2_comb_id_8947, justreadqueue_1_5_comb_id_8950, ispreviousendpacket_2_comb_id_8953, justreadaccesswire_6_comb_id_8956, justreadaccesswire_7_comb_id_8959, justreadqueue_1_7_comb_id_8962, justreadqueue_2_3_comb_id_8965, justreadqueue_1_8_comb_id_8968, vfb_check_samples_width_1_stage_1_id_9022, din_11_stage_1_id_9025, din_11_stage_2_id_9028, word_counter_trigger_flag_0_comb_id_9031, op_2415_comb_id_9034, op_2415_comb_0_id_9037, op_4676_comb_id_9040, op_4678_comb_id_9043, op_3549_comb_id_9046, op_3549_comb_0_id_9049, op_4691_comb_id_9052, op_4692_comb_id_9055, cond1105_0_stage_1_id_9058, cond1105_0_stage_2_id_9061, cond1105_0_stage_3_id_9064, empty_image_0_comb_id_9067, cond1195_0_stage_1_id_9070, cond1195_0_stage_2_id_9073, cond1195_0_stage_3_id_9076
alt_cusp110_muxhot16 as vfb_writer_length_counter_au_enable_muxinst, vfb_writer_word_counter_au_enable_muxinst, vfb_writer_word_counter_au_enable_trigger_muxinst, vfb_writer_word_counter_trigger_au_enable_muxinst, vfb_writer_write_address_au_enable_trigger_muxinst, vfb_writer_just_read_reg_enable_muxinst, sizemismatch_reg_d_muxinst, vfb_reader_packet_read_address_au_sload_muxinst, din_takeb_trigger_muxinst, dout_takeb_trigger_muxinst, dout_seteop_trigger_muxinst, dout_eop_muxinst, read_master_pull_pull_trigger_muxinst, write_master_cenable_trigger_muxinst, write_master_push_push_trigger_muxinst, pc0_usenextpc_trigger_muxinst, pc0_hold_trigger_muxinst, pc1_usenextpc_trigger_muxinst, pc1_hold_trigger_muxinst
alt_cusp110_avalon_st_input as din
alt_cusp110_muxfast4 as dout_wdata_muxinst
alt_cusp110_avalon_st_output as dout
alt_cusp110_avalon_mm_bursting_master_fifo as read_master, write_master
alt_cusp110_pulling_width_adapter as read_master_pull
alt_cusp110_pushing_width_adapter as write_master_push
alt_cusp110_pc as pc0, pc1
alt_cusp110_cmp as fu_id_5128_line317_93, fu_id_5144_line317_52, fu_id_5160_line201_52, fu_id_5330_line202_58, fu_id_5531_line330_94, fu_id_5547_line331_96, fu_id_5595_line330_94, fu_id_5611_line331_96, fu_id_5731_line625_71, fu_id_5959_line688_38, fu_id_6418_line502_66, fu_id_6666_line555_105, fu_id_6839_line925_38, fu_id_7077_line1054_114, fu_id_7093_line1055_112, fu_id_7109_line1070_53, fu_id_7125_line1086_53, fu_id_7189_line1180_29, fu_id_7331_line1240_53, fu_id_7577_line1118_52
alt_cusp110_clock_reset as clocksource
TR4_QSYS_alt_vip_vfb_0 as dut
alt_vipitc110_IS2Vid alt_vip_itc v11.0 |
TR4_QSYS_cpu altera_nios2_qsys v11.0 |
TR4_QSYS_mem altera_avalon_onchip_memory2 v11.0 |
TR4_QSYS_camera_sda altera_avalon_pio v11.0 |
TR4_QSYS_camera_scl altera_avalon_pio v11.0 |
TR4_QSYS_jtag_uart altera_avalon_jtag_uart v11.0 |
TR4_QSYS_sw altera_avalon_pio v11.0 |
TR4_QSYS_timer_0 altera_avalon_timer v11.0 |
altera_merlin_master_translator altera_merlin_master_translator v11.0 |
altera_merlin_slave_translator altera_merlin_slave_translator v11.0 |
altera_merlin_master_agent altera_merlin_master_agent v11.0 |
altera_merlin_slave_agent altera_merlin_slave_agent v11.0 |
altera_avalon_sc_fifo altera_avalon_sc_fifo v11.0 |
TR4_QSYS_addr_router altera_merlin_router v11.0 |
TR4_QSYS_id_router altera_merlin_router v11.0 |
TR4_QSYS_addr_router_002 altera_merlin_router v11.0 |
TR4_QSYS_addr_router_003 altera_merlin_router v11.0 |
TR4_QSYS_id_router_001 altera_merlin_router v11.0 |
TR4_QSYS_id_router_003 altera_merlin_router v11.0 |
altera_merlin_traffic_limiter altera_merlin_traffic_limiter v11.0 |
altera_reset_controller altera_reset_controller v11.0 |
TR4_QSYS_cmd_xbar_demux altera_merlin_demultiplexer v11.0 |
TR4_QSYS_cmd_xbar_mux altera_merlin_multiplexer v11.0 |
TR4_QSYS_rsp_xbar_demux altera_merlin_demultiplexer v11.0 |
TR4_QSYS_cmd_xbar_demux_002 altera_merlin_demultiplexer v11.0 |
TR4_QSYS_cmd_xbar_demux_003 altera_merlin_demultiplexer v11.0 |
TR4_QSYS_cmd_xbar_mux_001 altera_merlin_multiplexer v11.0 |
TR4_QSYS_rsp_xbar_demux_001 altera_merlin_demultiplexer v11.0 |
TR4_QSYS_rsp_xbar_demux_003 altera_merlin_demultiplexer v11.0 |
TR4_QSYS_rsp_xbar_mux_002 altera_merlin_multiplexer v11.0 |
TR4_QSYS_rsp_xbar_mux_003 altera_merlin_multiplexer v11.0 |
altera_merlin_width_adapter altera_merlin_width_adapter v11.0 |
TR4_QSYS_irq_mapper altera_irq_mapper v11.0 |
TR4_QSYS_uniphy_ddr3_c0 altera_mem_if_nextgen_ddr3_controller v11.0 | alt_mem_if_nextgen_ddr3_controller_core as ng0 alt_mem_ddrx_mm_st_converter as a0
TR4_QSYS_uniphy_ddr3_p0 altera_mem_if_ddr3_phy v11.0 |
alt_cusp110_muxbin2 alt_cusp_muxbin2 v11.0 |
alt_cusp110_au alt_au v11.0 |
alt_cusp110_reg alt_reg v11.0 |
alt_cusp110_muxhot16 alt_cusp_muxhot16 v11.0 |
alt_cusp110_avalon_st_input alt_avalon_st_input v11.0 |
alt_cusp110_muxfast4 alt_cusp_muxfast4 v11.0 |
alt_cusp110_avalon_st_output alt_avalon_st_output v11.0 |
alt_cusp110_avalon_mm_bursting_master_fifo alt_avalon_mm_bursting_master_fifo v11.0 |
alt_cusp110_pulling_width_adapter alt_cusp_pulling_width_adapter v11.0 |
alt_cusp110_pushing_width_adapter alt_cusp_pushing_width_adapter v11.0 |
alt_cusp110_pc alt_pc v11.0 |
alt_cusp110_cmp alt_cmp v11.0 |
alt_cusp110_clock_reset alt_cusp_testbench_clock v11.0 |
alt_mem_if_nextgen_ddr3_controller_core altera_mem_if_nextgen_ddr3_controller_core v11.0 |
alt_mem_ddrx_mm_st_converter alt_mem_ddrx_mm_st_converter v11.0 |

Generation Messages
2011.12.15.17:18:06 [Info] TR4_QSYS.uniphy_ddr3: Auto interface leveling mode set to 'Leveling' 2011.12.15.17:07:16 [Debug] TR4_QSYS.uniphy_ddr3.c0.altera_mem_if_nextgen_ddr3_controller_core: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.c0.ng0: Timing: VAL:1/0.031s ELA:1/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_reset: Timing: ELA:1/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_clk: Timing: ELA:1/0.016s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_half_clk: Timing: ELA:1/0.000s 2011.12.15.17:07:16 [Debug] TR4_QSYS.uniphy_ddr3.c0.alt_mem_ddrx_mm_st_converter: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.c0.a0: Timing: VAL:1/0.000s ELA:1/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.c0: Timing: VAL:1/0.031s COM:1/0.141s 2011.12.15.17:07:16 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_phy: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.p0: Timing: VAL:1/0.297s ELA:1/0.016s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.pll_ref_clk: Timing: ELA:1/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.global_reset: Timing: ELA:1/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.soft_reset: Timing: ELA:1/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.afi_clk: Timing: ELA:2/0.000s/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.afi_half_clk: Timing: ELA:2/0.000s/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3.afi_reset: Timing: ELA:1/0.000s 2011.12.15.17:18:07 [Debug] TR4_QSYS.uniphy_ddr3: Timing: VAL:1/0.328s COM:1/0.938s 2011.12.15.17:18:07 [Debug] TR4_QSYS.TERASIC_CAMERA_0: Timing: QME:1/7.531s(3.0s) 2011.12.15.17:18:07 [Debug] TR4_QSYS.alt_vip_itc_0: Timing: ELA:1/0.000s 2011.12.15.17:07:11 [Debug] TR4_QSYS.altera_nios2_qsys: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.12.15.17:18:07 [Debug] TR4_QSYS.cpu: Timing: VAL:1/0.047s ELA:1/0.015s 2011.12.15.17:18:07 [Info] TR4_QSYS.mem: Memory will be initialized from mem.hex 2011.12.15.17:18:07 [Info] TR4_QSYS.camera_sda: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2011.12.15.17:18:07 [Info] TR4_QSYS.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2011.12.15.17:18:07 [Info] TR4_QSYS: Generating TR4_QSYS "TR4_QSYS" for QUARTUS_SYNTH 2011.12.15.17:18:07 [Debug] TR4_QSYS: queue size: 0 starting:TR4_QSYS "TR4_QSYS" 2011.12.15.17:18:09 [Debug] Transform: PipelineBridgeSwap 2011.12.15.17:18:10 [Info] pipeline_bridge_swap_transform: After transform: 14 modules, 41 connections 2011.12.15.17:18:10 [Debug] Transform: ClockCrossingBridgeSwap 2011.12.15.17:18:12 [Debug] Transform: QsysBetaIPSwap 2011.12.15.17:18:13 [Debug] Transform: CustomInstructionTransform 2011.12.15.17:18:14 [Info] No custom instruction connections, skipping transform 2011.12.15.17:18:14 [Debug] Transform: TristateConduitUpgradeTransform 2011.12.15.17:18:17 [Debug] Transform: TranslatorTransform 2011.12.15.17:18:18 [Progress] min: 0 2011.12.15.17:18:18 [Progress] max: 1 2011.12.15.17:18:18 [Progress] current: 1 2011.12.15.17:18:18 [Progress] min: 0 2011.12.15.17:18:18 [Progress] max: 1 2011.12.15.17:18:18 [Progress] current: 1 2011.12.15.17:18:18 [Progress] min: 0 2011.12.15.17:18:18 [Progress] max: 1 2011.12.15.17:18:18 [Progress] current: 1 2011.12.15.17:18:18 [Progress] min: 0 2011.12.15.17:18:18 [Progress] max: 1 2011.12.15.17:18:18 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Progress] min: 0 2011.12.15.17:18:19 [Progress] max: 1 2011.12.15.17:18:19 [Progress] current: 1 2011.12.15.17:18:19 [Info] merlin_translator_transform: After transform: 27 modules, 80 connections 2011.12.15.17:18:19 [Debug] Transform: DomainTransform 2011.12.15.17:18:20 [Debug] Transform merlin_domain_transform not run on matched interfaces alt_vip_vfb_0.write_master and alt_vip_vfb_0_write_master_translator.avalon_anti_master_0 2011.12.15.17:18:20 [Debug] Transform merlin_domain_transform not run on matched interfaces alt_vip_vfb_0.read_master and alt_vip_vfb_0_read_master_translator.avalon_anti_master_0 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Debug] Transform merlin_domain_transform not run on matched interfaces uniphy_ddr3_avl_translator.avalon_anti_slave_0 and uniphy_ddr3.avl 2011.12.15.17:18:20 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 2011.12.15.17:18:20 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:20 [Progress] min: 0 2011.12.15.17:18:20 [Progress] max: 1 2011.12.15.17:18:20 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Progress] min: 0 2011.12.15.17:18:21 [Progress] max: 1 2011.12.15.17:18:21 [Progress] current: 1 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_jtag_debug_module_translator.avalon_anti_slave_0 and cpu.jtag_debug_module 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces mem_s1_translator.avalon_anti_slave_0 and mem.s1 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces camera_sda_s1_translator.avalon_anti_slave_0 and camera_sda.s1 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces camera_scl_s1_translator.avalon_anti_slave_0 and camera_scl.s1 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces camera_reset_n_s1_translator.avalon_anti_slave_0 and camera_reset_n.s1 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces sw_s1_translator.avalon_anti_slave_0 and sw.s1 2011.12.15.17:18:21 [Debug] Transform merlin_domain_transform not run on matched interfaces timer_0_s1_translator.avalon_anti_slave_0 and timer_0.s1 2011.12.15.17:18:21 [Info] merlin_domain_transform: After transform: 52 modules, 207 connections 2011.12.15.17:18:21 [Debug] Transform: RouterTransform 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Progress] min: 0 2011.12.15.17:18:22 [Progress] max: 1 2011.12.15.17:18:22 [Progress] current: 1 2011.12.15.17:18:22 [Info] merlin_router_transform: After transform: 65 modules, 246 connections 2011.12.15.17:18:22 [Debug] Transform: TrafficLimiterTransform 2011.12.15.17:18:24 [Progress] min: 0 2011.12.15.17:18:24 [Progress] max: 1 2011.12.15.17:18:24 [Progress] current: 1 2011.12.15.17:18:24 [Progress] min: 0 2011.12.15.17:18:24 [Progress] max: 1 2011.12.15.17:18:24 [Progress] current: 1 2011.12.15.17:18:24 [Info] merlin_traffic_limiter_transform: After transform: 67 modules, 254 connections 2011.12.15.17:18:24 [Debug] Transform: BurstTransform 2011.12.15.17:18:25 [Debug] Transform: ResetAdaptation 2011.12.15.17:18:27 [Progress] min: 0 2011.12.15.17:18:27 [Progress] max: 1 2011.12.15.17:18:27 [Progress] current: 1 2011.12.15.17:18:27 [Progress] min: 0 2011.12.15.17:18:27 [Progress] max: 1 2011.12.15.17:18:27 [Progress] current: 1 2011.12.15.17:18:27 [Progress] min: 0 2011.12.15.17:18:27 [Progress] max: 1 2011.12.15.17:18:27 [Progress] current: 1 2011.12.15.17:18:27 [Info] reset_adaptation_transform: After transform: 70 modules, 260 connections 2011.12.15.17:18:27 [Debug] Transform: NetworkToSwitchTransform 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Progress] min: 0 2011.12.15.17:18:28 [Progress] max: 1 2011.12.15.17:18:28 [Progress] current: 1 2011.12.15.17:18:28 [Info] merlin_network_to_switch_transform: After transform: 94 modules, 310 connections 2011.12.15.17:18:28 [Debug] Transform: WidthTransform 2011.12.15.17:18:30 [Progress] min: 0 2011.12.15.17:18:30 [Progress] max: 1 2011.12.15.17:18:30 [Progress] current: 1 2011.12.15.17:18:30 [Progress] min: 0 2011.12.15.17:18:30 [Progress] max: 1 2011.12.15.17:18:30 [Progress] current: 1 2011.12.15.17:18:30 [Info] merlin_width_transform: After transform: 96 modules, 316 connections 2011.12.15.17:18:30 [Debug] Transform: RouterTableTransform 2011.12.15.17:18:32 [Debug] Transform: ClockCrossingTransform 2011.12.15.17:18:34 [Debug] Transform: PipelineTransform 2011.12.15.17:18:36 [Debug] Transform: TrafficLimiterUpdateTransform 2011.12.15.17:18:37 [Info] limiter_update_transform: After transform: 96 modules, 318 connections 2011.12.15.17:18:37 [Debug] Transform: InterruptMapperTransform 2011.12.15.17:18:39 [Progress] min: 0 2011.12.15.17:18:39 [Progress] max: 1 2011.12.15.17:18:39 [Progress] current: 1 2011.12.15.17:18:39 [Info] merlin_interrupt_mapper_transform: After transform: 97 modules, 321 connections 2011.12.15.17:18:39 [Debug] Transform: InterruptSyncTransform 2011.12.15.17:18:41 [Debug] Transform: InterruptFanoutTransform 2011.12.15.17:18:44 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:dataavailable (dataavailable)" 2011.12.15.17:18:44 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:readyfordata (readyfordata)" 2011.12.15.17:18:44 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2011.12.15.17:18:44 [Debug] TR4_QSYS: "TR4_QSYS" reuses TERASIC_CAMERA "submodules/TERASIC_CAMERA" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses alt_vip_vfb "submodules/TR4_QSYS_alt_vip_vfb_0" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses alt_vip_itc "submodules/alt_vipitc110_IS2Vid" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_nios2_qsys "submodules/TR4_QSYS_cpu" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_onchip_memory2 "submodules/TR4_QSYS_mem" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_camera_sda" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_camera_scl" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_camera_scl" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_jtag_uart "submodules/TR4_QSYS_jtag_uart" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_sw" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_timer "submodules/TR4_QSYS_timer_0" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_002" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_001" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_001" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux_001" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux_001" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_001" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_001" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_002" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_003" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.12.15.17:18:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_irq_mapper "submodules/TR4_QSYS_irq_mapper" 2011.12.15.17:18:45 [Debug] TR4_QSYS: queue size: 86 starting:altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2011.12.15.17:18:45 [Info] uniphy_ddr3: Running transform AvalonTransform 2011.12.15.17:18:45 [Debug] Transform: PipelineBridgeSwap 2011.12.15.17:18:46 [Info] pipeline_bridge_swap_transform: After transform: 8 modules, 10 connections 2011.12.15.17:18:46 [Debug] Transform: ClockCrossingBridgeSwap 2011.12.15.17:18:46 [Debug] Transform: QsysBetaIPSwap 2011.12.15.17:18:46 [Debug] Transform: CustomInstructionTransform 2011.12.15.17:18:47 [Info] No custom instruction connections, skipping transform 2011.12.15.17:18:47 [Debug] Transform: TristateConduitUpgradeTransform 2011.12.15.17:18:48 [Debug] Transform: TranslatorTransform 2011.12.15.17:18:48 [Info] No Avalon connections, skipping transform 2011.12.15.17:18:48 [Debug] Transform: DomainTransform 2011.12.15.17:18:49 [Debug] Transform: RouterTransform 2011.12.15.17:18:49 [Debug] Transform: TrafficLimiterTransform 2011.12.15.17:18:50 [Debug] Transform: BurstTransform 2011.12.15.17:18:50 [Debug] Transform: ResetAdaptation 2011.12.15.17:18:51 [Debug] Transform: NetworkToSwitchTransform 2011.12.15.17:18:51 [Debug] Transform: WidthTransform 2011.12.15.17:18:52 [Debug] Transform: RouterTableTransform 2011.12.15.17:18:52 [Debug] Transform: ClockCrossingTransform 2011.12.15.17:18:53 [Debug] Transform: TrafficLimiterUpdateTransform 2011.12.15.17:18:53 [Debug] Transform: InterruptMapperTransform 2011.12.15.17:18:54 [Debug] Transform: InterruptSyncTransform 2011.12.15.17:18:55 [Debug] Transform: InterruptFanoutTransform 2011.12.15.17:18:56 [Info] uniphy_ddr3: Running transform AvalonTransform took 10.766s 2011.12.15.17:18:56 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2011.12.15.17:18:56 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_phy "submodules/TR4_QSYS_uniphy_ddr3_p0" 2011.12.15.17:18:56 [Info] uniphy_ddr3: "TR4_QSYS" instantiated altera_mem_if_ddr3_emif "uniphy_ddr3" 2011.12.15.17:18:56 [Debug] TR4_QSYS: queue size: 87 starting:TERASIC_CAMERA "submodules/TERASIC_CAMERA" 2011.12.15.17:06:47 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.12.15.17:06:47 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0001_sopcqmap/not_a_project_setup.tcl 2011.12.15.17:06:47 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=D:/SVN/tr4/daughter_card/TR4_AHA/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0001_sopcqmap/ 2011.12.15.17:06:50 [Debug] Command took 2.797s 2011.12.15.17:06:54 [Debug] Command took 4.640s 2011.12.15.17:18:56 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.12.15.17:18:56 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0002_sopcqmap/not_a_project_setup.tcl 2011.12.15.17:18:56 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe "not_a_project" "--generate_hdl_interface=D:\\SVN\\tr4\\daughter_card\\TR4_AHA\\ip\\TERASIC_CAMERA\\TERASIC_CAMERA.v" "--set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0002_sopcqmap/" "--set=HDL_INTERFACE_INSTANCE_NAME=inst" "--set=HDL_INTERFACE_INSTANCE_ENTITY=TERASIC_CAMERA" "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=VIDEO_W=D\"1280\";VIDEO_H=D\"720\";" 2011.12.15.17:18:59 [Debug] Command took 3.156s 2011.12.15.17:19:03 [Debug] Command took 3.953s 2011.12.15.17:19:03 [Info] TERASIC_CAMERA_0: "TR4_QSYS" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0" 2011.12.15.17:19:03 [Debug] TR4_QSYS: queue size: 86 starting:alt_vip_vfb "submodules/TR4_QSYS_alt_vip_vfb_0" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp110_avalon_st_input" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxfast4 "submodules/alt_cusp110_muxfast4" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp110_avalon_st_output" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp110_avalon_mm_bursting_master_fifo" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp110_pulling_width_adapter" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp110_avalon_mm_bursting_master_fifo" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp110_pushing_width_adapter" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp110_pc" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp110_pc" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp110_au" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:14 [Debug] alt_vip_vfb_0: "alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:19:16 [Debug] dut: "dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp110_clock_reset" 2011.12.15.17:19:16 [Debug] dut: "dut" reuses alt_vip_vfb "submodules/TR4_QSYS_alt_vip_vfb_0" 2011.12.15.17:19:16 [Info] alt_vip_vfb_0: "TR4_QSYS" instantiated alt_vip_vfb "alt_vip_vfb_0" 2011.12.15.17:19:16 [Debug] TR4_QSYS: queue size: 310 starting:alt_vip_itc "submodules/alt_vipitc110_IS2Vid" 2011.12.15.17:19:16 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.12.15.17:19:16 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0003_sopcqmap/not_a_project_setup.tcl 2011.12.15.17:19:16 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=C:/altera/11.0/ip/altera/clocked_video_output/src_hdl/alt_vipitc110_IS2Vid.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0003_sopcqmap/ 2011.12.15.17:19:19 [Debug] Command took 2.719s 2011.12.15.17:19:23 [Debug] Command took 3.860s 2011.12.15.17:19:23 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.12.15.17:19:23 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0004_sopcqmap/not_a_project_setup.tcl 2011.12.15.17:19:23 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe "not_a_project" "--generate_hdl_interface=C:\\altera\\11.0\\ip\\altera\\clocked_video_output\\src_hdl\\alt_vipitc110_IS2Vid.v" "--set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0004_sopcqmap/" "--set=HDL_INTERFACE_INSTANCE_NAME=inst" "--set=HDL_INTERFACE_INSTANCE_ENTITY=alt_vipitc110_IS2Vid" "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=NUMBER_OF_COLOUR_PLANES=D\"3\";COLOUR_PLANES_ARE_IN_PARALLEL=D\"1\";BPS=D\"8\";INTERLACED=D\"0\";H_ACTIVE_PIXELS=D\"1280\";V_ACTIVE_LINES=D\"720\";ACCEPT_COLOURS_IN_SEQ=D\"0\";FIFO_DEPTH=D\"1280\";CLOCKS_ARE_SAME=D\"0\";USE_CONTROL=D\"0\";NO_OF_MODES=D\"1\";THRESHOLD=D\"1279\";STD_WIDTH=D\"1\";GENERATE_SYNC=D\"0\";USE_EMBEDDED_SYNCS=D\"0\";AP_LINE=D\"0\";V_BLANK=D\"0\";H_BLANK=D\"0\";H_SYNC_LENGTH=D\"32\";H_FRONT_PORCH=D\"48\";H_BACK_PORCH=D\"80\";V_SYNC_LENGTH=D\"45\";V_FRONT_PORCH=D\"2\";V_BACK_PORCH=D\"14\";F_RISING_EDGE=D\"0\";F_FALLING_EDGE=D\"0\";FIELD0_V_RISING_EDGE=D\"0\";FIELD0_V_BLANK=D\"0\";FIELD0_V_SYNC_LENGTH=D\"0\";FIELD0_V_FRONT_PORCH=D\"0\";FIELD0_V_BACK_PORCH=D\"0\";ANC_LINE=D\"0\";FIELD0_ANC_LINE=D\"0\";" 2011.12.15.17:19:25 [Debug] Command took 2.766s 2011.12.15.17:19:30 [Debug] Command took 4.406s 2011.12.15.17:19:30 [Info] alt_vip_itc_0: "TR4_QSYS" instantiated alt_vip_itc "alt_vip_itc_0" 2011.12.15.17:19:30 [Debug] TR4_QSYS: queue size: 309 starting:altera_nios2_qsys "submodules/TR4_QSYS_cpu" 2011.12.15.17:19:30 [Info] cpu: Starting RTL generation for module 'TR4_QSYS_cpu' 2011.12.15.17:19:30 [Info] cpu: Generation command is [exec C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/11.0/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/11.0/quartus/sopc_builder/bin/europa -I C:/altera/11.0/quartus/sopc_builder/bin/perl_lib -I C:/altera/11.0/quartus/sopc_builder/bin -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/11.0/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=TR4_QSYS_cpu --dir=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0005_cpu_gen/ --quartus_dir=C:/altera/11.0/quartus --verilog --config=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0005_cpu_gen//TR4_QSYS_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:31 (*) Starting Nios II generation 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:31 (*) Checking for encrypted license (non-evaluation). 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:35 (*) Encrypted license found. SOF will not be time-limited. 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:35 (*) Elaborating CPU configuration settings 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:35 (*) Creating all objects for CPU 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:35 (*) Testbench 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:36 (*) Instruction decoding 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:36 (*) Instruction fields 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:36 (*) Instruction decodes 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:37 (*) Signals for RTL simulation waveforms 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:37 (*) Instruction controls 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:37 (*) Pipeline frontend 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:37 (*) Pipeline backend 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:40 (*) Generating RTL from CPU objects 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:43 (*) Creating encrypted RTL 2011.12.15.17:19:45 [Info] cpu: # 2011.12.15 17:19:45 (*) Done Nios II generation 2011.12.15.17:19:45 [Info] cpu: Done RTL generation for module 'TR4_QSYS_cpu' 2011.12.15.17:19:45 [Info] cpu: "TR4_QSYS" instantiated altera_nios2_qsys "cpu" 2011.12.15.17:19:45 [Debug] TR4_QSYS: queue size: 308 starting:altera_avalon_onchip_memory2 "submodules/TR4_QSYS_mem" 2011.12.15.17:19:45 [Info] Starting classic module elaboration. 2011.12.15.17:19:46 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0006_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:19:49 [Info] Finished elaborating classic module. 2011.12.15.17:19:49 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0006_sopclgen/yysystem.ptf 2011.12.15.17:19:49 [Info] Running sopc_builder... 2011.12.15.17:19:50 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0006_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:19:52 [Progress] No .sopc_builder configuration file(!) 2011.12.15.17:19:52 [Progress] . 2011.12.15.17:19:54 [Progress] # 2011.12.15 17:19:54 (*) Success: sopc_builder finished. 2011.12.15.17:19:55 [Info] mem: "TR4_QSYS" instantiated altera_avalon_onchip_memory2 "mem" 2011.12.15.17:19:55 [Debug] TR4_QSYS: queue size: 307 starting:altera_avalon_pio "submodules/TR4_QSYS_camera_sda" 2011.12.15.17:19:55 [Info] Starting classic module elaboration. 2011.12.15.17:19:56 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0007_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:19:57 [Info] Finished elaborating classic module. 2011.12.15.17:19:57 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0007_sopclgen/yysystem.ptf 2011.12.15.17:19:57 [Info] Running sopc_builder... 2011.12.15.17:19:58 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0007_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:00 [Progress] No .sopc_builder configuration file(!) 2011.12.15.17:20:00 [Progress] . 2011.12.15.17:20:01 [Progress] # 2011.12.15 17:20:01 (*) Success: sopc_builder finished. 2011.12.15.17:20:01 [Info] camera_sda: "TR4_QSYS" instantiated altera_avalon_pio "camera_sda" 2011.12.15.17:20:01 [Debug] TR4_QSYS: queue size: 306 starting:altera_avalon_pio "submodules/TR4_QSYS_camera_scl" 2011.12.15.17:20:01 [Info] Starting classic module elaboration. 2011.12.15.17:20:02 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0008_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:03 [Info] Finished elaborating classic module. 2011.12.15.17:20:03 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0008_sopclgen/yysystem.ptf 2011.12.15.17:20:03 [Info] Running sopc_builder... 2011.12.15.17:20:04 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0008_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:05 [Progress] No .sopc_builder configuration file(!) 2011.12.15.17:20:05 [Progress] . 2011.12.15.17:20:06 [Progress] # 2011.12.15 17:20:06 (*) Success: sopc_builder finished. 2011.12.15.17:20:07 [Info] camera_scl: "TR4_QSYS" instantiated altera_avalon_pio "camera_scl" 2011.12.15.17:20:07 [Debug] TR4_QSYS: queue size: 304 starting:altera_avalon_jtag_uart "submodules/TR4_QSYS_jtag_uart" 2011.12.15.17:20:07 [Info] Starting classic module elaboration. 2011.12.15.17:20:08 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0009_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:09 [Info] Finished elaborating classic module. 2011.12.15.17:20:09 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0009_sopclgen/yysystem.ptf 2011.12.15.17:20:09 [Info] Running sopc_builder... 2011.12.15.17:20:10 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0009_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:11 [Progress] No .sopc_builder configuration file(!) 2011.12.15.17:20:11 [Progress] . 2011.12.15.17:20:13 [Progress] # 2011.12.15 17:20:13 (*) Success: sopc_builder finished. 2011.12.15.17:20:13 [Info] jtag_uart: "TR4_QSYS" instantiated altera_avalon_jtag_uart "jtag_uart" 2011.12.15.17:20:13 [Debug] TR4_QSYS: queue size: 303 starting:altera_avalon_pio "submodules/TR4_QSYS_sw" 2011.12.15.17:20:13 [Info] Starting classic module elaboration. 2011.12.15.17:20:14 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0010_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:15 [Info] Finished elaborating classic module. 2011.12.15.17:20:15 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0010_sopclgen/yysystem.ptf 2011.12.15.17:20:15 [Info] Running sopc_builder... 2011.12.15.17:20:16 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0010_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:18 [Progress] No .sopc_builder configuration file(!) 2011.12.15.17:20:18 [Progress] . 2011.12.15.17:20:19 [Progress] # 2011.12.15 17:20:19 (*) Success: sopc_builder finished. 2011.12.15.17:20:19 [Info] sw: "TR4_QSYS" instantiated altera_avalon_pio "sw" 2011.12.15.17:20:19 [Debug] TR4_QSYS: queue size: 302 starting:altera_avalon_timer "submodules/TR4_QSYS_timer_0" 2011.12.15.17:20:19 [Info] Starting classic module elaboration. 2011.12.15.17:20:20 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0011_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:21 [Info] Finished elaborating classic module. 2011.12.15.17:20:21 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0011_sopclgen/yysystem.ptf 2011.12.15.17:20:21 [Info] Running sopc_builder... 2011.12.15.17:20:22 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0011_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5323_8605158740455665978.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip" 2011.12.15.17:20:23 [Progress] No .sopc_builder configuration file(!) 2011.12.15.17:20:23 [Progress] . 2011.12.15.17:20:24 [Progress] # 2011.12.15 17:20:24 (*) Success: sopc_builder finished. 2011.12.15.17:20:25 [Info] timer_0: "TR4_QSYS" instantiated altera_avalon_timer "timer_0" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 301 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.15.17:20:25 [Info] alt_vip_vfb_0_write_master_translator: "TR4_QSYS" instantiated altera_merlin_master_translator "alt_vip_vfb_0_write_master_translator" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 299 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.15.17:20:25 [Info] uniphy_ddr3_avl_translator: "TR4_QSYS" instantiated altera_merlin_slave_translator "uniphy_ddr3_avl_translator" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 288 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.15.17:20:25 [Info] alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent: "TR4_QSYS" instantiated altera_merlin_master_agent "alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 286 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.15.17:20:25 [Info] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent: "TR4_QSYS" instantiated altera_merlin_slave_agent "uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 285 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.15.17:20:25 [Info] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo: "TR4_QSYS" instantiated altera_avalon_sc_fifo "uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 265 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router" 2011.12.15.17:20:25 [Info] addr_router: "TR4_QSYS" instantiated altera_merlin_router "addr_router" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 263 starting:altera_merlin_router "submodules/TR4_QSYS_id_router" 2011.12.15.17:20:25 [Info] id_router: "TR4_QSYS" instantiated altera_merlin_router "id_router" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 262 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_002" 2011.12.15.17:20:25 [Info] addr_router_002: "TR4_QSYS" instantiated altera_merlin_router "addr_router_002" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 261 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_003" 2011.12.15.17:20:25 [Info] addr_router_003: "TR4_QSYS" instantiated altera_merlin_router "addr_router_003" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 260 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_001" 2011.12.15.17:20:25 [Info] id_router_001: "TR4_QSYS" instantiated altera_merlin_router "id_router_001" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 258 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2011.12.15.17:20:25 [Info] id_router_003: "TR4_QSYS" instantiated altera_merlin_router "id_router_003" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 252 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.12.15.17:20:25 [Info] limiter: "TR4_QSYS" instantiated altera_merlin_traffic_limiter "limiter" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 250 starting:altera_reset_controller "submodules/altera_reset_controller" 2011.12.15.17:20:25 [Info] rst_controller: "TR4_QSYS" instantiated altera_reset_controller "rst_controller" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 247 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2011.12.15.17:20:25 [Info] cmd_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 245 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2011.12.15.17:20:25 [Info] cmd_xbar_mux: "TR4_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 244 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2011.12.15.17:20:25 [Info] rsp_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 243 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2011.12.15.17:20:25 [Info] cmd_xbar_demux_002: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_002" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 242 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_003" 2011.12.15.17:20:25 [Info] cmd_xbar_demux_003: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_003" 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 241 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux_001" 2011.12.15.17:20:25 [Info] cmd_xbar_mux_001: "TR4_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux_001" 2011.12.15.17:20:25 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.12.15.17:20:25 [Debug] TR4_QSYS: queue size: 239 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_001" 2011.12.15.17:20:26 [Info] rsp_xbar_demux_001: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_001" 2011.12.15.17:20:26 [Debug] TR4_QSYS: queue size: 237 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_003" 2011.12.15.17:20:26 [Info] rsp_xbar_demux_003: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_003" 2011.12.15.17:20:26 [Debug] TR4_QSYS: queue size: 231 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_002" 2011.12.15.17:20:26 [Info] rsp_xbar_mux_002: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_002" 2011.12.15.17:20:26 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.12.15.17:20:26 [Debug] TR4_QSYS: queue size: 230 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_003" 2011.12.15.17:20:26 [Info] rsp_xbar_mux_003: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_003" 2011.12.15.17:20:26 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.12.15.17:20:26 [Debug] TR4_QSYS: queue size: 229 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.12.15.17:20:26 [Info] width_adapter: "TR4_QSYS" instantiated altera_merlin_width_adapter "width_adapter" 2011.12.15.17:20:26 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2011.12.15.17:20:26 [Debug] TR4_QSYS: queue size: 227 starting:altera_irq_mapper "submodules/TR4_QSYS_irq_mapper" 2011.12.15.17:20:26 [Info] irq_mapper: "TR4_QSYS" instantiated altera_irq_mapper "irq_mapper" 2011.12.15.17:20:26 [Debug] TR4_QSYS: queue size: 226 starting:altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2011.12.15.17:20:26 [Info] c0: Running transform AvalonTransform 2011.12.15.17:20:26 [Debug] Transform: PipelineBridgeSwap 2011.12.15.17:20:26 [Info] pipeline_bridge_swap_transform: After transform: 5 modules, 8 connections 2011.12.15.17:20:26 [Debug] Transform: ClockCrossingBridgeSwap 2011.12.15.17:20:26 [Debug] Transform: QsysBetaIPSwap 2011.12.15.17:20:26 [Debug] Transform: CustomInstructionTransform 2011.12.15.17:20:26 [Info] No custom instruction connections, skipping transform 2011.12.15.17:20:26 [Debug] Transform: TristateConduitUpgradeTransform 2011.12.15.17:20:26 [Debug] Transform: TranslatorTransform 2011.12.15.17:20:26 [Info] No Avalon connections, skipping transform 2011.12.15.17:20:26 [Debug] Transform: DomainTransform 2011.12.15.17:20:27 [Debug] Transform: RouterTransform 2011.12.15.17:20:27 [Debug] Transform: TrafficLimiterTransform 2011.12.15.17:20:27 [Debug] Transform: BurstTransform 2011.12.15.17:20:27 [Debug] Transform: ResetAdaptation 2011.12.15.17:20:27 [Debug] Transform: NetworkToSwitchTransform 2011.12.15.17:20:27 [Debug] Transform: WidthTransform 2011.12.15.17:20:27 [Debug] Transform: RouterTableTransform 2011.12.15.17:20:27 [Debug] Transform: ClockCrossingTransform 2011.12.15.17:20:27 [Debug] Transform: TrafficLimiterUpdateTransform 2011.12.15.17:20:27 [Debug] Transform: InterruptMapperTransform 2011.12.15.17:20:27 [Debug] Transform: InterruptSyncTransform 2011.12.15.17:20:27 [Debug] Transform: InterruptFanoutTransform 2011.12.15.17:20:27 [Info] c0: Running transform AvalonTransform took 1.531s 2011.12.15.17:20:27 [Debug] c0: "c0" reuses altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2011.12.15.17:20:27 [Debug] c0: "c0" reuses alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2011.12.15.17:20:27 [Info] c0: "uniphy_ddr3" instantiated altera_mem_if_nextgen_ddr3_controller "c0" 2011.12.15.17:20:27 [Debug] TR4_QSYS: queue size: 227 starting:altera_mem_if_ddr3_phy "submodules/TR4_QSYS_uniphy_ddr3_p0" 2011.12.15.17:21:53 [Info] p0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_phy "p0" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_reset_controller.v 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 226 starting:alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.12.15.17:21:53 [Info] vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst" 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 224 starting:alt_au "submodules/alt_cusp110_au" 2011.12.15.17:21:53 [Info] vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au" 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 215 starting:alt_reg "submodules/alt_cusp110_reg" 2011.12.15.17:21:53 [Info] vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 214 starting:alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.12.15.17:21:53 [Info] vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst" 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 180 starting:alt_avalon_st_input "submodules/alt_cusp110_avalon_st_input" 2011.12.15.17:21:53 [Info] din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 178 starting:alt_cusp_muxfast4 "submodules/alt_cusp110_muxfast4" 2011.12.15.17:21:53 [Info] dout_wdata_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxfast4 "dout_wdata_muxinst" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 175 starting:alt_avalon_st_output "submodules/alt_cusp110_avalon_st_output" 2011.12.15.17:21:53 [Info] dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 171 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp110_avalon_mm_bursting_master_fifo" 2011.12.15.17:21:53 [Info] read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 169 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp110_pulling_width_adapter" 2011.12.15.17:21:53 [Info] read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 163 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp110_pushing_width_adapter" 2011.12.15.17:21:53 [Info] write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 121 starting:alt_pc "submodules/alt_cusp110_pc" 2011.12.15.17:21:53 [Info] pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 59 starting:alt_cmp "submodules/alt_cusp110_cmp" 2011.12.15.17:21:53 [Info] fu_id_5128_line317_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_5128_line317_93" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 3 starting:alt_cusp_testbench_clock "submodules/alt_cusp110_clock_reset" 2011.12.15.17:21:53 [Info] clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource" 2011.12.15.17:21:53 [Info] Reusing file D:/SVN/tr4/daughter_card/TR4_AHA/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.12.15.17:21:53 [Debug] TR4_QSYS: queue size: 1 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2011.12.15.17:21:54 [Info] ng0: "c0" instantiated altera_mem_if_nextgen_ddr3_controller_core "ng0" 2011.12.15.17:21:54 [Debug] TR4_QSYS: queue size: 0 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2011.12.15.17:21:54 [Info] a0: "c0" instantiated alt_mem_ddrx_mm_st_converter "a0" 2011.12.15.17:21:54 [Info] TR4_QSYS: Done TR4_QSYS" with 54 modules, 712 files, 32408200 bytes