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TimeQuest Timing Analyzer Summary
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Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.174
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.174
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'mem_ck[0]'
Slack : 0.653
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'CK_IMG_IN_PIXCLK'
Slack : 0.733
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.041
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.041
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.130
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.130
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 1.702
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 2.160
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 2.160
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 5.200
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 5.200
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 9.335
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 9.335
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 11.264
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 11.307
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'altera_reserved_tck'
Slack : 47.454
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.099
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 0.103
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.103
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.154
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.154
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.181
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.181
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.195
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.195
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.195
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.217
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 0.232
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.232
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'CK_IMG_IN_PIXCLK'
Slack : 0.244
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'altera_reserved_tck'
Slack : 0.323
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'mem_ck[0]'
Slack : 0.630
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.080
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.080
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : -5.715
TNS   : -673.532

Type  : Slow 900mV 85C Model Recovery 'CK_IMG_IN_PIXCLK'
Slack : -3.252
TNS   : -433.150

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.014
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.014
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 2.316
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.316
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.359
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.359
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 14.576
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 37.291
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 37.291
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'altera_reserved_tck'
Slack : 48.797
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.378
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.378
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'altera_reserved_tck'
Slack : 0.517
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.534
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'CK_IMG_IN_PIXCLK'
Slack : 0.783
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.980
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.980
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 1.148
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 1.148
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 4.220
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.707
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.707
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk'
Slack : 0.503
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.503
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.639
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.709
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.709
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.707
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.707
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.902
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.902
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.211
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.211
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 4.463
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 4.463
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'CK_IMG_IN_PIXCLK'
Slack : 5.470
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 6.667
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 6.667
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 7.481
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 9.199
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'CLK_M4'
Slack : 9.762
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'CLK_M5'
Slack : 9.764
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.327
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.379
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.379
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'mem_ck[0]'
Slack : 0.666
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'CK_IMG_IN_PIXCLK'
Slack : 0.770
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.026
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.026
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.275
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.275
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 1.687
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 2.304
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 2.304
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 5.443
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 5.443
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 9.360
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 9.360
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 11.489
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 11.813
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'altera_reserved_tck'
Slack : 47.565
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 0.107
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.107
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.145
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.151
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.151
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.177
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.177
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.182
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.188
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.188
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.196
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 0.229
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.229
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'CK_IMG_IN_PIXCLK'
Slack : 0.234
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.318
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'mem_ck[0]'
Slack : 0.655
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.118
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.118
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : -5.403
TNS   : -637.087

Type  : Slow 900mV 0C Model Recovery 'CK_IMG_IN_PIXCLK'
Slack : -3.073
TNS   : -401.860

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.196
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.196
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 2.460
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.460
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.604
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.604
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 14.803
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 37.441
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 37.441
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'altera_reserved_tck'
Slack : 48.806
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.367
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.367
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'altera_reserved_tck'
Slack : 0.499
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.509
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'CK_IMG_IN_PIXCLK'
Slack : 0.765
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.963
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.963
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 1.089
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 1.089
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 4.015
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.454
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.454
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk'
Slack : 0.510
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.510
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.661
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.730
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.730
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.722
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.722
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.923
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.923
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.227
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.227
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 4.448
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 4.448
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'CK_IMG_IN_PIXCLK'
Slack : 5.474
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 6.667
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 6.667
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 7.463
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 9.215
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'CLK_M4'
Slack : 9.748
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'CLK_M5'
Slack : 9.749
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.356
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'mem_ck[0]'
Slack : 0.711
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.902
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.902
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.387
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.387
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'CK_IMG_IN_PIXCLK'
Slack : 1.446
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 1.549
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 2.132
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.132
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 3.319
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 3.319
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 7.296
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 7.296
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 9.632
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 9.632
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 13.593
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 14.531
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'altera_reserved_tck'
Slack : 48.743
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 0.043
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.043
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.078
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.078
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.086
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.086
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.098
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.098
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 0.108
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.108
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.129
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'CK_IMG_IN_PIXCLK'
Slack : 0.141
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.146
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.184
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.499
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'mem_ck[0]'
Slack : 0.716
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.343
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.343
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.923
TNS   : -342.335

Type  : Fast 900mV 0C Model Recovery 'CK_IMG_IN_PIXCLK'
Slack : -1.371
TNS   : -136.474

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 2.487
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.487
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 3.331
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 3.331
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 6.486
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 6.486
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 16.616
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 38.348
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 38.348
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'altera_reserved_tck'
Slack : 49.626
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.207
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.207
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.291
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'altera_reserved_tck'
Slack : 0.302
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'CK_IMG_IN_PIXCLK'
Slack : 0.476
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.577
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.577
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.691
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.691
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 2.700
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 2.984
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 2.984
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk'
Slack : 0.505
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.505
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.703
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.705
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.705
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.706
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.706
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 2.079
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.079
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.210
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.210
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 4.660
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 4.660
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'CK_IMG_IN_PIXCLK'
Slack : 5.231
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 6.667
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 6.667
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 7.540
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]'
Slack : 9.202
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'CLK_M4'
Slack : 9.874
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'CLK_M5'
Slack : 9.875
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.191
TNS   : 0.000

------------------------------------------------------------
