## Generated SDC file "TR4_AHA.out.sdc"

## Copyright (C) 1991-2011 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic 
## functions, and any output files from any of the foregoing 
## (including device programming or simulation files), and any 
## associated documentation or information are expressly subject 
## to the terms and conditions of the Altera Program License 
## Subscription Agreement, Altera MegaCore Function License 
## Agreement, or other applicable license agreement, including, 
## without limitation, that your use is for the sole purpose of 
## programming logic devices manufactured by Altera and sold by 
## Altera or its authorized distributors.  Please refer to the 
## applicable agreement for further details.


## VENDOR  "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 11.0 Build 157 04/27/2011 SJ Full Version"

## DATE    "Thu Dec 15 19:44:52 2011"

##
## DEVICE  "EP4SGX230KF40C2"
##


#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3



#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
create_clock -name {CLK_M1} -period 20.000 -waveform { 0.000 10.000 } [get_ports {OSC_50_BANK1}]
create_clock -name {CLK_M2} -period 20.000 -waveform { 0.000 10.000 } [get_ports {OSC_50_BANK3}]
create_clock -name {CLK_M3} -period 20.000 -waveform { 0.000 10.000 } [get_ports {OSC_50_BANK4}]
create_clock -name {CLK_M4} -period 20.000 -waveform { 0.000 10.000 } [get_ports {OSC_50_BANK7}]
create_clock -name {CLK_M5} -period 20.000 -waveform { 0.000 10.000 } [get_ports {OSC_50_BANK8}]
create_clock -name {CK_IMG_IN_PIXCLK} -period 12.500 -waveform { 0.000 6.250 } [get_ports {CK_IMG_IN_PIXCLK}]
create_clock -name {mem_dqs[0]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[0]}] -add
create_clock -name {mem_dqs[1]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[1]}] -add
create_clock -name {mem_dqs[2]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[2]}] -add
create_clock -name {mem_dqs[3]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[3]}] -add
create_clock -name {mem_dqs[4]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[4]}] -add
create_clock -name {mem_dqs[5]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[5]}] -add
create_clock -name {mem_dqs[6]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[6]}] -add
create_clock -name {mem_dqs[7]_IN} -period 2.500 -waveform { 0.000 1.250 } [get_ports {mem_dqs[7]}] -add


#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 8 -phase 90.000 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 270.000 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 2 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -add
create_generated_clock -name {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {sys_pll_inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 6 -divide_by 11 -master_clock {CLK_M4} [get_pins {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}] 
create_generated_clock -name {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {sys_pll_inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 6 -divide_by 5 -master_clock {CLK_M4} [get_pins {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] 
create_generated_clock -name {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {sys_pll_inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -master_clock {CLK_M4} [get_pins {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk} -source [get_ports {OSC_50_BANK8}] -multiply_by 4 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk} -source [get_ports {OSC_50_BANK8}] -multiply_by 8 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk} -source [get_ports {OSC_50_BANK8}] -multiply_by 8 -phase 90.000 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk} -source [get_ports {OSC_50_BANK8}] -multiply_by 4 -phase 270.000 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk} -source [get_ports {OSC_50_BANK8}] -multiply_by 2 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock} -source [get_ports {OSC_50_BANK8}] -multiply_by 2 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -add
create_generated_clock -name {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock} -source [get_ports {OSC_50_BANK8}] -divide_by 2 -master_clock {CLK_M5} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -add
create_generated_clock -name {mem_ck[0]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk} [get_ports {mem_ck[0]}] 
create_generated_clock -name {mem_ck_n[0]} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}] -master_clock {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk} -invert [get_ports {mem_ck_n[0]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_0} -source [get_ports {mem_dqs[0]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[0]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[0]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_1} -source [get_ports {mem_dqs[1]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[1]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[1]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_2} -source [get_ports {mem_dqs[2]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[2]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[2]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_3} -source [get_ports {mem_dqs[3]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[3]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[3]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_4} -source [get_ports {mem_dqs[4]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[4]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[4]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_5} -source [get_ports {mem_dqs[5]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[5]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[5]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_6} -source [get_ports {mem_dqs[6]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[6]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[6]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|div_clock_7} -source [get_ports {mem_dqs[7]}] -divide_by 2 -phase 90.000 -master_clock {mem_dqs[7]_IN} [get_registers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[7]}] 
create_generated_clock -name {u0|uniphy_ddr3|p0|memphy_leveling_clk} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk} [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk 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u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk 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u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk}] 
create_generated_clock -name {mem_dqs[0]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[0]}] -add
create_generated_clock -name {mem_dqs[1]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[1]}] -add
create_generated_clock -name {mem_dqs[2]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[2]}] -add
create_generated_clock -name {mem_dqs[3]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[3]}] -add
create_generated_clock -name {mem_dqs[4]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[4]}] -add
create_generated_clock -name {mem_dqs[5]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[5]}] -add
create_generated_clock -name {mem_dqs[6]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[6]}] -add
create_generated_clock -name {mem_dqs[7]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs[7]}] -add
create_generated_clock -name {mem_dqs_n[0]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[0]}] 
create_generated_clock -name {mem_dqs_n[1]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[1]}] 
create_generated_clock -name {mem_dqs_n[2]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[2]}] 
create_generated_clock -name {mem_dqs_n[3]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[3]}] 
create_generated_clock -name {mem_dqs_n[4]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[4]}] 
create_generated_clock -name {mem_dqs_n[5]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[5]}] 
create_generated_clock -name {mem_dqs_n[6]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[6]}] 
create_generated_clock -name {mem_dqs_n[7]_OUT} -source [get_pins {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o}] -phase 90.000 -master_clock {u0|uniphy_ddr3|p0|memphy_leveling_clk} [get_ports {mem_dqs_n[7]}] 


#**************************************************************
# Set Clock Latency
#**************************************************************



#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[2]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[2]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[3]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[3]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[4]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[4]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[5]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[5]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[6]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[6]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[7]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[7]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[0]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[1]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[2]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[2]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[3]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[3]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[4]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[4]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[5]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[5]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[6]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[6]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -rise_to [get_clocks {mem_dqs_n[7]_OUT}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}] -fall_to [get_clocks {mem_dqs_n[7]_OUT}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[0]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[1]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[2]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[3]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[4]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[5]_IN}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[6]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {altera_reserved_tck}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CLK_M5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_ck[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_ck_n[0]}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]  0.000 
set_clock_uncertainty -fall_from [get_clocks {mem_dqs[7]_IN}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]  0.000 
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {CK_IMG_IN_PIXCLK}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {CK_IMG_IN_PIXCLK}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {CK_IMG_IN_PIXCLK}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {CK_IMG_IN_PIXCLK}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {CK_IMG_IN_PIXCLK}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {CK_IMG_IN_PIXCLK}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {CK_IMG_IN_PIXCLK}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {CK_IMG_IN_PIXCLK}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {CK_IMG_IN_PIXCLK}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {CK_IMG_IN_PIXCLK}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {CK_IMG_IN_PIXCLK}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {CK_IMG_IN_PIXCLK}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {CLK_M1}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {CLK_M1}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {CLK_M1}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {CLK_M1}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {CK_IMG_IN_PIXCLK}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]}]  0.100 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|memphy_leveling_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[2]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[3]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[4]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[5]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[6]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[7]_IN}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[0]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[1]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[2]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[3]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[4]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[5]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[6]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -rise_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}] -fall_to [get_clocks {mem_dqs[7]_OUT}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -rise_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -fall_to [get_clocks {mem_ck[0]}]  0.050 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock}]  0.020 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -rise_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -rise_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 
set_clock_uncertainty -fall_from [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}] -fall_to [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  0.070 


#**************************************************************
# Set Input Delay
#**************************************************************

set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[0]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[1]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[1]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[2]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[2]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[3]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[3]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[4]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[4]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[5]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[5]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[6]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[6]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_IN}]  0.220 [get_ports {mem_dq[7]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_IN}]  -0.324 [get_ports {mem_dq[7]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[8]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[8]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[9]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[9]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[10]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[10]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[11]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[11]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[12]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[12]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[13]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[13]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[14]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[14]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_IN}]  0.220 [get_ports {mem_dq[15]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_IN}]  -0.324 [get_ports {mem_dq[15]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[16]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[16]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[17]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[17]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[18]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[18]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[19]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[19]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[20]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[20]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[21]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[21]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[22]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[22]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_IN}]  0.220 [get_ports {mem_dq[23]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_IN}]  -0.324 [get_ports {mem_dq[23]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[24]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[24]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[25]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[25]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[26]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[26]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[27]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[27]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[28]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[28]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[29]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[29]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[30]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[30]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_IN}]  0.220 [get_ports {mem_dq[31]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_IN}]  -0.324 [get_ports {mem_dq[31]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[32]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[32]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[33]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[33]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[34]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[34]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[35]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[35]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[36]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[36]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[37]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[37]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[38]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[38]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_IN}]  0.220 [get_ports {mem_dq[39]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_IN}]  -0.324 [get_ports {mem_dq[39]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[40]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[40]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[41]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[41]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[42]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[42]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[43]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[43]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[44]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[44]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[45]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[45]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[46]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[46]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_IN}]  0.220 [get_ports {mem_dq[47]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_IN}]  -0.324 [get_ports {mem_dq[47]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[48]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[48]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[49]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[49]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[50]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[50]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[51]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[51]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[52]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[52]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[53]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[53]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[54]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[54]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_IN}]  0.220 [get_ports {mem_dq[55]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_IN}]  -0.324 [get_ports {mem_dq[55]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[56]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[56]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[57]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[57]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[58]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[58]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[59]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[59]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[60]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[60]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[61]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[61]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[62]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[62]}]
set_input_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_IN}]  0.220 [get_ports {mem_dq[63]}]
set_input_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_IN}]  -0.324 [get_ports {mem_dq[63]}]


#**************************************************************
# Set Output Delay
#**************************************************************

set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_DE}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[0]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[1]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[2]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[3]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[4]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[5]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[6]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[7]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[8]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[9]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[10]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[11]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[12]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[13]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[14]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[15]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[16]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[17]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[18]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[19]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[20]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[21]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[22]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_D[23]}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_HS}]
set_output_delay -add_delay  -clock [get_clocks {CLK_M1}]  1.000 [get_ports {DVI_TX_VS}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[8]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[8]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[9]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[9]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[10]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[10]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[11]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[11]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[12]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[12]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_a[13]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_a[13]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_ba[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_ba[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_ba[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_cas_n}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_cas_n}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_cke[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_cke[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_cs_n[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_cs_n[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dm[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dm[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dm[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dm[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dm[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dm[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dm[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dm[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dm[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dm[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dm[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dm[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dm[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dm[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dm[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dm[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dm[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dm[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dm[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dm[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dm[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dm[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dm[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dm[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dm[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dm[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[1]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[2]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[3]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[4]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[5]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[6]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[0]_OUT}]  0.366 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[0]_OUT}]  -0.325 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[0]_OUT}]  0.366 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[0]_OUT}]  -0.325 [get_ports {mem_dq[7]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[8]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[9]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[10]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[11]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[12]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[13]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[14]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[1]_OUT}]  0.366 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[1]_OUT}]  -0.325 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[1]_OUT}]  0.366 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[1]_OUT}]  -0.325 [get_ports {mem_dq[15]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[16]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[16]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[16]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[16]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[17]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[17]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[17]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[17]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[18]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[18]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[18]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[18]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[19]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[19]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[19]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[19]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[20]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[20]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[20]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[20]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[21]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[21]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[21]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[21]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[22]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[22]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[22]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[22]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[2]_OUT}]  0.366 [get_ports {mem_dq[23]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[2]_OUT}]  -0.325 [get_ports {mem_dq[23]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[2]_OUT}]  0.366 [get_ports {mem_dq[23]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[2]_OUT}]  -0.325 [get_ports {mem_dq[23]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[24]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[24]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[24]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[24]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[25]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[25]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[25]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[25]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[26]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[26]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[26]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[26]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[27]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[27]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[27]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[27]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[28]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[28]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[28]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[28]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[29]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[29]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[29]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[29]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[30]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[30]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[30]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[30]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[3]_OUT}]  0.366 [get_ports {mem_dq[31]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[3]_OUT}]  -0.325 [get_ports {mem_dq[31]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[3]_OUT}]  0.366 [get_ports {mem_dq[31]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[3]_OUT}]  -0.325 [get_ports {mem_dq[31]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[32]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[32]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[32]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[32]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[33]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[33]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[33]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[33]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[34]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[34]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[34]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[34]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[35]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[35]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[35]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[35]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[36]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[36]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[36]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[36]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[37]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[37]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[37]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[37]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[38]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[38]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[38]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[38]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[4]_OUT}]  0.366 [get_ports {mem_dq[39]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[4]_OUT}]  -0.325 [get_ports {mem_dq[39]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[4]_OUT}]  0.366 [get_ports {mem_dq[39]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[4]_OUT}]  -0.325 [get_ports {mem_dq[39]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[40]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[40]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[40]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[40]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[41]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[41]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[41]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[41]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[42]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[42]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[42]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[42]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[43]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[43]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[43]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[43]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[44]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[44]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[44]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[44]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[45]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[45]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[45]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[45]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[46]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[46]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[46]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[46]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[5]_OUT}]  0.366 [get_ports {mem_dq[47]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[5]_OUT}]  -0.325 [get_ports {mem_dq[47]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[5]_OUT}]  0.366 [get_ports {mem_dq[47]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[5]_OUT}]  -0.325 [get_ports {mem_dq[47]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[48]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[48]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[48]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[48]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[49]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[49]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[49]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[49]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[50]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[50]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[50]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[50]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[51]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[51]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[51]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[51]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[52]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[52]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[52]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[52]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[53]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[53]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[53]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[53]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[54]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[54]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[54]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[54]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[6]_OUT}]  0.366 [get_ports {mem_dq[55]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[6]_OUT}]  -0.325 [get_ports {mem_dq[55]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[6]_OUT}]  0.366 [get_ports {mem_dq[55]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[6]_OUT}]  -0.325 [get_ports {mem_dq[55]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[56]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[56]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[56]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[56]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[57]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[57]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[57]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[57]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[58]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[58]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[58]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[58]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[59]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[59]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[59]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[59]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[60]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[60]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[60]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[60]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[61]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[61]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[61]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[61]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[62]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[62]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[62]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[62]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs[7]_OUT}]  0.366 [get_ports {mem_dq[63]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs[7]_OUT}]  -0.325 [get_ports {mem_dq[63]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_dqs_n[7]_OUT}]  0.366 [get_ports {mem_dq[63]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_dqs_n[7]_OUT}]  -0.325 [get_ports {mem_dq[63]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_odt[0]}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_odt[0]}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_ras_n}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_ras_n}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_reset_n}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_reset_n}]
set_output_delay -add_delay -max -clock [get_clocks {mem_ck[0]}]  0.332 [get_ports {mem_we_n}]
set_output_delay -add_delay -min -clock [get_clocks {mem_ck[0]}]  -0.348 [get_ports {mem_we_n}]


#**************************************************************
# Set Clock Groups
#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 


#**************************************************************
# Set False Path
#**************************************************************

set_false_path  -from  [get_clocks {mem_dqs[0]_OUT}]  -to  [get_clocks {mem_dqs[0]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[0]_IN}]  -to  [get_clocks {mem_dqs[0]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[1]_OUT}]  -to  [get_clocks {mem_dqs[1]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[1]_IN}]  -to  [get_clocks {mem_dqs[1]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[2]_OUT}]  -to  [get_clocks {mem_dqs[2]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[2]_IN}]  -to  [get_clocks {mem_dqs[2]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[3]_OUT}]  -to  [get_clocks {mem_dqs[3]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[3]_IN}]  -to  [get_clocks {mem_dqs[3]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[4]_OUT}]  -to  [get_clocks {mem_dqs[4]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[4]_IN}]  -to  [get_clocks {mem_dqs[4]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[5]_OUT}]  -to  [get_clocks {mem_dqs[5]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[5]_IN}]  -to  [get_clocks {mem_dqs[5]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[6]_OUT}]  -to  [get_clocks {mem_dqs[6]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[6]_IN}]  -to  [get_clocks {mem_dqs[6]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[7]_OUT}]  -to  [get_clocks {mem_dqs[7]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[7]_IN}]  -to  [get_clocks {mem_dqs[7]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[0]_OUT}]  -to  [get_clocks {mem_dqs[0]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[0]_IN}]  -to  [get_clocks {mem_dqs_n[0]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[1]_OUT}]  -to  [get_clocks {mem_dqs[1]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[1]_IN}]  -to  [get_clocks {mem_dqs_n[1]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[2]_OUT}]  -to  [get_clocks {mem_dqs[2]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[2]_IN}]  -to  [get_clocks {mem_dqs_n[2]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[3]_OUT}]  -to  [get_clocks {mem_dqs[3]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[3]_IN}]  -to  [get_clocks {mem_dqs_n[3]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[4]_OUT}]  -to  [get_clocks {mem_dqs[4]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[4]_IN}]  -to  [get_clocks {mem_dqs_n[4]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[5]_OUT}]  -to  [get_clocks {mem_dqs[5]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[5]_IN}]  -to  [get_clocks {mem_dqs_n[5]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[6]_OUT}]  -to  [get_clocks {mem_dqs[6]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[6]_IN}]  -to  [get_clocks {mem_dqs_n[6]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[7]_OUT}]  -to  [get_clocks {mem_dqs[7]_IN}]
set_false_path  -from  [get_clocks {mem_dqs[7]_IN}]  -to  [get_clocks {mem_dqs_n[7]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs[0]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  -to  [get_clocks {mem_dqs[0]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[0]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]  -to  [get_clocks {mem_dqs_n[0]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_0}]
set_false_path  -from  [get_clocks {mem_dqs[1]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  -to  [get_clocks {mem_dqs[1]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[1]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]  -to  [get_clocks {mem_dqs_n[1]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_1}]
set_false_path  -from  [get_clocks {mem_dqs[2]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  -to  [get_clocks {mem_dqs[2]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[2]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]  -to  [get_clocks {mem_dqs_n[2]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_2}]
set_false_path  -from  [get_clocks {mem_dqs[3]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  -to  [get_clocks {mem_dqs[3]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[3]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]  -to  [get_clocks {mem_dqs_n[3]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_3}]
set_false_path  -from  [get_clocks {mem_dqs[4]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  -to  [get_clocks {mem_dqs[4]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[4]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]  -to  [get_clocks {mem_dqs_n[4]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_4}]
set_false_path  -from  [get_clocks {mem_dqs[5]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  -to  [get_clocks {mem_dqs[5]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[5]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]  -to  [get_clocks {mem_dqs_n[5]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_5}]
set_false_path  -from  [get_clocks {mem_dqs[6]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  -to  [get_clocks {mem_dqs[6]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[6]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]  -to  [get_clocks {mem_dqs_n[6]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_6}]
set_false_path  -from  [get_clocks {mem_dqs[7]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]  -to  [get_clocks {mem_dqs[7]_OUT}]
set_false_path  -from  [get_clocks {mem_dqs_n[7]_OUT}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]  -to  [get_clocks {mem_dqs_n[7]_OUT}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}]  -to  [get_clocks {u0|uniphy_ddr3|p0|div_clock_7}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk}]  -to  [get_clocks {*_IN}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]  -to  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]
set_false_path  -from  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}]  -to  [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] 
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_write}] -to [get_registers {*|alt_jtag_atlantic:*|read_write1*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}]
set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|td_shift[0]*}]
set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|write_stalled*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers *]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}]
set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] 
set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_ue9:dffpipe19|dffe20a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_re9:dffpipe16|dffe17a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_te9:dffpipe18|dffe19a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_se9:dffpipe15|dffe16a*}]
set_false_path -to [get_pins -nocase -compatibility_mode {*|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn}]
set_false_path -from [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_break:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_break|break_readreg*}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug|*resetlatch}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck|*sr[33]}]
set_false_path -from [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug|monitor_ready}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck|*sr[0]}]
set_false_path -from [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug|monitor_error}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck|*sr[34]}]
set_false_path -from [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_ocimem:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_ocimem|*MonDReg*}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck|*sr*}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk|*jdo*}]
set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk|ir*}]
set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst:*|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci|TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug:the_TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_nios2_oci_debug|monitor_go}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|enable_ctrl~DQS_ENABLE_OUT_DFF}] -to [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|dqs_enable_block~DFFIN}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|enable_ctrl~DFFEXTENDDQSENABLE}] -to [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|dqs_enable_block~DFFIN}]
set_false_path -to [get_ports {mem_dqs[0]}]
set_false_path -to [get_ports {mem_dqs[1]}]
set_false_path -to [get_ports {mem_dqs[2]}]
set_false_path -to [get_ports {mem_dqs[3]}]
set_false_path -to [get_ports {mem_dqs[4]}]
set_false_path -to [get_ports {mem_dqs[5]}]
set_false_path -to [get_ports {mem_dqs[6]}]
set_false_path -to [get_ports {mem_dqs[7]}]
set_false_path -to [get_ports {mem_dqs_n[0]}]
set_false_path -to [get_ports {mem_dqs_n[1]}]
set_false_path -to [get_ports {mem_dqs_n[2]}]
set_false_path -to [get_ports {mem_dqs_n[3]}]
set_false_path -to [get_ports {mem_dqs_n[4]}]
set_false_path -to [get_ports {mem_dqs_n[5]}]
set_false_path -to [get_ports {mem_dqs_n[6]}]
set_false_path -to [get_ports {mem_dqs_n[7]}]
set_false_path -to [get_ports {mem_ck[0]}]
set_false_path -to [get_ports {mem_ck_n[0]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[0]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[0]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[0]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[0]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[0]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[1]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[1]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[1]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[1]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[1]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[2]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[2]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[2]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[2]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[2]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[3]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[3]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[3]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[3]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[3]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[4]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[4]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[4]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[4]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[4]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[5]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[5]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[5]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[5]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[5]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[6]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[6]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[6]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[6]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[6]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[7]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[7]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[7]}]
set_false_path -from [get_clocks {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[7]}]
set_false_path -from [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*}] -to [get_keepers {u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[7]}]
set_false_path -from [get_registers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_buffering[*].read_subgroup[*].uread_fifo*|data_stored[*][*]}] -to [get_registers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_buffering[*].uread_fifo*|rd_data[*]}]
set_false_path -to [get_keepers {*alt_vipitc110_IS2Vid:*|rst_vid_clk_reg}]
set_false_path -to [get_keepers {*alt_vipitc110_IS2Vid:*|alt_vipitc110_common_sync:enable_sync|data_out_sync0[*]}]
set_false_path -from [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_nios2_oci_break:the_TR4_QSYS_cpu_nios2_oci_break|break_readreg*}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_tck:the_TR4_QSYS_cpu_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_nios2_oci_debug:the_TR4_QSYS_cpu_nios2_oci_debug|*resetlatch}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_tck:the_TR4_QSYS_cpu_jtag_debug_module_tck|*sr[33]}]
set_false_path -from [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_nios2_oci_debug:the_TR4_QSYS_cpu_nios2_oci_debug|monitor_ready}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_tck:the_TR4_QSYS_cpu_jtag_debug_module_tck|*sr[0]}]
set_false_path -from [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_nios2_oci_debug:the_TR4_QSYS_cpu_nios2_oci_debug|monitor_error}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_tck:the_TR4_QSYS_cpu_jtag_debug_module_tck|*sr[34]}]
set_false_path -from [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_nios2_ocimem:the_TR4_QSYS_cpu_nios2_ocimem|*MonDReg*}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_tck:the_TR4_QSYS_cpu_jtag_debug_module_tck|*sr*}]
set_false_path -from [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_tck:the_TR4_QSYS_cpu_jtag_debug_module_tck|*sr*}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_sysclk:the_TR4_QSYS_cpu_jtag_debug_module_sysclk|*jdo*}]
set_false_path -from [get_keepers {sld_hub:*|irf_reg*}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_jtag_debug_module_wrapper:the_TR4_QSYS_cpu_jtag_debug_module_wrapper|TR4_QSYS_cpu_jtag_debug_module_sysclk:the_TR4_QSYS_cpu_jtag_debug_module_sysclk|ir*}]
set_false_path -from [get_keepers {sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1]}] -to [get_keepers {*TR4_QSYS_cpu:*|TR4_QSYS_cpu_nios2_oci:the_TR4_QSYS_cpu_nios2_oci|TR4_QSYS_cpu_nios2_oci_debug:the_TR4_QSYS_cpu_nios2_oci_debug|monitor_go}]


#**************************************************************
# Set Multicycle Path
#**************************************************************

set_multicycle_path -setup -end -from [get_registers {*:u0|*:uniphy_ddr3|*:p0*usequencer|*sequencer_phy_mgr_inst|phy_mux_sel}] -to [remove_from_collection [get_keepers *] [get_registers {*:u0|*:uniphy_ddr3|*:p0*usequencer|*sequencer_phy_mgr_inst|phy_mux_sel}]] 3
set_multicycle_path -hold -end -from [get_registers {*:u0|*:uniphy_ddr3|*:p0*usequencer|*sequencer_phy_mgr_inst|phy_mux_sel}] -to [remove_from_collection [get_keepers *] [get_registers {*:u0|*:uniphy_ddr3|*:p0*usequencer|*sequencer_phy_mgr_inst|phy_mux_sel}]] 2
set_multicycle_path -setup -end -through [get_nets {u0|uniphy_ddr3|p0*usequencer|*rw_mgr_core_inst|group_select[*]}] 3
set_multicycle_path -hold -end -through [get_nets {u0|uniphy_ddr3|p0*usequencer|*rw_mgr_core_inst|group_select[*]}] 2


#**************************************************************
# Set Maximum Delay
#**************************************************************

set_max_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[2]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[3]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[4]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[5]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[6]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[7]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[8]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[9]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[10]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[11]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[12]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[13]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[14]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[15]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[16]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[17]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[18]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[19]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[20]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[21]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[22]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[23]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[24]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[25]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[26]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[27]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[28]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[29]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[30]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[31]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[32]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[33]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[34]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[35]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[36]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[37]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[38]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[39]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[40]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[41]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[42]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[43]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[44]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[45]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[46]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[47]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[48]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[49]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[50]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[51]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[52]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[53]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[54]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[55]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[56]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[57]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[58]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[59]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[60]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[61]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[62]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_ports {mem_dq[63]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] 0.000
set_max_delay -from [get_registers {*:u0|*:uniphy_ddr3|*:p0*read_data_out*}] -to [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_buffering[*].read_subgroup[*].uread_fifo*|data_stored[*][*]}] -0.050


#**************************************************************
# Set Minimum Delay
#**************************************************************

set_min_delay -from [get_ports {mem_dq[0]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[1]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[2]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[3]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[4]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[5]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[6]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[7]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[8]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[9]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[10]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[11]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[12]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[13]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[14]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[15]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[16]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[17]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[18]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[19]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[20]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[21]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[22]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[23]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[24]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[25]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[26]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[27]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[28]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[29]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[30]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[31]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[32]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[33]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[34]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[35]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[36]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[37]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[38]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[39]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[40]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[41]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[42]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[43]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[44]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[45]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[46]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[47]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[48]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[49]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[50]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[51]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[52]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[53]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[54]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[55]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[56]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[57]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[58]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[59]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[60]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[61]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[62]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_ports {mem_dq[63]}] -to [get_keepers {{*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}}] -1.250
set_min_delay -from [get_registers {*:u0|*:uniphy_ddr3|*:p0*read_data_out*}] -to [get_keepers {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_buffering[*].read_subgroup[*].uread_fifo*|data_stored[*][*]}] -2.300


#**************************************************************
# Set Input Transition
#**************************************************************

