<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="System" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element $${FILENAME}
   {
   }
   element TERASIC_CAMERA_0
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
   }
   element alt_vip_itc_0
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
   }
   element alt_vip_vfb_0
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{}";
         type = "String";
      }
   }
   element jtag_uart.avalon_jtag_slave
   {
      datum baseAddress
      {
         value = "266336";
         type = "long";
      }
   }
   element uniphy_ddr3.avl
   {
      datum baseAddress
      {
         value = "1073741824";
         type = "long";
      }
   }
   element camera_reset_n
   {
      datum _sortIndex
      {
         value = "11";
         type = "int";
      }
   }
   element camera_scl
   {
      datum _sortIndex
      {
         value = "10";
         type = "int";
      }
   }
   element camera_sda
   {
      datum _sortIndex
      {
         value = "9";
         type = "int";
      }
   }
   element clk_50
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element cpu_clk.clk_reset
   {
      datum _tags
      {
         value = "";
         type = "String";
      }
   }
   element cpu
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
   }
   element cpu_clk
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
   }
   element cpu.jtag_debug_module
   {
      datum baseAddress
      {
         value = "264192";
         type = "long";
      }
   }
   element jtag_uart
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
   }
   element mem
   {
      datum _sortIndex
      {
         value = "8";
         type = "int";
      }
   }
   element sw.s1
   {
      datum baseAddress
      {
         value = "266320";
         type = "long";
      }
   }
   element camera_reset_n.s1
   {
      datum baseAddress
      {
         value = "266304";
         type = "long";
      }
   }
   element camera_scl.s1
   {
      datum baseAddress
      {
         value = "266288";
         type = "long";
      }
   }
   element timer_0.s1
   {
      datum baseAddress
      {
         value = "266240";
         type = "long";
      }
   }
   element mem.s1
   {
      datum baseAddress
      {
         value = "131072";
         type = "long";
      }
   }
   element camera_sda.s1
   {
      datum baseAddress
      {
         value = "266272";
         type = "long";
      }
   }
   element sw
   {
      datum _sortIndex
      {
         value = "12";
         type = "int";
      }
   }
   element timer_0
   {
      datum _sortIndex
      {
         value = "13";
         type = "int";
      }
   }
   element uniphy_ddr3
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="deviceFamily" value="STRATIXIV" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="maxAdditionalLatency" value="1" />
 <parameter name="projectName" value="TR4_AHA.qpf" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="1" />
 <parameter name="timeStamp" value="1323940006000" />
 <interface name="external_clk50" internal="clk_50.clk_in" type="clock" dir="end" />
 <interface
   name="external_reset"
   internal="clk_50.clk_in_reset"
   type="reset"
   dir="end" />
 <interface name="memory" internal="uniphy_ddr3.memory" type="conduit" dir="end" />
 <interface name="oct" internal="uniphy_ddr3.oct" type="conduit" dir="end" />
 <interface name="uniphy_ddr3_oct_sharing" internal="uniphy_ddr3.oct_sharing" />
 <interface name="uniphy_ddr3_pll_sharing" internal="uniphy_ddr3.pll_sharing" />
 <interface name="uniphy_ddr3_dll_sharing" internal="uniphy_ddr3.dll_sharing" />
 <interface
   name="uniphy_ddr3_local_powerdown"
   internal="uniphy_ddr3.local_powerdown"
   type="conduit"
   dir="end" />
 <interface
   name="uniphy_ddr3_status"
   internal="uniphy_ddr3.status"
   type="conduit"
   dir="end" />
 <interface
   name="terasic_camera_0_conduit_end"
   internal="TERASIC_CAMERA_0.conduit_end"
   type="conduit"
   dir="end" />
 <interface
   name="alt_vip_itc_0_clocked_video"
   internal="alt_vip_itc_0.clocked_video"
   type="conduit"
   dir="end" />
 <interface name="clk" internal="cpu_clk.clk_in" type="clock" dir="end" />
 <interface name="reset" internal="cpu_clk.clk_in_reset" type="reset" dir="end" />
 <interface
   name="sda"
   internal="camera_sda.external_connection"
   type="conduit"
   dir="end" />
 <interface
   name="scl"
   internal="camera_scl.external_connection"
   type="conduit"
   dir="end" />
 <interface
   name="c_reset"
   internal="camera_reset_n.external_connection"
   type="conduit"
   dir="end" />
 <interface name="sw" internal="sw.external_connection" type="conduit" dir="end" />
 <module kind="clock_source" version="11.0" enabled="1" name="clk_50">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   kind="altera_mem_if_ddr3_emif"
   version="11.0"
   enabled="1"
   name="uniphy_ddr3">
  <parameter name="MEM_VENDOR" value="Hynix" />
  <parameter name="MEM_FORMAT" value="UNBUFFERED" />
  <parameter name="AC_PARITY" value="false" />
  <parameter name="RDIMM_CONFIG" value="0" />
  <parameter name="DISCRETE_FLY_BY" value="true" />
  <parameter name="DEVICE_DEPTH" value="1" />
  <parameter name="MEM_MIRROR_ADDRESSING" value="0" />
  <parameter name="MEM_CLK_FREQ_MAX" value="533.333" />
  <parameter name="MEM_ROW_ADDR_WIDTH" value="14" />
  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
  <parameter name="MEM_DQ_WIDTH" value="64" />
  <parameter name="MEM_DQ_PER_DQS" value="8" />
  <parameter name="MEM_BANKADDR_WIDTH" value="3" />
  <parameter name="MEM_IF_DM_PINS_EN" value="true" />
  <parameter name="MEM_IF_DQSN_EN" value="true" />
  <parameter name="MEM_NUMBER_OF_DIMMS" value="1" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" />
  <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" />
  <parameter name="MEM_CK_WIDTH" value="1" />
  <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" />
  <parameter name="NEXTGEN" value="true" />
  <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" />
  <parameter name="MEM_BL" value="OTF" />
  <parameter name="MEM_BT" value="Sequential" />
  <parameter name="MEM_ASR" value="Automatic" />
  <parameter name="MEM_SRT" value="Normal" />
  <parameter name="MEM_PD" value="DLL off" />
  <parameter name="MEM_DRV_STR" value="RZQ/7" />
  <parameter name="MEM_DLL_EN" value="true" />
  <parameter name="MEM_RTT_NOM" value="RZQ/6" />
  <parameter name="MEM_RTT_WR" value="RZQ/4" />
  <parameter name="MEM_WTCL" value="6" />
  <parameter name="MEM_ATCL" value="CL-1" />
  <parameter name="MEM_TCL" value="7" />
  <parameter name="MEM_AUTO_LEVELING_MODE" value="true" />
  <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" />
  <parameter name="MEM_INIT_EN" value="false" />
  <parameter name="MEM_INIT_FILE" value="" />
  <parameter name="DAT_DATA_WIDTH" value="32" />
  <parameter name="TIMING_TIS" value="125" />
  <parameter name="TIMING_TIH" value="200" />
  <parameter name="TIMING_TDS" value="25" />
  <parameter name="TIMING_TDH" value="100" />
  <parameter name="TIMING_TDQSQ" value="150" />
  <parameter name="TIMING_TQH" value="0.38" />
  <parameter name="TIMING_TDQSCK" value="400" />
  <parameter name="TIMING_TDQSS" value="0.25" />
  <parameter name="TIMING_TQSH" value="0.38" />
  <parameter name="TIMING_TDSH" value="0.2" />
  <parameter name="TIMING_TDSS" value="0.2" />
  <parameter name="MEM_TINIT_US" value="500" />
  <parameter name="MEM_TMRD_CK" value="4" />
  <parameter name="MEM_TRAS_NS" value="37.5" />
  <parameter name="MEM_TRCD_NS" value="13.125" />
  <parameter name="MEM_TRP_NS" value="13.125" />
  <parameter name="MEM_TREFI_US" value="7.8" />
  <parameter name="MEM_TRFC_NS" value="110.0" />
  <parameter name="MEM_TWR_NS" value="15.0" />
  <parameter name="MEM_TWTR" value="4" />
  <parameter name="MEM_TFAW_NS" value="37.5" />
  <parameter name="MEM_TRRD_NS" value="13.2" />
  <parameter name="MEM_TRTP_NS" value="13.2" />
  <parameter name="CSR_ADDR_WIDTH" value="16" />
  <parameter name="CSR_DATA_WIDTH" value="32" />
  <parameter name="POWER_OF_TWO_BUS" value="false" />
  <parameter name="SOPC_COMPAT_RESET" value="false" />
  <parameter name="AVL_MAX_SIZE" value="8" />
  <parameter name="BYTE_ENABLE" value="false" />
  <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" />
  <parameter name="CTL_SELF_REFRESH_EN" value="false" />
  <parameter name="AUTO_POWERDN_EN" value="false" />
  <parameter name="MEM_AUTO_PD_CYCLES" value="0" />
  <parameter name="CTL_USR_REFRESH_EN" value="false" />
  <parameter name="CTL_AUTOPCH_EN" value="false" />
  <parameter name="ADDR_ORDER" value="0" />
  <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" />
  <parameter name="CONTROLLER_LATENCY" value="5" />
  <parameter name="CFG_REORDER_DATA" value="true" />
  <parameter name="CFG_STARVE_LIMIT" value="10" />
  <parameter name="CTL_CSR_ENABLED" value="false" />
  <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="CTL_ECC_ENABLED" value="false" />
  <parameter name="CTL_HRB_ENABLED" value="false" />
  <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" />
  <parameter name="MULTICAST_EN" value="false" />
  <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" />
  <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" />
  <parameter name="DEBUG_MODE" value="false" />
  <parameter name="ENABLE_BURST_MERGE" value="false" />
  <parameter name="LOCAL_ID_WIDTH" value="8" />
  <parameter name="RDBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="WRBUFFER_ADDR_WIDTH" value="6" />
  <parameter name="USE_MM_ADAPTOR" value="true" />
  <parameter name="USE_AXI_ADAPTOR" value="false" />
  <parameter name="HCX_COMPAT_MODE" value="false" />
  <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" />
  <parameter name="CTL_CSR_READ_ONLY" value="1" />
  <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" />
  <parameter name="REF_CLK_FREQ" value="50.0" />
  <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" />
  <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" />
  <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" />
  <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" />
  <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" />
  <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" />
  <parameter name="PLL_CLK_PARAM_VALID" value="false" />
  <parameter name="ENABLE_EXTRA_REPORTING" value="false" />
  <parameter name="NUM_EXTRA_REPORT_PATH" value="10" />
  <parameter name="ENABLE_ISS_PROBES" value="false" />
  <parameter name="READ_VALID_FIFO_SIZE" value="16" />
  <parameter name="CALIB_REG_WIDTH" value="8" />
  <parameter name="MAX_LATENCY_COUNT_WIDTH" value="5" />
  <parameter name="DLL_DELAY_CHAIN_LENGTH" value="10" />
  <parameter name="USE_SEQUENCER_BFM" value="false" />
  <parameter name="DEFAULT_FAST_SIM_MODEL" value="true" />
  <parameter name="PLL_SHARING_MODE" value="None" />
  <parameter name="DLL_SHARING_MODE" value="None" />
  <parameter name="OCT_SHARING_MODE" value="None" />
  <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
  <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" />
  <parameter name="EXTRA_SETTINGS" value="" />
  <parameter name="MEM_DEVICE" value="MISSING_MODEL" />
  <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" />
  <parameter name="QSYS_SEQUENCER_DEBUG" value="true" />
  <parameter name="SEQUENCER_TYPE" value="NIOS" />
  <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" />
  <parameter name="SEQ_MODE" value="0" />
  <parameter name="ADVANCED_CK_PHASES" value="false" />
  <parameter name="COMMAND_PHASE" value="0.0" />
  <parameter name="MEM_CK_PHASE" value="0.0" />
  <parameter name="MEM_VOLTAGE" value="1.5V DDR3" />
  <parameter name="PLL_LOCATION" value="Top_Bottom" />
  <parameter name="SKIP_MEM_INIT" value="true" />
  <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" />
  <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" />
  <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" />
  <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" />
  <parameter name="CALIBRATION_MODE" value="Full" />
  <parameter name="NIOS_ROM_DATA_WIDTH" value="32" />
  <parameter name="NIOS_ROM_ADDRESS_WIDTH" value="12" />
  <parameter name="DQS_TRK_ENABLED" value="false" />
  <parameter name="READ_FIFO_SIZE" value="8" />
  <parameter name="PHY_CSR_ENABLED" value="false" />
  <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" />
  <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" />
  <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" />
  <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" />
  <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" />
  <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" />
  <parameter name="TIMING_BOARD_TIS" value="0.0" />
  <parameter name="TIMING_BOARD_TIH" value="0.0" />
  <parameter name="TIMING_BOARD_TDS" value="0.0" />
  <parameter name="TIMING_BOARD_TDH" value="0.0" />
  <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" />
  <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" />
  <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" />
  <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" />
  <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" />
  <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="0.02" />
  <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.07" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" />
  <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.0090" />
  <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.05" />
  <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0040" />
  <parameter name="TIMING_BOARD_AC_SKEW" value="0.04" />
  <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" />
  <parameter name="RATE" value="Half" />
  <parameter name="MEM_CLK_FREQ" value="400.0" />
  <parameter name="SYS_INFO_DEVICE_FAMILY" value="Stratix IV" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" />
  <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" />
  <parameter name="DEVICE_FAMILY_PARAM" value="" />
  <parameter name="DISABLE_CHILD_MESSAGING" value="false" />
  <parameter name="SPEED_GRADE" value="2" />
  <parameter name="ADD_EFFICIENCY_MONITOR" value="false" />
  <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" />
  <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
 </module>
 <module
   kind="TERASIC_CAMERA"
   version="1.0"
   enabled="1"
   name="TERASIC_CAMERA_0">
  <parameter name="VIDEO_W" value="1280" />
  <parameter name="VIDEO_H" value="720" />
  <parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="200000000" />
 </module>
 <module kind="alt_vip_vfb" version="11.0" enabled="1" name="alt_vip_vfb_0">
  <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
  <parameter name="PARAMETERISATION"><![CDATA[<frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>1280</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>720</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>0</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>1</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>1</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>false</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>8</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>8</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>2</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>false</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>true</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>true</VFB_DROP_INVALID_FIELDS></frameBufferParams>]]></parameter>
 </module>
 <module kind="alt_vip_itc" version="11.0" enabled="1" name="alt_vip_itc_0">
  <parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
  <parameter name="COLOUR_PLANES_ARE_IN_PARALLEL" value="1" />
  <parameter name="BPS" value="8" />
  <parameter name="INTERLACED" value="0" />
  <parameter name="H_ACTIVE_PIXELS" value="1280" />
  <parameter name="V_ACTIVE_LINES" value="720" />
  <parameter name="ACCEPT_COLOURS_IN_SEQ" value="0" />
  <parameter name="FIFO_DEPTH" value="1280" />
  <parameter name="CLOCKS_ARE_SAME" value="0" />
  <parameter name="USE_CONTROL" value="0" />
  <parameter name="NO_OF_MODES" value="1" />
  <parameter name="THRESHOLD" value="1279" />
  <parameter name="STD_WIDTH" value="1" />
  <parameter name="GENERATE_SYNC" value="0" />
  <parameter name="USE_EMBEDDED_SYNCS" value="0" />
  <parameter name="AP_LINE" value="0" />
  <parameter name="V_BLANK" value="0" />
  <parameter name="H_BLANK" value="0" />
  <parameter name="H_SYNC_LENGTH" value="32" />
  <parameter name="H_FRONT_PORCH" value="48" />
  <parameter name="H_BACK_PORCH" value="80" />
  <parameter name="V_SYNC_LENGTH" value="45" />
  <parameter name="V_FRONT_PORCH" value="2" />
  <parameter name="V_BACK_PORCH" value="14" />
  <parameter name="F_RISING_EDGE" value="0" />
  <parameter name="F_FALLING_EDGE" value="0" />
  <parameter name="FIELD0_V_RISING_EDGE" value="0" />
  <parameter name="FIELD0_V_BLANK" value="0" />
  <parameter name="FIELD0_V_SYNC_LENGTH" value="0" />
  <parameter name="FIELD0_V_FRONT_PORCH" value="0" />
  <parameter name="FIELD0_V_BACK_PORCH" value="0" />
  <parameter name="ANC_LINE" value="0" />
  <parameter name="FIELD0_ANC_LINE" value="0" />
  <parameter name="AUTO_IS_CLK_RST_CLOCK_RATE" value="200000000" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
 </module>
 <module kind="altera_nios2_qsys" version="11.0" enabled="1" name="cpu">
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="setting_preciseDivisionErrorException" value="false" />
  <parameter name="setting_performanceCounter" value="false" />
  <parameter name="setting_illegalMemAccessDetection" value="false" />
  <parameter name="setting_illegalInstructionsTrap" value="false" />
  <parameter name="setting_fullWaveformSignals" value="false" />
  <parameter name="setting_extraExceptionInfo" value="false" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_debugSimGen" value="false" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="setting_bhtIndexPcOnly" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_allowFullAddressRange" value="false" />
  <parameter name="setting_activateTrace" value="true" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="setting_activateModelChecker" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="muldiv_divider" value="false" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="manuallyAssignCpuID" value="false" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_embeddedPLL" value="true" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="dcache_omitDataMaster" value="false" />
  <parameter name="cpuReset" value="false" />
  <parameter name="is_hardcopy_compatible" value="false" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="resetOffset" value="0" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="cpuID" value="0" />
  <parameter name="breakOffset" value="32" />
  <parameter name="userDefinedSettings" value="" />
  <parameter name="resetSlave" value="mem.s1" />
  <parameter name="mmu_TLBMissExcSlave" value="" />
  <parameter name="exceptionSlave" value="mem.s1" />
  <parameter name="breakSlave">cpu.jtag_debug_module</parameter>
  <parameter name="setting_perfCounterWidth" value="32" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="setting_branchPredictionType" value="Automatic" />
  <parameter name="setting_bhtPtrSz" value="8" />
  <parameter name="muldiv_multiplierType" value="DSPBlock" />
  <parameter name="mpu_minInstRegionSize" value="12" />
  <parameter name="mpu_minDataRegionSize" value="12" />
  <parameter name="mmu_uitlbNumEntries" value="4" />
  <parameter name="mmu_udtlbNumEntries" value="6" />
  <parameter name="mmu_tlbPtrSz" value="7" />
  <parameter name="mmu_tlbNumWays" value="16" />
  <parameter name="mmu_processIDNumBits" value="8" />
  <parameter name="impl" value="Fast" />
  <parameter name="icache_size" value="4096" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="icache_numTCIM" value="0" />
  <parameter name="icache_burstType" value="None" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="debug_level" value="Level1" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dcache_size" value="2048" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dcache_numTCDM" value="0" />
  <parameter name="dcache_lineSize" value="32" />
  <parameter name="instAddrWidth" value="19" />
  <parameter name="dataAddrWidth" value="19" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x20000' end='0x39000' /><slave name='cpu.jtag_debug_module' start='0x40800' end='0x41000' /></address-map>]]></parameter>
  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x20000' end='0x39000' /><slave name='cpu.jtag_debug_module' start='0x40800' end='0x41000' /><slave name='timer_0.s1' start='0x41000' end='0x41020' /><slave name='camera_sda.s1' start='0x41020' end='0x41030' /><slave name='camera_scl.s1' start='0x41030' end='0x41040' /><slave name='camera_reset_n.s1' start='0x41040' end='0x41050' /><slave name='sw.s1' start='0x41050' end='0x41060' /><slave name='jtag_uart.avalon_jtag_slave' start='0x41060' end='0x41068' /></address-map>]]></parameter>
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="deviceFamilyName" value="Stratix IV" />
  <parameter name="internalIrqMaskSystemInfo" value="3" />
  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
  <parameter name="deviceFeaturesSystemInfo">M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 1 MRAM_MEMORY 0 MLAB_MEMORY 1 ESB 0 EPCS 1 DSP 1 EMUL 0 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 DSP_SHIFTER_BLOCK 1</parameter>
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
 </module>
 <module
   kind="altera_avalon_onchip_memory2"
   version="11.0"
   enabled="1"
   name="mem">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="autoInitializationFileName" value="mem" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="dataWidth" value="32" />
  <parameter name="deviceFamily" value="Stratix IV" />
  <parameter name="dualPort" value="false" />
  <parameter name="initMemContent" value="true" />
  <parameter name="initializationFileName" value="mem" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="102400" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module kind="altera_avalon_pio" version="11.0" enabled="1" name="camera_sda">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Bidir" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="altera_avalon_pio" version="11.0" enabled="1" name="camera_scl">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Output" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module kind="clock_source" version="11.0" enabled="1" name="cpu_clk">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   kind="altera_avalon_pio"
   version="11.0"
   enabled="1"
   name="camera_reset_n">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Output" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="1" />
 </module>
 <module
   kind="altera_avalon_jtag_uart"
   version="11.0"
   enabled="1"
   name="jtag_uart">
  <parameter name="allowMultipleConnections" value="false" />
  <parameter name="hubInstanceID" value="0" />
  <parameter name="readBufferDepth" value="64" />
  <parameter name="readIRQThreshold" value="8" />
  <parameter name="simInputCharacterStream" value="" />
  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
  <parameter name="useRegistersForReadBuffer" value="false" />
  <parameter name="useRegistersForWriteBuffer" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
  <parameter name="writeBufferDepth" value="64" />
  <parameter name="writeIRQThreshold" value="8" />
 </module>
 <module kind="altera_avalon_pio" version="11.0" enabled="1" name="sw">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="4" />
 </module>
 <module kind="altera_avalon_timer" version="11.0" enabled="1" name="timer_0">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="1" />
  <parameter name="periodUnits" value="MSEC" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="true" />
  <parameter name="systemFrequency" value="50000000" />
  <parameter name="timeoutPulseOutput" value="false" />
  <parameter name="timerPreset" value="CUSTOM" />
 </module>
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="uniphy_ddr3.global_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="uniphy_ddr3.soft_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="TERASIC_CAMERA_0.clock_reset_reset" />
 <connection
   kind="avalon"
   version="11.0"
   start="alt_vip_vfb_0.write_master"
   end="uniphy_ddr3.avl">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x40000000" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="alt_vip_vfb_0.read_master"
   end="uniphy_ddr3.avl">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x40000000" />
 </connection>
 <connection
   kind="avalon_streaming"
   version="11.0"
   start="TERASIC_CAMERA_0.avalon_streaming_source"
   end="alt_vip_vfb_0.din" />
 <connection
   kind="avalon_streaming"
   version="11.0"
   start="alt_vip_vfb_0.dout"
   end="alt_vip_itc_0.din" />
 <connection
   kind="reset"
   version="11.0"
   start="uniphy_ddr3.afi_reset"
   end="alt_vip_itc_0.is_clk_rst_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="alt_vip_vfb_0.reset" />
 <connection
   kind="avalon"
   version="11.0"
   start="cpu.instruction_master"
   end="cpu.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00040800" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu.data_master"
   end="cpu.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00040800" />
 </connection>
 <connection kind="avalon" version="11.0" start="cpu.data_master" end="mem.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00020000" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu.instruction_master"
   end="mem.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00020000" />
 </connection>
 <connection kind="clock" version="11.0" start="cpu_clk.clk" end="cpu.clk" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_clk.clk_reset"
   end="cpu.reset_n" />
 <connection kind="clock" version="11.0" start="cpu_clk.clk" end="mem.clk1" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_clk.clk_reset"
   end="mem.reset1" />
 <connection kind="clock" version="11.0" start="cpu_clk.clk" end="camera_sda.clk" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_clk.clk_reset"
   end="camera_sda.reset" />
 <connection
   kind="avalon"
   version="11.0"
   start="cpu.data_master"
   end="camera_sda.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00041020" />
 </connection>
 <connection kind="clock" version="11.0" start="cpu_clk.clk" end="camera_scl.clk" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_clk.clk_reset"
   end="camera_scl.reset" />
 <connection
   kind="avalon"
   version="11.0"
   start="cpu.data_master"
   end="camera_scl.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00041030" />
 </connection>
 <connection
   kind="clock"
   version="11.0"
   start="cpu_clk.clk"
   end="camera_reset_n.clk" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_clk.clk_reset"
   end="camera_reset_n.reset" />
 <connection
   kind="avalon"
   version="11.0"
   start="cpu.data_master"
   end="camera_reset_n.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00041040" />
 </connection>
 <connection kind="clock" version="11.0" start="cpu_clk.clk" end="jtag_uart.clk" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_clk.clk_reset"
   end="jtag_uart.reset" />
 <connection
   kind="avalon"
   version="11.0"
   start="cpu.data_master"
   end="jtag_uart.avalon_jtag_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00041060" />
 </connection>
 <connection kind="clock" version="11.0" start="cpu_clk.clk" end="sw.clk" />
 <connection kind="reset" version="11.0" start="cpu_clk.clk_reset" end="sw.reset" />
 <connection kind="avalon" version="11.0" start="cpu.data_master" end="sw.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00041050" />
 </connection>
 <connection kind="clock" version="11.0" start="cpu_clk.clk" end="timer_0.clk" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_clk.clk_reset"
   end="timer_0.reset" />
 <connection kind="avalon" version="11.0" start="cpu.data_master" end="timer_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00041000" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu.d_irq" end="timer_0.irq">
  <parameter name="irqNumber" value="1" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu.d_irq" end="jtag_uart.irq">
  <parameter name="irqNumber" value="0" />
 </connection>
 <connection
   kind="clock"
   version="11.0"
   start="clk_50.clk"
   end="uniphy_ddr3.pll_ref_clk" />
 <connection
   kind="clock"
   version="11.0"
   start="uniphy_ddr3.afi_clk"
   end="TERASIC_CAMERA_0.clock_reset" />
 <connection
   kind="clock"
   version="11.0"
   start="uniphy_ddr3.afi_clk"
   end="alt_vip_vfb_0.clock" />
 <connection
   kind="clock"
   version="11.0"
   start="uniphy_ddr3.afi_clk"
   end="alt_vip_itc_0.is_clk_rst" />
</system>
