Core: TR4_QSYS_uniphy_ddr3_p0 - Instance: u0|uniphy_ddr3|p0
Path, Setup Margin, Hold Margin
"Address Command (Slow 900mV 85C Model)",0.338,0.312
"Bus Turnaround Time (Slow 900mV 85C Model)",3.536,--
"Core (Slow 900mV 85C Model)",0.275,0.078
"Core Recovery/Removal (Slow 900mV 85C Model)",0.849,0.374
"Read Capture (Slow 900mV 85C Model)",0.188,0.148
"Read Resync (Slow 900mV 85C Model)",1.187,2.232
"Write (Slow 900mV 85C Model)",0.082,0.082
"Write Leveling tDQSS (Slow 900mV 85C Model)",0.417,0.417
"Write Leveling tDSS/tDSH (Slow 900mV 85C Model)",0.441,0.441
"Address Command (Slow 900mV 0C Model)",0.346,0.339
"Bus Turnaround Time (Slow 900mV 0C Model)",3.56,--
"Core (Slow 900mV 0C Model)",0.287,0.141
"Core Recovery/Removal (Slow 900mV 0C Model)",0.986,0.362
"Read Capture (Slow 900mV 0C Model)",0.192,0.152
"Read Resync (Slow 900mV 0C Model)",1.282,2.26
"Write (Slow 900mV 0C Model)",0.12,0.12
"Write Leveling tDQSS (Slow 900mV 0C Model)",0.417,0.417
"Write Leveling tDSS/tDSH (Slow 900mV 0C Model)",0.441,0.441
"Address Command (Fast 900mV 0C Model)",0.398,0.399
"Bus Turnaround Time (Fast 900mV 0C Model)",3.599,--
"Core (Fast 900mV 0C Model)",0.29,0.07
"Core Recovery/Removal (Fast 900mV 0C Model)",1.949,0.207
"Read Capture (Fast 900mV 0C Model)",0.224,0.184
"Read Resync (Fast 900mV 0C Model)",1.949,2.72
"Write (Fast 900mV 0C Model)",0.118,0.118
"Write Leveling tDQSS (Fast 900mV 0C Model)",0.417,0.417
"Write Leveling tDSS/tDSH (Fast 900mV 0C Model)",0.441,0.441
