// TR4_QSYS.v


`timescale 1 ps / 1 ps
module TR4_QSYS (
		output wire        alt_vip_itc_0_clocked_video_vid_v,             //  alt_vip_itc_0_clocked_video.vid_v
		output wire        alt_vip_itc_0_clocked_video_underflow,         //                             .underflow
		output wire        alt_vip_itc_0_clocked_video_vid_h,             //                             .vid_h
		output wire        alt_vip_itc_0_clocked_video_vid_v_sync,        //                             .vid_v_sync
		output wire        alt_vip_itc_0_clocked_video_vid_datavalid,     //                             .vid_datavalid
		output wire        alt_vip_itc_0_clocked_video_vid_h_sync,        //                             .vid_h_sync
		output wire [23:0] alt_vip_itc_0_clocked_video_vid_data,          //                             .vid_data
		output wire        alt_vip_itc_0_clocked_video_vid_f,             //                             .vid_f
		input  wire        alt_vip_itc_0_clocked_video_vid_clk,           //                             .vid_clk
		input  wire        oct_rup,                                       //                          oct.rup
		input  wire        oct_rdn,                                       //                             .rdn
		input  wire        external_reset_reset_n,                        //               external_reset.reset_n
		input  wire        uniphy_ddr3_local_powerdown_local_powerdn_req, //  uniphy_ddr3_local_powerdown.local_powerdn_req
		output wire        uniphy_ddr3_local_powerdown_local_powerdn_ack, //                             .local_powerdn_ack
		input  wire        terasic_camera_0_conduit_end_PIXCLK,           // terasic_camera_0_conduit_end.PIXCLK
		input  wire        terasic_camera_0_conduit_end_FVAL,             //                             .FVAL
		input  wire        terasic_camera_0_conduit_end_LVAL,             //                             .LVAL
		input  wire [11:0] terasic_camera_0_conduit_end_D,                //                             .D
		output wire        uniphy_ddr3_status_local_init_done,            //           uniphy_ddr3_status.local_init_done
		output wire        uniphy_ddr3_status_local_cal_success,          //                             .local_cal_success
		output wire        uniphy_ddr3_status_local_cal_fail,             //                             .local_cal_fail
		input  wire        external_clk50_clk,                            //               external_clk50.clk
		output wire        memory_mem_cas_n,                              //                       memory.mem_cas_n
		output wire [2:0]  memory_mem_ba,                                 //                             .mem_ba
		inout  wire [63:0] memory_mem_dq,                                 //                             .mem_dq
		output wire        memory_mem_cs_n,                               //                             .mem_cs_n
		output wire        memory_mem_cke,                                //                             .mem_cke
		output wire        memory_mem_we_n,                               //                             .mem_we_n
		output wire [13:0] memory_mem_a,                                  //                             .mem_a
		output wire        memory_mem_ck_n,                               //                             .mem_ck_n
		output wire        memory_mem_odt,                                //                             .mem_odt
		inout  wire [7:0]  memory_mem_dqs,                                //                             .mem_dqs
		output wire        memory_mem_reset_n,                            //                             .mem_reset_n
		output wire [7:0]  memory_mem_dm,                                 //                             .mem_dm
		inout  wire [7:0]  memory_mem_dqs_n,                              //                             .mem_dqs_n
		output wire        memory_mem_ck,                                 //                             .mem_ck
		output wire        memory_mem_ras_n                               //                             .mem_ras_n
	);

	wire          terasic_camera_0_avalon_streaming_source_endofpacket;                                   // TERASIC_CAMERA_0:st_eop -> alt_vip_vfb_0:din_endofpacket
	wire          terasic_camera_0_avalon_streaming_source_valid;                                         // TERASIC_CAMERA_0:st_valid -> alt_vip_vfb_0:din_valid
	wire          terasic_camera_0_avalon_streaming_source_startofpacket;                                 // TERASIC_CAMERA_0:st_sop -> alt_vip_vfb_0:din_startofpacket
	wire   [23:0] terasic_camera_0_avalon_streaming_source_data;                                          // TERASIC_CAMERA_0:st_data -> alt_vip_vfb_0:din_data
	wire          terasic_camera_0_avalon_streaming_source_ready;                                         // alt_vip_vfb_0:din_ready -> TERASIC_CAMERA_0:st_ready
	wire          alt_vip_vfb_0_dout_endofpacket;                                                         // alt_vip_vfb_0:dout_endofpacket -> alt_vip_itc_0:is_eop
	wire          alt_vip_vfb_0_dout_valid;                                                               // alt_vip_vfb_0:dout_valid -> alt_vip_itc_0:is_valid
	wire          alt_vip_vfb_0_dout_startofpacket;                                                       // alt_vip_vfb_0:dout_startofpacket -> alt_vip_itc_0:is_sop
	wire   [23:0] alt_vip_vfb_0_dout_data;                                                                // alt_vip_vfb_0:dout_data -> alt_vip_itc_0:is_data
	wire          alt_vip_vfb_0_dout_ready;                                                               // alt_vip_itc_0:is_ready -> alt_vip_vfb_0:dout_ready
	wire          uniphy_ddr3_afi_clk_clk;                                                                // uniphy_ddr3:afi_clk -> [TERASIC_CAMERA_0:clk, addr_router:clk, addr_router_001:clk, alt_vip_itc_0:is_clk, alt_vip_vfb_0:clock, alt_vip_vfb_0_read_master_translator:clk, alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:clk, alt_vip_vfb_0_write_master_translator:clk, alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, id_router:clk, rsp_xbar_demux:clk, rst_controller:clk, rst_controller_001:clk, uniphy_ddr3_avl_translator:clk, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:clk, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk]
	wire    [5:0] alt_vip_vfb_0_write_master_burstcount;                                                  // alt_vip_vfb_0:write_master_av_burstcount -> alt_vip_vfb_0_write_master_translator:av_burstcount
	wire          alt_vip_vfb_0_write_master_waitrequest;                                                 // alt_vip_vfb_0_write_master_translator:av_waitrequest -> alt_vip_vfb_0:write_master_av_waitrequest
	wire   [31:0] alt_vip_vfb_0_write_master_writedata;                                                   // alt_vip_vfb_0:write_master_av_writedata -> alt_vip_vfb_0_write_master_translator:av_writedata
	wire   [31:0] alt_vip_vfb_0_write_master_address;                                                     // alt_vip_vfb_0:write_master_av_address -> alt_vip_vfb_0_write_master_translator:av_address
	wire          alt_vip_vfb_0_write_master_write;                                                       // alt_vip_vfb_0:write_master_av_write -> alt_vip_vfb_0_write_master_translator:av_write
	wire    [5:0] alt_vip_vfb_0_read_master_burstcount;                                                   // alt_vip_vfb_0:read_master_av_burstcount -> alt_vip_vfb_0_read_master_translator:av_burstcount
	wire          alt_vip_vfb_0_read_master_waitrequest;                                                  // alt_vip_vfb_0_read_master_translator:av_waitrequest -> alt_vip_vfb_0:read_master_av_waitrequest
	wire   [31:0] alt_vip_vfb_0_read_master_address;                                                      // alt_vip_vfb_0:read_master_av_address -> alt_vip_vfb_0_read_master_translator:av_address
	wire          alt_vip_vfb_0_read_master_read;                                                         // alt_vip_vfb_0:read_master_av_read -> alt_vip_vfb_0_read_master_translator:av_read
	wire   [31:0] alt_vip_vfb_0_read_master_readdata;                                                     // alt_vip_vfb_0_read_master_translator:av_readdata -> alt_vip_vfb_0:read_master_av_readdata
	wire          alt_vip_vfb_0_read_master_readdatavalid;                                                // alt_vip_vfb_0_read_master_translator:av_readdatavalid -> alt_vip_vfb_0:read_master_av_readdatavalid
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_waitrequest;                             // uniphy_ddr3:avl_ready -> uniphy_ddr3_avl_translator:av_waitrequest
	wire    [3:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_burstcount;                              // uniphy_ddr3_avl_translator:av_burstcount -> uniphy_ddr3:avl_size
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_writedata;                               // uniphy_ddr3_avl_translator:av_writedata -> uniphy_ddr3:avl_wdata
	wire   [24:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_address;                                 // uniphy_ddr3_avl_translator:av_address -> uniphy_ddr3:avl_addr
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_write;                                   // uniphy_ddr3_avl_translator:av_write -> uniphy_ddr3:avl_write_req
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_beginbursttransfer;                      // uniphy_ddr3_avl_translator:av_beginbursttransfer -> uniphy_ddr3:avl_burstbegin
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_read;                                    // uniphy_ddr3_avl_translator:av_read -> uniphy_ddr3:avl_read_req
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdata;                                // uniphy_ddr3:avl_rdata -> uniphy_ddr3_avl_translator:av_readdata
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdatavalid;                           // uniphy_ddr3:avl_rdata_valid -> uniphy_ddr3_avl_translator:av_readdatavalid
	wire   [31:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_byteenable;                              // uniphy_ddr3_avl_translator:av_byteenable -> uniphy_ddr3:avl_be
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_waitrequest;            // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_waitrequest -> alt_vip_vfb_0_write_master_translator:uav_waitrequest
	wire    [7:0] alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_burstcount;             // alt_vip_vfb_0_write_master_translator:uav_burstcount -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [31:0] alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_writedata;              // alt_vip_vfb_0_write_master_translator:uav_writedata -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_address;                // alt_vip_vfb_0_write_master_translator:uav_address -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_address
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_lock;                   // alt_vip_vfb_0_write_master_translator:uav_lock -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_lock
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_write;                  // alt_vip_vfb_0_write_master_translator:uav_write -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_write
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_read;                   // alt_vip_vfb_0_write_master_translator:uav_read -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_read
	wire   [31:0] alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_readdata;               // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_readdata -> alt_vip_vfb_0_write_master_translator:uav_readdata
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_debugaccess;            // alt_vip_vfb_0_write_master_translator:uav_debugaccess -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [3:0] alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_byteenable;             // alt_vip_vfb_0_write_master_translator:uav_byteenable -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_readdatavalid;          // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> alt_vip_vfb_0_write_master_translator:uav_readdatavalid
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_waitrequest;             // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_waitrequest -> alt_vip_vfb_0_read_master_translator:uav_waitrequest
	wire    [7:0] alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_burstcount;              // alt_vip_vfb_0_read_master_translator:uav_burstcount -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [31:0] alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_writedata;               // alt_vip_vfb_0_read_master_translator:uav_writedata -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_address;                 // alt_vip_vfb_0_read_master_translator:uav_address -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_address
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_lock;                    // alt_vip_vfb_0_read_master_translator:uav_lock -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_lock
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_write;                   // alt_vip_vfb_0_read_master_translator:uav_write -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_write
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_read;                    // alt_vip_vfb_0_read_master_translator:uav_read -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_read
	wire   [31:0] alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_readdata;                // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_readdata -> alt_vip_vfb_0_read_master_translator:uav_readdata
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_debugaccess;             // alt_vip_vfb_0_read_master_translator:uav_debugaccess -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [3:0] alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_byteenable;              // alt_vip_vfb_0_read_master_translator:uav_byteenable -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_readdatavalid;           // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> alt_vip_vfb_0_read_master_translator:uav_readdatavalid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;               // uniphy_ddr3_avl_translator:uav_waitrequest -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [8:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;                // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> uniphy_ddr3_avl_translator:uav_burstcount
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                 // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> uniphy_ddr3_avl_translator:uav_writedata
	wire   [31:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_address;                   // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_address -> uniphy_ddr3_avl_translator:uav_address
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_write;                     // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_write -> uniphy_ddr3_avl_translator:uav_write
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_lock;                      // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_lock -> uniphy_ddr3_avl_translator:uav_lock
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_read;                      // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_read -> uniphy_ddr3_avl_translator:uav_read
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                  // uniphy_ddr3_avl_translator:uav_readdata -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;             // uniphy_ddr3_avl_translator:uav_readdatavalid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;               // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> uniphy_ddr3_avl_translator:uav_debugaccess
	wire   [31:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;                // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> uniphy_ddr3_avl_translator:uav_byteenable
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;        // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;              // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;      // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [349:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_data;               // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;              // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [349:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid;         // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data;          // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready;         // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket;   // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_valid;         // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
	wire   [96:0] alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_data;          // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
	wire          alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_ready;         // addr_router:sink_ready -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket;    // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_valid;          // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket;  // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
	wire   [96:0] alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_data;           // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
	wire          alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_ready;          // addr_router_001:sink_ready -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;               // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_valid;                     // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;             // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
	wire  [348:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_data;                      // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_ready;                     // id_router:sink_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire          rst_controller_reset_out_reset;                                                         // rst_controller:reset_out -> [TERASIC_CAMERA_0:reset_n, addr_router:reset, addr_router_001:reset, alt_vip_vfb_0:reset, alt_vip_vfb_0_read_master_translator:reset, alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:reset, alt_vip_vfb_0_write_master_translator:reset, alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset]
	wire          rst_controller_001_reset_out_reset;                                                     // rst_controller_001:reset_out -> [alt_vip_itc_0:rst, cmd_xbar_mux:reset, id_router:reset, rsp_xbar_demux:reset, uniphy_ddr3_avl_translator:reset, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:reset, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset]
	wire          uniphy_ddr3_afi_reset_reset;                                                            // uniphy_ddr3:afi_reset_n -> rst_controller_001:reset_in0
	wire          cmd_xbar_demux_src0_endofpacket;                                                        // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire          cmd_xbar_demux_src0_valid;                                                              // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
	wire          cmd_xbar_demux_src0_startofpacket;                                                      // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire   [96:0] cmd_xbar_demux_src0_data;                                                               // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
	wire    [1:0] cmd_xbar_demux_src0_channel;                                                            // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
	wire          cmd_xbar_demux_src0_ready;                                                              // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
	wire          cmd_xbar_demux_001_src0_endofpacket;                                                    // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
	wire          cmd_xbar_demux_001_src0_valid;                                                          // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
	wire          cmd_xbar_demux_001_src0_startofpacket;                                                  // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
	wire   [96:0] cmd_xbar_demux_001_src0_data;                                                           // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
	wire    [1:0] cmd_xbar_demux_001_src0_channel;                                                        // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
	wire          cmd_xbar_demux_001_src0_ready;                                                          // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
	wire          rsp_xbar_demux_src0_endofpacket;                                                        // rsp_xbar_demux:src0_endofpacket -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          rsp_xbar_demux_src0_valid;                                                              // rsp_xbar_demux:src0_valid -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          rsp_xbar_demux_src0_startofpacket;                                                      // rsp_xbar_demux:src0_startofpacket -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire   [96:0] rsp_xbar_demux_src0_data;                                                               // rsp_xbar_demux:src0_data -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [1:0] rsp_xbar_demux_src0_channel;                                                            // rsp_xbar_demux:src0_channel -> alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          rsp_xbar_demux_src1_endofpacket;                                                        // rsp_xbar_demux:src1_endofpacket -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          rsp_xbar_demux_src1_valid;                                                              // rsp_xbar_demux:src1_valid -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          rsp_xbar_demux_src1_startofpacket;                                                      // rsp_xbar_demux:src1_startofpacket -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire   [96:0] rsp_xbar_demux_src1_data;                                                               // rsp_xbar_demux:src1_data -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [1:0] rsp_xbar_demux_src1_channel;                                                            // rsp_xbar_demux:src1_channel -> alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          addr_router_src_endofpacket;                                                            // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire          addr_router_src_valid;                                                                  // addr_router:src_valid -> cmd_xbar_demux:sink_valid
	wire          addr_router_src_startofpacket;                                                          // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire   [96:0] addr_router_src_data;                                                                   // addr_router:src_data -> cmd_xbar_demux:sink_data
	wire    [1:0] addr_router_src_channel;                                                                // addr_router:src_channel -> cmd_xbar_demux:sink_channel
	wire          addr_router_src_ready;                                                                  // cmd_xbar_demux:sink_ready -> addr_router:src_ready
	wire          rsp_xbar_demux_src0_ready;                                                              // alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux:src0_ready
	wire          addr_router_001_src_endofpacket;                                                        // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire          addr_router_001_src_valid;                                                              // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
	wire          addr_router_001_src_startofpacket;                                                      // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire   [96:0] addr_router_001_src_data;                                                               // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
	wire    [1:0] addr_router_001_src_channel;                                                            // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
	wire          addr_router_001_src_ready;                                                              // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
	wire          rsp_xbar_demux_src1_ready;                                                              // alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux:src1_ready
	wire          cmd_xbar_mux_src_endofpacket;                                                           // cmd_xbar_mux:src_endofpacket -> width_adapter:in_endofpacket
	wire          cmd_xbar_mux_src_valid;                                                                 // cmd_xbar_mux:src_valid -> width_adapter:in_valid
	wire          cmd_xbar_mux_src_startofpacket;                                                         // cmd_xbar_mux:src_startofpacket -> width_adapter:in_startofpacket
	wire   [96:0] cmd_xbar_mux_src_data;                                                                  // cmd_xbar_mux:src_data -> width_adapter:in_data
	wire    [1:0] cmd_xbar_mux_src_channel;                                                               // cmd_xbar_mux:src_channel -> width_adapter:in_channel
	wire          cmd_xbar_mux_src_ready;                                                                 // width_adapter:in_ready -> cmd_xbar_mux:src_ready
	wire          width_adapter_src_endofpacket;                                                          // width_adapter:out_endofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          width_adapter_src_valid;                                                                // width_adapter:out_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire          width_adapter_src_startofpacket;                                                        // width_adapter:out_startofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [348:0] width_adapter_src_data;                                                                 // width_adapter:out_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire          width_adapter_src_ready;                                                                // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_ready -> width_adapter:out_ready
	wire    [1:0] width_adapter_src_channel;                                                              // width_adapter:out_channel -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire          id_router_src_endofpacket;                                                              // id_router:src_endofpacket -> width_adapter_001:in_endofpacket
	wire          id_router_src_valid;                                                                    // id_router:src_valid -> width_adapter_001:in_valid
	wire          id_router_src_startofpacket;                                                            // id_router:src_startofpacket -> width_adapter_001:in_startofpacket
	wire  [348:0] id_router_src_data;                                                                     // id_router:src_data -> width_adapter_001:in_data
	wire    [1:0] id_router_src_channel;                                                                  // id_router:src_channel -> width_adapter_001:in_channel
	wire          id_router_src_ready;                                                                    // width_adapter_001:in_ready -> id_router:src_ready
	wire          width_adapter_001_src_endofpacket;                                                      // width_adapter_001:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire          width_adapter_001_src_valid;                                                            // width_adapter_001:out_valid -> rsp_xbar_demux:sink_valid
	wire          width_adapter_001_src_startofpacket;                                                    // width_adapter_001:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire   [96:0] width_adapter_001_src_data;                                                             // width_adapter_001:out_data -> rsp_xbar_demux:sink_data
	wire          width_adapter_001_src_ready;                                                            // rsp_xbar_demux:sink_ready -> width_adapter_001:out_ready
	wire    [1:0] width_adapter_001_src_channel;                                                          // width_adapter_001:out_channel -> rsp_xbar_demux:sink_channel

	TR4_QSYS_uniphy_ddr3 uniphy_ddr3 (
		.pll_ref_clk       (external_clk50_clk),                                                //     pll_ref_clk.clk
		.global_reset_n    (external_reset_reset_n),                                            //    global_reset.reset_n
		.soft_reset_n      (external_reset_reset_n),                                            //      soft_reset.reset_n
		.afi_clk           (uniphy_ddr3_afi_clk_clk),                                           //         afi_clk.clk
		.afi_half_clk      (),                                                                  //    afi_half_clk.clk
		.afi_reset_n       (uniphy_ddr3_afi_reset_reset),                                       //       afi_reset.reset_n
		.mem_ba            (memory_mem_ba),                                                     //          memory.mem_ba
		.mem_odt           (memory_mem_odt),                                                    //                .mem_odt
		.mem_dq            (memory_mem_dq),                                                     //                .mem_dq
		.mem_dm            (memory_mem_dm),                                                     //                .mem_dm
		.mem_cas_n         (memory_mem_cas_n),                                                  //                .mem_cas_n
		.mem_cs_n          (memory_mem_cs_n),                                                   //                .mem_cs_n
		.mem_we_n          (memory_mem_we_n),                                                   //                .mem_we_n
		.mem_dqs           (memory_mem_dqs),                                                    //                .mem_dqs
		.mem_dqs_n         (memory_mem_dqs_n),                                                  //                .mem_dqs_n
		.mem_a             (memory_mem_a),                                                      //                .mem_a
		.mem_cke           (memory_mem_cke),                                                    //                .mem_cke
		.mem_ck_n          (memory_mem_ck_n),                                                   //                .mem_ck_n
		.mem_ck            (memory_mem_ck),                                                     //                .mem_ck
		.mem_ras_n         (memory_mem_ras_n),                                                  //                .mem_ras_n
		.mem_reset_n       (memory_mem_reset_n),                                                //                .mem_reset_n
		.avl_ready         (uniphy_ddr3_avl_translator_avalon_anti_slave_0_waitrequest),        //             avl.waitrequest_n
		.avl_burstbegin    (uniphy_ddr3_avl_translator_avalon_anti_slave_0_beginbursttransfer), //                .beginbursttransfer
		.avl_addr          (uniphy_ddr3_avl_translator_avalon_anti_slave_0_address),            //                .address
		.avl_rdata_valid   (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdatavalid),      //                .readdatavalid
		.avl_rdata         (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdata),           //                .readdata
		.avl_wdata         (uniphy_ddr3_avl_translator_avalon_anti_slave_0_writedata),          //                .writedata
		.avl_be            (uniphy_ddr3_avl_translator_avalon_anti_slave_0_byteenable),         //                .byteenable
		.avl_read_req      (uniphy_ddr3_avl_translator_avalon_anti_slave_0_read),               //                .read
		.avl_write_req     (uniphy_ddr3_avl_translator_avalon_anti_slave_0_write),              //                .write
		.avl_size          (uniphy_ddr3_avl_translator_avalon_anti_slave_0_burstcount),         //                .burstcount
		.local_cal_fail    (uniphy_ddr3_status_local_cal_fail),                                 //          status.local_cal_fail
		.local_cal_success (uniphy_ddr3_status_local_cal_success),                              //                .local_cal_success
		.local_init_done   (uniphy_ddr3_status_local_init_done),                                //                .local_init_done
		.oct_rdn           (oct_rdn),                                                           //             oct.rdn
		.oct_rup           (oct_rup),                                                           //                .rup
		.local_powerdn_ack (uniphy_ddr3_local_powerdown_local_powerdn_ack),                     // local_powerdown.local_powerdn_ack
		.local_powerdn_req (uniphy_ddr3_local_powerdown_local_powerdn_req)                      //                .local_powerdn_req
	);

	TERASIC_CAMERA #(
		.VIDEO_W (1280),
		.VIDEO_H (720)
	) terasic_camera_0 (
		.clk           (uniphy_ddr3_afi_clk_clk),                                //             clock_reset.clk
		.reset_n       (~rst_controller_reset_out_reset),                        //       clock_reset_reset.reset_n
		.CAMERA_D      (terasic_camera_0_conduit_end_D),                         //             conduit_end.export
		.CAMERA_FVAL   (terasic_camera_0_conduit_end_FVAL),                      //                        .export
		.CAMERA_LVAL   (terasic_camera_0_conduit_end_LVAL),                      //                        .export
		.CAMERA_PIXCLK (terasic_camera_0_conduit_end_PIXCLK),                    //                        .export
		.st_data       (terasic_camera_0_avalon_streaming_source_data),          // avalon_streaming_source.data
		.st_sop        (terasic_camera_0_avalon_streaming_source_startofpacket), //                        .startofpacket
		.st_eop        (terasic_camera_0_avalon_streaming_source_endofpacket),   //                        .endofpacket
		.st_ready      (terasic_camera_0_avalon_streaming_source_ready),         //                        .ready
		.st_valid      (terasic_camera_0_avalon_streaming_source_valid)          //                        .valid
	);

	TR4_QSYS_alt_vip_vfb_0 #(
		.PARAMETERISATION                      ("<frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>1280</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>720</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>0</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>1</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>1</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>32</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>32</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>true</VFB_DROP_INVALID_FIELDS></frameBufferParams>"),
		.AUTO_DEVICE_FAMILY                    ("Stratix IV"),
		.AUTO_READER_CONTROL_CLOCKS_SAME       ("0"),
		.AUTO_READ_MASTER_CLOCKS_SAME          ("2"),
		.AUTO_READ_MASTER_INTERRUPT_USED_MASK  ("0"),
		.AUTO_READ_MASTER_MAX_READ_LATENCY     ("2"),
		.AUTO_READ_MASTER_NEED_ADDR_WIDTH      ("35"),
		.AUTO_WRITER_CONTROL_CLOCKS_SAME       ("0"),
		.AUTO_WRITE_MASTER_CLOCKS_SAME         ("2"),
		.AUTO_WRITE_MASTER_INTERRUPT_USED_MASK ("0"),
		.AUTO_WRITE_MASTER_MAX_READ_LATENCY    ("2"),
		.AUTO_WRITE_MASTER_NEED_ADDR_WIDTH     ("35")
	) alt_vip_vfb_0 (
		.clock                        (uniphy_ddr3_afi_clk_clk),                                //        clock.clk
		.reset                        (rst_controller_reset_out_reset),                         //        reset.reset
		.din_ready                    (terasic_camera_0_avalon_streaming_source_ready),         //          din.ready
		.din_valid                    (terasic_camera_0_avalon_streaming_source_valid),         //             .valid
		.din_data                     (terasic_camera_0_avalon_streaming_source_data),          //             .data
		.din_startofpacket            (terasic_camera_0_avalon_streaming_source_startofpacket), //             .startofpacket
		.din_endofpacket              (terasic_camera_0_avalon_streaming_source_endofpacket),   //             .endofpacket
		.dout_ready                   (alt_vip_vfb_0_dout_ready),                               //         dout.ready
		.dout_valid                   (alt_vip_vfb_0_dout_valid),                               //             .valid
		.dout_data                    (alt_vip_vfb_0_dout_data),                                //             .data
		.dout_startofpacket           (alt_vip_vfb_0_dout_startofpacket),                       //             .startofpacket
		.dout_endofpacket             (alt_vip_vfb_0_dout_endofpacket),                         //             .endofpacket
		.read_master_av_address       (alt_vip_vfb_0_read_master_address),                      //  read_master.address
		.read_master_av_read          (alt_vip_vfb_0_read_master_read),                         //             .read
		.read_master_av_waitrequest   (alt_vip_vfb_0_read_master_waitrequest),                  //             .waitrequest
		.read_master_av_readdatavalid (alt_vip_vfb_0_read_master_readdatavalid),                //             .readdatavalid
		.read_master_av_readdata      (alt_vip_vfb_0_read_master_readdata),                     //             .readdata
		.read_master_av_burstcount    (alt_vip_vfb_0_read_master_burstcount),                   //             .burstcount
		.write_master_av_address      (alt_vip_vfb_0_write_master_address),                     // write_master.address
		.write_master_av_write        (alt_vip_vfb_0_write_master_write),                       //             .write
		.write_master_av_writedata    (alt_vip_vfb_0_write_master_writedata),                   //             .writedata
		.write_master_av_waitrequest  (alt_vip_vfb_0_write_master_waitrequest),                 //             .waitrequest
		.write_master_av_burstcount   (alt_vip_vfb_0_write_master_burstcount)                   //             .burstcount
	);

	alt_vipitc110_IS2Vid #(
		.NUMBER_OF_COLOUR_PLANES       (3),
		.COLOUR_PLANES_ARE_IN_PARALLEL (1),
		.BPS                           (8),
		.INTERLACED                    (0),
		.H_ACTIVE_PIXELS               (1280),
		.V_ACTIVE_LINES                (720),
		.ACCEPT_COLOURS_IN_SEQ         (0),
		.FIFO_DEPTH                    (1280),
		.CLOCKS_ARE_SAME               (0),
		.USE_CONTROL                   (0),
		.NO_OF_MODES                   (1),
		.THRESHOLD                     (1279),
		.STD_WIDTH                     (1),
		.GENERATE_SYNC                 (0),
		.USE_EMBEDDED_SYNCS            (0),
		.AP_LINE                       (0),
		.V_BLANK                       (0),
		.H_BLANK                       (0),
		.H_SYNC_LENGTH                 (32),
		.H_FRONT_PORCH                 (48),
		.H_BACK_PORCH                  (80),
		.V_SYNC_LENGTH                 (45),
		.V_FRONT_PORCH                 (2),
		.V_BACK_PORCH                  (14),
		.F_RISING_EDGE                 (0),
		.F_FALLING_EDGE                (0),
		.FIELD0_V_RISING_EDGE          (0),
		.FIELD0_V_BLANK                (0),
		.FIELD0_V_SYNC_LENGTH          (0),
		.FIELD0_V_FRONT_PORCH          (0),
		.FIELD0_V_BACK_PORCH           (0),
		.ANC_LINE                      (0),
		.FIELD0_ANC_LINE               (0)
	) alt_vip_itc_0 (
		.is_clk        (uniphy_ddr3_afi_clk_clk),                   //       is_clk_rst.clk
		.rst           (rst_controller_001_reset_out_reset),        // is_clk_rst_reset.reset
		.is_data       (alt_vip_vfb_0_dout_data),                   //              din.data
		.is_valid      (alt_vip_vfb_0_dout_valid),                  //                 .valid
		.is_ready      (alt_vip_vfb_0_dout_ready),                  //                 .ready
		.is_sop        (alt_vip_vfb_0_dout_startofpacket),          //                 .startofpacket
		.is_eop        (alt_vip_vfb_0_dout_endofpacket),            //                 .endofpacket
		.vid_clk       (alt_vip_itc_0_clocked_video_vid_clk),       //    clocked_video.export
		.vid_data      (alt_vip_itc_0_clocked_video_vid_data),      //                 .export
		.underflow     (alt_vip_itc_0_clocked_video_underflow),     //                 .export
		.vid_datavalid (alt_vip_itc_0_clocked_video_vid_datavalid), //                 .export
		.vid_v_sync    (alt_vip_itc_0_clocked_video_vid_v_sync),    //                 .export
		.vid_h_sync    (alt_vip_itc_0_clocked_video_vid_h_sync),    //                 .export
		.vid_f         (alt_vip_itc_0_clocked_video_vid_f),         //                 .export
		.vid_h         (alt_vip_itc_0_clocked_video_vid_h),         //                 .export
		.vid_v         (alt_vip_itc_0_clocked_video_vid_v)          //                 .export
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (6),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (8),
		.USE_READ                    (0),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) alt_vip_vfb_0_write_master_translator (
		.clk                   (uniphy_ddr3_afi_clk_clk),                                                       //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                //                     reset.reset
		.uav_address           (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (alt_vip_vfb_0_write_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (alt_vip_vfb_0_write_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (alt_vip_vfb_0_write_master_burstcount),                                         //                          .burstcount
		.av_write              (alt_vip_vfb_0_write_master_write),                                              //                          .write
		.av_writedata          (alt_vip_vfb_0_write_master_writedata),                                          //                          .writedata
		.av_byteenable         (4'b1111),                                                                       //               (terminated)
		.av_beginbursttransfer (1'b0),                                                                          //               (terminated)
		.av_begintransfer      (1'b0),                                                                          //               (terminated)
		.av_chipselect         (1'b0),                                                                          //               (terminated)
		.av_read               (1'b0),                                                                          //               (terminated)
		.av_readdata           (),                                                                              //               (terminated)
		.av_readdatavalid      (),                                                                              //               (terminated)
		.av_lock               (1'b0),                                                                          //               (terminated)
		.av_debugaccess        (1'b0),                                                                          //               (terminated)
		.uav_clken             (),                                                                              //               (terminated)
		.av_clken              (1'b1)                                                                           //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (6),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (8),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) alt_vip_vfb_0_read_master_translator (
		.clk                   (uniphy_ddr3_afi_clk_clk),                                                      //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                               //                     reset.reset
		.uav_address           (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (alt_vip_vfb_0_read_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (alt_vip_vfb_0_read_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (alt_vip_vfb_0_read_master_burstcount),                                         //                          .burstcount
		.av_read               (alt_vip_vfb_0_read_master_read),                                               //                          .read
		.av_readdata           (alt_vip_vfb_0_read_master_readdata),                                           //                          .readdata
		.av_readdatavalid      (alt_vip_vfb_0_read_master_readdatavalid),                                      //                          .readdatavalid
		.av_byteenable         (4'b1111),                                                                      //               (terminated)
		.av_beginbursttransfer (1'b0),                                                                         //               (terminated)
		.av_begintransfer      (1'b0),                                                                         //               (terminated)
		.av_chipselect         (1'b0),                                                                         //               (terminated)
		.av_write              (1'b0),                                                                         //               (terminated)
		.av_writedata          (32'b00000000000000000000000000000000),                                         //               (terminated)
		.av_lock               (1'b0),                                                                         //               (terminated)
		.av_debugaccess        (1'b0),                                                                         //               (terminated)
		.uav_clken             (),                                                                             //               (terminated)
		.av_clken              (1'b1)                                                                          //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (25),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (4),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (9),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) uniphy_ddr3_avl_translator (
		.clk                   (uniphy_ddr3_afi_clk_clk),                                                    //                      clk.clk
		.reset                 (rst_controller_001_reset_out_reset),                                         //                    reset.reset
		.uav_address           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (uniphy_ddr3_avl_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (uniphy_ddr3_avl_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (uniphy_ddr3_avl_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (uniphy_ddr3_avl_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_beginbursttransfer (uniphy_ddr3_avl_translator_avalon_anti_slave_0_beginbursttransfer),          //                         .beginbursttransfer
		.av_burstcount         (uniphy_ddr3_avl_translator_avalon_anti_slave_0_burstcount),                  //                         .burstcount
		.av_byteenable         (uniphy_ddr3_avl_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_readdatavalid      (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdatavalid),               //                         .readdatavalid
		.av_waitrequest        (~uniphy_ddr3_avl_translator_avalon_anti_slave_0_waitrequest),                //                         .waitrequest
		.av_begintransfer      (),                                                                           //              (terminated)
		.av_writebyteenable    (),                                                                           //              (terminated)
		.av_lock               (),                                                                           //              (terminated)
		.av_chipselect         (),                                                                           //              (terminated)
		.av_clken              (),                                                                           //              (terminated)
		.uav_clken             (1'b0),                                                                       //              (terminated)
		.av_debugaccess        (),                                                                           //              (terminated)
		.av_outputenable       ()                                                                            //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (96),
		.PKT_BEGIN_BURST           (91),
		.PKT_BURSTWRAP_H           (90),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (73),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (93),
		.PKT_SRC_ID_L              (92),
		.PKT_DEST_ID_H             (95),
		.PKT_DEST_ID_L             (94),
		.ST_DATA_W                 (97),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (8),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (1),
		.BURSTWRAP_VALUE           (511)
	) alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent (
		.clk              (uniphy_ddr3_afi_clk_clk),                                                                //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                         // clk_reset.reset
		.av_address       (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (rsp_xbar_demux_src0_valid),                                                              //        rp.valid
		.rp_data          (rsp_xbar_demux_src0_data),                                                               //          .data
		.rp_channel       (rsp_xbar_demux_src0_channel),                                                            //          .channel
		.rp_startofpacket (rsp_xbar_demux_src0_startofpacket),                                                      //          .startofpacket
		.rp_endofpacket   (rsp_xbar_demux_src0_endofpacket),                                                        //          .endofpacket
		.rp_ready         (rsp_xbar_demux_src0_ready)                                                               //          .ready
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (96),
		.PKT_PROTECTION_L          (96),
		.PKT_BEGIN_BURST           (91),
		.PKT_BURSTWRAP_H           (90),
		.PKT_BURSTWRAP_L           (82),
		.PKT_BYTE_CNT_H            (81),
		.PKT_BYTE_CNT_L            (73),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_TRANS_LOCK            (72),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (93),
		.PKT_SRC_ID_L              (92),
		.PKT_DEST_ID_H             (95),
		.PKT_DEST_ID_L             (94),
		.ST_DATA_W                 (97),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (8),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (2),
		.BURSTWRAP_VALUE           (511)
	) alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent (
		.clk              (uniphy_ddr3_afi_clk_clk),                                                               //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                        // clk_reset.reset
		.av_address       (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (rsp_xbar_demux_src1_valid),                                                             //        rp.valid
		.rp_data          (rsp_xbar_demux_src1_data),                                                              //          .data
		.rp_channel       (rsp_xbar_demux_src1_channel),                                                           //          .channel
		.rp_startofpacket (rsp_xbar_demux_src1_startofpacket),                                                     //          .startofpacket
		.rp_endofpacket   (rsp_xbar_demux_src1_endofpacket),                                                       //          .endofpacket
		.rp_ready         (rsp_xbar_demux_src1_ready)                                                              //          .ready
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (343),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_TRANS_LOCK            (324),
		.PKT_SRC_ID_H              (345),
		.PKT_SRC_ID_L              (344),
		.PKT_DEST_ID_H             (347),
		.PKT_DEST_ID_L             (346),
		.PKT_BURSTWRAP_H           (342),
		.PKT_BURSTWRAP_L           (334),
		.PKT_BYTE_CNT_H            (333),
		.PKT_BYTE_CNT_L            (325),
		.PKT_PROTECTION_H          (348),
		.PKT_PROTECTION_L          (348),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (349),
		.AVS_BURSTCOUNT_W          (9),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (uniphy_ddr3_afi_clk_clk),                                                              //             clk.clk
		.reset                   (rst_controller_001_reset_out_reset),                                                   //       clk_reset.reset
		.m0_address              (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (width_adapter_src_ready),                                                              //              cp.ready
		.cp_valid                (width_adapter_src_valid),                                                              //                .valid
		.cp_data                 (width_adapter_src_data),                                                               //                .data
		.cp_startofpacket        (width_adapter_src_startofpacket),                                                      //                .startofpacket
		.cp_endofpacket          (width_adapter_src_endofpacket),                                                        //                .endofpacket
		.cp_channel              (width_adapter_src_channel),                                                            //                .channel
		.rf_sink_ready           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (350),
		.FIFO_DEPTH          (33),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (uniphy_ddr3_afi_clk_clk),                                                              //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                                   // clk_reset.reset
		.in_data           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                // (terminated)
		.csr_read          (1'b0),                                                                                 // (terminated)
		.csr_write         (1'b0),                                                                                 // (terminated)
		.csr_readdata      (),                                                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                 // (terminated)
		.almost_full_data  (),                                                                                     // (terminated)
		.almost_empty_data (),                                                                                     // (terminated)
		.in_empty          (1'b0),                                                                                 // (terminated)
		.out_empty         (),                                                                                     // (terminated)
		.in_error          (1'b0),                                                                                 // (terminated)
		.out_error         (),                                                                                     // (terminated)
		.in_channel        (1'b0),                                                                                 // (terminated)
		.out_channel       ()                                                                                      // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (256),
		.FIFO_DEPTH          (256),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo (
		.clk               (uniphy_ddr3_afi_clk_clk),                                                        //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                             // clk_reset.reset
		.in_data           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                                          // (terminated)
		.csr_read          (1'b0),                                                                           // (terminated)
		.csr_write         (1'b0),                                                                           // (terminated)
		.csr_readdata      (),                                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                           // (terminated)
		.almost_full_data  (),                                                                               // (terminated)
		.almost_empty_data (),                                                                               // (terminated)
		.in_startofpacket  (1'b0),                                                                           // (terminated)
		.in_endofpacket    (1'b0),                                                                           // (terminated)
		.out_startofpacket (),                                                                               // (terminated)
		.out_endofpacket   (),                                                                               // (terminated)
		.in_empty          (1'b0),                                                                           // (terminated)
		.out_empty         (),                                                                               // (terminated)
		.in_error          (1'b0),                                                                           // (terminated)
		.out_error         (),                                                                               // (terminated)
		.in_channel        (1'b0),                                                                           // (terminated)
		.out_channel       ()                                                                                // (terminated)
	);

	TR4_QSYS_addr_router addr_router (
		.sink_ready         (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (alt_vip_vfb_0_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (uniphy_ddr3_afi_clk_clk),                                                                //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                         // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                                                  //       src.ready
		.src_valid          (addr_router_src_valid),                                                                  //          .valid
		.src_data           (addr_router_src_data),                                                                   //          .data
		.src_channel        (addr_router_src_channel),                                                                //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                                          //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                                             //          .endofpacket
	);

	TR4_QSYS_addr_router addr_router_001 (
		.sink_ready         (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (alt_vip_vfb_0_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (uniphy_ddr3_afi_clk_clk),                                                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                        // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                                             //       src.ready
		.src_valid          (addr_router_001_src_valid),                                                             //          .valid
		.src_data           (addr_router_001_src_data),                                                              //          .data
		.src_channel        (addr_router_001_src_channel),                                                           //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                                     //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                                        //          .endofpacket
	);

	TR4_QSYS_id_router id_router (
		.sink_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (uniphy_ddr3_afi_clk_clk),                                                    //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),                                         // clk_reset.reset
		.src_ready          (id_router_src_ready),                                                        //       src.ready
		.src_valid          (id_router_src_valid),                                                        //          .valid
		.src_data           (id_router_src_data),                                                         //          .data
		.src_channel        (id_router_src_channel),                                                      //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                                //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                                   //          .endofpacket
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~external_reset_reset_n),        // reset_in0.reset
		.clk        (uniphy_ddr3_afi_clk_clk),        //       clk.clk
		.reset_out  (rst_controller_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                           // (terminated)
		.reset_in2  (1'b0),                           // (terminated)
		.reset_in3  (1'b0),                           // (terminated)
		.reset_in4  (1'b0),                           // (terminated)
		.reset_in5  (1'b0),                           // (terminated)
		.reset_in6  (1'b0),                           // (terminated)
		.reset_in7  (1'b0),                           // (terminated)
		.reset_in8  (1'b0),                           // (terminated)
		.reset_in9  (1'b0),                           // (terminated)
		.reset_in10 (1'b0),                           // (terminated)
		.reset_in11 (1'b0),                           // (terminated)
		.reset_in12 (1'b0),                           // (terminated)
		.reset_in13 (1'b0),                           // (terminated)
		.reset_in14 (1'b0),                           // (terminated)
		.reset_in15 (1'b0)                            // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller_001 (
		.reset_in0  (~uniphy_ddr3_afi_reset_reset),       // reset_in0.reset
		.clk        (uniphy_ddr3_afi_clk_clk),            //       clk.clk
		.reset_out  (rst_controller_001_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                               // (terminated)
		.reset_in2  (1'b0),                               // (terminated)
		.reset_in3  (1'b0),                               // (terminated)
		.reset_in4  (1'b0),                               // (terminated)
		.reset_in5  (1'b0),                               // (terminated)
		.reset_in6  (1'b0),                               // (terminated)
		.reset_in7  (1'b0),                               // (terminated)
		.reset_in8  (1'b0),                               // (terminated)
		.reset_in9  (1'b0),                               // (terminated)
		.reset_in10 (1'b0),                               // (terminated)
		.reset_in11 (1'b0),                               // (terminated)
		.reset_in12 (1'b0),                               // (terminated)
		.reset_in13 (1'b0),                               // (terminated)
		.reset_in14 (1'b0),                               // (terminated)
		.reset_in15 (1'b0)                                // (terminated)
	);

	TR4_QSYS_cmd_xbar_demux cmd_xbar_demux (
		.clk                (uniphy_ddr3_afi_clk_clk),           //       clk.clk
		.reset              (rst_controller_reset_out_reset),    // clk_reset.reset
		.sink_ready         (addr_router_src_ready),             //      sink.ready
		.sink_channel       (addr_router_src_channel),           //          .channel
		.sink_data          (addr_router_src_data),              //          .data
		.sink_startofpacket (addr_router_src_startofpacket),     //          .startofpacket
		.sink_endofpacket   (addr_router_src_endofpacket),       //          .endofpacket
		.sink_valid         (addr_router_src_valid),             //          .valid
		.src0_ready         (cmd_xbar_demux_src0_ready),         //      src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),         //          .valid
		.src0_data          (cmd_xbar_demux_src0_data),          //          .data
		.src0_channel       (cmd_xbar_demux_src0_channel),       //          .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_cmd_xbar_demux cmd_xbar_demux_001 (
		.clk                (uniphy_ddr3_afi_clk_clk),               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (addr_router_001_src_ready),             //      sink.ready
		.sink_channel       (addr_router_001_src_channel),           //          .channel
		.sink_data          (addr_router_001_src_data),              //          .data
		.sink_startofpacket (addr_router_001_src_startofpacket),     //          .startofpacket
		.sink_endofpacket   (addr_router_001_src_endofpacket),       //          .endofpacket
		.sink_valid         (addr_router_001_src_valid),             //          .valid
		.src0_ready         (cmd_xbar_demux_001_src0_ready),         //      src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),         //          .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),          //          .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),       //          .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (uniphy_ddr3_afi_clk_clk),               //       clk.clk
		.reset               (rst_controller_001_reset_out_reset),    // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),                //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),                //          .valid
		.src_data            (cmd_xbar_mux_src_data),                 //          .data
		.src_channel         (cmd_xbar_mux_src_channel),              //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),        //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),          //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src0_ready),             //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src0_valid),             //          .valid
		.sink0_channel       (cmd_xbar_demux_src0_channel),           //          .channel
		.sink0_data          (cmd_xbar_demux_src0_data),              //          .data
		.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src0_endofpacket),       //          .endofpacket
		.sink1_ready         (cmd_xbar_demux_001_src0_ready),         //     sink1.ready
		.sink1_valid         (cmd_xbar_demux_001_src0_valid),         //          .valid
		.sink1_channel       (cmd_xbar_demux_001_src0_channel),       //          .channel
		.sink1_data          (cmd_xbar_demux_001_src0_data),          //          .data
		.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_rsp_xbar_demux rsp_xbar_demux (
		.clk                (uniphy_ddr3_afi_clk_clk),             //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),  // clk_reset.reset
		.sink_ready         (width_adapter_001_src_ready),         //      sink.ready
		.sink_channel       (width_adapter_001_src_channel),       //          .channel
		.sink_data          (width_adapter_001_src_data),          //          .data
		.sink_startofpacket (width_adapter_001_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (width_adapter_001_src_endofpacket),   //          .endofpacket
		.sink_valid         (width_adapter_001_src_valid),         //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),           //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),           //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),            //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),         //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket),   //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket),     //          .endofpacket
		.src1_ready         (rsp_xbar_demux_src1_ready),           //      src1.ready
		.src1_valid         (rsp_xbar_demux_src1_valid),           //          .valid
		.src1_data          (rsp_xbar_demux_src1_data),            //          .data
		.src1_channel       (rsp_xbar_demux_src1_channel),         //          .channel
		.src1_startofpacket (rsp_xbar_demux_src1_startofpacket),   //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_src1_endofpacket)      //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (81),
		.IN_PKT_BYTE_CNT_L             (73),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_BURSTWRAP_H            (90),
		.IN_PKT_BURSTWRAP_L            (82),
		.IN_ST_DATA_W                  (97),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (333),
		.OUT_PKT_BYTE_CNT_L            (325),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_ST_DATA_W                 (349),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter (
		.clk               (uniphy_ddr3_afi_clk_clk),            //       clk.clk
		.reset             (rst_controller_001_reset_out_reset), // clk_reset.reset
		.in_valid          (cmd_xbar_mux_src_valid),             //      sink.valid
		.in_channel        (cmd_xbar_mux_src_channel),           //          .channel
		.in_startofpacket  (cmd_xbar_mux_src_startofpacket),     //          .startofpacket
		.in_endofpacket    (cmd_xbar_mux_src_endofpacket),       //          .endofpacket
		.in_ready          (cmd_xbar_mux_src_ready),             //          .ready
		.in_data           (cmd_xbar_mux_src_data),              //          .data
		.out_endofpacket   (width_adapter_src_endofpacket),      //       src.endofpacket
		.out_data          (width_adapter_src_data),             //          .data
		.out_channel       (width_adapter_src_channel),          //          .channel
		.out_valid         (width_adapter_src_valid),            //          .valid
		.out_ready         (width_adapter_src_ready),            //          .ready
		.out_startofpacket (width_adapter_src_startofpacket)     //          .startofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (333),
		.IN_PKT_BYTE_CNT_L             (325),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_BURSTWRAP_H            (342),
		.IN_PKT_BURSTWRAP_L            (334),
		.IN_ST_DATA_W                  (349),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (81),
		.OUT_PKT_BYTE_CNT_L            (73),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_ST_DATA_W                 (97),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_001 (
		.clk               (uniphy_ddr3_afi_clk_clk),             //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),  // clk_reset.reset
		.in_valid          (id_router_src_valid),                 //      sink.valid
		.in_channel        (id_router_src_channel),               //          .channel
		.in_startofpacket  (id_router_src_startofpacket),         //          .startofpacket
		.in_endofpacket    (id_router_src_endofpacket),           //          .endofpacket
		.in_ready          (id_router_src_ready),                 //          .ready
		.in_data           (id_router_src_data),                  //          .data
		.out_endofpacket   (width_adapter_001_src_endofpacket),   //       src.endofpacket
		.out_data          (width_adapter_001_src_data),          //          .data
		.out_channel       (width_adapter_001_src_channel),       //          .channel
		.out_valid         (width_adapter_001_src_valid),         //          .valid
		.out_ready         (width_adapter_001_src_ready),         //          .ready
		.out_startofpacket (width_adapter_001_src_startofpacket)  //          .startofpacket
	);

endmodule
