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TimeQuest Timing Analyzer Summary
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Type  : Slow 900mV 85C Model Setup 'D5M_PIXCLK'
Slack : -1.952
TNS   : -49.669

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : -1.013
TNS   : -507.517

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.013
TNS   : -507.517

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.303
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.303
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'mem_ck[0]'
Slack : 0.338
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.481
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.481
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.807
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 1.411
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 1.411
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 5.941
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 5.941
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 6.828
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 6.828
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 11.622
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'CLK_M2'
Slack : 16.497
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'altera_reserved_tck'
Slack : 47.817
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'D5M_PIXCLK'
Slack : 0.109
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.144
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.144
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.183
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.183
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 0.187
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.187
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.187
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.187
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 0.225
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.225
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.239
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'CLK_M2'
Slack : 0.267
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'altera_reserved_tck'
Slack : 0.309
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'mem_ck[0]'
Slack : 0.312
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.331
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.152
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.152
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'D5M_PIXCLK'
Slack : -6.040
TNS   : -1047.742

Type  : Slow 900mV 85C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : -3.762
TNS   : -438.293

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : -1.468
TNS   : -2220.433

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.468
TNS   : -2220.433

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.456
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.456
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 3.185
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 3.185
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'CLK_M2'
Slack : 13.068
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 42.749
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 42.749
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'altera_reserved_tck'
Slack : 49.012
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.374
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.374
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'altera_reserved_tck'
Slack : 0.486
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.510
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'D5M_PIXCLK'
Slack : 0.763
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.789
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.789
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'CLK_M2'
Slack : 0.949
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.019
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.019
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 6.782
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 6.782
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk'
Slack : 0.190
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.190
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.326
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.396
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.396
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.084
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.084
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.277
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.277
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 3.210
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 3.210
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.830
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.830
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'D5M_PIXCLK'
Slack : 5.929
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 7.482
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'CLK_M2'
Slack : 9.428
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'CLK_M5'
Slack : 9.764
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 11.667
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 11.667
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.328
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'D5M_PIXCLK'
Slack : -1.890
TNS   : -48.152

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : -0.785
TNS   : -319.617

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.785
TNS   : -319.617

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.318
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.318
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'mem_ck[0]'
Slack : 0.346
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.621
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.621
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.822
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 1.507
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 1.507
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 6.154
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 6.154
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 6.854
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 6.854
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 11.822
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'CLK_M2'
Slack : 16.715
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'altera_reserved_tck'
Slack : 47.844
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'D5M_PIXCLK'
Slack : 0.108
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.141
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.141
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.181
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.181
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.185
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.185
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 0.186
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.186
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 0.223
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.223
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.231
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'CLK_M2'
Slack : 0.258
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.297
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'mem_ck[0]'
Slack : 0.339
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.354
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.168
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.168
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'D5M_PIXCLK'
Slack : -5.784
TNS   : -1001.041

Type  : Slow 900mV 0C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : -3.573
TNS   : -416.643

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : -1.234
TNS   : -1809.018

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.234
TNS   : -1809.018

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.544
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.544
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 3.666
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 3.666
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'CLK_M2'
Slack : 13.561
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 42.850
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 42.850
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'altera_reserved_tck'
Slack : 49.010
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.362
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.362
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'altera_reserved_tck'
Slack : 0.467
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.490
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'D5M_PIXCLK'
Slack : 0.716
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.761
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.761
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'CLK_M2'
Slack : 0.902
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.992
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.992
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 6.302
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 6.302
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk'
Slack : 0.197
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.197
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.348
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.417
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.417
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.084
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.084
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.298
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.298
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 3.190
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 3.190
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.846
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.846
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'D5M_PIXCLK'
Slack : 5.907
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 7.462
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'CLK_M2'
Slack : 9.431
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'CLK_M5'
Slack : 9.749
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 11.667
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 11.667
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.358
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'D5M_PIXCLK'
Slack : -1.207
TNS   : -30.717

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.282
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.282
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.298
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.298
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'mem_ck[0]'
Slack : 0.398
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.788
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.355
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.355
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 2.349
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 2.349
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 7.128
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 7.128
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 8.261
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 8.261
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 13.761
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'CLK_M2'
Slack : 17.946
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'altera_reserved_tck'
Slack : 49.086
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'D5M_PIXCLK'
Slack : 0.036
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.070
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.070
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.087
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.087
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.090
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.090
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 0.091
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.091
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 0.104
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.104
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.137
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'CLK_M2'
Slack : 0.145
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.173
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'mem_ck[0]'
Slack : 0.399
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.611
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 1.297
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 1.297
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'D5M_PIXCLK'
Slack : -3.957
TNS   : -687.708

Type  : Fast 900mV 0C Model Recovery 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : -2.270
TNS   : -263.226

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.386
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.386
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 2.277
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 2.277
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 6.157
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 6.157
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'CLK_M2'
Slack : 15.632
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 43.629
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 43.629
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'altera_reserved_tck'
Slack : 49.771
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 0.207
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.207
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'altera_reserved_tck'
Slack : 0.275
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.279
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 0.476
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.476
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'D5M_PIXCLK'
Slack : 0.505
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'CLK_M2'
Slack : 0.557
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 0.619
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.619
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.335
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.335
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_mem_clk'
Slack : 0.192
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.192
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|memphy_leveling_clk'
Slack : 0.389
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_write_clk'
Slack : 0.391
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]'
Slack : 0.391
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_clk'
Slack : 1.084
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.084
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_addr_cmd_clk'
Slack : 1.454
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.454
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_afi_half_clk'
Slack : 3.405
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]'
Slack : 3.405
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_avl_clock'
Slack : 4.831
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.831
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'D5M_PIXCLK'
Slack : 5.679
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[1]'
Slack : 7.542
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'CLK_M2'
Slack : 9.357
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'CLK_M5'
Slack : 9.875
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|TR4_QSYS_uniphy_ddr3_p0_pll_config_clock'
Slack : 11.667
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]'
Slack : 11.667
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.190
TNS   : 0.000

------------------------------------------------------------
