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//	support information, device programming or simulation file, and any other
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//   NCO ver 9.1 VERILOG HDL TESTBENCH
`timescale 1ps / 1ps
module lpm_10M_nco_tb;

wire out_valid;
wire [12:0] sin_val;
wire [12:0] cos_val;
reg [31:0] phi;
reg reset_n;
reg clken;
reg clk;

parameter CYCLE = 10000;
parameter HALF_CYCLE = 5000;
initial
  begin
    $dumpvars;
    #0 clk = 1'b0;
    #0 reset_n = 1'b0;
    #0 clken = 1'b1;
    #0 phi = 32'b00011001100110011001100110011010;
    #(14*HALF_CYCLE) reset_n = 1'b1;
  end

always
  begin
    #HALF_CYCLE clk = 1;
    #HALF_CYCLE clk = 0;
  end

integer sin_ch, sin_print;
integer cos_ch, cos_print;
initial
  begin
    sin_ch = $fopen ("fsin_o_ver_lpm_10M_nco.txt");
    cos_ch = $fopen ("fcos_o_ver_lpm_10M_nco.txt");
  end

always @(posedge clk)
  begin
    if(reset_n==1'b1 & out_valid==1'b1)
      begin
        if (sin_val[12:0] < (1<<12))
          sin_print = sin_val[12:0];
        else
          sin_print =  sin_val[12:0] - (1<<13);

      if (cos_val[12:0] < (1<<12))
        cos_print = cos_val[12:0];
      else
        cos_print =  cos_val[12:0] - (1<<13);

    $fdisplay (sin_ch, "%0d", sin_print);
    $fdisplay (cos_ch, "%0d", cos_print);
      end
end

lpm_10M_nco i_lpm_10M_nco (
    .out_valid(out_valid),
    .fsin_o(sin_val[12:0]),
    .fcos_o(cos_val[12:0]),
    .phi_inc_i(phi[31:0]),
    .reset_n(reset_n),
    .clken(clken),
    .clk(clk)
    );

endmodule
