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# EDA Tool  , 1 - Modelsim, 2 - Modelsim-Altera,  3 - NCSim , 4 - VCS, 5 - ActiveHDL
set eda_tool 1

# Testbench simulation files
set testbench_files [glob -nocomplain -- *.hex]

# The top-level in HDL type "Verilog"
set ipfs_ext "vo"
if {[file exists lpm_nco.vo]} {
	set hdl_ext "v"
} else {
	puts "Warning: Could not find lpm_nco.$ipfs_ext!"
}

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "Verilog" -section_id eda_simulation

# Set test bench name
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation


# test bench settings
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME lpm_nco_inst -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME work.lpm_nco_tb -section_id tb

# IPFS file
set_global_assignment -name EDA_IPFS_FILE "lpm_nco.${ipfs_ext}" -section_id eda_simulation -library work

# Add Testbench files
foreach i $testbench_files {
  set_global_assignment -name EDA_TEST_BENCH_FILE "$i" -section_id tb -library work
}

set_global_assignment -name EDA_TEST_BENCH_FILE "lpm_nco_tb.${hdl_ext}" -section_id tb -library work

set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR 22000ns -section_id tb -library work

# Specify testbench mode for nativelink
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation

# Specify active testbench for nativelink
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation




