/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'cpu' in SOPC Builder design 'TR4_HDMI_TX_RX_SOPC'
 * SOPC Builder design path: D:/SVN/tr4/trunk/daughter_card/TR4_HDMI_TX_RX/TR4_HDMI_TX_RX_SOPC.sopcinfo
 *
 * Generated: Wed May 23 18:03:52 CST 2012
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x1040820
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "small"
#define ALT_CPU_DATA_ADDR_WIDTH 0x19
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x1020020
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 1
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INST_ADDR_WIDTH 0x19
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_RESET_ADDR 0x1020000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x1040820
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "small"
#define NIOS2_DATA_ADDR_WIDTH 0x19
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x1020020
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 1
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INST_ADDR_WIDTH 0x19
#define NIOS2_RESET_ADDR 0x1020000


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
#define __ALTERA_NIOS2_QSYS
#define __ALTPLL
#define __TERASIC_I2S_TX


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Stratix IV"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_BASE 0x1041020
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_BASE 0x1041020
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x1041020
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "TR4_HDMI_TX_RX_SOPC"


/*
 * hal configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER
#define ALT_TIMESTAMP_CLK none


/*
 * hdmi_rx0_ep_scl configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx0_ep_scl altera_avalon_pio
#define HDMI_RX0_EP_SCL_BASE 0xe0
#define HDMI_RX0_EP_SCL_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX0_EP_SCL_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX0_EP_SCL_CAPTURE 0
#define HDMI_RX0_EP_SCL_DATA_WIDTH 1
#define HDMI_RX0_EP_SCL_DO_TEST_BENCH_WIRING 0
#define HDMI_RX0_EP_SCL_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX0_EP_SCL_EDGE_TYPE "NONE"
#define HDMI_RX0_EP_SCL_FREQ 10000000u
#define HDMI_RX0_EP_SCL_HAS_IN 0
#define HDMI_RX0_EP_SCL_HAS_OUT 0
#define HDMI_RX0_EP_SCL_HAS_TRI 1
#define HDMI_RX0_EP_SCL_IRQ -1
#define HDMI_RX0_EP_SCL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX0_EP_SCL_IRQ_TYPE "NONE"
#define HDMI_RX0_EP_SCL_NAME "/dev/hdmi_rx0_ep_scl"
#define HDMI_RX0_EP_SCL_RESET_VALUE 0x0
#define HDMI_RX0_EP_SCL_SPAN 16
#define HDMI_RX0_EP_SCL_TYPE "altera_avalon_pio"


/*
 * hdmi_rx0_ep_sda configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx0_ep_sda altera_avalon_pio
#define HDMI_RX0_EP_SDA_BASE 0xf0
#define HDMI_RX0_EP_SDA_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX0_EP_SDA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX0_EP_SDA_CAPTURE 0
#define HDMI_RX0_EP_SDA_DATA_WIDTH 1
#define HDMI_RX0_EP_SDA_DO_TEST_BENCH_WIRING 0
#define HDMI_RX0_EP_SDA_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX0_EP_SDA_EDGE_TYPE "NONE"
#define HDMI_RX0_EP_SDA_FREQ 10000000u
#define HDMI_RX0_EP_SDA_HAS_IN 0
#define HDMI_RX0_EP_SDA_HAS_OUT 0
#define HDMI_RX0_EP_SDA_HAS_TRI 1
#define HDMI_RX0_EP_SDA_IRQ -1
#define HDMI_RX0_EP_SDA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX0_EP_SDA_IRQ_TYPE "NONE"
#define HDMI_RX0_EP_SDA_NAME "/dev/hdmi_rx0_ep_sda"
#define HDMI_RX0_EP_SDA_RESET_VALUE 0x0
#define HDMI_RX0_EP_SDA_SPAN 16
#define HDMI_RX0_EP_SDA_TYPE "altera_avalon_pio"


/*
 * hdmi_rx1_ep_scl configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx1_ep_scl altera_avalon_pio
#define HDMI_RX1_EP_SCL_BASE 0x100
#define HDMI_RX1_EP_SCL_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX1_EP_SCL_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX1_EP_SCL_CAPTURE 0
#define HDMI_RX1_EP_SCL_DATA_WIDTH 1
#define HDMI_RX1_EP_SCL_DO_TEST_BENCH_WIRING 0
#define HDMI_RX1_EP_SCL_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX1_EP_SCL_EDGE_TYPE "NONE"
#define HDMI_RX1_EP_SCL_FREQ 10000000u
#define HDMI_RX1_EP_SCL_HAS_IN 0
#define HDMI_RX1_EP_SCL_HAS_OUT 0
#define HDMI_RX1_EP_SCL_HAS_TRI 1
#define HDMI_RX1_EP_SCL_IRQ -1
#define HDMI_RX1_EP_SCL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX1_EP_SCL_IRQ_TYPE "NONE"
#define HDMI_RX1_EP_SCL_NAME "/dev/hdmi_rx1_ep_scl"
#define HDMI_RX1_EP_SCL_RESET_VALUE 0x0
#define HDMI_RX1_EP_SCL_SPAN 16
#define HDMI_RX1_EP_SCL_TYPE "altera_avalon_pio"


/*
 * hdmi_rx1_ep_sda configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx1_ep_sda altera_avalon_pio
#define HDMI_RX1_EP_SDA_BASE 0x110
#define HDMI_RX1_EP_SDA_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX1_EP_SDA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX1_EP_SDA_CAPTURE 0
#define HDMI_RX1_EP_SDA_DATA_WIDTH 1
#define HDMI_RX1_EP_SDA_DO_TEST_BENCH_WIRING 0
#define HDMI_RX1_EP_SDA_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX1_EP_SDA_EDGE_TYPE "NONE"
#define HDMI_RX1_EP_SDA_FREQ 10000000u
#define HDMI_RX1_EP_SDA_HAS_IN 0
#define HDMI_RX1_EP_SDA_HAS_OUT 0
#define HDMI_RX1_EP_SDA_HAS_TRI 1
#define HDMI_RX1_EP_SDA_IRQ -1
#define HDMI_RX1_EP_SDA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX1_EP_SDA_IRQ_TYPE "NONE"
#define HDMI_RX1_EP_SDA_NAME "/dev/hdmi_rx1_ep_sda"
#define HDMI_RX1_EP_SDA_RESET_VALUE 0x0
#define HDMI_RX1_EP_SDA_SPAN 16
#define HDMI_RX1_EP_SDA_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_cec configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_cec altera_avalon_pio
#define HDMI_RX_CEC_BASE 0xd0
#define HDMI_RX_CEC_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_CEC_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_CEC_CAPTURE 0
#define HDMI_RX_CEC_DATA_WIDTH 2
#define HDMI_RX_CEC_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_CEC_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_CEC_EDGE_TYPE "NONE"
#define HDMI_RX_CEC_FREQ 10000000u
#define HDMI_RX_CEC_HAS_IN 0
#define HDMI_RX_CEC_HAS_OUT 0
#define HDMI_RX_CEC_HAS_TRI 1
#define HDMI_RX_CEC_IRQ -1
#define HDMI_RX_CEC_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_CEC_IRQ_TYPE "NONE"
#define HDMI_RX_CEC_NAME "/dev/hdmi_rx_cec"
#define HDMI_RX_CEC_RESET_VALUE 0x0
#define HDMI_RX_CEC_SPAN 16
#define HDMI_RX_CEC_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_edid_wp configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_edid_wp altera_avalon_pio
#define HDMI_RX_EDID_WP_BASE 0x160
#define HDMI_RX_EDID_WP_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_EDID_WP_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_EDID_WP_CAPTURE 0
#define HDMI_RX_EDID_WP_DATA_WIDTH 1
#define HDMI_RX_EDID_WP_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_EDID_WP_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_EDID_WP_EDGE_TYPE "NONE"
#define HDMI_RX_EDID_WP_FREQ 10000000u
#define HDMI_RX_EDID_WP_HAS_IN 0
#define HDMI_RX_EDID_WP_HAS_OUT 1
#define HDMI_RX_EDID_WP_HAS_TRI 0
#define HDMI_RX_EDID_WP_IRQ -1
#define HDMI_RX_EDID_WP_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_EDID_WP_IRQ_TYPE "NONE"
#define HDMI_RX_EDID_WP_NAME "/dev/hdmi_rx_edid_wp"
#define HDMI_RX_EDID_WP_RESET_VALUE 0x1
#define HDMI_RX_EDID_WP_SPAN 16
#define HDMI_RX_EDID_WP_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_hpd_n configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_hpd_n altera_avalon_pio
#define HDMI_RX_HPD_N_BASE 0xc0
#define HDMI_RX_HPD_N_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_HPD_N_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_HPD_N_CAPTURE 0
#define HDMI_RX_HPD_N_DATA_WIDTH 2
#define HDMI_RX_HPD_N_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_HPD_N_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_HPD_N_EDGE_TYPE "NONE"
#define HDMI_RX_HPD_N_FREQ 10000000u
#define HDMI_RX_HPD_N_HAS_IN 0
#define HDMI_RX_HPD_N_HAS_OUT 1
#define HDMI_RX_HPD_N_HAS_TRI 0
#define HDMI_RX_HPD_N_IRQ -1
#define HDMI_RX_HPD_N_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_HPD_N_IRQ_TYPE "NONE"
#define HDMI_RX_HPD_N_NAME "/dev/hdmi_rx_hpd_n"
#define HDMI_RX_HPD_N_RESET_VALUE 0x0
#define HDMI_RX_HPD_N_SPAN 16
#define HDMI_RX_HPD_N_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_i2c_scl configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_i2c_scl altera_avalon_pio
#define HDMI_RX_I2C_SCL_BASE 0x40
#define HDMI_RX_I2C_SCL_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_I2C_SCL_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_I2C_SCL_CAPTURE 0
#define HDMI_RX_I2C_SCL_DATA_WIDTH 1
#define HDMI_RX_I2C_SCL_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_I2C_SCL_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_I2C_SCL_EDGE_TYPE "NONE"
#define HDMI_RX_I2C_SCL_FREQ 10000000u
#define HDMI_RX_I2C_SCL_HAS_IN 0
#define HDMI_RX_I2C_SCL_HAS_OUT 1
#define HDMI_RX_I2C_SCL_HAS_TRI 0
#define HDMI_RX_I2C_SCL_IRQ -1
#define HDMI_RX_I2C_SCL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_I2C_SCL_IRQ_TYPE "NONE"
#define HDMI_RX_I2C_SCL_NAME "/dev/hdmi_rx_i2c_scl"
#define HDMI_RX_I2C_SCL_RESET_VALUE 0x0
#define HDMI_RX_I2C_SCL_SPAN 16
#define HDMI_RX_I2C_SCL_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_i2c_sda configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_i2c_sda altera_avalon_pio
#define HDMI_RX_I2C_SDA_BASE 0x50
#define HDMI_RX_I2C_SDA_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_I2C_SDA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_I2C_SDA_CAPTURE 0
#define HDMI_RX_I2C_SDA_DATA_WIDTH 1
#define HDMI_RX_I2C_SDA_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_I2C_SDA_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_I2C_SDA_EDGE_TYPE "NONE"
#define HDMI_RX_I2C_SDA_FREQ 10000000u
#define HDMI_RX_I2C_SDA_HAS_IN 0
#define HDMI_RX_I2C_SDA_HAS_OUT 0
#define HDMI_RX_I2C_SDA_HAS_TRI 1
#define HDMI_RX_I2C_SDA_IRQ -1
#define HDMI_RX_I2C_SDA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_I2C_SDA_IRQ_TYPE "NONE"
#define HDMI_RX_I2C_SDA_NAME "/dev/hdmi_rx_i2c_sda"
#define HDMI_RX_I2C_SDA_RESET_VALUE 0x0
#define HDMI_RX_I2C_SDA_SPAN 16
#define HDMI_RX_I2C_SDA_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_irq_n configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_irq_n altera_avalon_pio
#define HDMI_RX_IRQ_N_BASE 0xb0
#define HDMI_RX_IRQ_N_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_IRQ_N_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_IRQ_N_CAPTURE 0
#define HDMI_RX_IRQ_N_DATA_WIDTH 1
#define HDMI_RX_IRQ_N_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_IRQ_N_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_IRQ_N_EDGE_TYPE "NONE"
#define HDMI_RX_IRQ_N_FREQ 10000000u
#define HDMI_RX_IRQ_N_HAS_IN 1
#define HDMI_RX_IRQ_N_HAS_OUT 0
#define HDMI_RX_IRQ_N_HAS_TRI 0
#define HDMI_RX_IRQ_N_IRQ -1
#define HDMI_RX_IRQ_N_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_IRQ_N_IRQ_TYPE "NONE"
#define HDMI_RX_IRQ_N_NAME "/dev/hdmi_rx_irq_n"
#define HDMI_RX_IRQ_N_RESET_VALUE 0x0
#define HDMI_RX_IRQ_N_SPAN 16
#define HDMI_RX_IRQ_N_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_reset_n configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_reset_n altera_avalon_pio
#define HDMI_RX_RESET_N_BASE 0x80
#define HDMI_RX_RESET_N_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_RESET_N_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_RESET_N_CAPTURE 0
#define HDMI_RX_RESET_N_DATA_WIDTH 1
#define HDMI_RX_RESET_N_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_RESET_N_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_RESET_N_EDGE_TYPE "NONE"
#define HDMI_RX_RESET_N_FREQ 10000000u
#define HDMI_RX_RESET_N_HAS_IN 0
#define HDMI_RX_RESET_N_HAS_OUT 1
#define HDMI_RX_RESET_N_HAS_TRI 0
#define HDMI_RX_RESET_N_IRQ -1
#define HDMI_RX_RESET_N_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_RESET_N_IRQ_TYPE "NONE"
#define HDMI_RX_RESET_N_NAME "/dev/hdmi_rx_reset_n"
#define HDMI_RX_RESET_N_RESET_VALUE 0x0
#define HDMI_RX_RESET_N_SPAN 16
#define HDMI_RX_RESET_N_TYPE "altera_avalon_pio"


/*
 * hdmi_rx_sync configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_rx_sync altera_avalon_pio
#define HDMI_RX_SYNC_BASE 0x120
#define HDMI_RX_SYNC_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_RX_SYNC_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_RX_SYNC_CAPTURE 0
#define HDMI_RX_SYNC_DATA_WIDTH 1
#define HDMI_RX_SYNC_DO_TEST_BENCH_WIRING 0
#define HDMI_RX_SYNC_DRIVEN_SIM_VALUE 0x0
#define HDMI_RX_SYNC_EDGE_TYPE "NONE"
#define HDMI_RX_SYNC_FREQ 10000000u
#define HDMI_RX_SYNC_HAS_IN 0
#define HDMI_RX_SYNC_HAS_OUT 1
#define HDMI_RX_SYNC_HAS_TRI 0
#define HDMI_RX_SYNC_IRQ -1
#define HDMI_RX_SYNC_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_RX_SYNC_IRQ_TYPE "NONE"
#define HDMI_RX_SYNC_NAME "/dev/hdmi_rx_sync"
#define HDMI_RX_SYNC_RESET_VALUE 0x0
#define HDMI_RX_SYNC_SPAN 16
#define HDMI_RX_SYNC_TYPE "altera_avalon_pio"


/*
 * hdmi_tx_disp_mode configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_tx_disp_mode altera_avalon_pio
#define HDMI_TX_DISP_MODE_BASE 0x130
#define HDMI_TX_DISP_MODE_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_TX_DISP_MODE_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_TX_DISP_MODE_CAPTURE 0
#define HDMI_TX_DISP_MODE_DATA_WIDTH 4
#define HDMI_TX_DISP_MODE_DO_TEST_BENCH_WIRING 0
#define HDMI_TX_DISP_MODE_DRIVEN_SIM_VALUE 0x0
#define HDMI_TX_DISP_MODE_EDGE_TYPE "NONE"
#define HDMI_TX_DISP_MODE_FREQ 10000000u
#define HDMI_TX_DISP_MODE_HAS_IN 0
#define HDMI_TX_DISP_MODE_HAS_OUT 1
#define HDMI_TX_DISP_MODE_HAS_TRI 0
#define HDMI_TX_DISP_MODE_IRQ -1
#define HDMI_TX_DISP_MODE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_TX_DISP_MODE_IRQ_TYPE "NONE"
#define HDMI_TX_DISP_MODE_NAME "/dev/hdmi_tx_disp_mode"
#define HDMI_TX_DISP_MODE_RESET_VALUE 0x0
#define HDMI_TX_DISP_MODE_SPAN 16
#define HDMI_TX_DISP_MODE_TYPE "altera_avalon_pio"


/*
 * hdmi_tx_i2c_scl configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_tx_i2c_scl altera_avalon_pio
#define HDMI_TX_I2C_SCL_BASE 0x20
#define HDMI_TX_I2C_SCL_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_TX_I2C_SCL_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_TX_I2C_SCL_CAPTURE 0
#define HDMI_TX_I2C_SCL_DATA_WIDTH 1
#define HDMI_TX_I2C_SCL_DO_TEST_BENCH_WIRING 0
#define HDMI_TX_I2C_SCL_DRIVEN_SIM_VALUE 0x0
#define HDMI_TX_I2C_SCL_EDGE_TYPE "NONE"
#define HDMI_TX_I2C_SCL_FREQ 10000000u
#define HDMI_TX_I2C_SCL_HAS_IN 0
#define HDMI_TX_I2C_SCL_HAS_OUT 1
#define HDMI_TX_I2C_SCL_HAS_TRI 0
#define HDMI_TX_I2C_SCL_IRQ -1
#define HDMI_TX_I2C_SCL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_TX_I2C_SCL_IRQ_TYPE "NONE"
#define HDMI_TX_I2C_SCL_NAME "/dev/hdmi_tx_i2c_scl"
#define HDMI_TX_I2C_SCL_RESET_VALUE 0x0
#define HDMI_TX_I2C_SCL_SPAN 16
#define HDMI_TX_I2C_SCL_TYPE "altera_avalon_pio"


/*
 * hdmi_tx_i2c_sda configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_tx_i2c_sda altera_avalon_pio
#define HDMI_TX_I2C_SDA_BASE 0x30
#define HDMI_TX_I2C_SDA_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_TX_I2C_SDA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_TX_I2C_SDA_CAPTURE 0
#define HDMI_TX_I2C_SDA_DATA_WIDTH 1
#define HDMI_TX_I2C_SDA_DO_TEST_BENCH_WIRING 0
#define HDMI_TX_I2C_SDA_DRIVEN_SIM_VALUE 0x0
#define HDMI_TX_I2C_SDA_EDGE_TYPE "NONE"
#define HDMI_TX_I2C_SDA_FREQ 10000000u
#define HDMI_TX_I2C_SDA_HAS_IN 0
#define HDMI_TX_I2C_SDA_HAS_OUT 0
#define HDMI_TX_I2C_SDA_HAS_TRI 1
#define HDMI_TX_I2C_SDA_IRQ -1
#define HDMI_TX_I2C_SDA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_TX_I2C_SDA_IRQ_TYPE "NONE"
#define HDMI_TX_I2C_SDA_NAME "/dev/hdmi_tx_i2c_sda"
#define HDMI_TX_I2C_SDA_RESET_VALUE 0x0
#define HDMI_TX_I2C_SDA_SPAN 16
#define HDMI_TX_I2C_SDA_TYPE "altera_avalon_pio"


/*
 * hdmi_tx_irq_n configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_tx_irq_n altera_avalon_pio
#define HDMI_TX_IRQ_N_BASE 0x70
#define HDMI_TX_IRQ_N_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_TX_IRQ_N_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_TX_IRQ_N_CAPTURE 1
#define HDMI_TX_IRQ_N_DATA_WIDTH 1
#define HDMI_TX_IRQ_N_DO_TEST_BENCH_WIRING 0
#define HDMI_TX_IRQ_N_DRIVEN_SIM_VALUE 0x0
#define HDMI_TX_IRQ_N_EDGE_TYPE "FALLING"
#define HDMI_TX_IRQ_N_FREQ 10000000u
#define HDMI_TX_IRQ_N_HAS_IN 1
#define HDMI_TX_IRQ_N_HAS_OUT 0
#define HDMI_TX_IRQ_N_HAS_TRI 0
#define HDMI_TX_IRQ_N_IRQ 3
#define HDMI_TX_IRQ_N_IRQ_INTERRUPT_CONTROLLER_ID 0
#define HDMI_TX_IRQ_N_IRQ_TYPE "EDGE"
#define HDMI_TX_IRQ_N_NAME "/dev/hdmi_tx_irq_n"
#define HDMI_TX_IRQ_N_RESET_VALUE 0x0
#define HDMI_TX_IRQ_N_SPAN 16
#define HDMI_TX_IRQ_N_TYPE "altera_avalon_pio"


/*
 * hdmi_tx_mode_change configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_tx_mode_change altera_avalon_pio
#define HDMI_TX_MODE_CHANGE_BASE 0x140
#define HDMI_TX_MODE_CHANGE_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_TX_MODE_CHANGE_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_TX_MODE_CHANGE_CAPTURE 0
#define HDMI_TX_MODE_CHANGE_DATA_WIDTH 1
#define HDMI_TX_MODE_CHANGE_DO_TEST_BENCH_WIRING 0
#define HDMI_TX_MODE_CHANGE_DRIVEN_SIM_VALUE 0x0
#define HDMI_TX_MODE_CHANGE_EDGE_TYPE "NONE"
#define HDMI_TX_MODE_CHANGE_FREQ 10000000u
#define HDMI_TX_MODE_CHANGE_HAS_IN 0
#define HDMI_TX_MODE_CHANGE_HAS_OUT 1
#define HDMI_TX_MODE_CHANGE_HAS_TRI 0
#define HDMI_TX_MODE_CHANGE_IRQ -1
#define HDMI_TX_MODE_CHANGE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_TX_MODE_CHANGE_IRQ_TYPE "NONE"
#define HDMI_TX_MODE_CHANGE_NAME "/dev/hdmi_tx_mode_change"
#define HDMI_TX_MODE_CHANGE_RESET_VALUE 0x0
#define HDMI_TX_MODE_CHANGE_SPAN 16
#define HDMI_TX_MODE_CHANGE_TYPE "altera_avalon_pio"


/*
 * hdmi_tx_reset_n configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_tx_reset_n altera_avalon_pio
#define HDMI_TX_RESET_N_BASE 0x60
#define HDMI_TX_RESET_N_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_TX_RESET_N_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_TX_RESET_N_CAPTURE 0
#define HDMI_TX_RESET_N_DATA_WIDTH 1
#define HDMI_TX_RESET_N_DO_TEST_BENCH_WIRING 0
#define HDMI_TX_RESET_N_DRIVEN_SIM_VALUE 0x0
#define HDMI_TX_RESET_N_EDGE_TYPE "NONE"
#define HDMI_TX_RESET_N_FREQ 10000000u
#define HDMI_TX_RESET_N_HAS_IN 0
#define HDMI_TX_RESET_N_HAS_OUT 1
#define HDMI_TX_RESET_N_HAS_TRI 0
#define HDMI_TX_RESET_N_IRQ -1
#define HDMI_TX_RESET_N_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_TX_RESET_N_IRQ_TYPE "NONE"
#define HDMI_TX_RESET_N_NAME "/dev/hdmi_tx_reset_n"
#define HDMI_TX_RESET_N_RESET_VALUE 0x0
#define HDMI_TX_RESET_N_SPAN 16
#define HDMI_TX_RESET_N_TYPE "altera_avalon_pio"


/*
 * hdmi_tx_vpg_color configuration
 *
 */

#define ALT_MODULE_CLASS_hdmi_tx_vpg_color altera_avalon_pio
#define HDMI_TX_VPG_COLOR_BASE 0x150
#define HDMI_TX_VPG_COLOR_BIT_CLEARING_EDGE_REGISTER 0
#define HDMI_TX_VPG_COLOR_BIT_MODIFYING_OUTPUT_REGISTER 0
#define HDMI_TX_VPG_COLOR_CAPTURE 0
#define HDMI_TX_VPG_COLOR_DATA_WIDTH 2
#define HDMI_TX_VPG_COLOR_DO_TEST_BENCH_WIRING 0
#define HDMI_TX_VPG_COLOR_DRIVEN_SIM_VALUE 0x0
#define HDMI_TX_VPG_COLOR_EDGE_TYPE "NONE"
#define HDMI_TX_VPG_COLOR_FREQ 10000000u
#define HDMI_TX_VPG_COLOR_HAS_IN 0
#define HDMI_TX_VPG_COLOR_HAS_OUT 1
#define HDMI_TX_VPG_COLOR_HAS_TRI 0
#define HDMI_TX_VPG_COLOR_IRQ -1
#define HDMI_TX_VPG_COLOR_IRQ_INTERRUPT_CONTROLLER_ID -1
#define HDMI_TX_VPG_COLOR_IRQ_TYPE "NONE"
#define HDMI_TX_VPG_COLOR_NAME "/dev/hdmi_tx_vpg_color"
#define HDMI_TX_VPG_COLOR_RESET_VALUE 0x0
#define HDMI_TX_VPG_COLOR_SPAN 16
#define HDMI_TX_VPG_COLOR_TYPE "altera_avalon_pio"


/*
 * i2s_tx configuration
 *
 */

#define ALT_MODULE_CLASS_i2s_tx terasic_i2s_tx
#define I2S_TX_BASE 0x1041010
#define I2S_TX_IRQ 1
#define I2S_TX_IRQ_INTERRUPT_CONTROLLER_ID 0
#define I2S_TX_NAME "/dev/i2s_tx"
#define I2S_TX_SPAN 16
#define I2S_TX_TYPE "terasic_i2s_tx"


/*
 * jtag_uart configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x1041020
#define JTAG_UART_IRQ 0
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_SPAN 8
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8


/*
 * onchip_memory2 configuration
 *
 */

#define ALT_MODULE_CLASS_onchip_memory2 altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_BASE 0x1020000
#define ONCHIP_MEMORY2_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_DUAL_PORT 0
#define ONCHIP_MEMORY2_GUI_RAM_BLOCK_TYPE "Automatic"
#define ONCHIP_MEMORY2_INIT_CONTENTS_FILE "onchip_memory2"
#define ONCHIP_MEMORY2_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY2_INSTANCE_ID "NONE"
#define ONCHIP_MEMORY2_IRQ -1
#define ONCHIP_MEMORY2_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_MEMORY2_NAME "/dev/onchip_memory2"
#define ONCHIP_MEMORY2_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY2_RAM_BLOCK_TYPE "Auto"
#define ONCHIP_MEMORY2_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY2_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_SIZE_VALUE 131072u
#define ONCHIP_MEMORY2_SPAN 131072
#define ONCHIP_MEMORY2_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY2_WRITABLE 1


/*
 * pio_button configuration
 *
 */

#define ALT_MODULE_CLASS_pio_button altera_avalon_pio
#define PIO_BUTTON_BASE 0xa0
#define PIO_BUTTON_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_BUTTON_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_BUTTON_CAPTURE 1
#define PIO_BUTTON_DATA_WIDTH 2
#define PIO_BUTTON_DO_TEST_BENCH_WIRING 0
#define PIO_BUTTON_DRIVEN_SIM_VALUE 0x0
#define PIO_BUTTON_EDGE_TYPE "FALLING"
#define PIO_BUTTON_FREQ 10000000u
#define PIO_BUTTON_HAS_IN 1
#define PIO_BUTTON_HAS_OUT 0
#define PIO_BUTTON_HAS_TRI 0
#define PIO_BUTTON_IRQ 4
#define PIO_BUTTON_IRQ_INTERRUPT_CONTROLLER_ID 0
#define PIO_BUTTON_IRQ_TYPE "EDGE"
#define PIO_BUTTON_NAME "/dev/pio_button"
#define PIO_BUTTON_RESET_VALUE 0x0
#define PIO_BUTTON_SPAN 16
#define PIO_BUTTON_TYPE "altera_avalon_pio"


/*
 * pio_led configuration
 *
 */

#define ALT_MODULE_CLASS_pio_led altera_avalon_pio
#define PIO_LED_BASE 0x90
#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_LED_CAPTURE 0
#define PIO_LED_DATA_WIDTH 4
#define PIO_LED_DO_TEST_BENCH_WIRING 0
#define PIO_LED_DRIVEN_SIM_VALUE 0x0
#define PIO_LED_EDGE_TYPE "NONE"
#define PIO_LED_FREQ 10000000u
#define PIO_LED_HAS_IN 0
#define PIO_LED_HAS_OUT 1
#define PIO_LED_HAS_TRI 0
#define PIO_LED_IRQ -1
#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PIO_LED_IRQ_TYPE "NONE"
#define PIO_LED_NAME "/dev/pio_led"
#define PIO_LED_RESET_VALUE 0x0
#define PIO_LED_SPAN 16
#define PIO_LED_TYPE "altera_avalon_pio"


/*
 * pll configuration
 *
 */

#define ALT_MODULE_CLASS_pll altpll
#define PLL_BASE 0x1041000
#define PLL_IRQ -1
#define PLL_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PLL_NAME "/dev/pll"
#define PLL_SPAN 16
#define PLL_TYPE "altpll"


/*
 * sysid configuration
 *
 */

#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys
#define SYSID_BASE 0x170
#define SYSID_ID 0
#define SYSID_IRQ -1
#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_NAME "/dev/sysid"
#define SYSID_SPAN 8
#define SYSID_TIMESTAMP 1324469509
#define SYSID_TYPE "altera_avalon_sysid_qsys"


/*
 * timer configuration
 *
 */

#define ALT_MODULE_CLASS_timer altera_avalon_timer
#define TIMER_ALWAYS_RUN 0
#define TIMER_BASE 0x0
#define TIMER_COUNTER_SIZE 32
#define TIMER_FIXED_PERIOD 0
#define TIMER_FREQ 10000000u
#define TIMER_IRQ 2
#define TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_LOAD_VALUE 9999ull
#define TIMER_MULT 0.0010
#define TIMER_NAME "/dev/timer"
#define TIMER_PERIOD 1
#define TIMER_PERIOD_UNITS "ms"
#define TIMER_RESET_OUTPUT 0
#define TIMER_SNAPSHOT 1
#define TIMER_SPAN 32
#define TIMER_TICKS_PER_SEC 1000u
#define TIMER_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_TYPE "altera_avalon_timer"

#endif /* __SYSTEM_H_ */
