// TR4_HDMI_TX_RX_SOPC.v


`timescale 1 ps / 1 ps
module TR4_HDMI_TX_RX_SOPC (
		output wire       pll_io,                                     //                              c1_out_clk.clk
		inout  wire       bidir_port_to_and_from_the_hdmi_rx1_ep_sda, //     hdmi_rx1_ep_sda_external_connection.export
		input  wire       areset_to_the_pll,                          //                      pll_areset_conduit.export
		inout  wire       bidir_port_to_and_from_the_hdmi_rx_i2c_sda, //     hdmi_rx_i2c_sda_external_connection.export
		output wire       out_port_from_the_hdmi_tx_mode_change,      // hdmi_tx_mode_change_external_connection.export
		output wire       out_port_from_the_hdmi_rx_edid_wp,          //     hdmi_rx_edid_wp_external_connection.export
		output wire [3:0] out_port_from_the_hdmi_tx_disp_mode,        //   hdmi_tx_disp_mode_external_connection.export
		input  wire [1:0] in_port_to_the_pio_button,                  //          pio_button_external_connection.export
		output wire [3:0] out_port_from_the_pio_led,                  //             pio_led_external_connection.export
		output wire       phasedone_from_the_pll,                     //                   pll_phasedone_conduit.export
		output wire       pll_cpu,                                    //                              c0_out_clk.clk
		inout  wire       bidir_port_to_and_from_the_hdmi_rx0_ep_scl, //     hdmi_rx0_ep_scl_external_connection.export
		output wire       out_port_from_the_hdmi_rx_sync,             //        hdmi_rx_sync_external_connection.export
		output wire [1:0] out_port_from_the_hdmi_tx_vpg_color,        //   hdmi_tx_vpg_color_external_connection.export
		output wire [1:0] out_port_from_the_hdmi_rx_hpd_n,            //       hdmi_rx_hpd_n_external_connection.export
		input  wire       clk,                                        //                              clk_clk_in.clk
		output wire       out_port_from_the_hdmi_tx_i2c_scl,          //     hdmi_tx_i2c_scl_external_connection.export
		input  wire       reset_n,                                    //                        clk_clk_in_reset.reset_n
		output wire       out_port_from_the_hdmi_rx_reset_n,          //     hdmi_rx_reset_n_external_connection.export
		input  wire       in_port_to_the_hdmi_tx_irq_n,               //       hdmi_tx_irq_n_external_connection.export
		output wire       out_port_from_the_hdmi_tx_reset_n,          //     hdmi_tx_reset_n_external_connection.export
		inout  wire       bidir_port_to_and_from_the_hdmi_tx_i2c_sda, //     hdmi_tx_i2c_sda_external_connection.export
		output wire       locked_from_the_pll,                        //                      pll_locked_conduit.export
		output wire       out_port_from_the_hdmi_rx_i2c_scl,          //     hdmi_rx_i2c_scl_external_connection.export
		inout  wire       bidir_port_to_and_from_the_hdmi_rx0_ep_sda, //     hdmi_rx0_ep_sda_external_connection.export
		output wire       i2s_ws_from_the_i2s_tx,                     //                      i2s_tx_conduit_end.ws
		input  wire       i2s_sck_to_the_i2s_tx,                      //                                        .sck
		output wire       i2s_sd_from_the_i2s_tx,                     //                                        .sd
		inout  wire       bidir_port_to_and_from_the_hdmi_rx1_ep_scl, //     hdmi_rx1_ep_scl_external_connection.export
		inout  wire [1:0] bidir_port_to_and_from_the_hdmi_rx_cec,     //         hdmi_rx_cec_external_connection.export
		input  wire       in_port_to_the_hdmi_rx_irq_n                //       hdmi_rx_irq_n_external_connection.export
	);

	wire         cpu_instruction_master_waitrequest;                                                               // cpu_instruction_master_translator:av_waitrequest -> cpu:i_waitrequest
	wire  [24:0] cpu_instruction_master_address;                                                                   // cpu:i_address -> cpu_instruction_master_translator:av_address
	wire         cpu_instruction_master_read;                                                                      // cpu:i_read -> cpu_instruction_master_translator:av_read
	wire  [31:0] cpu_instruction_master_readdata;                                                                  // cpu_instruction_master_translator:av_readdata -> cpu:i_readdata
	wire         cpu_instruction_master_readdatavalid;                                                             // cpu_instruction_master_translator:av_readdatavalid -> cpu:i_readdatavalid
	wire         cpu_data_master_waitrequest;                                                                      // cpu_data_master_translator:av_waitrequest -> cpu:d_waitrequest
	wire  [31:0] cpu_data_master_writedata;                                                                        // cpu:d_writedata -> cpu_data_master_translator:av_writedata
	wire  [24:0] cpu_data_master_address;                                                                          // cpu:d_address -> cpu_data_master_translator:av_address
	wire         cpu_data_master_write;                                                                            // cpu:d_write -> cpu_data_master_translator:av_write
	wire         cpu_data_master_read;                                                                             // cpu:d_read -> cpu_data_master_translator:av_read
	wire  [31:0] cpu_data_master_readdata;                                                                         // cpu_data_master_translator:av_readdata -> cpu:d_readdata
	wire         cpu_data_master_debugaccess;                                                                      // cpu:jtag_debug_module_debugaccess_to_roms -> cpu_data_master_translator:av_debugaccess
	wire   [3:0] cpu_data_master_byteenable;                                                                       // cpu:d_byteenable -> cpu_data_master_translator:av_byteenable
	wire  [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata;                                   // cpu_jtag_debug_module_translator:av_writedata -> cpu:jtag_debug_module_writedata
	wire   [8:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_address;                                     // cpu_jtag_debug_module_translator:av_address -> cpu:jtag_debug_module_address
	wire         cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect;                                  // cpu_jtag_debug_module_translator:av_chipselect -> cpu:jtag_debug_module_select
	wire         cpu_jtag_debug_module_translator_avalon_anti_slave_0_write;                                       // cpu_jtag_debug_module_translator:av_write -> cpu:jtag_debug_module_write
	wire  [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata;                                    // cpu:jtag_debug_module_readdata -> cpu_jtag_debug_module_translator:av_readdata
	wire         cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer;                               // cpu_jtag_debug_module_translator:av_begintransfer -> cpu:jtag_debug_module_begintransfer
	wire         cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess;                                 // cpu_jtag_debug_module_translator:av_debugaccess -> cpu:jtag_debug_module_debugaccess
	wire   [3:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable;                                  // cpu_jtag_debug_module_translator:av_byteenable -> cpu:jtag_debug_module_byteenable
	wire  [31:0] onchip_memory2_s1_translator_avalon_anti_slave_0_writedata;                                       // onchip_memory2_s1_translator:av_writedata -> onchip_memory2:writedata
	wire  [14:0] onchip_memory2_s1_translator_avalon_anti_slave_0_address;                                         // onchip_memory2_s1_translator:av_address -> onchip_memory2:address
	wire         onchip_memory2_s1_translator_avalon_anti_slave_0_chipselect;                                      // onchip_memory2_s1_translator:av_chipselect -> onchip_memory2:chipselect
	wire         onchip_memory2_s1_translator_avalon_anti_slave_0_clken;                                           // onchip_memory2_s1_translator:av_clken -> onchip_memory2:clken
	wire         onchip_memory2_s1_translator_avalon_anti_slave_0_write;                                           // onchip_memory2_s1_translator:av_write -> onchip_memory2:write
	wire  [31:0] onchip_memory2_s1_translator_avalon_anti_slave_0_readdata;                                        // onchip_memory2:readdata -> onchip_memory2_s1_translator:av_readdata
	wire   [3:0] onchip_memory2_s1_translator_avalon_anti_slave_0_byteenable;                                      // onchip_memory2_s1_translator:av_byteenable -> onchip_memory2:byteenable
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest;                           // jtag_uart:av_waitrequest -> jtag_uart_avalon_jtag_slave_translator:av_waitrequest
	wire  [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata;                             // jtag_uart_avalon_jtag_slave_translator:av_writedata -> jtag_uart:av_writedata
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address;                               // jtag_uart_avalon_jtag_slave_translator:av_address -> jtag_uart:av_address
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect;                            // jtag_uart_avalon_jtag_slave_translator:av_chipselect -> jtag_uart:av_chipselect
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write;                                 // jtag_uart_avalon_jtag_slave_translator:av_write -> jtag_uart:av_write_n
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read;                                  // jtag_uart_avalon_jtag_slave_translator:av_read -> jtag_uart:av_read_n
	wire  [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata;                              // jtag_uart:av_readdata -> jtag_uart_avalon_jtag_slave_translator:av_readdata
	wire  [31:0] pll_pll_slave_translator_avalon_anti_slave_0_writedata;                                           // pll_pll_slave_translator:av_writedata -> pll:writedata
	wire   [1:0] pll_pll_slave_translator_avalon_anti_slave_0_address;                                             // pll_pll_slave_translator:av_address -> pll:address
	wire         pll_pll_slave_translator_avalon_anti_slave_0_write;                                               // pll_pll_slave_translator:av_write -> pll:write
	wire         pll_pll_slave_translator_avalon_anti_slave_0_read;                                                // pll_pll_slave_translator:av_read -> pll:read
	wire  [31:0] pll_pll_slave_translator_avalon_anti_slave_0_readdata;                                            // pll:readdata -> pll_pll_slave_translator:av_readdata
	wire  [31:0] i2s_tx_slave_translator_avalon_anti_slave_0_writedata;                                            // i2s_tx_slave_translator:av_writedata -> i2s_tx:s_writedata
	wire   [1:0] i2s_tx_slave_translator_avalon_anti_slave_0_address;                                              // i2s_tx_slave_translator:av_address -> i2s_tx:s_address
	wire         i2s_tx_slave_translator_avalon_anti_slave_0_chipselect;                                           // i2s_tx_slave_translator:av_chipselect -> i2s_tx:s_chipselect
	wire         i2s_tx_slave_translator_avalon_anti_slave_0_write;                                                // i2s_tx_slave_translator:av_write -> i2s_tx:s_write
	wire         i2s_tx_slave_translator_avalon_anti_slave_0_read;                                                 // i2s_tx_slave_translator:av_read -> i2s_tx:s_read
	wire  [31:0] i2s_tx_slave_translator_avalon_anti_slave_0_readdata;                                             // i2s_tx:s_readdata -> i2s_tx_slave_translator:av_readdata
	wire         clock_crossing_bridge_s0_translator_avalon_anti_slave_0_waitrequest;                              // clock_crossing_bridge:s0_waitrequest -> clock_crossing_bridge_s0_translator:av_waitrequest
	wire         clock_crossing_bridge_s0_translator_avalon_anti_slave_0_burstcount;                               // clock_crossing_bridge_s0_translator:av_burstcount -> clock_crossing_bridge:s0_burstcount
	wire  [31:0] clock_crossing_bridge_s0_translator_avalon_anti_slave_0_writedata;                                // clock_crossing_bridge_s0_translator:av_writedata -> clock_crossing_bridge:s0_writedata
	wire   [8:0] clock_crossing_bridge_s0_translator_avalon_anti_slave_0_address;                                  // clock_crossing_bridge_s0_translator:av_address -> clock_crossing_bridge:s0_address
	wire         clock_crossing_bridge_s0_translator_avalon_anti_slave_0_write;                                    // clock_crossing_bridge_s0_translator:av_write -> clock_crossing_bridge:s0_write
	wire         clock_crossing_bridge_s0_translator_avalon_anti_slave_0_read;                                     // clock_crossing_bridge_s0_translator:av_read -> clock_crossing_bridge:s0_read
	wire  [31:0] clock_crossing_bridge_s0_translator_avalon_anti_slave_0_readdata;                                 // clock_crossing_bridge:s0_readdata -> clock_crossing_bridge_s0_translator:av_readdata
	wire         clock_crossing_bridge_s0_translator_avalon_anti_slave_0_debugaccess;                              // clock_crossing_bridge_s0_translator:av_debugaccess -> clock_crossing_bridge:s0_debugaccess
	wire         clock_crossing_bridge_s0_translator_avalon_anti_slave_0_readdatavalid;                            // clock_crossing_bridge:s0_readdatavalid -> clock_crossing_bridge_s0_translator:av_readdatavalid
	wire   [3:0] clock_crossing_bridge_s0_translator_avalon_anti_slave_0_byteenable;                               // clock_crossing_bridge_s0_translator:av_byteenable -> clock_crossing_bridge:s0_byteenable
	wire   [0:0] clock_crossing_bridge_m0_burstcount;                                                              // clock_crossing_bridge:m0_burstcount -> clock_crossing_bridge_m0_translator:av_burstcount
	wire         clock_crossing_bridge_m0_waitrequest;                                                             // clock_crossing_bridge_m0_translator:av_waitrequest -> clock_crossing_bridge:m0_waitrequest
	wire   [8:0] clock_crossing_bridge_m0_address;                                                                 // clock_crossing_bridge:m0_address -> clock_crossing_bridge_m0_translator:av_address
	wire  [31:0] clock_crossing_bridge_m0_writedata;                                                               // clock_crossing_bridge:m0_writedata -> clock_crossing_bridge_m0_translator:av_writedata
	wire         clock_crossing_bridge_m0_write;                                                                   // clock_crossing_bridge:m0_write -> clock_crossing_bridge_m0_translator:av_write
	wire         clock_crossing_bridge_m0_read;                                                                    // clock_crossing_bridge:m0_read -> clock_crossing_bridge_m0_translator:av_read
	wire  [31:0] clock_crossing_bridge_m0_readdata;                                                                // clock_crossing_bridge_m0_translator:av_readdata -> clock_crossing_bridge:m0_readdata
	wire         clock_crossing_bridge_m0_debugaccess;                                                             // clock_crossing_bridge:m0_debugaccess -> clock_crossing_bridge_m0_translator:av_debugaccess
	wire   [3:0] clock_crossing_bridge_m0_byteenable;                                                              // clock_crossing_bridge:m0_byteenable -> clock_crossing_bridge_m0_translator:av_byteenable
	wire         clock_crossing_bridge_m0_readdatavalid;                                                           // clock_crossing_bridge_m0_translator:av_readdatavalid -> clock_crossing_bridge:m0_readdatavalid
	wire  [15:0] timer_s1_translator_avalon_anti_slave_0_writedata;                                                // timer_s1_translator:av_writedata -> timer:writedata
	wire   [2:0] timer_s1_translator_avalon_anti_slave_0_address;                                                  // timer_s1_translator:av_address -> timer:address
	wire         timer_s1_translator_avalon_anti_slave_0_chipselect;                                               // timer_s1_translator:av_chipselect -> timer:chipselect
	wire         timer_s1_translator_avalon_anti_slave_0_write;                                                    // timer_s1_translator:av_write -> timer:write_n
	wire  [15:0] timer_s1_translator_avalon_anti_slave_0_readdata;                                                 // timer:readdata -> timer_s1_translator:av_readdata
	wire  [31:0] hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_tx_i2c_scl_s1_translator:av_writedata -> hdmi_tx_i2c_scl:writedata
	wire   [1:0] hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_tx_i2c_scl_s1_translator:av_address -> hdmi_tx_i2c_scl:address
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_tx_i2c_scl_s1_translator:av_chipselect -> hdmi_tx_i2c_scl:chipselect
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_tx_i2c_scl_s1_translator:av_write -> hdmi_tx_i2c_scl:write_n
	wire  [31:0] hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_tx_i2c_scl:readdata -> hdmi_tx_i2c_scl_s1_translator:av_readdata
	wire  [31:0] hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_tx_i2c_sda_s1_translator:av_writedata -> hdmi_tx_i2c_sda:writedata
	wire   [1:0] hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_tx_i2c_sda_s1_translator:av_address -> hdmi_tx_i2c_sda:address
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_tx_i2c_sda_s1_translator:av_chipselect -> hdmi_tx_i2c_sda:chipselect
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_tx_i2c_sda_s1_translator:av_write -> hdmi_tx_i2c_sda:write_n
	wire  [31:0] hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_tx_i2c_sda:readdata -> hdmi_tx_i2c_sda_s1_translator:av_readdata
	wire  [31:0] hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx_i2c_scl_s1_translator:av_writedata -> hdmi_rx_i2c_scl:writedata
	wire   [1:0] hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx_i2c_scl_s1_translator:av_address -> hdmi_rx_i2c_scl:address
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx_i2c_scl_s1_translator:av_chipselect -> hdmi_rx_i2c_scl:chipselect
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx_i2c_scl_s1_translator:av_write -> hdmi_rx_i2c_scl:write_n
	wire  [31:0] hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx_i2c_scl:readdata -> hdmi_rx_i2c_scl_s1_translator:av_readdata
	wire  [31:0] hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx_i2c_sda_s1_translator:av_writedata -> hdmi_rx_i2c_sda:writedata
	wire   [1:0] hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx_i2c_sda_s1_translator:av_address -> hdmi_rx_i2c_sda:address
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx_i2c_sda_s1_translator:av_chipselect -> hdmi_rx_i2c_sda:chipselect
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx_i2c_sda_s1_translator:av_write -> hdmi_rx_i2c_sda:write_n
	wire  [31:0] hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx_i2c_sda:readdata -> hdmi_rx_i2c_sda_s1_translator:av_readdata
	wire  [31:0] hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_tx_reset_n_s1_translator:av_writedata -> hdmi_tx_reset_n:writedata
	wire   [1:0] hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_tx_reset_n_s1_translator:av_address -> hdmi_tx_reset_n:address
	wire         hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_tx_reset_n_s1_translator:av_chipselect -> hdmi_tx_reset_n:chipselect
	wire         hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_tx_reset_n_s1_translator:av_write -> hdmi_tx_reset_n:write_n
	wire  [31:0] hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_tx_reset_n:readdata -> hdmi_tx_reset_n_s1_translator:av_readdata
	wire  [31:0] hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_writedata;                                        // hdmi_tx_irq_n_s1_translator:av_writedata -> hdmi_tx_irq_n:writedata
	wire   [1:0] hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_address;                                          // hdmi_tx_irq_n_s1_translator:av_address -> hdmi_tx_irq_n:address
	wire         hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_chipselect;                                       // hdmi_tx_irq_n_s1_translator:av_chipselect -> hdmi_tx_irq_n:chipselect
	wire         hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_write;                                            // hdmi_tx_irq_n_s1_translator:av_write -> hdmi_tx_irq_n:write_n
	wire  [31:0] hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_readdata;                                         // hdmi_tx_irq_n:readdata -> hdmi_tx_irq_n_s1_translator:av_readdata
	wire  [31:0] hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx_reset_n_s1_translator:av_writedata -> hdmi_rx_reset_n:writedata
	wire   [1:0] hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx_reset_n_s1_translator:av_address -> hdmi_rx_reset_n:address
	wire         hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx_reset_n_s1_translator:av_chipselect -> hdmi_rx_reset_n:chipselect
	wire         hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx_reset_n_s1_translator:av_write -> hdmi_rx_reset_n:write_n
	wire  [31:0] hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx_reset_n:readdata -> hdmi_rx_reset_n_s1_translator:av_readdata
	wire  [31:0] pio_led_s1_translator_avalon_anti_slave_0_writedata;                                              // pio_led_s1_translator:av_writedata -> pio_led:writedata
	wire   [1:0] pio_led_s1_translator_avalon_anti_slave_0_address;                                                // pio_led_s1_translator:av_address -> pio_led:address
	wire         pio_led_s1_translator_avalon_anti_slave_0_chipselect;                                             // pio_led_s1_translator:av_chipselect -> pio_led:chipselect
	wire         pio_led_s1_translator_avalon_anti_slave_0_write;                                                  // pio_led_s1_translator:av_write -> pio_led:write_n
	wire  [31:0] pio_led_s1_translator_avalon_anti_slave_0_readdata;                                               // pio_led:readdata -> pio_led_s1_translator:av_readdata
	wire  [31:0] pio_button_s1_translator_avalon_anti_slave_0_writedata;                                           // pio_button_s1_translator:av_writedata -> pio_button:writedata
	wire   [1:0] pio_button_s1_translator_avalon_anti_slave_0_address;                                             // pio_button_s1_translator:av_address -> pio_button:address
	wire         pio_button_s1_translator_avalon_anti_slave_0_chipselect;                                          // pio_button_s1_translator:av_chipselect -> pio_button:chipselect
	wire         pio_button_s1_translator_avalon_anti_slave_0_write;                                               // pio_button_s1_translator:av_write -> pio_button:write_n
	wire  [31:0] pio_button_s1_translator_avalon_anti_slave_0_readdata;                                            // pio_button:readdata -> pio_button_s1_translator:av_readdata
	wire         sysid_control_slave_translator_avalon_anti_slave_0_address;                                       // sysid_control_slave_translator:av_address -> sysid:address
	wire  [31:0] sysid_control_slave_translator_avalon_anti_slave_0_readdata;                                      // sysid:readdata -> sysid_control_slave_translator:av_readdata
	wire   [1:0] hdmi_rx_irq_n_s1_translator_avalon_anti_slave_0_address;                                          // hdmi_rx_irq_n_s1_translator:av_address -> hdmi_rx_irq_n:address
	wire  [31:0] hdmi_rx_irq_n_s1_translator_avalon_anti_slave_0_readdata;                                         // hdmi_rx_irq_n:readdata -> hdmi_rx_irq_n_s1_translator:av_readdata
	wire  [31:0] hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_writedata;                                        // hdmi_rx_hpd_n_s1_translator:av_writedata -> hdmi_rx_hpd_n:writedata
	wire   [1:0] hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_address;                                          // hdmi_rx_hpd_n_s1_translator:av_address -> hdmi_rx_hpd_n:address
	wire         hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_chipselect;                                       // hdmi_rx_hpd_n_s1_translator:av_chipselect -> hdmi_rx_hpd_n:chipselect
	wire         hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_write;                                            // hdmi_rx_hpd_n_s1_translator:av_write -> hdmi_rx_hpd_n:write_n
	wire  [31:0] hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_readdata;                                         // hdmi_rx_hpd_n:readdata -> hdmi_rx_hpd_n_s1_translator:av_readdata
	wire  [31:0] hdmi_rx_cec_s1_translator_avalon_anti_slave_0_writedata;                                          // hdmi_rx_cec_s1_translator:av_writedata -> hdmi_rx_cec:writedata
	wire   [1:0] hdmi_rx_cec_s1_translator_avalon_anti_slave_0_address;                                            // hdmi_rx_cec_s1_translator:av_address -> hdmi_rx_cec:address
	wire         hdmi_rx_cec_s1_translator_avalon_anti_slave_0_chipselect;                                         // hdmi_rx_cec_s1_translator:av_chipselect -> hdmi_rx_cec:chipselect
	wire         hdmi_rx_cec_s1_translator_avalon_anti_slave_0_write;                                              // hdmi_rx_cec_s1_translator:av_write -> hdmi_rx_cec:write_n
	wire  [31:0] hdmi_rx_cec_s1_translator_avalon_anti_slave_0_readdata;                                           // hdmi_rx_cec:readdata -> hdmi_rx_cec_s1_translator:av_readdata
	wire  [31:0] hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx0_ep_scl_s1_translator:av_writedata -> hdmi_rx0_ep_scl:writedata
	wire   [1:0] hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx0_ep_scl_s1_translator:av_address -> hdmi_rx0_ep_scl:address
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx0_ep_scl_s1_translator:av_chipselect -> hdmi_rx0_ep_scl:chipselect
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx0_ep_scl_s1_translator:av_write -> hdmi_rx0_ep_scl:write_n
	wire  [31:0] hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx0_ep_scl:readdata -> hdmi_rx0_ep_scl_s1_translator:av_readdata
	wire  [31:0] hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx0_ep_sda_s1_translator:av_writedata -> hdmi_rx0_ep_sda:writedata
	wire   [1:0] hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx0_ep_sda_s1_translator:av_address -> hdmi_rx0_ep_sda:address
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx0_ep_sda_s1_translator:av_chipselect -> hdmi_rx0_ep_sda:chipselect
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx0_ep_sda_s1_translator:av_write -> hdmi_rx0_ep_sda:write_n
	wire  [31:0] hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx0_ep_sda:readdata -> hdmi_rx0_ep_sda_s1_translator:av_readdata
	wire  [31:0] hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx1_ep_scl_s1_translator:av_writedata -> hdmi_rx1_ep_scl:writedata
	wire   [1:0] hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx1_ep_scl_s1_translator:av_address -> hdmi_rx1_ep_scl:address
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx1_ep_scl_s1_translator:av_chipselect -> hdmi_rx1_ep_scl:chipselect
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx1_ep_scl_s1_translator:av_write -> hdmi_rx1_ep_scl:write_n
	wire  [31:0] hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx1_ep_scl:readdata -> hdmi_rx1_ep_scl_s1_translator:av_readdata
	wire  [31:0] hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx1_ep_sda_s1_translator:av_writedata -> hdmi_rx1_ep_sda:writedata
	wire   [1:0] hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx1_ep_sda_s1_translator:av_address -> hdmi_rx1_ep_sda:address
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx1_ep_sda_s1_translator:av_chipselect -> hdmi_rx1_ep_sda:chipselect
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx1_ep_sda_s1_translator:av_write -> hdmi_rx1_ep_sda:write_n
	wire  [31:0] hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx1_ep_sda:readdata -> hdmi_rx1_ep_sda_s1_translator:av_readdata
	wire  [31:0] hdmi_rx_sync_s1_translator_avalon_anti_slave_0_writedata;                                         // hdmi_rx_sync_s1_translator:av_writedata -> hdmi_rx_sync:writedata
	wire   [1:0] hdmi_rx_sync_s1_translator_avalon_anti_slave_0_address;                                           // hdmi_rx_sync_s1_translator:av_address -> hdmi_rx_sync:address
	wire         hdmi_rx_sync_s1_translator_avalon_anti_slave_0_chipselect;                                        // hdmi_rx_sync_s1_translator:av_chipselect -> hdmi_rx_sync:chipselect
	wire         hdmi_rx_sync_s1_translator_avalon_anti_slave_0_write;                                             // hdmi_rx_sync_s1_translator:av_write -> hdmi_rx_sync:write_n
	wire  [31:0] hdmi_rx_sync_s1_translator_avalon_anti_slave_0_readdata;                                          // hdmi_rx_sync:readdata -> hdmi_rx_sync_s1_translator:av_readdata
	wire  [31:0] hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_writedata;                                    // hdmi_tx_disp_mode_s1_translator:av_writedata -> hdmi_tx_disp_mode:writedata
	wire   [1:0] hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_address;                                      // hdmi_tx_disp_mode_s1_translator:av_address -> hdmi_tx_disp_mode:address
	wire         hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_chipselect;                                   // hdmi_tx_disp_mode_s1_translator:av_chipselect -> hdmi_tx_disp_mode:chipselect
	wire         hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_write;                                        // hdmi_tx_disp_mode_s1_translator:av_write -> hdmi_tx_disp_mode:write_n
	wire  [31:0] hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_readdata;                                     // hdmi_tx_disp_mode:readdata -> hdmi_tx_disp_mode_s1_translator:av_readdata
	wire  [31:0] hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_writedata;                                  // hdmi_tx_mode_change_s1_translator:av_writedata -> hdmi_tx_mode_change:writedata
	wire   [1:0] hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_address;                                    // hdmi_tx_mode_change_s1_translator:av_address -> hdmi_tx_mode_change:address
	wire         hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_chipselect;                                 // hdmi_tx_mode_change_s1_translator:av_chipselect -> hdmi_tx_mode_change:chipselect
	wire         hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_write;                                      // hdmi_tx_mode_change_s1_translator:av_write -> hdmi_tx_mode_change:write_n
	wire  [31:0] hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_readdata;                                   // hdmi_tx_mode_change:readdata -> hdmi_tx_mode_change_s1_translator:av_readdata
	wire  [31:0] hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_writedata;                                    // hdmi_tx_vpg_color_s1_translator:av_writedata -> hdmi_tx_vpg_color:writedata
	wire   [1:0] hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_address;                                      // hdmi_tx_vpg_color_s1_translator:av_address -> hdmi_tx_vpg_color:address
	wire         hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_chipselect;                                   // hdmi_tx_vpg_color_s1_translator:av_chipselect -> hdmi_tx_vpg_color:chipselect
	wire         hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_write;                                        // hdmi_tx_vpg_color_s1_translator:av_write -> hdmi_tx_vpg_color:write_n
	wire  [31:0] hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_readdata;                                     // hdmi_tx_vpg_color:readdata -> hdmi_tx_vpg_color_s1_translator:av_readdata
	wire  [31:0] hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_writedata;                                      // hdmi_rx_edid_wp_s1_translator:av_writedata -> hdmi_rx_edid_wp:writedata
	wire   [1:0] hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_address;                                        // hdmi_rx_edid_wp_s1_translator:av_address -> hdmi_rx_edid_wp:address
	wire         hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_chipselect;                                     // hdmi_rx_edid_wp_s1_translator:av_chipselect -> hdmi_rx_edid_wp:chipselect
	wire         hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_write;                                          // hdmi_rx_edid_wp_s1_translator:av_write -> hdmi_rx_edid_wp:write_n
	wire  [31:0] hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_readdata;                                       // hdmi_rx_edid_wp:readdata -> hdmi_rx_edid_wp_s1_translator:av_readdata
	wire         cpu_instruction_master_translator_avalon_universal_master_0_waitrequest;                          // cpu_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
	wire   [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount;                           // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire  [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata;                            // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
	wire  [24:0] cpu_instruction_master_translator_avalon_universal_master_0_address;                              // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_address
	wire         cpu_instruction_master_translator_avalon_universal_master_0_lock;                                 // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_lock
	wire         cpu_instruction_master_translator_avalon_universal_master_0_write;                                // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_write
	wire         cpu_instruction_master_translator_avalon_universal_master_0_read;                                 // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_read
	wire  [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata;                             // cpu_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
	wire         cpu_instruction_master_translator_avalon_universal_master_0_debugaccess;                          // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire   [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable;                           // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire         cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid;                        // cpu_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
	wire         cpu_data_master_translator_avalon_universal_master_0_waitrequest;                                 // cpu_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
	wire   [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount;                                  // cpu_data_master_translator:uav_burstcount -> cpu_data_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire  [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata;                                   // cpu_data_master_translator:uav_writedata -> cpu_data_master_translator_avalon_universal_master_0_agent:av_writedata
	wire  [24:0] cpu_data_master_translator_avalon_universal_master_0_address;                                     // cpu_data_master_translator:uav_address -> cpu_data_master_translator_avalon_universal_master_0_agent:av_address
	wire         cpu_data_master_translator_avalon_universal_master_0_lock;                                        // cpu_data_master_translator:uav_lock -> cpu_data_master_translator_avalon_universal_master_0_agent:av_lock
	wire         cpu_data_master_translator_avalon_universal_master_0_write;                                       // cpu_data_master_translator:uav_write -> cpu_data_master_translator_avalon_universal_master_0_agent:av_write
	wire         cpu_data_master_translator_avalon_universal_master_0_read;                                        // cpu_data_master_translator:uav_read -> cpu_data_master_translator_avalon_universal_master_0_agent:av_read
	wire  [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata;                                    // cpu_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_data_master_translator:uav_readdata
	wire         cpu_data_master_translator_avalon_universal_master_0_debugaccess;                                 // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire   [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable;                                  // cpu_data_master_translator:uav_byteenable -> cpu_data_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire         cpu_data_master_translator_avalon_universal_master_0_readdatavalid;                               // cpu_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest;                   // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount;                    // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
	wire  [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata;                     // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
	wire  [24:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address;                       // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write;                         // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock;                          // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read;                          // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
	wire  [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata;                      // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                 // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess;                   // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
	wire   [3:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable;                    // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;            // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid;                  // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;          // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [80:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data;                   // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready;                  // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;         // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;               // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;       // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [80:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;               // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;             // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;              // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;             // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                       // onchip_memory2_s1_translator:uav_waitrequest -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                        // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_s1_translator:uav_burstcount
	wire  [31:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                         // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_s1_translator:uav_writedata
	wire  [24:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_address;                           // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_s1_translator:uav_address
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_write;                             // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_s1_translator:uav_write
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_lock;                              // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_s1_translator:uav_lock
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_read;                              // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_s1_translator:uav_read
	wire  [31:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                          // onchip_memory2_s1_translator:uav_readdata -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                     // onchip_memory2_s1_translator:uav_readdatavalid -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                       // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_s1_translator:uav_debugaccess
	wire   [3:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                        // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_s1_translator:uav_byteenable
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                      // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;              // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [80:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                       // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                      // onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;             // onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                   // onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;           // onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [80:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                    // onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                   // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                 // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                  // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                 // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount;              // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
	wire  [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata;               // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
	wire  [24:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address;                 // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write;                   // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock;                    // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read;                    // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
	wire  [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata;                // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
	wire   [3:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable;              // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid;            // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [80:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data;             // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready;            // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [80:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest;                           // pll_pll_slave_translator:uav_waitrequest -> pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount;                            // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> pll_pll_slave_translator:uav_burstcount
	wire  [31:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata;                             // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> pll_pll_slave_translator:uav_writedata
	wire  [24:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_address;                               // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> pll_pll_slave_translator:uav_address
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_write;                                 // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> pll_pll_slave_translator:uav_write
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock;                                  // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> pll_pll_slave_translator:uav_lock
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_read;                                  // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> pll_pll_slave_translator:uav_read
	wire  [31:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata;                              // pll_pll_slave_translator:uav_readdata -> pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                         // pll_pll_slave_translator:uav_readdatavalid -> pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess;                           // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pll_pll_slave_translator:uav_debugaccess
	wire   [3:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable;                            // pll_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> pll_pll_slave_translator:uav_byteenable
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                    // pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid;                          // pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                  // pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [80:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data;                           // pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready;                          // pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                 // pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                       // pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;               // pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [80:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                        // pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                       // pll_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                     // pll_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
	wire  [31:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                      // pll_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                     // pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid;                     // pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data;                      // pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready;                     // pll_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest;                            // i2s_tx_slave_translator:uav_waitrequest -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_burstcount;                             // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> i2s_tx_slave_translator:uav_burstcount
	wire  [31:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_writedata;                              // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> i2s_tx_slave_translator:uav_writedata
	wire  [24:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_address;                                // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_address -> i2s_tx_slave_translator:uav_address
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_write;                                  // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_write -> i2s_tx_slave_translator:uav_write
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_lock;                                   // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_lock -> i2s_tx_slave_translator:uav_lock
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_read;                                   // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_read -> i2s_tx_slave_translator:uav_read
	wire  [31:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_readdata;                               // i2s_tx_slave_translator:uav_readdata -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                          // i2s_tx_slave_translator:uav_readdatavalid -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess;                            // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> i2s_tx_slave_translator:uav_debugaccess
	wire   [3:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_byteenable;                             // i2s_tx_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> i2s_tx_slave_translator:uav_byteenable
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                     // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_valid;                           // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                   // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [80:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_data;                            // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_ready;                           // i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                  // i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                        // i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                // i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [80:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                         // i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                        // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                      // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                       // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                      // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest;                // clock_crossing_bridge_s0_translator:uav_waitrequest -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount;                 // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> clock_crossing_bridge_s0_translator:uav_burstcount
	wire  [31:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata;                  // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> clock_crossing_bridge_s0_translator:uav_writedata
	wire  [24:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address;                    // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_address -> clock_crossing_bridge_s0_translator:uav_address
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write;                      // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_write -> clock_crossing_bridge_s0_translator:uav_write
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock;                       // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_lock -> clock_crossing_bridge_s0_translator:uav_lock
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read;                       // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_read -> clock_crossing_bridge_s0_translator:uav_read
	wire  [31:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata;                   // clock_crossing_bridge_s0_translator:uav_readdata -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid;              // clock_crossing_bridge_s0_translator:uav_readdatavalid -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess;                // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> clock_crossing_bridge_s0_translator:uav_debugaccess
	wire   [3:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable;                 // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> clock_crossing_bridge_s0_translator:uav_byteenable
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;         // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid;               // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;       // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [80:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data;                // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready;               // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;      // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;            // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;    // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [80:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;             // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;            // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;          // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;           // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;          // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_waitrequest;                        // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_waitrequest -> clock_crossing_bridge_m0_translator:uav_waitrequest
	wire   [2:0] clock_crossing_bridge_m0_translator_avalon_universal_master_0_burstcount;                         // clock_crossing_bridge_m0_translator:uav_burstcount -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_burstcount
	wire  [31:0] clock_crossing_bridge_m0_translator_avalon_universal_master_0_writedata;                          // clock_crossing_bridge_m0_translator:uav_writedata -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_writedata
	wire   [8:0] clock_crossing_bridge_m0_translator_avalon_universal_master_0_address;                            // clock_crossing_bridge_m0_translator:uav_address -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_address
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_lock;                               // clock_crossing_bridge_m0_translator:uav_lock -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_lock
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_write;                              // clock_crossing_bridge_m0_translator:uav_write -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_write
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_read;                               // clock_crossing_bridge_m0_translator:uav_read -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_read
	wire  [31:0] clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdata;                           // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_readdata -> clock_crossing_bridge_m0_translator:uav_readdata
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_debugaccess;                        // clock_crossing_bridge_m0_translator:uav_debugaccess -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_debugaccess
	wire   [3:0] clock_crossing_bridge_m0_translator_avalon_universal_master_0_byteenable;                         // clock_crossing_bridge_m0_translator:uav_byteenable -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_byteenable
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid;                      // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:av_readdatavalid -> clock_crossing_bridge_m0_translator:uav_readdatavalid
	wire         timer_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                                // timer_s1_translator:uav_waitrequest -> timer_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] timer_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                                 // timer_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_s1_translator:uav_burstcount
	wire  [31:0] timer_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                  // timer_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_s1_translator:uav_writedata
	wire   [8:0] timer_s1_translator_avalon_universal_slave_0_agent_m0_address;                                    // timer_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_s1_translator:uav_address
	wire         timer_s1_translator_avalon_universal_slave_0_agent_m0_write;                                      // timer_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_s1_translator:uav_write
	wire         timer_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                       // timer_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_s1_translator:uav_lock
	wire         timer_s1_translator_avalon_universal_slave_0_agent_m0_read;                                       // timer_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_s1_translator:uav_read
	wire  [31:0] timer_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                   // timer_s1_translator:uav_readdata -> timer_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         timer_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                              // timer_s1_translator:uav_readdatavalid -> timer_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         timer_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                                // timer_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_s1_translator:uav_debugaccess
	wire   [3:0] timer_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                                 // timer_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_s1_translator:uav_byteenable
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                         // timer_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                               // timer_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                       // timer_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] timer_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                                // timer_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                               // timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                      // timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                            // timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                    // timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                             // timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                            // timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                          // timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                           // timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                          // timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_tx_i2c_scl_s1_translator:uav_waitrequest -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_tx_i2c_scl_s1_translator:uav_burstcount
	wire  [31:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_tx_i2c_scl_s1_translator:uav_writedata
	wire   [8:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_tx_i2c_scl_s1_translator:uav_address
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_tx_i2c_scl_s1_translator:uav_write
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_tx_i2c_scl_s1_translator:uav_lock
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_tx_i2c_scl_s1_translator:uav_read
	wire  [31:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_tx_i2c_scl_s1_translator:uav_readdata -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_tx_i2c_scl_s1_translator:uav_readdatavalid -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_tx_i2c_scl_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_tx_i2c_scl_s1_translator:uav_byteenable
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_tx_i2c_sda_s1_translator:uav_waitrequest -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_tx_i2c_sda_s1_translator:uav_burstcount
	wire  [31:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_tx_i2c_sda_s1_translator:uav_writedata
	wire   [8:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_tx_i2c_sda_s1_translator:uav_address
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_tx_i2c_sda_s1_translator:uav_write
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_tx_i2c_sda_s1_translator:uav_lock
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_tx_i2c_sda_s1_translator:uav_read
	wire  [31:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_tx_i2c_sda_s1_translator:uav_readdata -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_tx_i2c_sda_s1_translator:uav_readdatavalid -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_tx_i2c_sda_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_tx_i2c_sda_s1_translator:uav_byteenable
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx_i2c_scl_s1_translator:uav_waitrequest -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_i2c_scl_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_i2c_scl_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_i2c_scl_s1_translator:uav_address
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_i2c_scl_s1_translator:uav_write
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_i2c_scl_s1_translator:uav_lock
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_i2c_scl_s1_translator:uav_read
	wire  [31:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx_i2c_scl_s1_translator:uav_readdata -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx_i2c_scl_s1_translator:uav_readdatavalid -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_i2c_scl_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_i2c_scl_s1_translator:uav_byteenable
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx_i2c_sda_s1_translator:uav_waitrequest -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_i2c_sda_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_i2c_sda_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_i2c_sda_s1_translator:uav_address
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_i2c_sda_s1_translator:uav_write
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_i2c_sda_s1_translator:uav_lock
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_i2c_sda_s1_translator:uav_read
	wire  [31:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx_i2c_sda_s1_translator:uav_readdata -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx_i2c_sda_s1_translator:uav_readdatavalid -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_i2c_sda_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_i2c_sda_s1_translator:uav_byteenable
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_tx_reset_n_s1_translator:uav_waitrequest -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_tx_reset_n_s1_translator:uav_burstcount
	wire  [31:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_tx_reset_n_s1_translator:uav_writedata
	wire   [8:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_tx_reset_n_s1_translator:uav_address
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_tx_reset_n_s1_translator:uav_write
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_tx_reset_n_s1_translator:uav_lock
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_tx_reset_n_s1_translator:uav_read
	wire  [31:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_tx_reset_n_s1_translator:uav_readdata -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_tx_reset_n_s1_translator:uav_readdatavalid -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_tx_reset_n_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_tx_reset_n_s1_translator:uav_byteenable
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                        // hdmi_tx_irq_n_s1_translator:uav_waitrequest -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                         // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_tx_irq_n_s1_translator:uav_burstcount
	wire  [31:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                          // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_tx_irq_n_s1_translator:uav_writedata
	wire   [8:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_address;                            // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_tx_irq_n_s1_translator:uav_address
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_write;                              // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_tx_irq_n_s1_translator:uav_write
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_lock;                               // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_tx_irq_n_s1_translator:uav_lock
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_read;                               // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_tx_irq_n_s1_translator:uav_read
	wire  [31:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                           // hdmi_tx_irq_n_s1_translator:uav_readdata -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                      // hdmi_tx_irq_n_s1_translator:uav_readdatavalid -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                        // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_tx_irq_n_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                         // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_tx_irq_n_s1_translator:uav_byteenable
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                 // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                       // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;               // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                        // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                       // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;              // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                    // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;            // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                     // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                    // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                  // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                   // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                  // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx_reset_n_s1_translator:uav_waitrequest -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_reset_n_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_reset_n_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_reset_n_s1_translator:uav_address
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_reset_n_s1_translator:uav_write
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_reset_n_s1_translator:uav_lock
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_reset_n_s1_translator:uav_read
	wire  [31:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx_reset_n_s1_translator:uav_readdata -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx_reset_n_s1_translator:uav_readdatavalid -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_reset_n_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_reset_n_s1_translator:uav_byteenable
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                              // pio_led_s1_translator:uav_waitrequest -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                               // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_led_s1_translator:uav_burstcount
	wire  [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                                // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_led_s1_translator:uav_writedata
	wire   [8:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address;                                  // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_led_s1_translator:uav_address
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write;                                    // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_led_s1_translator:uav_write
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                     // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_led_s1_translator:uav_lock
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read;                                     // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_led_s1_translator:uav_read
	wire  [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                                 // pio_led_s1_translator:uav_readdata -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                            // pio_led_s1_translator:uav_readdatavalid -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                              // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_led_s1_translator:uav_debugaccess
	wire   [3:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                               // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_led_s1_translator:uav_byteenable
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                       // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                             // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                     // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                              // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                             // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                    // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                          // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;                  // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                           // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                          // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                        // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                         // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                        // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                           // pio_button_s1_translator:uav_waitrequest -> pio_button_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] pio_button_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                            // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_button_s1_translator:uav_burstcount
	wire  [31:0] pio_button_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                             // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_button_s1_translator:uav_writedata
	wire   [8:0] pio_button_s1_translator_avalon_universal_slave_0_agent_m0_address;                               // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_button_s1_translator:uav_address
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_m0_write;                                 // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_button_s1_translator:uav_write
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                  // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_button_s1_translator:uav_lock
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_m0_read;                                  // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_button_s1_translator:uav_read
	wire  [31:0] pio_button_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                              // pio_button_s1_translator:uav_readdata -> pio_button_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                         // pio_button_s1_translator:uav_readdatavalid -> pio_button_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                           // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_button_s1_translator:uav_debugaccess
	wire   [3:0] pio_button_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                            // pio_button_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_button_s1_translator:uav_byteenable
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                    // pio_button_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                          // pio_button_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                  // pio_button_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                           // pio_button_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                          // pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_button_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                 // pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_button_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                       // pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_button_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;               // pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_button_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                        // pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_button_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                       // pio_button_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                     // pio_button_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_button_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                      // pio_button_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_button_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                     // pio_button_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_button_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest;                     // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount;                      // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount
	wire  [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata;                       // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata
	wire   [8:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address;                         // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_control_slave_translator:uav_address
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write;                           // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_control_slave_translator:uav_write
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock;                            // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_control_slave_translator:uav_lock
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read;                            // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_control_slave_translator:uav_read
	wire  [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata;                        // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                   // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess;                     // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess
	wire   [3:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable;                      // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;              // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid;                    // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;            // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data;                     // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready;                    // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;           // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                 // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;         // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                  // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                 // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;               // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;               // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                        // hdmi_rx_irq_n_s1_translator:uav_waitrequest -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                         // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_irq_n_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                          // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_irq_n_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_address;                            // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_irq_n_s1_translator:uav_address
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_write;                              // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_irq_n_s1_translator:uav_write
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_lock;                               // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_irq_n_s1_translator:uav_lock
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_read;                               // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_irq_n_s1_translator:uav_read
	wire  [31:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                           // hdmi_rx_irq_n_s1_translator:uav_readdata -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                      // hdmi_rx_irq_n_s1_translator:uav_readdatavalid -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                        // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_irq_n_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                         // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_irq_n_s1_translator:uav_byteenable
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                 // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                       // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;               // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                        // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                       // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;              // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                    // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;            // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                     // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                    // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                  // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                   // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                  // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                        // hdmi_rx_hpd_n_s1_translator:uav_waitrequest -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                         // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_hpd_n_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                          // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_hpd_n_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_address;                            // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_hpd_n_s1_translator:uav_address
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_write;                              // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_hpd_n_s1_translator:uav_write
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_lock;                               // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_hpd_n_s1_translator:uav_lock
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_read;                               // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_hpd_n_s1_translator:uav_read
	wire  [31:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                           // hdmi_rx_hpd_n_s1_translator:uav_readdata -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                      // hdmi_rx_hpd_n_s1_translator:uav_readdatavalid -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                        // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_hpd_n_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                         // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_hpd_n_s1_translator:uav_byteenable
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                 // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                       // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;               // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                        // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                       // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;              // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                    // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;            // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                     // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                    // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                  // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                   // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                  // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                          // hdmi_rx_cec_s1_translator:uav_waitrequest -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                           // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_cec_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                            // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_cec_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_address;                              // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_cec_s1_translator:uav_address
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_write;                                // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_cec_s1_translator:uav_write
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                 // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_cec_s1_translator:uav_lock
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_read;                                 // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_cec_s1_translator:uav_read
	wire  [31:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                             // hdmi_rx_cec_s1_translator:uav_readdata -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                        // hdmi_rx_cec_s1_translator:uav_readdatavalid -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                          // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_cec_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                           // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_cec_s1_translator:uav_byteenable
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                   // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                         // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                 // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                          // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                         // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;                // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                      // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;              // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                       // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                      // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                    // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                     // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                    // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx0_ep_scl_s1_translator:uav_waitrequest -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx0_ep_scl_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx0_ep_scl_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx0_ep_scl_s1_translator:uav_address
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx0_ep_scl_s1_translator:uav_write
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx0_ep_scl_s1_translator:uav_lock
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx0_ep_scl_s1_translator:uav_read
	wire  [31:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx0_ep_scl_s1_translator:uav_readdata -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx0_ep_scl_s1_translator:uav_readdatavalid -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx0_ep_scl_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx0_ep_scl_s1_translator:uav_byteenable
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx0_ep_sda_s1_translator:uav_waitrequest -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx0_ep_sda_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx0_ep_sda_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx0_ep_sda_s1_translator:uav_address
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx0_ep_sda_s1_translator:uav_write
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx0_ep_sda_s1_translator:uav_lock
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx0_ep_sda_s1_translator:uav_read
	wire  [31:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx0_ep_sda_s1_translator:uav_readdata -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx0_ep_sda_s1_translator:uav_readdatavalid -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx0_ep_sda_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx0_ep_sda_s1_translator:uav_byteenable
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx1_ep_scl_s1_translator:uav_waitrequest -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx1_ep_scl_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx1_ep_scl_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx1_ep_scl_s1_translator:uav_address
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx1_ep_scl_s1_translator:uav_write
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx1_ep_scl_s1_translator:uav_lock
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx1_ep_scl_s1_translator:uav_read
	wire  [31:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx1_ep_scl_s1_translator:uav_readdata -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx1_ep_scl_s1_translator:uav_readdatavalid -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx1_ep_scl_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx1_ep_scl_s1_translator:uav_byteenable
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx1_ep_sda_s1_translator:uav_waitrequest -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx1_ep_sda_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx1_ep_sda_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx1_ep_sda_s1_translator:uav_address
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx1_ep_sda_s1_translator:uav_write
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx1_ep_sda_s1_translator:uav_lock
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx1_ep_sda_s1_translator:uav_read
	wire  [31:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx1_ep_sda_s1_translator:uav_readdata -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx1_ep_sda_s1_translator:uav_readdatavalid -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx1_ep_sda_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx1_ep_sda_s1_translator:uav_byteenable
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                         // hdmi_rx_sync_s1_translator:uav_waitrequest -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                          // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_sync_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                           // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_sync_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_address;                             // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_sync_s1_translator:uav_address
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_write;                               // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_sync_s1_translator:uav_write
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_lock;                                // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_sync_s1_translator:uav_lock
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_read;                                // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_sync_s1_translator:uav_read
	wire  [31:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                            // hdmi_rx_sync_s1_translator:uav_readdata -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                       // hdmi_rx_sync_s1_translator:uav_readdatavalid -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                         // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_sync_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                          // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_sync_s1_translator:uav_byteenable
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                  // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                        // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;                // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                         // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                        // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;               // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                     // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;             // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                      // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                     // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                   // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                    // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                   // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                    // hdmi_tx_disp_mode_s1_translator:uav_waitrequest -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                     // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_tx_disp_mode_s1_translator:uav_burstcount
	wire  [31:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                      // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_tx_disp_mode_s1_translator:uav_writedata
	wire   [8:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_address;                        // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_tx_disp_mode_s1_translator:uav_address
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_write;                          // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_tx_disp_mode_s1_translator:uav_write
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_lock;                           // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_tx_disp_mode_s1_translator:uav_lock
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_read;                           // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_tx_disp_mode_s1_translator:uav_read
	wire  [31:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                       // hdmi_tx_disp_mode_s1_translator:uav_readdata -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                  // hdmi_tx_disp_mode_s1_translator:uav_readdatavalid -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                    // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_tx_disp_mode_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                     // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_tx_disp_mode_s1_translator:uav_byteenable
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;             // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                   // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;           // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                    // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                   // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;          // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;        // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                 // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;              // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;               // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;              // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                  // hdmi_tx_mode_change_s1_translator:uav_waitrequest -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                   // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_tx_mode_change_s1_translator:uav_burstcount
	wire  [31:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                    // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_tx_mode_change_s1_translator:uav_writedata
	wire   [8:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_address;                      // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_tx_mode_change_s1_translator:uav_address
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_write;                        // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_tx_mode_change_s1_translator:uav_write
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_lock;                         // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_tx_mode_change_s1_translator:uav_lock
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_read;                         // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_tx_mode_change_s1_translator:uav_read
	wire  [31:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                     // hdmi_tx_mode_change_s1_translator:uav_readdata -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                // hdmi_tx_mode_change_s1_translator:uav_readdatavalid -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                  // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_tx_mode_change_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                   // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_tx_mode_change_s1_translator:uav_byteenable
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;           // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                 // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;         // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                  // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                 // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;        // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;              // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;      // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;               // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;              // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;            // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;             // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;            // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                    // hdmi_tx_vpg_color_s1_translator:uav_waitrequest -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                     // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_tx_vpg_color_s1_translator:uav_burstcount
	wire  [31:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                      // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_tx_vpg_color_s1_translator:uav_writedata
	wire   [8:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_address;                        // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_tx_vpg_color_s1_translator:uav_address
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_write;                          // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_tx_vpg_color_s1_translator:uav_write
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_lock;                           // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_tx_vpg_color_s1_translator:uav_lock
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_read;                           // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_tx_vpg_color_s1_translator:uav_read
	wire  [31:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                       // hdmi_tx_vpg_color_s1_translator:uav_readdata -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                  // hdmi_tx_vpg_color_s1_translator:uav_readdatavalid -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                    // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_tx_vpg_color_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                     // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_tx_vpg_color_s1_translator:uav_byteenable
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;             // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                   // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;           // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                    // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                   // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;          // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;        // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                 // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;              // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;               // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;              // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                      // hdmi_rx_edid_wp_s1_translator:uav_waitrequest -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                       // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> hdmi_rx_edid_wp_s1_translator:uav_burstcount
	wire  [31:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                        // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> hdmi_rx_edid_wp_s1_translator:uav_writedata
	wire   [8:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_address;                          // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_address -> hdmi_rx_edid_wp_s1_translator:uav_address
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_write;                            // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_write -> hdmi_rx_edid_wp_s1_translator:uav_write
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_lock;                             // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_lock -> hdmi_rx_edid_wp_s1_translator:uav_lock
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_read;                             // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_read -> hdmi_rx_edid_wp_s1_translator:uav_read
	wire  [31:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                         // hdmi_rx_edid_wp_s1_translator:uav_readdata -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                    // hdmi_rx_edid_wp_s1_translator:uav_readdatavalid -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                      // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> hdmi_rx_edid_wp_s1_translator:uav_debugaccess
	wire   [3:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                       // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> hdmi_rx_edid_wp_s1_translator:uav_byteenable
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;               // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                     // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;             // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [68:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                      // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                     // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;            // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                  // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;          // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [68:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                   // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                  // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                 // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                 // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
	wire         cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid;                       // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
	wire         cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket;               // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
	wire  [79:0] cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data;                        // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
	wire         cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready;                       // addr_router:sink_ready -> cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
	wire         cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                        // cpu_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
	wire         cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid;                              // cpu_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
	wire         cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket;                      // cpu_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
	wire  [79:0] cpu_data_master_translator_avalon_universal_master_0_agent_cp_data;                               // cpu_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
	wire         cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready;                              // addr_router_001:sink_ready -> cpu_data_master_translator_avalon_universal_master_0_agent:cp_ready
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket;                   // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid;                         // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket;                 // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
	wire  [79:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data;                          // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
	wire         cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready;                         // id_router:sink_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                       // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_valid;                             // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                     // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
	wire  [79:0] onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_data;                              // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
	wire         onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_ready;                             // id_router_001:sink_ready -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid;                   // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
	wire  [79:0] jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data;                    // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
	wire         jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router_002:sink_ready -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket;                           // pll_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid;                                 // pll_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket;                         // pll_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
	wire  [79:0] pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_data;                                  // pll_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
	wire         pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready;                                 // id_router_003:sink_ready -> pll_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket;                            // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_valid;                                  // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket;                          // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
	wire  [79:0] i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_data;                                   // i2s_tx_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
	wire         i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_ready;                                  // id_router_004:sink_ready -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:rp_ready
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket;                // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid;                      // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket;              // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
	wire  [79:0] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data;                       // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
	wire         clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready;                      // id_router_005:sink_ready -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:rp_ready
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket;               // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid;                     // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket;             // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
	wire  [67:0] clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_data;                      // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
	wire         clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready;                     // addr_router_002:sink_ready -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:cp_ready
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                                // timer_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                      // timer_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                              // timer_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
	wire  [67:0] timer_s1_translator_avalon_universal_slave_0_agent_rp_data;                                       // timer_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
	wire         timer_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                      // id_router_006:sink_ready -> timer_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
	wire  [67:0] hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
	wire         hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_007:sink_ready -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
	wire  [67:0] hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
	wire         hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_008:sink_ready -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
	wire  [67:0] hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
	wire         hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_009:sink_ready -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
	wire  [67:0] hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
	wire         hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_010:sink_ready -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
	wire  [67:0] hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
	wire         hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_011:sink_ready -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                        // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_valid;                              // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                      // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket
	wire  [67:0] hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_data;                               // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data
	wire         hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_ready;                              // id_router_012:sink_ready -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_013:sink_endofpacket
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_013:sink_valid
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_013:sink_startofpacket
	wire  [67:0] hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_013:sink_data
	wire         hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_013:sink_ready -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                              // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_014:sink_endofpacket
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                    // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_014:sink_valid
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                            // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_014:sink_startofpacket
	wire  [67:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data;                                     // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_014:sink_data
	wire         pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                    // id_router_014:sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                           // pio_button_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_015:sink_endofpacket
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                 // pio_button_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_015:sink_valid
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                         // pio_button_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_015:sink_startofpacket
	wire  [67:0] pio_button_s1_translator_avalon_universal_slave_0_agent_rp_data;                                  // pio_button_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_015:sink_data
	wire         pio_button_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                 // id_router_015:sink_ready -> pio_button_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket;                     // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_016:sink_endofpacket
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid;                           // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_016:sink_valid
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket;                   // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_016:sink_startofpacket
	wire  [67:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data;                            // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_016:sink_data
	wire         sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready;                           // id_router_016:sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                        // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_017:sink_endofpacket
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_valid;                              // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_017:sink_valid
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                      // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_017:sink_startofpacket
	wire  [67:0] hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_data;                               // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_017:sink_data
	wire         hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_ready;                              // id_router_017:sink_ready -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                        // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_018:sink_endofpacket
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_valid;                              // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_018:sink_valid
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                      // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_018:sink_startofpacket
	wire  [67:0] hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_data;                               // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_018:sink_data
	wire         hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_ready;                              // id_router_018:sink_ready -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                          // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_019:sink_endofpacket
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_valid;                                // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_019:sink_valid
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                        // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_019:sink_startofpacket
	wire  [67:0] hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_data;                                 // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_019:sink_data
	wire         hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_ready;                                // id_router_019:sink_ready -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_020:sink_endofpacket
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_020:sink_valid
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_020:sink_startofpacket
	wire  [67:0] hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_020:sink_data
	wire         hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_020:sink_ready -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_021:sink_endofpacket
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_021:sink_valid
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_021:sink_startofpacket
	wire  [67:0] hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_021:sink_data
	wire         hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_021:sink_ready -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_022:sink_endofpacket
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_022:sink_valid
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_022:sink_startofpacket
	wire  [67:0] hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_022:sink_data
	wire         hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_022:sink_ready -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_023:sink_endofpacket
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_023:sink_valid
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_023:sink_startofpacket
	wire  [67:0] hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_023:sink_data
	wire         hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_023:sink_ready -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                         // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_024:sink_endofpacket
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_valid;                               // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_024:sink_valid
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                       // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_024:sink_startofpacket
	wire  [67:0] hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_data;                                // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_024:sink_data
	wire         hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_ready;                               // id_router_024:sink_ready -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                    // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_025:sink_endofpacket
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_valid;                          // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_025:sink_valid
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                  // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_025:sink_startofpacket
	wire  [67:0] hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_data;                           // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_025:sink_data
	wire         hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_ready;                          // id_router_025:sink_ready -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                  // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_026:sink_endofpacket
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_valid;                        // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_026:sink_valid
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_026:sink_startofpacket
	wire  [67:0] hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_data;                         // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_026:sink_data
	wire         hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_ready;                        // id_router_026:sink_ready -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                    // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_027:sink_endofpacket
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_valid;                          // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_027:sink_valid
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                  // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_027:sink_startofpacket
	wire  [67:0] hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_data;                           // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_027:sink_data
	wire         hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_ready;                          // id_router_027:sink_ready -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                      // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_028:sink_endofpacket
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_valid;                            // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_028:sink_valid
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                    // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_028:sink_startofpacket
	wire  [67:0] hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_data;                             // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_028:sink_data
	wire         hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_ready;                            // id_router_028:sink_ready -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         addr_router_src_endofpacket;                                                                      // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
	wire         addr_router_src_valid;                                                                            // addr_router:src_valid -> limiter:cmd_sink_valid
	wire         addr_router_src_startofpacket;                                                                    // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
	wire  [79:0] addr_router_src_data;                                                                             // addr_router:src_data -> limiter:cmd_sink_data
	wire   [5:0] addr_router_src_channel;                                                                          // addr_router:src_channel -> limiter:cmd_sink_channel
	wire         addr_router_src_ready;                                                                            // limiter:cmd_sink_ready -> addr_router:src_ready
	wire         limiter_rsp_src_endofpacket;                                                                      // limiter:rsp_src_endofpacket -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire         limiter_rsp_src_valid;                                                                            // limiter:rsp_src_valid -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
	wire         limiter_rsp_src_startofpacket;                                                                    // limiter:rsp_src_startofpacket -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [79:0] limiter_rsp_src_data;                                                                             // limiter:rsp_src_data -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_data
	wire   [5:0] limiter_rsp_src_channel;                                                                          // limiter:rsp_src_channel -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
	wire         limiter_rsp_src_ready;                                                                            // cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
	wire         addr_router_001_src_endofpacket;                                                                  // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
	wire         addr_router_001_src_valid;                                                                        // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
	wire         addr_router_001_src_startofpacket;                                                                // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
	wire  [79:0] addr_router_001_src_data;                                                                         // addr_router_001:src_data -> limiter_001:cmd_sink_data
	wire   [5:0] addr_router_001_src_channel;                                                                      // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
	wire         addr_router_001_src_ready;                                                                        // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
	wire         limiter_001_rsp_src_endofpacket;                                                                  // limiter_001:rsp_src_endofpacket -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire         limiter_001_rsp_src_valid;                                                                        // limiter_001:rsp_src_valid -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_valid
	wire         limiter_001_rsp_src_startofpacket;                                                                // limiter_001:rsp_src_startofpacket -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [79:0] limiter_001_rsp_src_data;                                                                         // limiter_001:rsp_src_data -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_data
	wire   [5:0] limiter_001_rsp_src_channel;                                                                      // limiter_001:rsp_src_channel -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_channel
	wire         limiter_001_rsp_src_ready;                                                                        // cpu_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
	wire         addr_router_002_src_endofpacket;                                                                  // addr_router_002:src_endofpacket -> limiter_002:cmd_sink_endofpacket
	wire         addr_router_002_src_valid;                                                                        // addr_router_002:src_valid -> limiter_002:cmd_sink_valid
	wire         addr_router_002_src_startofpacket;                                                                // addr_router_002:src_startofpacket -> limiter_002:cmd_sink_startofpacket
	wire  [67:0] addr_router_002_src_data;                                                                         // addr_router_002:src_data -> limiter_002:cmd_sink_data
	wire  [22:0] addr_router_002_src_channel;                                                                      // addr_router_002:src_channel -> limiter_002:cmd_sink_channel
	wire         addr_router_002_src_ready;                                                                        // limiter_002:cmd_sink_ready -> addr_router_002:src_ready
	wire         limiter_002_rsp_src_endofpacket;                                                                  // limiter_002:rsp_src_endofpacket -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire         limiter_002_rsp_src_valid;                                                                        // limiter_002:rsp_src_valid -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:rp_valid
	wire         limiter_002_rsp_src_startofpacket;                                                                // limiter_002:rsp_src_startofpacket -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [67:0] limiter_002_rsp_src_data;                                                                         // limiter_002:rsp_src_data -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:rp_data
	wire  [22:0] limiter_002_rsp_src_channel;                                                                      // limiter_002:rsp_src_channel -> clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:rp_channel
	wire         limiter_002_rsp_src_ready;                                                                        // clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:rp_ready -> limiter_002:rsp_src_ready
	wire         rst_controller_reset_out_reset;                                                                   // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, clock_crossing_bridge:s0_reset, clock_crossing_bridge_s0_translator:reset, clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:reset, clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cpu:reset_n, cpu_data_master_translator:reset, cpu_data_master_translator_avalon_universal_master_0_agent:reset, cpu_instruction_master_translator:reset, cpu_instruction_master_translator_avalon_universal_master_0_agent:reset, cpu_jtag_debug_module_translator:reset, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:in_reset, crosser_001:out_reset, i2s_tx:s_reset, i2s_tx_slave_translator:reset, i2s_tx_slave_translator_avalon_universal_slave_0_agent:reset, i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, jtag_uart:rst_n, jtag_uart_avalon_jtag_slave_translator:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, onchip_memory2:reset, onchip_memory2_s1_translator:reset, onchip_memory2_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset]
	wire         cpu_jtag_debug_module_reset_reset;                                                                // cpu:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
	wire         rst_controller_001_reset_out_reset;                                                               // rst_controller_001:reset_out -> [crosser:out_reset, crosser_001:in_reset, id_router_003:reset, pll:reset, pll_pll_slave_translator:reset, pll_pll_slave_translator_avalon_universal_slave_0_agent:reset, pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux_003:reset]
	wire         rst_controller_002_reset_out_reset;                                                               // rst_controller_002:reset_out -> [addr_router_002:reset, clock_crossing_bridge:m0_reset, clock_crossing_bridge_m0_translator:reset, clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent:reset, cmd_xbar_demux_002:reset, hdmi_rx0_ep_scl:reset_n, hdmi_rx0_ep_scl_s1_translator:reset, hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx0_ep_sda:reset_n, hdmi_rx0_ep_sda_s1_translator:reset, hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx1_ep_scl:reset_n, hdmi_rx1_ep_scl_s1_translator:reset, hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx1_ep_sda:reset_n, hdmi_rx1_ep_sda_s1_translator:reset, hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_cec:reset_n, hdmi_rx_cec_s1_translator:reset, hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_edid_wp:reset_n, hdmi_rx_edid_wp_s1_translator:reset, hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_hpd_n:reset_n, hdmi_rx_hpd_n_s1_translator:reset, hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_i2c_scl:reset_n, hdmi_rx_i2c_scl_s1_translator:reset, hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_i2c_sda:reset_n, hdmi_rx_i2c_sda_s1_translator:reset, hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_irq_n:reset_n, hdmi_rx_irq_n_s1_translator:reset, hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_reset_n:reset_n, hdmi_rx_reset_n_s1_translator:reset, hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_rx_sync:reset_n, hdmi_rx_sync_s1_translator:reset, hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_tx_disp_mode:reset_n, hdmi_tx_disp_mode_s1_translator:reset, hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_tx_i2c_scl:reset_n, hdmi_tx_i2c_scl_s1_translator:reset, hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_tx_i2c_sda:reset_n, hdmi_tx_i2c_sda_s1_translator:reset, hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_tx_irq_n:reset_n, hdmi_tx_irq_n_s1_translator:reset, hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_tx_mode_change:reset_n, hdmi_tx_mode_change_s1_translator:reset, hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_tx_reset_n:reset_n, hdmi_tx_reset_n_s1_translator:reset, hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, hdmi_tx_vpg_color:reset_n, hdmi_tx_vpg_color_s1_translator:reset, hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:reset, hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, id_router_013:reset, id_router_014:reset, id_router_015:reset, id_router_016:reset, id_router_017:reset, id_router_018:reset, id_router_019:reset, id_router_020:reset, id_router_021:reset, id_router_022:reset, id_router_023:reset, id_router_024:reset, id_router_025:reset, id_router_026:reset, id_router_027:reset, id_router_028:reset, irq_synchronizer:receiver_reset, irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, limiter_002:reset, pio_button:reset_n, pio_button_s1_translator:reset, pio_button_s1_translator_avalon_universal_slave_0_agent:reset, pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pio_led:reset_n, pio_led_s1_translator:reset, pio_led_s1_translator_avalon_universal_slave_0_agent:reset, pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_demux_013:reset, rsp_xbar_demux_014:reset, rsp_xbar_demux_015:reset, rsp_xbar_demux_016:reset, rsp_xbar_demux_017:reset, rsp_xbar_demux_018:reset, rsp_xbar_demux_019:reset, rsp_xbar_demux_020:reset, rsp_xbar_demux_021:reset, rsp_xbar_demux_022:reset, rsp_xbar_demux_023:reset, rsp_xbar_demux_024:reset, rsp_xbar_demux_025:reset, rsp_xbar_demux_026:reset, rsp_xbar_demux_027:reset, rsp_xbar_demux_028:reset, rsp_xbar_mux_002:reset, sysid:reset_n, sysid_control_slave_translator:reset, sysid_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer:reset_n, timer_s1_translator:reset, timer_s1_translator_avalon_universal_slave_0_agent:reset, timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
	wire         cmd_xbar_demux_src0_endofpacket;                                                                  // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire         cmd_xbar_demux_src0_valid;                                                                        // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
	wire         cmd_xbar_demux_src0_startofpacket;                                                                // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire  [79:0] cmd_xbar_demux_src0_data;                                                                         // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
	wire   [5:0] cmd_xbar_demux_src0_channel;                                                                      // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
	wire         cmd_xbar_demux_src0_ready;                                                                        // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
	wire         cmd_xbar_demux_src1_endofpacket;                                                                  // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
	wire         cmd_xbar_demux_src1_valid;                                                                        // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
	wire         cmd_xbar_demux_src1_startofpacket;                                                                // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
	wire  [79:0] cmd_xbar_demux_src1_data;                                                                         // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
	wire   [5:0] cmd_xbar_demux_src1_channel;                                                                      // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
	wire         cmd_xbar_demux_src1_ready;                                                                        // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
	wire         cmd_xbar_demux_001_src0_endofpacket;                                                              // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
	wire         cmd_xbar_demux_001_src0_valid;                                                                    // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
	wire         cmd_xbar_demux_001_src0_startofpacket;                                                            // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
	wire  [79:0] cmd_xbar_demux_001_src0_data;                                                                     // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
	wire   [5:0] cmd_xbar_demux_001_src0_channel;                                                                  // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
	wire         cmd_xbar_demux_001_src0_ready;                                                                    // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
	wire         cmd_xbar_demux_001_src1_endofpacket;                                                              // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
	wire         cmd_xbar_demux_001_src1_valid;                                                                    // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
	wire         cmd_xbar_demux_001_src1_startofpacket;                                                            // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
	wire  [79:0] cmd_xbar_demux_001_src1_data;                                                                     // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
	wire   [5:0] cmd_xbar_demux_001_src1_channel;                                                                  // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
	wire         cmd_xbar_demux_001_src1_ready;                                                                    // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
	wire         cmd_xbar_demux_001_src2_endofpacket;                                                              // cmd_xbar_demux_001:src2_endofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_001_src2_valid;                                                                    // cmd_xbar_demux_001:src2_valid -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_001_src2_startofpacket;                                                            // cmd_xbar_demux_001:src2_startofpacket -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [79:0] cmd_xbar_demux_001_src2_data;                                                                     // cmd_xbar_demux_001:src2_data -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_001_src2_channel;                                                                  // cmd_xbar_demux_001:src2_channel -> jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_001_src4_endofpacket;                                                              // cmd_xbar_demux_001:src4_endofpacket -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_001_src4_valid;                                                                    // cmd_xbar_demux_001:src4_valid -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_001_src4_startofpacket;                                                            // cmd_xbar_demux_001:src4_startofpacket -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [79:0] cmd_xbar_demux_001_src4_data;                                                                     // cmd_xbar_demux_001:src4_data -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_001_src4_channel;                                                                  // cmd_xbar_demux_001:src4_channel -> i2s_tx_slave_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_001_src5_endofpacket;                                                              // cmd_xbar_demux_001:src5_endofpacket -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_001_src5_valid;                                                                    // cmd_xbar_demux_001:src5_valid -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_001_src5_startofpacket;                                                            // cmd_xbar_demux_001:src5_startofpacket -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [79:0] cmd_xbar_demux_001_src5_data;                                                                     // cmd_xbar_demux_001:src5_data -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_001_src5_channel;                                                                  // cmd_xbar_demux_001:src5_channel -> clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:cp_channel
	wire         rsp_xbar_demux_src0_endofpacket;                                                                  // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
	wire         rsp_xbar_demux_src0_valid;                                                                        // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
	wire         rsp_xbar_demux_src0_startofpacket;                                                                // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
	wire  [79:0] rsp_xbar_demux_src0_data;                                                                         // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
	wire   [5:0] rsp_xbar_demux_src0_channel;                                                                      // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
	wire         rsp_xbar_demux_src0_ready;                                                                        // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
	wire         rsp_xbar_demux_src1_endofpacket;                                                                  // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
	wire         rsp_xbar_demux_src1_valid;                                                                        // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
	wire         rsp_xbar_demux_src1_startofpacket;                                                                // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
	wire  [79:0] rsp_xbar_demux_src1_data;                                                                         // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
	wire   [5:0] rsp_xbar_demux_src1_channel;                                                                      // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
	wire         rsp_xbar_demux_src1_ready;                                                                        // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
	wire         rsp_xbar_demux_001_src0_endofpacket;                                                              // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
	wire         rsp_xbar_demux_001_src0_valid;                                                                    // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
	wire         rsp_xbar_demux_001_src0_startofpacket;                                                            // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
	wire  [79:0] rsp_xbar_demux_001_src0_data;                                                                     // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
	wire   [5:0] rsp_xbar_demux_001_src0_channel;                                                                  // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
	wire         rsp_xbar_demux_001_src0_ready;                                                                    // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
	wire         rsp_xbar_demux_001_src1_endofpacket;                                                              // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
	wire         rsp_xbar_demux_001_src1_valid;                                                                    // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
	wire         rsp_xbar_demux_001_src1_startofpacket;                                                            // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
	wire  [79:0] rsp_xbar_demux_001_src1_data;                                                                     // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
	wire   [5:0] rsp_xbar_demux_001_src1_channel;                                                                  // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
	wire         rsp_xbar_demux_001_src1_ready;                                                                    // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
	wire         rsp_xbar_demux_002_src0_endofpacket;                                                              // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
	wire         rsp_xbar_demux_002_src0_valid;                                                                    // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid
	wire         rsp_xbar_demux_002_src0_startofpacket;                                                            // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
	wire  [79:0] rsp_xbar_demux_002_src0_data;                                                                     // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data
	wire   [5:0] rsp_xbar_demux_002_src0_channel;                                                                  // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel
	wire         rsp_xbar_demux_002_src0_ready;                                                                    // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready
	wire         rsp_xbar_demux_004_src0_endofpacket;                                                              // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
	wire         rsp_xbar_demux_004_src0_valid;                                                                    // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
	wire         rsp_xbar_demux_004_src0_startofpacket;                                                            // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
	wire  [79:0] rsp_xbar_demux_004_src0_data;                                                                     // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
	wire   [5:0] rsp_xbar_demux_004_src0_channel;                                                                  // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
	wire         rsp_xbar_demux_004_src0_ready;                                                                    // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
	wire         rsp_xbar_demux_005_src0_endofpacket;                                                              // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
	wire         rsp_xbar_demux_005_src0_valid;                                                                    // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
	wire         rsp_xbar_demux_005_src0_startofpacket;                                                            // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
	wire  [79:0] rsp_xbar_demux_005_src0_data;                                                                     // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
	wire   [5:0] rsp_xbar_demux_005_src0_channel;                                                                  // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
	wire         rsp_xbar_demux_005_src0_ready;                                                                    // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
	wire         limiter_cmd_src_endofpacket;                                                                      // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire         limiter_cmd_src_startofpacket;                                                                    // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [79:0] limiter_cmd_src_data;                                                                             // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
	wire   [5:0] limiter_cmd_src_channel;                                                                          // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
	wire         limiter_cmd_src_ready;                                                                            // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
	wire         rsp_xbar_mux_src_endofpacket;                                                                     // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
	wire         rsp_xbar_mux_src_valid;                                                                           // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
	wire         rsp_xbar_mux_src_startofpacket;                                                                   // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
	wire  [79:0] rsp_xbar_mux_src_data;                                                                            // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
	wire   [5:0] rsp_xbar_mux_src_channel;                                                                         // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
	wire         rsp_xbar_mux_src_ready;                                                                           // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
	wire         limiter_001_cmd_src_endofpacket;                                                                  // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire         limiter_001_cmd_src_startofpacket;                                                                // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire  [79:0] limiter_001_cmd_src_data;                                                                         // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
	wire   [5:0] limiter_001_cmd_src_channel;                                                                      // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
	wire         limiter_001_cmd_src_ready;                                                                        // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
	wire         rsp_xbar_mux_001_src_endofpacket;                                                                 // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
	wire         rsp_xbar_mux_001_src_valid;                                                                       // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
	wire         rsp_xbar_mux_001_src_startofpacket;                                                               // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
	wire  [79:0] rsp_xbar_mux_001_src_data;                                                                        // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
	wire   [5:0] rsp_xbar_mux_001_src_channel;                                                                     // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
	wire         rsp_xbar_mux_001_src_ready;                                                                       // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
	wire         cmd_xbar_mux_src_endofpacket;                                                                     // cmd_xbar_mux:src_endofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_mux_src_valid;                                                                           // cmd_xbar_mux:src_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_mux_src_startofpacket;                                                                   // cmd_xbar_mux:src_startofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [79:0] cmd_xbar_mux_src_data;                                                                            // cmd_xbar_mux:src_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_mux_src_channel;                                                                         // cmd_xbar_mux:src_channel -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_mux_src_ready;                                                                           // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
	wire         id_router_src_endofpacket;                                                                        // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire         id_router_src_valid;                                                                              // id_router:src_valid -> rsp_xbar_demux:sink_valid
	wire         id_router_src_startofpacket;                                                                      // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [79:0] id_router_src_data;                                                                               // id_router:src_data -> rsp_xbar_demux:sink_data
	wire   [5:0] id_router_src_channel;                                                                            // id_router:src_channel -> rsp_xbar_demux:sink_channel
	wire         id_router_src_ready;                                                                              // rsp_xbar_demux:sink_ready -> id_router:src_ready
	wire         cmd_xbar_mux_001_src_endofpacket;                                                                 // cmd_xbar_mux_001:src_endofpacket -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_mux_001_src_valid;                                                                       // cmd_xbar_mux_001:src_valid -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_mux_001_src_startofpacket;                                                               // cmd_xbar_mux_001:src_startofpacket -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [79:0] cmd_xbar_mux_001_src_data;                                                                        // cmd_xbar_mux_001:src_data -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_mux_001_src_channel;                                                                     // cmd_xbar_mux_001:src_channel -> onchip_memory2_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_mux_001_src_ready;                                                                       // onchip_memory2_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
	wire         id_router_001_src_endofpacket;                                                                    // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
	wire         id_router_001_src_valid;                                                                          // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
	wire         id_router_001_src_startofpacket;                                                                  // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
	wire  [79:0] id_router_001_src_data;                                                                           // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
	wire   [5:0] id_router_001_src_channel;                                                                        // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
	wire         id_router_001_src_ready;                                                                          // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
	wire         cmd_xbar_demux_001_src2_ready;                                                                    // jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready
	wire         id_router_002_src_endofpacket;                                                                    // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
	wire         id_router_002_src_valid;                                                                          // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
	wire         id_router_002_src_startofpacket;                                                                  // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
	wire  [79:0] id_router_002_src_data;                                                                           // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
	wire   [5:0] id_router_002_src_channel;                                                                        // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
	wire         id_router_002_src_ready;                                                                          // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
	wire         crosser_out_ready;                                                                                // pll_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
	wire         id_router_003_src_endofpacket;                                                                    // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
	wire         id_router_003_src_valid;                                                                          // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
	wire         id_router_003_src_startofpacket;                                                                  // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
	wire  [79:0] id_router_003_src_data;                                                                           // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
	wire   [5:0] id_router_003_src_channel;                                                                        // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
	wire         id_router_003_src_ready;                                                                          // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
	wire         cmd_xbar_demux_001_src4_ready;                                                                    // i2s_tx_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
	wire         id_router_004_src_endofpacket;                                                                    // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
	wire         id_router_004_src_valid;                                                                          // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
	wire         id_router_004_src_startofpacket;                                                                  // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
	wire  [79:0] id_router_004_src_data;                                                                           // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
	wire   [5:0] id_router_004_src_channel;                                                                        // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
	wire         id_router_004_src_ready;                                                                          // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
	wire         cmd_xbar_demux_001_src5_ready;                                                                    // clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
	wire         id_router_005_src_endofpacket;                                                                    // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
	wire         id_router_005_src_valid;                                                                          // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
	wire         id_router_005_src_startofpacket;                                                                  // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
	wire  [79:0] id_router_005_src_data;                                                                           // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
	wire   [5:0] id_router_005_src_channel;                                                                        // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
	wire         id_router_005_src_ready;                                                                          // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
	wire         cmd_xbar_demux_002_src0_endofpacket;                                                              // cmd_xbar_demux_002:src0_endofpacket -> timer_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src0_valid;                                                                    // cmd_xbar_demux_002:src0_valid -> timer_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src0_startofpacket;                                                            // cmd_xbar_demux_002:src0_startofpacket -> timer_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src0_data;                                                                     // cmd_xbar_demux_002:src0_data -> timer_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src0_channel;                                                                  // cmd_xbar_demux_002:src0_channel -> timer_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src1_endofpacket;                                                              // cmd_xbar_demux_002:src1_endofpacket -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src1_valid;                                                                    // cmd_xbar_demux_002:src1_valid -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src1_startofpacket;                                                            // cmd_xbar_demux_002:src1_startofpacket -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src1_data;                                                                     // cmd_xbar_demux_002:src1_data -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src1_channel;                                                                  // cmd_xbar_demux_002:src1_channel -> hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src2_endofpacket;                                                              // cmd_xbar_demux_002:src2_endofpacket -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src2_valid;                                                                    // cmd_xbar_demux_002:src2_valid -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src2_startofpacket;                                                            // cmd_xbar_demux_002:src2_startofpacket -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src2_data;                                                                     // cmd_xbar_demux_002:src2_data -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src2_channel;                                                                  // cmd_xbar_demux_002:src2_channel -> hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src3_endofpacket;                                                              // cmd_xbar_demux_002:src3_endofpacket -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src3_valid;                                                                    // cmd_xbar_demux_002:src3_valid -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src3_startofpacket;                                                            // cmd_xbar_demux_002:src3_startofpacket -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src3_data;                                                                     // cmd_xbar_demux_002:src3_data -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src3_channel;                                                                  // cmd_xbar_demux_002:src3_channel -> hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src4_endofpacket;                                                              // cmd_xbar_demux_002:src4_endofpacket -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src4_valid;                                                                    // cmd_xbar_demux_002:src4_valid -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src4_startofpacket;                                                            // cmd_xbar_demux_002:src4_startofpacket -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src4_data;                                                                     // cmd_xbar_demux_002:src4_data -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src4_channel;                                                                  // cmd_xbar_demux_002:src4_channel -> hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src5_endofpacket;                                                              // cmd_xbar_demux_002:src5_endofpacket -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src5_valid;                                                                    // cmd_xbar_demux_002:src5_valid -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src5_startofpacket;                                                            // cmd_xbar_demux_002:src5_startofpacket -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src5_data;                                                                     // cmd_xbar_demux_002:src5_data -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src5_channel;                                                                  // cmd_xbar_demux_002:src5_channel -> hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src6_endofpacket;                                                              // cmd_xbar_demux_002:src6_endofpacket -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src6_valid;                                                                    // cmd_xbar_demux_002:src6_valid -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src6_startofpacket;                                                            // cmd_xbar_demux_002:src6_startofpacket -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src6_data;                                                                     // cmd_xbar_demux_002:src6_data -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src6_channel;                                                                  // cmd_xbar_demux_002:src6_channel -> hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src7_endofpacket;                                                              // cmd_xbar_demux_002:src7_endofpacket -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src7_valid;                                                                    // cmd_xbar_demux_002:src7_valid -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src7_startofpacket;                                                            // cmd_xbar_demux_002:src7_startofpacket -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src7_data;                                                                     // cmd_xbar_demux_002:src7_data -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src7_channel;                                                                  // cmd_xbar_demux_002:src7_channel -> hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src8_endofpacket;                                                              // cmd_xbar_demux_002:src8_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src8_valid;                                                                    // cmd_xbar_demux_002:src8_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src8_startofpacket;                                                            // cmd_xbar_demux_002:src8_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src8_data;                                                                     // cmd_xbar_demux_002:src8_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src8_channel;                                                                  // cmd_xbar_demux_002:src8_channel -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src9_endofpacket;                                                              // cmd_xbar_demux_002:src9_endofpacket -> pio_button_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src9_valid;                                                                    // cmd_xbar_demux_002:src9_valid -> pio_button_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src9_startofpacket;                                                            // cmd_xbar_demux_002:src9_startofpacket -> pio_button_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src9_data;                                                                     // cmd_xbar_demux_002:src9_data -> pio_button_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src9_channel;                                                                  // cmd_xbar_demux_002:src9_channel -> pio_button_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src10_endofpacket;                                                             // cmd_xbar_demux_002:src10_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src10_valid;                                                                   // cmd_xbar_demux_002:src10_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src10_startofpacket;                                                           // cmd_xbar_demux_002:src10_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src10_data;                                                                    // cmd_xbar_demux_002:src10_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src10_channel;                                                                 // cmd_xbar_demux_002:src10_channel -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src11_endofpacket;                                                             // cmd_xbar_demux_002:src11_endofpacket -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src11_valid;                                                                   // cmd_xbar_demux_002:src11_valid -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src11_startofpacket;                                                           // cmd_xbar_demux_002:src11_startofpacket -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src11_data;                                                                    // cmd_xbar_demux_002:src11_data -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src11_channel;                                                                 // cmd_xbar_demux_002:src11_channel -> hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src12_endofpacket;                                                             // cmd_xbar_demux_002:src12_endofpacket -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src12_valid;                                                                   // cmd_xbar_demux_002:src12_valid -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src12_startofpacket;                                                           // cmd_xbar_demux_002:src12_startofpacket -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src12_data;                                                                    // cmd_xbar_demux_002:src12_data -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src12_channel;                                                                 // cmd_xbar_demux_002:src12_channel -> hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src13_endofpacket;                                                             // cmd_xbar_demux_002:src13_endofpacket -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src13_valid;                                                                   // cmd_xbar_demux_002:src13_valid -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src13_startofpacket;                                                           // cmd_xbar_demux_002:src13_startofpacket -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src13_data;                                                                    // cmd_xbar_demux_002:src13_data -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src13_channel;                                                                 // cmd_xbar_demux_002:src13_channel -> hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src14_endofpacket;                                                             // cmd_xbar_demux_002:src14_endofpacket -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src14_valid;                                                                   // cmd_xbar_demux_002:src14_valid -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src14_startofpacket;                                                           // cmd_xbar_demux_002:src14_startofpacket -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src14_data;                                                                    // cmd_xbar_demux_002:src14_data -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src14_channel;                                                                 // cmd_xbar_demux_002:src14_channel -> hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src15_endofpacket;                                                             // cmd_xbar_demux_002:src15_endofpacket -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src15_valid;                                                                   // cmd_xbar_demux_002:src15_valid -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src15_startofpacket;                                                           // cmd_xbar_demux_002:src15_startofpacket -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src15_data;                                                                    // cmd_xbar_demux_002:src15_data -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src15_channel;                                                                 // cmd_xbar_demux_002:src15_channel -> hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src16_endofpacket;                                                             // cmd_xbar_demux_002:src16_endofpacket -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src16_valid;                                                                   // cmd_xbar_demux_002:src16_valid -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src16_startofpacket;                                                           // cmd_xbar_demux_002:src16_startofpacket -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src16_data;                                                                    // cmd_xbar_demux_002:src16_data -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src16_channel;                                                                 // cmd_xbar_demux_002:src16_channel -> hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src17_endofpacket;                                                             // cmd_xbar_demux_002:src17_endofpacket -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src17_valid;                                                                   // cmd_xbar_demux_002:src17_valid -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src17_startofpacket;                                                           // cmd_xbar_demux_002:src17_startofpacket -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src17_data;                                                                    // cmd_xbar_demux_002:src17_data -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src17_channel;                                                                 // cmd_xbar_demux_002:src17_channel -> hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src18_endofpacket;                                                             // cmd_xbar_demux_002:src18_endofpacket -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src18_valid;                                                                   // cmd_xbar_demux_002:src18_valid -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src18_startofpacket;                                                           // cmd_xbar_demux_002:src18_startofpacket -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src18_data;                                                                    // cmd_xbar_demux_002:src18_data -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src18_channel;                                                                 // cmd_xbar_demux_002:src18_channel -> hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src19_endofpacket;                                                             // cmd_xbar_demux_002:src19_endofpacket -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src19_valid;                                                                   // cmd_xbar_demux_002:src19_valid -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src19_startofpacket;                                                           // cmd_xbar_demux_002:src19_startofpacket -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src19_data;                                                                    // cmd_xbar_demux_002:src19_data -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src19_channel;                                                                 // cmd_xbar_demux_002:src19_channel -> hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src20_endofpacket;                                                             // cmd_xbar_demux_002:src20_endofpacket -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src20_valid;                                                                   // cmd_xbar_demux_002:src20_valid -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src20_startofpacket;                                                           // cmd_xbar_demux_002:src20_startofpacket -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src20_data;                                                                    // cmd_xbar_demux_002:src20_data -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src20_channel;                                                                 // cmd_xbar_demux_002:src20_channel -> hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src21_endofpacket;                                                             // cmd_xbar_demux_002:src21_endofpacket -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src21_valid;                                                                   // cmd_xbar_demux_002:src21_valid -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src21_startofpacket;                                                           // cmd_xbar_demux_002:src21_startofpacket -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src21_data;                                                                    // cmd_xbar_demux_002:src21_data -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src21_channel;                                                                 // cmd_xbar_demux_002:src21_channel -> hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_002_src22_endofpacket;                                                             // cmd_xbar_demux_002:src22_endofpacket -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_002_src22_valid;                                                                   // cmd_xbar_demux_002:src22_valid -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_002_src22_startofpacket;                                                           // cmd_xbar_demux_002:src22_startofpacket -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [67:0] cmd_xbar_demux_002_src22_data;                                                                    // cmd_xbar_demux_002:src22_data -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire  [22:0] cmd_xbar_demux_002_src22_channel;                                                                 // cmd_xbar_demux_002:src22_channel -> hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         rsp_xbar_demux_006_src0_endofpacket;                                                              // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_002:sink0_endofpacket
	wire         rsp_xbar_demux_006_src0_valid;                                                                    // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_002:sink0_valid
	wire         rsp_xbar_demux_006_src0_startofpacket;                                                            // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_002:sink0_startofpacket
	wire  [67:0] rsp_xbar_demux_006_src0_data;                                                                     // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_002:sink0_data
	wire  [22:0] rsp_xbar_demux_006_src0_channel;                                                                  // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_002:sink0_channel
	wire         rsp_xbar_demux_006_src0_ready;                                                                    // rsp_xbar_mux_002:sink0_ready -> rsp_xbar_demux_006:src0_ready
	wire         rsp_xbar_demux_007_src0_endofpacket;                                                              // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_002:sink1_endofpacket
	wire         rsp_xbar_demux_007_src0_valid;                                                                    // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_002:sink1_valid
	wire         rsp_xbar_demux_007_src0_startofpacket;                                                            // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_002:sink1_startofpacket
	wire  [67:0] rsp_xbar_demux_007_src0_data;                                                                     // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_002:sink1_data
	wire  [22:0] rsp_xbar_demux_007_src0_channel;                                                                  // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_002:sink1_channel
	wire         rsp_xbar_demux_007_src0_ready;                                                                    // rsp_xbar_mux_002:sink1_ready -> rsp_xbar_demux_007:src0_ready
	wire         rsp_xbar_demux_008_src0_endofpacket;                                                              // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_002:sink2_endofpacket
	wire         rsp_xbar_demux_008_src0_valid;                                                                    // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_002:sink2_valid
	wire         rsp_xbar_demux_008_src0_startofpacket;                                                            // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_002:sink2_startofpacket
	wire  [67:0] rsp_xbar_demux_008_src0_data;                                                                     // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_002:sink2_data
	wire  [22:0] rsp_xbar_demux_008_src0_channel;                                                                  // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_002:sink2_channel
	wire         rsp_xbar_demux_008_src0_ready;                                                                    // rsp_xbar_mux_002:sink2_ready -> rsp_xbar_demux_008:src0_ready
	wire         rsp_xbar_demux_009_src0_endofpacket;                                                              // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_002:sink3_endofpacket
	wire         rsp_xbar_demux_009_src0_valid;                                                                    // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_002:sink3_valid
	wire         rsp_xbar_demux_009_src0_startofpacket;                                                            // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_002:sink3_startofpacket
	wire  [67:0] rsp_xbar_demux_009_src0_data;                                                                     // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_002:sink3_data
	wire  [22:0] rsp_xbar_demux_009_src0_channel;                                                                  // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_002:sink3_channel
	wire         rsp_xbar_demux_009_src0_ready;                                                                    // rsp_xbar_mux_002:sink3_ready -> rsp_xbar_demux_009:src0_ready
	wire         rsp_xbar_demux_010_src0_endofpacket;                                                              // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_002:sink4_endofpacket
	wire         rsp_xbar_demux_010_src0_valid;                                                                    // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_002:sink4_valid
	wire         rsp_xbar_demux_010_src0_startofpacket;                                                            // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_002:sink4_startofpacket
	wire  [67:0] rsp_xbar_demux_010_src0_data;                                                                     // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_002:sink4_data
	wire  [22:0] rsp_xbar_demux_010_src0_channel;                                                                  // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_002:sink4_channel
	wire         rsp_xbar_demux_010_src0_ready;                                                                    // rsp_xbar_mux_002:sink4_ready -> rsp_xbar_demux_010:src0_ready
	wire         rsp_xbar_demux_011_src0_endofpacket;                                                              // rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_002:sink5_endofpacket
	wire         rsp_xbar_demux_011_src0_valid;                                                                    // rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_002:sink5_valid
	wire         rsp_xbar_demux_011_src0_startofpacket;                                                            // rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_002:sink5_startofpacket
	wire  [67:0] rsp_xbar_demux_011_src0_data;                                                                     // rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_002:sink5_data
	wire  [22:0] rsp_xbar_demux_011_src0_channel;                                                                  // rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_002:sink5_channel
	wire         rsp_xbar_demux_011_src0_ready;                                                                    // rsp_xbar_mux_002:sink5_ready -> rsp_xbar_demux_011:src0_ready
	wire         rsp_xbar_demux_012_src0_endofpacket;                                                              // rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_002:sink6_endofpacket
	wire         rsp_xbar_demux_012_src0_valid;                                                                    // rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_002:sink6_valid
	wire         rsp_xbar_demux_012_src0_startofpacket;                                                            // rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_002:sink6_startofpacket
	wire  [67:0] rsp_xbar_demux_012_src0_data;                                                                     // rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_002:sink6_data
	wire  [22:0] rsp_xbar_demux_012_src0_channel;                                                                  // rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_002:sink6_channel
	wire         rsp_xbar_demux_012_src0_ready;                                                                    // rsp_xbar_mux_002:sink6_ready -> rsp_xbar_demux_012:src0_ready
	wire         rsp_xbar_demux_013_src0_endofpacket;                                                              // rsp_xbar_demux_013:src0_endofpacket -> rsp_xbar_mux_002:sink7_endofpacket
	wire         rsp_xbar_demux_013_src0_valid;                                                                    // rsp_xbar_demux_013:src0_valid -> rsp_xbar_mux_002:sink7_valid
	wire         rsp_xbar_demux_013_src0_startofpacket;                                                            // rsp_xbar_demux_013:src0_startofpacket -> rsp_xbar_mux_002:sink7_startofpacket
	wire  [67:0] rsp_xbar_demux_013_src0_data;                                                                     // rsp_xbar_demux_013:src0_data -> rsp_xbar_mux_002:sink7_data
	wire  [22:0] rsp_xbar_demux_013_src0_channel;                                                                  // rsp_xbar_demux_013:src0_channel -> rsp_xbar_mux_002:sink7_channel
	wire         rsp_xbar_demux_013_src0_ready;                                                                    // rsp_xbar_mux_002:sink7_ready -> rsp_xbar_demux_013:src0_ready
	wire         rsp_xbar_demux_014_src0_endofpacket;                                                              // rsp_xbar_demux_014:src0_endofpacket -> rsp_xbar_mux_002:sink8_endofpacket
	wire         rsp_xbar_demux_014_src0_valid;                                                                    // rsp_xbar_demux_014:src0_valid -> rsp_xbar_mux_002:sink8_valid
	wire         rsp_xbar_demux_014_src0_startofpacket;                                                            // rsp_xbar_demux_014:src0_startofpacket -> rsp_xbar_mux_002:sink8_startofpacket
	wire  [67:0] rsp_xbar_demux_014_src0_data;                                                                     // rsp_xbar_demux_014:src0_data -> rsp_xbar_mux_002:sink8_data
	wire  [22:0] rsp_xbar_demux_014_src0_channel;                                                                  // rsp_xbar_demux_014:src0_channel -> rsp_xbar_mux_002:sink8_channel
	wire         rsp_xbar_demux_014_src0_ready;                                                                    // rsp_xbar_mux_002:sink8_ready -> rsp_xbar_demux_014:src0_ready
	wire         rsp_xbar_demux_015_src0_endofpacket;                                                              // rsp_xbar_demux_015:src0_endofpacket -> rsp_xbar_mux_002:sink9_endofpacket
	wire         rsp_xbar_demux_015_src0_valid;                                                                    // rsp_xbar_demux_015:src0_valid -> rsp_xbar_mux_002:sink9_valid
	wire         rsp_xbar_demux_015_src0_startofpacket;                                                            // rsp_xbar_demux_015:src0_startofpacket -> rsp_xbar_mux_002:sink9_startofpacket
	wire  [67:0] rsp_xbar_demux_015_src0_data;                                                                     // rsp_xbar_demux_015:src0_data -> rsp_xbar_mux_002:sink9_data
	wire  [22:0] rsp_xbar_demux_015_src0_channel;                                                                  // rsp_xbar_demux_015:src0_channel -> rsp_xbar_mux_002:sink9_channel
	wire         rsp_xbar_demux_015_src0_ready;                                                                    // rsp_xbar_mux_002:sink9_ready -> rsp_xbar_demux_015:src0_ready
	wire         rsp_xbar_demux_016_src0_endofpacket;                                                              // rsp_xbar_demux_016:src0_endofpacket -> rsp_xbar_mux_002:sink10_endofpacket
	wire         rsp_xbar_demux_016_src0_valid;                                                                    // rsp_xbar_demux_016:src0_valid -> rsp_xbar_mux_002:sink10_valid
	wire         rsp_xbar_demux_016_src0_startofpacket;                                                            // rsp_xbar_demux_016:src0_startofpacket -> rsp_xbar_mux_002:sink10_startofpacket
	wire  [67:0] rsp_xbar_demux_016_src0_data;                                                                     // rsp_xbar_demux_016:src0_data -> rsp_xbar_mux_002:sink10_data
	wire  [22:0] rsp_xbar_demux_016_src0_channel;                                                                  // rsp_xbar_demux_016:src0_channel -> rsp_xbar_mux_002:sink10_channel
	wire         rsp_xbar_demux_016_src0_ready;                                                                    // rsp_xbar_mux_002:sink10_ready -> rsp_xbar_demux_016:src0_ready
	wire         rsp_xbar_demux_017_src0_endofpacket;                                                              // rsp_xbar_demux_017:src0_endofpacket -> rsp_xbar_mux_002:sink11_endofpacket
	wire         rsp_xbar_demux_017_src0_valid;                                                                    // rsp_xbar_demux_017:src0_valid -> rsp_xbar_mux_002:sink11_valid
	wire         rsp_xbar_demux_017_src0_startofpacket;                                                            // rsp_xbar_demux_017:src0_startofpacket -> rsp_xbar_mux_002:sink11_startofpacket
	wire  [67:0] rsp_xbar_demux_017_src0_data;                                                                     // rsp_xbar_demux_017:src0_data -> rsp_xbar_mux_002:sink11_data
	wire  [22:0] rsp_xbar_demux_017_src0_channel;                                                                  // rsp_xbar_demux_017:src0_channel -> rsp_xbar_mux_002:sink11_channel
	wire         rsp_xbar_demux_017_src0_ready;                                                                    // rsp_xbar_mux_002:sink11_ready -> rsp_xbar_demux_017:src0_ready
	wire         rsp_xbar_demux_018_src0_endofpacket;                                                              // rsp_xbar_demux_018:src0_endofpacket -> rsp_xbar_mux_002:sink12_endofpacket
	wire         rsp_xbar_demux_018_src0_valid;                                                                    // rsp_xbar_demux_018:src0_valid -> rsp_xbar_mux_002:sink12_valid
	wire         rsp_xbar_demux_018_src0_startofpacket;                                                            // rsp_xbar_demux_018:src0_startofpacket -> rsp_xbar_mux_002:sink12_startofpacket
	wire  [67:0] rsp_xbar_demux_018_src0_data;                                                                     // rsp_xbar_demux_018:src0_data -> rsp_xbar_mux_002:sink12_data
	wire  [22:0] rsp_xbar_demux_018_src0_channel;                                                                  // rsp_xbar_demux_018:src0_channel -> rsp_xbar_mux_002:sink12_channel
	wire         rsp_xbar_demux_018_src0_ready;                                                                    // rsp_xbar_mux_002:sink12_ready -> rsp_xbar_demux_018:src0_ready
	wire         rsp_xbar_demux_019_src0_endofpacket;                                                              // rsp_xbar_demux_019:src0_endofpacket -> rsp_xbar_mux_002:sink13_endofpacket
	wire         rsp_xbar_demux_019_src0_valid;                                                                    // rsp_xbar_demux_019:src0_valid -> rsp_xbar_mux_002:sink13_valid
	wire         rsp_xbar_demux_019_src0_startofpacket;                                                            // rsp_xbar_demux_019:src0_startofpacket -> rsp_xbar_mux_002:sink13_startofpacket
	wire  [67:0] rsp_xbar_demux_019_src0_data;                                                                     // rsp_xbar_demux_019:src0_data -> rsp_xbar_mux_002:sink13_data
	wire  [22:0] rsp_xbar_demux_019_src0_channel;                                                                  // rsp_xbar_demux_019:src0_channel -> rsp_xbar_mux_002:sink13_channel
	wire         rsp_xbar_demux_019_src0_ready;                                                                    // rsp_xbar_mux_002:sink13_ready -> rsp_xbar_demux_019:src0_ready
	wire         rsp_xbar_demux_020_src0_endofpacket;                                                              // rsp_xbar_demux_020:src0_endofpacket -> rsp_xbar_mux_002:sink14_endofpacket
	wire         rsp_xbar_demux_020_src0_valid;                                                                    // rsp_xbar_demux_020:src0_valid -> rsp_xbar_mux_002:sink14_valid
	wire         rsp_xbar_demux_020_src0_startofpacket;                                                            // rsp_xbar_demux_020:src0_startofpacket -> rsp_xbar_mux_002:sink14_startofpacket
	wire  [67:0] rsp_xbar_demux_020_src0_data;                                                                     // rsp_xbar_demux_020:src0_data -> rsp_xbar_mux_002:sink14_data
	wire  [22:0] rsp_xbar_demux_020_src0_channel;                                                                  // rsp_xbar_demux_020:src0_channel -> rsp_xbar_mux_002:sink14_channel
	wire         rsp_xbar_demux_020_src0_ready;                                                                    // rsp_xbar_mux_002:sink14_ready -> rsp_xbar_demux_020:src0_ready
	wire         rsp_xbar_demux_021_src0_endofpacket;                                                              // rsp_xbar_demux_021:src0_endofpacket -> rsp_xbar_mux_002:sink15_endofpacket
	wire         rsp_xbar_demux_021_src0_valid;                                                                    // rsp_xbar_demux_021:src0_valid -> rsp_xbar_mux_002:sink15_valid
	wire         rsp_xbar_demux_021_src0_startofpacket;                                                            // rsp_xbar_demux_021:src0_startofpacket -> rsp_xbar_mux_002:sink15_startofpacket
	wire  [67:0] rsp_xbar_demux_021_src0_data;                                                                     // rsp_xbar_demux_021:src0_data -> rsp_xbar_mux_002:sink15_data
	wire  [22:0] rsp_xbar_demux_021_src0_channel;                                                                  // rsp_xbar_demux_021:src0_channel -> rsp_xbar_mux_002:sink15_channel
	wire         rsp_xbar_demux_021_src0_ready;                                                                    // rsp_xbar_mux_002:sink15_ready -> rsp_xbar_demux_021:src0_ready
	wire         rsp_xbar_demux_022_src0_endofpacket;                                                              // rsp_xbar_demux_022:src0_endofpacket -> rsp_xbar_mux_002:sink16_endofpacket
	wire         rsp_xbar_demux_022_src0_valid;                                                                    // rsp_xbar_demux_022:src0_valid -> rsp_xbar_mux_002:sink16_valid
	wire         rsp_xbar_demux_022_src0_startofpacket;                                                            // rsp_xbar_demux_022:src0_startofpacket -> rsp_xbar_mux_002:sink16_startofpacket
	wire  [67:0] rsp_xbar_demux_022_src0_data;                                                                     // rsp_xbar_demux_022:src0_data -> rsp_xbar_mux_002:sink16_data
	wire  [22:0] rsp_xbar_demux_022_src0_channel;                                                                  // rsp_xbar_demux_022:src0_channel -> rsp_xbar_mux_002:sink16_channel
	wire         rsp_xbar_demux_022_src0_ready;                                                                    // rsp_xbar_mux_002:sink16_ready -> rsp_xbar_demux_022:src0_ready
	wire         rsp_xbar_demux_023_src0_endofpacket;                                                              // rsp_xbar_demux_023:src0_endofpacket -> rsp_xbar_mux_002:sink17_endofpacket
	wire         rsp_xbar_demux_023_src0_valid;                                                                    // rsp_xbar_demux_023:src0_valid -> rsp_xbar_mux_002:sink17_valid
	wire         rsp_xbar_demux_023_src0_startofpacket;                                                            // rsp_xbar_demux_023:src0_startofpacket -> rsp_xbar_mux_002:sink17_startofpacket
	wire  [67:0] rsp_xbar_demux_023_src0_data;                                                                     // rsp_xbar_demux_023:src0_data -> rsp_xbar_mux_002:sink17_data
	wire  [22:0] rsp_xbar_demux_023_src0_channel;                                                                  // rsp_xbar_demux_023:src0_channel -> rsp_xbar_mux_002:sink17_channel
	wire         rsp_xbar_demux_023_src0_ready;                                                                    // rsp_xbar_mux_002:sink17_ready -> rsp_xbar_demux_023:src0_ready
	wire         rsp_xbar_demux_024_src0_endofpacket;                                                              // rsp_xbar_demux_024:src0_endofpacket -> rsp_xbar_mux_002:sink18_endofpacket
	wire         rsp_xbar_demux_024_src0_valid;                                                                    // rsp_xbar_demux_024:src0_valid -> rsp_xbar_mux_002:sink18_valid
	wire         rsp_xbar_demux_024_src0_startofpacket;                                                            // rsp_xbar_demux_024:src0_startofpacket -> rsp_xbar_mux_002:sink18_startofpacket
	wire  [67:0] rsp_xbar_demux_024_src0_data;                                                                     // rsp_xbar_demux_024:src0_data -> rsp_xbar_mux_002:sink18_data
	wire  [22:0] rsp_xbar_demux_024_src0_channel;                                                                  // rsp_xbar_demux_024:src0_channel -> rsp_xbar_mux_002:sink18_channel
	wire         rsp_xbar_demux_024_src0_ready;                                                                    // rsp_xbar_mux_002:sink18_ready -> rsp_xbar_demux_024:src0_ready
	wire         rsp_xbar_demux_025_src0_endofpacket;                                                              // rsp_xbar_demux_025:src0_endofpacket -> rsp_xbar_mux_002:sink19_endofpacket
	wire         rsp_xbar_demux_025_src0_valid;                                                                    // rsp_xbar_demux_025:src0_valid -> rsp_xbar_mux_002:sink19_valid
	wire         rsp_xbar_demux_025_src0_startofpacket;                                                            // rsp_xbar_demux_025:src0_startofpacket -> rsp_xbar_mux_002:sink19_startofpacket
	wire  [67:0] rsp_xbar_demux_025_src0_data;                                                                     // rsp_xbar_demux_025:src0_data -> rsp_xbar_mux_002:sink19_data
	wire  [22:0] rsp_xbar_demux_025_src0_channel;                                                                  // rsp_xbar_demux_025:src0_channel -> rsp_xbar_mux_002:sink19_channel
	wire         rsp_xbar_demux_025_src0_ready;                                                                    // rsp_xbar_mux_002:sink19_ready -> rsp_xbar_demux_025:src0_ready
	wire         rsp_xbar_demux_026_src0_endofpacket;                                                              // rsp_xbar_demux_026:src0_endofpacket -> rsp_xbar_mux_002:sink20_endofpacket
	wire         rsp_xbar_demux_026_src0_valid;                                                                    // rsp_xbar_demux_026:src0_valid -> rsp_xbar_mux_002:sink20_valid
	wire         rsp_xbar_demux_026_src0_startofpacket;                                                            // rsp_xbar_demux_026:src0_startofpacket -> rsp_xbar_mux_002:sink20_startofpacket
	wire  [67:0] rsp_xbar_demux_026_src0_data;                                                                     // rsp_xbar_demux_026:src0_data -> rsp_xbar_mux_002:sink20_data
	wire  [22:0] rsp_xbar_demux_026_src0_channel;                                                                  // rsp_xbar_demux_026:src0_channel -> rsp_xbar_mux_002:sink20_channel
	wire         rsp_xbar_demux_026_src0_ready;                                                                    // rsp_xbar_mux_002:sink20_ready -> rsp_xbar_demux_026:src0_ready
	wire         rsp_xbar_demux_027_src0_endofpacket;                                                              // rsp_xbar_demux_027:src0_endofpacket -> rsp_xbar_mux_002:sink21_endofpacket
	wire         rsp_xbar_demux_027_src0_valid;                                                                    // rsp_xbar_demux_027:src0_valid -> rsp_xbar_mux_002:sink21_valid
	wire         rsp_xbar_demux_027_src0_startofpacket;                                                            // rsp_xbar_demux_027:src0_startofpacket -> rsp_xbar_mux_002:sink21_startofpacket
	wire  [67:0] rsp_xbar_demux_027_src0_data;                                                                     // rsp_xbar_demux_027:src0_data -> rsp_xbar_mux_002:sink21_data
	wire  [22:0] rsp_xbar_demux_027_src0_channel;                                                                  // rsp_xbar_demux_027:src0_channel -> rsp_xbar_mux_002:sink21_channel
	wire         rsp_xbar_demux_027_src0_ready;                                                                    // rsp_xbar_mux_002:sink21_ready -> rsp_xbar_demux_027:src0_ready
	wire         rsp_xbar_demux_028_src0_endofpacket;                                                              // rsp_xbar_demux_028:src0_endofpacket -> rsp_xbar_mux_002:sink22_endofpacket
	wire         rsp_xbar_demux_028_src0_valid;                                                                    // rsp_xbar_demux_028:src0_valid -> rsp_xbar_mux_002:sink22_valid
	wire         rsp_xbar_demux_028_src0_startofpacket;                                                            // rsp_xbar_demux_028:src0_startofpacket -> rsp_xbar_mux_002:sink22_startofpacket
	wire  [67:0] rsp_xbar_demux_028_src0_data;                                                                     // rsp_xbar_demux_028:src0_data -> rsp_xbar_mux_002:sink22_data
	wire  [22:0] rsp_xbar_demux_028_src0_channel;                                                                  // rsp_xbar_demux_028:src0_channel -> rsp_xbar_mux_002:sink22_channel
	wire         rsp_xbar_demux_028_src0_ready;                                                                    // rsp_xbar_mux_002:sink22_ready -> rsp_xbar_demux_028:src0_ready
	wire         limiter_002_cmd_src_endofpacket;                                                                  // limiter_002:cmd_src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
	wire         limiter_002_cmd_src_startofpacket;                                                                // limiter_002:cmd_src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
	wire  [67:0] limiter_002_cmd_src_data;                                                                         // limiter_002:cmd_src_data -> cmd_xbar_demux_002:sink_data
	wire  [22:0] limiter_002_cmd_src_channel;                                                                      // limiter_002:cmd_src_channel -> cmd_xbar_demux_002:sink_channel
	wire         limiter_002_cmd_src_ready;                                                                        // cmd_xbar_demux_002:sink_ready -> limiter_002:cmd_src_ready
	wire         rsp_xbar_mux_002_src_endofpacket;                                                                 // rsp_xbar_mux_002:src_endofpacket -> limiter_002:rsp_sink_endofpacket
	wire         rsp_xbar_mux_002_src_valid;                                                                       // rsp_xbar_mux_002:src_valid -> limiter_002:rsp_sink_valid
	wire         rsp_xbar_mux_002_src_startofpacket;                                                               // rsp_xbar_mux_002:src_startofpacket -> limiter_002:rsp_sink_startofpacket
	wire  [67:0] rsp_xbar_mux_002_src_data;                                                                        // rsp_xbar_mux_002:src_data -> limiter_002:rsp_sink_data
	wire  [22:0] rsp_xbar_mux_002_src_channel;                                                                     // rsp_xbar_mux_002:src_channel -> limiter_002:rsp_sink_channel
	wire         rsp_xbar_mux_002_src_ready;                                                                       // limiter_002:rsp_sink_ready -> rsp_xbar_mux_002:src_ready
	wire         cmd_xbar_demux_002_src0_ready;                                                                    // timer_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src0_ready
	wire         id_router_006_src_endofpacket;                                                                    // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
	wire         id_router_006_src_valid;                                                                          // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
	wire         id_router_006_src_startofpacket;                                                                  // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
	wire  [67:0] id_router_006_src_data;                                                                           // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
	wire  [22:0] id_router_006_src_channel;                                                                        // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
	wire         id_router_006_src_ready;                                                                          // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
	wire         cmd_xbar_demux_002_src1_ready;                                                                    // hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src1_ready
	wire         id_router_007_src_endofpacket;                                                                    // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
	wire         id_router_007_src_valid;                                                                          // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
	wire         id_router_007_src_startofpacket;                                                                  // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
	wire  [67:0] id_router_007_src_data;                                                                           // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
	wire  [22:0] id_router_007_src_channel;                                                                        // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
	wire         id_router_007_src_ready;                                                                          // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
	wire         cmd_xbar_demux_002_src2_ready;                                                                    // hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src2_ready
	wire         id_router_008_src_endofpacket;                                                                    // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
	wire         id_router_008_src_valid;                                                                          // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
	wire         id_router_008_src_startofpacket;                                                                  // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
	wire  [67:0] id_router_008_src_data;                                                                           // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
	wire  [22:0] id_router_008_src_channel;                                                                        // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
	wire         id_router_008_src_ready;                                                                          // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
	wire         cmd_xbar_demux_002_src3_ready;                                                                    // hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src3_ready
	wire         id_router_009_src_endofpacket;                                                                    // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
	wire         id_router_009_src_valid;                                                                          // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
	wire         id_router_009_src_startofpacket;                                                                  // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
	wire  [67:0] id_router_009_src_data;                                                                           // id_router_009:src_data -> rsp_xbar_demux_009:sink_data
	wire  [22:0] id_router_009_src_channel;                                                                        // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
	wire         id_router_009_src_ready;                                                                          // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
	wire         cmd_xbar_demux_002_src4_ready;                                                                    // hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src4_ready
	wire         id_router_010_src_endofpacket;                                                                    // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
	wire         id_router_010_src_valid;                                                                          // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
	wire         id_router_010_src_startofpacket;                                                                  // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
	wire  [67:0] id_router_010_src_data;                                                                           // id_router_010:src_data -> rsp_xbar_demux_010:sink_data
	wire  [22:0] id_router_010_src_channel;                                                                        // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
	wire         id_router_010_src_ready;                                                                          // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
	wire         cmd_xbar_demux_002_src5_ready;                                                                    // hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src5_ready
	wire         id_router_011_src_endofpacket;                                                                    // id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
	wire         id_router_011_src_valid;                                                                          // id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid
	wire         id_router_011_src_startofpacket;                                                                  // id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
	wire  [67:0] id_router_011_src_data;                                                                           // id_router_011:src_data -> rsp_xbar_demux_011:sink_data
	wire  [22:0] id_router_011_src_channel;                                                                        // id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel
	wire         id_router_011_src_ready;                                                                          // rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready
	wire         cmd_xbar_demux_002_src6_ready;                                                                    // hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src6_ready
	wire         id_router_012_src_endofpacket;                                                                    // id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket
	wire         id_router_012_src_valid;                                                                          // id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid
	wire         id_router_012_src_startofpacket;                                                                  // id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket
	wire  [67:0] id_router_012_src_data;                                                                           // id_router_012:src_data -> rsp_xbar_demux_012:sink_data
	wire  [22:0] id_router_012_src_channel;                                                                        // id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel
	wire         id_router_012_src_ready;                                                                          // rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready
	wire         cmd_xbar_demux_002_src7_ready;                                                                    // hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src7_ready
	wire         id_router_013_src_endofpacket;                                                                    // id_router_013:src_endofpacket -> rsp_xbar_demux_013:sink_endofpacket
	wire         id_router_013_src_valid;                                                                          // id_router_013:src_valid -> rsp_xbar_demux_013:sink_valid
	wire         id_router_013_src_startofpacket;                                                                  // id_router_013:src_startofpacket -> rsp_xbar_demux_013:sink_startofpacket
	wire  [67:0] id_router_013_src_data;                                                                           // id_router_013:src_data -> rsp_xbar_demux_013:sink_data
	wire  [22:0] id_router_013_src_channel;                                                                        // id_router_013:src_channel -> rsp_xbar_demux_013:sink_channel
	wire         id_router_013_src_ready;                                                                          // rsp_xbar_demux_013:sink_ready -> id_router_013:src_ready
	wire         cmd_xbar_demux_002_src8_ready;                                                                    // pio_led_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src8_ready
	wire         id_router_014_src_endofpacket;                                                                    // id_router_014:src_endofpacket -> rsp_xbar_demux_014:sink_endofpacket
	wire         id_router_014_src_valid;                                                                          // id_router_014:src_valid -> rsp_xbar_demux_014:sink_valid
	wire         id_router_014_src_startofpacket;                                                                  // id_router_014:src_startofpacket -> rsp_xbar_demux_014:sink_startofpacket
	wire  [67:0] id_router_014_src_data;                                                                           // id_router_014:src_data -> rsp_xbar_demux_014:sink_data
	wire  [22:0] id_router_014_src_channel;                                                                        // id_router_014:src_channel -> rsp_xbar_demux_014:sink_channel
	wire         id_router_014_src_ready;                                                                          // rsp_xbar_demux_014:sink_ready -> id_router_014:src_ready
	wire         cmd_xbar_demux_002_src9_ready;                                                                    // pio_button_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src9_ready
	wire         id_router_015_src_endofpacket;                                                                    // id_router_015:src_endofpacket -> rsp_xbar_demux_015:sink_endofpacket
	wire         id_router_015_src_valid;                                                                          // id_router_015:src_valid -> rsp_xbar_demux_015:sink_valid
	wire         id_router_015_src_startofpacket;                                                                  // id_router_015:src_startofpacket -> rsp_xbar_demux_015:sink_startofpacket
	wire  [67:0] id_router_015_src_data;                                                                           // id_router_015:src_data -> rsp_xbar_demux_015:sink_data
	wire  [22:0] id_router_015_src_channel;                                                                        // id_router_015:src_channel -> rsp_xbar_demux_015:sink_channel
	wire         id_router_015_src_ready;                                                                          // rsp_xbar_demux_015:sink_ready -> id_router_015:src_ready
	wire         cmd_xbar_demux_002_src10_ready;                                                                   // sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src10_ready
	wire         id_router_016_src_endofpacket;                                                                    // id_router_016:src_endofpacket -> rsp_xbar_demux_016:sink_endofpacket
	wire         id_router_016_src_valid;                                                                          // id_router_016:src_valid -> rsp_xbar_demux_016:sink_valid
	wire         id_router_016_src_startofpacket;                                                                  // id_router_016:src_startofpacket -> rsp_xbar_demux_016:sink_startofpacket
	wire  [67:0] id_router_016_src_data;                                                                           // id_router_016:src_data -> rsp_xbar_demux_016:sink_data
	wire  [22:0] id_router_016_src_channel;                                                                        // id_router_016:src_channel -> rsp_xbar_demux_016:sink_channel
	wire         id_router_016_src_ready;                                                                          // rsp_xbar_demux_016:sink_ready -> id_router_016:src_ready
	wire         cmd_xbar_demux_002_src11_ready;                                                                   // hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src11_ready
	wire         id_router_017_src_endofpacket;                                                                    // id_router_017:src_endofpacket -> rsp_xbar_demux_017:sink_endofpacket
	wire         id_router_017_src_valid;                                                                          // id_router_017:src_valid -> rsp_xbar_demux_017:sink_valid
	wire         id_router_017_src_startofpacket;                                                                  // id_router_017:src_startofpacket -> rsp_xbar_demux_017:sink_startofpacket
	wire  [67:0] id_router_017_src_data;                                                                           // id_router_017:src_data -> rsp_xbar_demux_017:sink_data
	wire  [22:0] id_router_017_src_channel;                                                                        // id_router_017:src_channel -> rsp_xbar_demux_017:sink_channel
	wire         id_router_017_src_ready;                                                                          // rsp_xbar_demux_017:sink_ready -> id_router_017:src_ready
	wire         cmd_xbar_demux_002_src12_ready;                                                                   // hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src12_ready
	wire         id_router_018_src_endofpacket;                                                                    // id_router_018:src_endofpacket -> rsp_xbar_demux_018:sink_endofpacket
	wire         id_router_018_src_valid;                                                                          // id_router_018:src_valid -> rsp_xbar_demux_018:sink_valid
	wire         id_router_018_src_startofpacket;                                                                  // id_router_018:src_startofpacket -> rsp_xbar_demux_018:sink_startofpacket
	wire  [67:0] id_router_018_src_data;                                                                           // id_router_018:src_data -> rsp_xbar_demux_018:sink_data
	wire  [22:0] id_router_018_src_channel;                                                                        // id_router_018:src_channel -> rsp_xbar_demux_018:sink_channel
	wire         id_router_018_src_ready;                                                                          // rsp_xbar_demux_018:sink_ready -> id_router_018:src_ready
	wire         cmd_xbar_demux_002_src13_ready;                                                                   // hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src13_ready
	wire         id_router_019_src_endofpacket;                                                                    // id_router_019:src_endofpacket -> rsp_xbar_demux_019:sink_endofpacket
	wire         id_router_019_src_valid;                                                                          // id_router_019:src_valid -> rsp_xbar_demux_019:sink_valid
	wire         id_router_019_src_startofpacket;                                                                  // id_router_019:src_startofpacket -> rsp_xbar_demux_019:sink_startofpacket
	wire  [67:0] id_router_019_src_data;                                                                           // id_router_019:src_data -> rsp_xbar_demux_019:sink_data
	wire  [22:0] id_router_019_src_channel;                                                                        // id_router_019:src_channel -> rsp_xbar_demux_019:sink_channel
	wire         id_router_019_src_ready;                                                                          // rsp_xbar_demux_019:sink_ready -> id_router_019:src_ready
	wire         cmd_xbar_demux_002_src14_ready;                                                                   // hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src14_ready
	wire         id_router_020_src_endofpacket;                                                                    // id_router_020:src_endofpacket -> rsp_xbar_demux_020:sink_endofpacket
	wire         id_router_020_src_valid;                                                                          // id_router_020:src_valid -> rsp_xbar_demux_020:sink_valid
	wire         id_router_020_src_startofpacket;                                                                  // id_router_020:src_startofpacket -> rsp_xbar_demux_020:sink_startofpacket
	wire  [67:0] id_router_020_src_data;                                                                           // id_router_020:src_data -> rsp_xbar_demux_020:sink_data
	wire  [22:0] id_router_020_src_channel;                                                                        // id_router_020:src_channel -> rsp_xbar_demux_020:sink_channel
	wire         id_router_020_src_ready;                                                                          // rsp_xbar_demux_020:sink_ready -> id_router_020:src_ready
	wire         cmd_xbar_demux_002_src15_ready;                                                                   // hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src15_ready
	wire         id_router_021_src_endofpacket;                                                                    // id_router_021:src_endofpacket -> rsp_xbar_demux_021:sink_endofpacket
	wire         id_router_021_src_valid;                                                                          // id_router_021:src_valid -> rsp_xbar_demux_021:sink_valid
	wire         id_router_021_src_startofpacket;                                                                  // id_router_021:src_startofpacket -> rsp_xbar_demux_021:sink_startofpacket
	wire  [67:0] id_router_021_src_data;                                                                           // id_router_021:src_data -> rsp_xbar_demux_021:sink_data
	wire  [22:0] id_router_021_src_channel;                                                                        // id_router_021:src_channel -> rsp_xbar_demux_021:sink_channel
	wire         id_router_021_src_ready;                                                                          // rsp_xbar_demux_021:sink_ready -> id_router_021:src_ready
	wire         cmd_xbar_demux_002_src16_ready;                                                                   // hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src16_ready
	wire         id_router_022_src_endofpacket;                                                                    // id_router_022:src_endofpacket -> rsp_xbar_demux_022:sink_endofpacket
	wire         id_router_022_src_valid;                                                                          // id_router_022:src_valid -> rsp_xbar_demux_022:sink_valid
	wire         id_router_022_src_startofpacket;                                                                  // id_router_022:src_startofpacket -> rsp_xbar_demux_022:sink_startofpacket
	wire  [67:0] id_router_022_src_data;                                                                           // id_router_022:src_data -> rsp_xbar_demux_022:sink_data
	wire  [22:0] id_router_022_src_channel;                                                                        // id_router_022:src_channel -> rsp_xbar_demux_022:sink_channel
	wire         id_router_022_src_ready;                                                                          // rsp_xbar_demux_022:sink_ready -> id_router_022:src_ready
	wire         cmd_xbar_demux_002_src17_ready;                                                                   // hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src17_ready
	wire         id_router_023_src_endofpacket;                                                                    // id_router_023:src_endofpacket -> rsp_xbar_demux_023:sink_endofpacket
	wire         id_router_023_src_valid;                                                                          // id_router_023:src_valid -> rsp_xbar_demux_023:sink_valid
	wire         id_router_023_src_startofpacket;                                                                  // id_router_023:src_startofpacket -> rsp_xbar_demux_023:sink_startofpacket
	wire  [67:0] id_router_023_src_data;                                                                           // id_router_023:src_data -> rsp_xbar_demux_023:sink_data
	wire  [22:0] id_router_023_src_channel;                                                                        // id_router_023:src_channel -> rsp_xbar_demux_023:sink_channel
	wire         id_router_023_src_ready;                                                                          // rsp_xbar_demux_023:sink_ready -> id_router_023:src_ready
	wire         cmd_xbar_demux_002_src18_ready;                                                                   // hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src18_ready
	wire         id_router_024_src_endofpacket;                                                                    // id_router_024:src_endofpacket -> rsp_xbar_demux_024:sink_endofpacket
	wire         id_router_024_src_valid;                                                                          // id_router_024:src_valid -> rsp_xbar_demux_024:sink_valid
	wire         id_router_024_src_startofpacket;                                                                  // id_router_024:src_startofpacket -> rsp_xbar_demux_024:sink_startofpacket
	wire  [67:0] id_router_024_src_data;                                                                           // id_router_024:src_data -> rsp_xbar_demux_024:sink_data
	wire  [22:0] id_router_024_src_channel;                                                                        // id_router_024:src_channel -> rsp_xbar_demux_024:sink_channel
	wire         id_router_024_src_ready;                                                                          // rsp_xbar_demux_024:sink_ready -> id_router_024:src_ready
	wire         cmd_xbar_demux_002_src19_ready;                                                                   // hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src19_ready
	wire         id_router_025_src_endofpacket;                                                                    // id_router_025:src_endofpacket -> rsp_xbar_demux_025:sink_endofpacket
	wire         id_router_025_src_valid;                                                                          // id_router_025:src_valid -> rsp_xbar_demux_025:sink_valid
	wire         id_router_025_src_startofpacket;                                                                  // id_router_025:src_startofpacket -> rsp_xbar_demux_025:sink_startofpacket
	wire  [67:0] id_router_025_src_data;                                                                           // id_router_025:src_data -> rsp_xbar_demux_025:sink_data
	wire  [22:0] id_router_025_src_channel;                                                                        // id_router_025:src_channel -> rsp_xbar_demux_025:sink_channel
	wire         id_router_025_src_ready;                                                                          // rsp_xbar_demux_025:sink_ready -> id_router_025:src_ready
	wire         cmd_xbar_demux_002_src20_ready;                                                                   // hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src20_ready
	wire         id_router_026_src_endofpacket;                                                                    // id_router_026:src_endofpacket -> rsp_xbar_demux_026:sink_endofpacket
	wire         id_router_026_src_valid;                                                                          // id_router_026:src_valid -> rsp_xbar_demux_026:sink_valid
	wire         id_router_026_src_startofpacket;                                                                  // id_router_026:src_startofpacket -> rsp_xbar_demux_026:sink_startofpacket
	wire  [67:0] id_router_026_src_data;                                                                           // id_router_026:src_data -> rsp_xbar_demux_026:sink_data
	wire  [22:0] id_router_026_src_channel;                                                                        // id_router_026:src_channel -> rsp_xbar_demux_026:sink_channel
	wire         id_router_026_src_ready;                                                                          // rsp_xbar_demux_026:sink_ready -> id_router_026:src_ready
	wire         cmd_xbar_demux_002_src21_ready;                                                                   // hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src21_ready
	wire         id_router_027_src_endofpacket;                                                                    // id_router_027:src_endofpacket -> rsp_xbar_demux_027:sink_endofpacket
	wire         id_router_027_src_valid;                                                                          // id_router_027:src_valid -> rsp_xbar_demux_027:sink_valid
	wire         id_router_027_src_startofpacket;                                                                  // id_router_027:src_startofpacket -> rsp_xbar_demux_027:sink_startofpacket
	wire  [67:0] id_router_027_src_data;                                                                           // id_router_027:src_data -> rsp_xbar_demux_027:sink_data
	wire  [22:0] id_router_027_src_channel;                                                                        // id_router_027:src_channel -> rsp_xbar_demux_027:sink_channel
	wire         id_router_027_src_ready;                                                                          // rsp_xbar_demux_027:sink_ready -> id_router_027:src_ready
	wire         cmd_xbar_demux_002_src22_ready;                                                                   // hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_002:src22_ready
	wire         id_router_028_src_endofpacket;                                                                    // id_router_028:src_endofpacket -> rsp_xbar_demux_028:sink_endofpacket
	wire         id_router_028_src_valid;                                                                          // id_router_028:src_valid -> rsp_xbar_demux_028:sink_valid
	wire         id_router_028_src_startofpacket;                                                                  // id_router_028:src_startofpacket -> rsp_xbar_demux_028:sink_startofpacket
	wire  [67:0] id_router_028_src_data;                                                                           // id_router_028:src_data -> rsp_xbar_demux_028:sink_data
	wire  [22:0] id_router_028_src_channel;                                                                        // id_router_028:src_channel -> rsp_xbar_demux_028:sink_channel
	wire         id_router_028_src_ready;                                                                          // rsp_xbar_demux_028:sink_ready -> id_router_028:src_ready
	wire         crosser_out_endofpacket;                                                                          // crosser:out_endofpacket -> pll_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         crosser_out_valid;                                                                                // crosser:out_valid -> pll_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid
	wire         crosser_out_startofpacket;                                                                        // crosser:out_startofpacket -> pll_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [79:0] crosser_out_data;                                                                                 // crosser:out_data -> pll_pll_slave_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] crosser_out_channel;                                                                              // crosser:out_channel -> pll_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_001_src3_endofpacket;                                                              // cmd_xbar_demux_001:src3_endofpacket -> crosser:in_endofpacket
	wire         cmd_xbar_demux_001_src3_valid;                                                                    // cmd_xbar_demux_001:src3_valid -> crosser:in_valid
	wire         cmd_xbar_demux_001_src3_startofpacket;                                                            // cmd_xbar_demux_001:src3_startofpacket -> crosser:in_startofpacket
	wire  [79:0] cmd_xbar_demux_001_src3_data;                                                                     // cmd_xbar_demux_001:src3_data -> crosser:in_data
	wire   [5:0] cmd_xbar_demux_001_src3_channel;                                                                  // cmd_xbar_demux_001:src3_channel -> crosser:in_channel
	wire         cmd_xbar_demux_001_src3_ready;                                                                    // crosser:in_ready -> cmd_xbar_demux_001:src3_ready
	wire         crosser_001_out_endofpacket;                                                                      // crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
	wire         crosser_001_out_valid;                                                                            // crosser_001:out_valid -> rsp_xbar_mux_001:sink3_valid
	wire         crosser_001_out_startofpacket;                                                                    // crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
	wire  [79:0] crosser_001_out_data;                                                                             // crosser_001:out_data -> rsp_xbar_mux_001:sink3_data
	wire   [5:0] crosser_001_out_channel;                                                                          // crosser_001:out_channel -> rsp_xbar_mux_001:sink3_channel
	wire         crosser_001_out_ready;                                                                            // rsp_xbar_mux_001:sink3_ready -> crosser_001:out_ready
	wire         rsp_xbar_demux_003_src0_endofpacket;                                                              // rsp_xbar_demux_003:src0_endofpacket -> crosser_001:in_endofpacket
	wire         rsp_xbar_demux_003_src0_valid;                                                                    // rsp_xbar_demux_003:src0_valid -> crosser_001:in_valid
	wire         rsp_xbar_demux_003_src0_startofpacket;                                                            // rsp_xbar_demux_003:src0_startofpacket -> crosser_001:in_startofpacket
	wire  [79:0] rsp_xbar_demux_003_src0_data;                                                                     // rsp_xbar_demux_003:src0_data -> crosser_001:in_data
	wire   [5:0] rsp_xbar_demux_003_src0_channel;                                                                  // rsp_xbar_demux_003:src0_channel -> crosser_001:in_channel
	wire         rsp_xbar_demux_003_src0_ready;                                                                    // crosser_001:in_ready -> rsp_xbar_demux_003:src0_ready
	wire   [5:0] limiter_cmd_valid_data;                                                                           // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
	wire   [5:0] limiter_001_cmd_valid_data;                                                                       // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
	wire  [22:0] limiter_002_cmd_valid_data;                                                                       // limiter_002:cmd_src_valid -> cmd_xbar_demux_002:sink_valid
	wire         irq_mapper_receiver0_irq;                                                                         // jtag_uart:av_irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver4_irq;                                                                         // i2s_tx:s_irq -> irq_mapper:receiver4_irq
	wire  [31:0] cpu_d_irq_irq;                                                                                    // irq_mapper:sender_irq -> cpu:d_irq
	wire         irq_mapper_receiver1_irq;                                                                         // irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
	wire   [0:0] irq_synchronizer_receiver_irq;                                                                    // timer:irq -> irq_synchronizer:receiver_irq
	wire         irq_mapper_receiver2_irq;                                                                         // irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq
	wire   [0:0] irq_synchronizer_001_receiver_irq;                                                                // hdmi_tx_irq_n:irq -> irq_synchronizer_001:receiver_irq
	wire         irq_mapper_receiver3_irq;                                                                         // irq_synchronizer_002:sender_irq -> irq_mapper:receiver3_irq
	wire   [0:0] irq_synchronizer_002_receiver_irq;                                                                // pio_button:irq -> irq_synchronizer_002:receiver_irq

	TR4_HDMI_TX_RX_SOPC_jtag_uart jtag_uart (
		.clk            (pll_cpu),                                                                //               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                                        //             reset.reset_n
		.av_chipselect  (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect),  // avalon_jtag_slave.chipselect
		.av_address     (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address),     //                  .address
		.av_read_n      (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read),       //                  .read_n
		.av_readdata    (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata),    //                  .readdata
		.av_write_n     (~jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write),      //                  .write_n
		.av_writedata   (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata),   //                  .writedata
		.av_waitrequest (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), //                  .waitrequest
		.dataavailable  (),                                                                       //                  .dataavailable
		.readyfordata   (),                                                                       //                  .readyfordata
		.av_irq         (irq_mapper_receiver0_irq)                                                //               irq.irq
	);

	TR4_HDMI_TX_RX_SOPC_onchip_memory2 onchip_memory2 (
		.clk        (pll_cpu),                                                     //   clk1.clk
		.address    (onchip_memory2_s1_translator_avalon_anti_slave_0_address),    //     s1.address
		.chipselect (onchip_memory2_s1_translator_avalon_anti_slave_0_chipselect), //       .chipselect
		.clken      (onchip_memory2_s1_translator_avalon_anti_slave_0_clken),      //       .clken
		.readdata   (onchip_memory2_s1_translator_avalon_anti_slave_0_readdata),   //       .readdata
		.write      (onchip_memory2_s1_translator_avalon_anti_slave_0_write),      //       .write
		.writedata  (onchip_memory2_s1_translator_avalon_anti_slave_0_writedata),  //       .writedata
		.byteenable (onchip_memory2_s1_translator_avalon_anti_slave_0_byteenable), //       .byteenable
		.reset      (rst_controller_reset_out_reset)                               // reset1.reset
	);

	TR4_HDMI_TX_RX_SOPC_pll pll (
		.clk       (clk),                                                    //       inclk_interface.clk
		.reset     (rst_controller_001_reset_out_reset),                     // inclk_interface_reset.reset
		.read      (pll_pll_slave_translator_avalon_anti_slave_0_read),      //             pll_slave.read
		.write     (pll_pll_slave_translator_avalon_anti_slave_0_write),     //                      .write
		.address   (pll_pll_slave_translator_avalon_anti_slave_0_address),   //                      .address
		.readdata  (pll_pll_slave_translator_avalon_anti_slave_0_readdata),  //                      .readdata
		.writedata (pll_pll_slave_translator_avalon_anti_slave_0_writedata), //                      .writedata
		.c0        (pll_cpu),                                                //                    c0.clk
		.c1        (pll_io),                                                 //                    c1.clk
		.areset    (areset_to_the_pll),                                      //        areset_conduit.export
		.locked    (locked_from_the_pll),                                    //        locked_conduit.export
		.phasedone (phasedone_from_the_pll)                                  //     phasedone_conduit.export
	);

	TR4_HDMI_TX_RX_SOPC_timer timer (
		.clk        (pll_io),                                             //   clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                // reset.reset_n
		.address    (timer_s1_translator_avalon_anti_slave_0_address),    //    s1.address
		.writedata  (timer_s1_translator_avalon_anti_slave_0_writedata),  //      .writedata
		.readdata   (timer_s1_translator_avalon_anti_slave_0_readdata),   //      .readdata
		.chipselect (timer_s1_translator_avalon_anti_slave_0_chipselect), //      .chipselect
		.write_n    (~timer_s1_translator_avalon_anti_slave_0_write),     //      .write_n
		.irq        (irq_synchronizer_receiver_irq)                       //   irq.irq
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_scl hdmi_tx_i2c_scl (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_tx_i2c_scl)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_sda hdmi_tx_i2c_sda (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.bidir_port (bidir_port_to_and_from_the_hdmi_tx_i2c_sda)                    // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_scl hdmi_rx_i2c_scl (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_rx_i2c_scl)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_sda hdmi_rx_i2c_sda (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.bidir_port (bidir_port_to_and_from_the_hdmi_rx_i2c_sda)                    // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_scl hdmi_tx_reset_n (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_tx_reset_n)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_irq_n hdmi_tx_irq_n (
		.clk        (pll_io),                                                     //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                        //               reset.reset_n
		.address    (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.in_port    (in_port_to_the_hdmi_tx_irq_n),                               // external_connection.export
		.irq        (irq_synchronizer_001_receiver_irq)                           //                 irq.irq
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_scl hdmi_rx_reset_n (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_rx_reset_n)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_pio_led pio_led (
		.clk        (pll_io),                                               //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                  //               reset.reset_n
		.address    (pio_led_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~pio_led_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (pio_led_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (pio_led_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (pio_led_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_pio_led)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_pio_button pio_button (
		.clk        (pll_io),                                                  //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                     //               reset.reset_n
		.address    (pio_button_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~pio_button_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (pio_button_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (pio_button_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (pio_button_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.in_port    (in_port_to_the_pio_button),                               // external_connection.export
		.irq        (irq_synchronizer_002_receiver_irq)                        //                 irq.irq
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_rx_irq_n hdmi_rx_irq_n (
		.clk      (pll_io),                                                   //                 clk.clk
		.reset_n  (~rst_controller_002_reset_out_reset),                      //               reset.reset_n
		.address  (hdmi_rx_irq_n_s1_translator_avalon_anti_slave_0_address),  //                  s1.address
		.readdata (hdmi_rx_irq_n_s1_translator_avalon_anti_slave_0_readdata), //                    .readdata
		.in_port  (in_port_to_the_hdmi_rx_irq_n)                              // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_rx_hpd_n hdmi_rx_hpd_n (
		.clk        (pll_io),                                                     //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                        //               reset.reset_n
		.address    (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_rx_hpd_n)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_rx_cec hdmi_rx_cec (
		.clk        (pll_io),                                                   //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                      //               reset.reset_n
		.address    (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx_cec_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.bidir_port (bidir_port_to_and_from_the_hdmi_rx_cec)                    // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_sda hdmi_rx0_ep_scl (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.bidir_port (bidir_port_to_and_from_the_hdmi_rx0_ep_scl)                    // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_sda hdmi_rx0_ep_sda (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.bidir_port (bidir_port_to_and_from_the_hdmi_rx0_ep_sda)                    // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_sda hdmi_rx1_ep_scl (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.bidir_port (bidir_port_to_and_from_the_hdmi_rx1_ep_scl)                    // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_sda hdmi_rx1_ep_sda (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.bidir_port (bidir_port_to_and_from_the_hdmi_rx1_ep_sda)                    // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_scl hdmi_rx_sync (
		.clk        (pll_io),                                                    //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                       //               reset.reset_n
		.address    (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx_sync_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_rx_sync)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_pio_led hdmi_tx_disp_mode (
		.clk        (pll_io),                                                         //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                            //               reset.reset_n
		.address    (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_tx_disp_mode)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_tx_i2c_scl hdmi_tx_mode_change (
		.clk        (pll_io),                                                           //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                              //               reset.reset_n
		.address    (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_tx_mode_change)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_rx_hpd_n hdmi_tx_vpg_color (
		.clk        (pll_io),                                                         //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                            //               reset.reset_n
		.address    (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_tx_vpg_color)                             // external_connection.export
	);

	TR4_HDMI_TX_RX_SOPC_hdmi_rx_edid_wp hdmi_rx_edid_wp (
		.clk        (pll_io),                                                       //                 clk.clk
		.reset_n    (~rst_controller_002_reset_out_reset),                          //               reset.reset_n
		.address    (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_address),    //                  s1.address
		.write_n    (~hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_write),     //                    .write_n
		.writedata  (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_writedata),  //                    .writedata
		.chipselect (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_chipselect), //                    .chipselect
		.readdata   (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_readdata),   //                    .readdata
		.out_port   (out_port_from_the_hdmi_rx_edid_wp)                             // external_connection.export
	);

	TERASIC_I2S_TX i2s_tx (
		.s_chipselect (i2s_tx_slave_translator_avalon_anti_slave_0_chipselect), //       slave.chipselect
		.s_address    (i2s_tx_slave_translator_avalon_anti_slave_0_address),    //            .address
		.s_read       (i2s_tx_slave_translator_avalon_anti_slave_0_read),       //            .read
		.s_readdata   (i2s_tx_slave_translator_avalon_anti_slave_0_readdata),   //            .readdata
		.s_write      (i2s_tx_slave_translator_avalon_anti_slave_0_write),      //            .write
		.s_writedata  (i2s_tx_slave_translator_avalon_anti_slave_0_writedata),  //            .writedata
		.s_clk        (pll_cpu),                                                //         clk.clk
		.s_reset      (rst_controller_reset_out_reset),                         //   clk_reset.reset
		.i2s_sck      (i2s_sck_to_the_i2s_tx),                                  // conduit_end.export
		.i2s_ws       (i2s_ws_from_the_i2s_tx),                                 //            .export
		.i2s_sd       (i2s_sd_from_the_i2s_tx),                                 //            .export
		.s_irq        (irq_mapper_receiver4_irq)                                //         irq.irq
	);

	altera_avalon_mm_clock_crossing_bridge #(
		.DATA_WIDTH          (32),
		.SYMBOL_WIDTH        (8),
		.ADDRESS_WIDTH       (9),
		.BURSTCOUNT_WIDTH    (1),
		.COMMAND_FIFO_DEPTH  (32),
		.RESPONSE_FIFO_DEPTH (2048),
		.MASTER_SYNC_DEPTH   (3),
		.SLAVE_SYNC_DEPTH    (3)
	) clock_crossing_bridge (
		.m0_clk           (pll_io),                                                                //   m0_clk.clk
		.m0_reset         (rst_controller_002_reset_out_reset),                                    // m0_reset.reset
		.s0_clk           (pll_cpu),                                                               //   s0_clk.clk
		.s0_reset         (rst_controller_reset_out_reset),                                        // s0_reset.reset
		.s0_waitrequest   (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_waitrequest),   //       s0.waitrequest
		.s0_readdata      (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_readdata),      //         .readdata
		.s0_readdatavalid (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_readdatavalid), //         .readdatavalid
		.s0_burstcount    (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_burstcount),    //         .burstcount
		.s0_writedata     (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_writedata),     //         .writedata
		.s0_address       (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_address),       //         .address
		.s0_write         (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_write),         //         .write
		.s0_read          (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_read),          //         .read
		.s0_byteenable    (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_byteenable),    //         .byteenable
		.s0_debugaccess   (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_debugaccess),   //         .debugaccess
		.m0_waitrequest   (clock_crossing_bridge_m0_waitrequest),                                  //       m0.waitrequest
		.m0_readdata      (clock_crossing_bridge_m0_readdata),                                     //         .readdata
		.m0_readdatavalid (clock_crossing_bridge_m0_readdatavalid),                                //         .readdatavalid
		.m0_burstcount    (clock_crossing_bridge_m0_burstcount),                                   //         .burstcount
		.m0_writedata     (clock_crossing_bridge_m0_writedata),                                    //         .writedata
		.m0_address       (clock_crossing_bridge_m0_address),                                      //         .address
		.m0_write         (clock_crossing_bridge_m0_write),                                        //         .write
		.m0_read          (clock_crossing_bridge_m0_read),                                         //         .read
		.m0_byteenable    (clock_crossing_bridge_m0_byteenable),                                   //         .byteenable
		.m0_debugaccess   (clock_crossing_bridge_m0_debugaccess)                                   //         .debugaccess
	);

	TR4_HDMI_TX_RX_SOPC_cpu cpu (
		.clk                                   (pll_cpu),                                                            //                       clk.clk
		.reset_n                               (~rst_controller_reset_out_reset),                                    //                   reset_n.reset_n
		.d_address                             (cpu_data_master_address),                                            //               data_master.address
		.d_byteenable                          (cpu_data_master_byteenable),                                         //                          .byteenable
		.d_read                                (cpu_data_master_read),                                               //                          .read
		.d_readdata                            (cpu_data_master_readdata),                                           //                          .readdata
		.d_waitrequest                         (cpu_data_master_waitrequest),                                        //                          .waitrequest
		.d_write                               (cpu_data_master_write),                                              //                          .write
		.d_writedata                           (cpu_data_master_writedata),                                          //                          .writedata
		.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess),                                        //                          .debugaccess
		.i_address                             (cpu_instruction_master_address),                                     //        instruction_master.address
		.i_read                                (cpu_instruction_master_read),                                        //                          .read
		.i_readdata                            (cpu_instruction_master_readdata),                                    //                          .readdata
		.i_waitrequest                         (cpu_instruction_master_waitrequest),                                 //                          .waitrequest
		.i_readdatavalid                       (cpu_instruction_master_readdatavalid),                               //                          .readdatavalid
		.d_irq                                 (cpu_d_irq_irq),                                                      //                     d_irq.irq
		.jtag_debug_module_resetrequest        (cpu_jtag_debug_module_reset_reset),                                  //   jtag_debug_module_reset.reset
		.jtag_debug_module_address             (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address),       //         jtag_debug_module.address
		.jtag_debug_module_begintransfer       (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), //                          .begintransfer
		.jtag_debug_module_byteenable          (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable),    //                          .byteenable
		.jtag_debug_module_debugaccess         (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess),   //                          .debugaccess
		.jtag_debug_module_readdata            (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata),      //                          .readdata
		.jtag_debug_module_select              (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect),    //                          .chipselect
		.jtag_debug_module_write               (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write),         //                          .write
		.jtag_debug_module_writedata           (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata),     //                          .writedata
		.no_ci_readra                          ()                                                                    // custom_instruction_master.readra
	);

	TR4_HDMI_TX_RX_SOPC_sysid sysid (
		.clock    (pll_io),                                                      //           clk.clk
		.reset_n  (~rst_controller_002_reset_out_reset),                         //         reset.reset_n
		.readdata (sysid_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
		.address  (sysid_control_slave_translator_avalon_anti_slave_0_address)   //              .address
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (25),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (25),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cpu_instruction_master_translator (
		.clk                   (pll_cpu),                                                                   //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                            //                     reset.reset
		.uav_address           (cpu_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (cpu_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (cpu_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (cpu_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (cpu_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (cpu_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (cpu_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (cpu_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_read               (cpu_instruction_master_read),                                               //                          .read
		.av_readdata           (cpu_instruction_master_readdata),                                           //                          .readdata
		.av_readdatavalid      (cpu_instruction_master_readdatavalid),                                      //                          .readdatavalid
		.av_burstcount         (1'b1),                                                                      //               (terminated)
		.av_byteenable         (4'b1111),                                                                   //               (terminated)
		.av_beginbursttransfer (1'b0),                                                                      //               (terminated)
		.av_begintransfer      (1'b0),                                                                      //               (terminated)
		.av_chipselect         (1'b0),                                                                      //               (terminated)
		.av_write              (1'b0),                                                                      //               (terminated)
		.av_writedata          (32'b00000000000000000000000000000000),                                      //               (terminated)
		.av_lock               (1'b0),                                                                      //               (terminated)
		.av_debugaccess        (1'b0),                                                                      //               (terminated)
		.uav_clken             (),                                                                          //               (terminated)
		.av_clken              (1'b1)                                                                       //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (25),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (25),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cpu_data_master_translator (
		.clk                   (pll_cpu),                                                            //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                     //                     reset.reset
		.uav_address           (cpu_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (cpu_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (cpu_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (cpu_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (cpu_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (cpu_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (cpu_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (cpu_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (cpu_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (cpu_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (cpu_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (cpu_data_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable         (cpu_data_master_byteenable),                                         //                          .byteenable
		.av_read               (cpu_data_master_read),                                               //                          .read
		.av_readdata           (cpu_data_master_readdata),                                           //                          .readdata
		.av_write              (cpu_data_master_write),                                              //                          .write
		.av_writedata          (cpu_data_master_writedata),                                          //                          .writedata
		.av_debugaccess        (cpu_data_master_debugaccess),                                        //                          .debugaccess
		.av_burstcount         (1'b1),                                                               //               (terminated)
		.av_beginbursttransfer (1'b0),                                                               //               (terminated)
		.av_begintransfer      (1'b0),                                                               //               (terminated)
		.av_chipselect         (1'b0),                                                               //               (terminated)
		.av_readdatavalid      (),                                                                   //               (terminated)
		.av_lock               (1'b0),                                                               //               (terminated)
		.uav_clken             (),                                                                   //               (terminated)
		.av_clken              (1'b1)                                                                //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (9),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (25),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) cpu_jtag_debug_module_translator (
		.clk                   (pll_cpu),                                                                          //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                   //                    reset.reset
		.uav_address           (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_begintransfer      (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer),               //                         .begintransfer
		.av_byteenable         (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_chipselect         (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_debugaccess        (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess),                 //                         .debugaccess
		.av_read               (),                                                                                 //              (terminated)
		.av_beginbursttransfer (),                                                                                 //              (terminated)
		.av_burstcount         (),                                                                                 //              (terminated)
		.av_readdatavalid      (1'b0),                                                                             //              (terminated)
		.av_waitrequest        (1'b0),                                                                             //              (terminated)
		.av_writebyteenable    (),                                                                                 //              (terminated)
		.av_lock               (),                                                                                 //              (terminated)
		.av_clken              (),                                                                                 //              (terminated)
		.uav_clken             (1'b0),                                                                             //              (terminated)
		.av_outputenable       ()                                                                                  //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (15),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (25),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) onchip_memory2_s1_translator (
		.clk                   (pll_cpu),                                                                      //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                               //                    reset.reset
		.uav_address           (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (onchip_memory2_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (onchip_memory2_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (onchip_memory2_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (onchip_memory2_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_byteenable         (onchip_memory2_s1_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_chipselect         (onchip_memory2_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_clken              (onchip_memory2_s1_translator_avalon_anti_slave_0_clken),                       //                         .clken
		.av_read               (),                                                                             //              (terminated)
		.av_begintransfer      (),                                                                             //              (terminated)
		.av_beginbursttransfer (),                                                                             //              (terminated)
		.av_burstcount         (),                                                                             //              (terminated)
		.av_readdatavalid      (1'b0),                                                                         //              (terminated)
		.av_waitrequest        (1'b0),                                                                         //              (terminated)
		.av_writebyteenable    (),                                                                             //              (terminated)
		.av_lock               (),                                                                             //              (terminated)
		.uav_clken             (1'b0),                                                                         //              (terminated)
		.av_debugaccess        (),                                                                             //              (terminated)
		.av_outputenable       ()                                                                              //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (25),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) jtag_uart_avalon_jtag_slave_translator (
		.clk                   (pll_cpu),                                                                                //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                         //                    reset.reset
		.uav_address           (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_waitrequest        (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_chipselect         (jtag_uart_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_begintransfer      (),                                                                                       //              (terminated)
		.av_beginbursttransfer (),                                                                                       //              (terminated)
		.av_burstcount         (),                                                                                       //              (terminated)
		.av_byteenable         (),                                                                                       //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                   //              (terminated)
		.av_writebyteenable    (),                                                                                       //              (terminated)
		.av_lock               (),                                                                                       //              (terminated)
		.av_clken              (),                                                                                       //              (terminated)
		.uav_clken             (1'b0),                                                                                   //              (terminated)
		.av_debugaccess        (),                                                                                       //              (terminated)
		.av_outputenable       ()                                                                                        //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (25),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pll_pll_slave_translator (
		.clk                   (clk),                                                                      //                      clk.clk
		.reset                 (rst_controller_001_reset_out_reset),                                       //                    reset.reset
		.uav_address           (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (pll_pll_slave_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (pll_pll_slave_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (pll_pll_slave_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (pll_pll_slave_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (pll_pll_slave_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_begintransfer      (),                                                                         //              (terminated)
		.av_beginbursttransfer (),                                                                         //              (terminated)
		.av_burstcount         (),                                                                         //              (terminated)
		.av_byteenable         (),                                                                         //              (terminated)
		.av_readdatavalid      (1'b0),                                                                     //              (terminated)
		.av_waitrequest        (1'b0),                                                                     //              (terminated)
		.av_writebyteenable    (),                                                                         //              (terminated)
		.av_lock               (),                                                                         //              (terminated)
		.av_chipselect         (),                                                                         //              (terminated)
		.av_clken              (),                                                                         //              (terminated)
		.uav_clken             (1'b0),                                                                     //              (terminated)
		.av_debugaccess        (),                                                                         //              (terminated)
		.av_outputenable       ()                                                                          //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (25),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) i2s_tx_slave_translator (
		.clk                   (pll_cpu),                                                                 //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                          //                    reset.reset
		.uav_address           (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (i2s_tx_slave_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (i2s_tx_slave_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (i2s_tx_slave_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (i2s_tx_slave_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (i2s_tx_slave_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (i2s_tx_slave_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_begintransfer      (),                                                                        //              (terminated)
		.av_beginbursttransfer (),                                                                        //              (terminated)
		.av_burstcount         (),                                                                        //              (terminated)
		.av_byteenable         (),                                                                        //              (terminated)
		.av_readdatavalid      (1'b0),                                                                    //              (terminated)
		.av_waitrequest        (1'b0),                                                                    //              (terminated)
		.av_writebyteenable    (),                                                                        //              (terminated)
		.av_lock               (),                                                                        //              (terminated)
		.av_clken              (),                                                                        //              (terminated)
		.uav_clken             (1'b0),                                                                    //              (terminated)
		.av_debugaccess        (),                                                                        //              (terminated)
		.av_outputenable       ()                                                                         //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (9),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (25),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) clock_crossing_bridge_s0_translator (
		.clk                   (pll_cpu),                                                                             //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                      //                    reset.reset
		.uav_address           (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_burstcount         (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_burstcount),                  //                         .burstcount
		.av_byteenable         (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_readdatavalid      (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_readdatavalid),               //                         .readdatavalid
		.av_waitrequest        (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_debugaccess        (clock_crossing_bridge_s0_translator_avalon_anti_slave_0_debugaccess),                 //                         .debugaccess
		.av_begintransfer      (),                                                                                    //              (terminated)
		.av_beginbursttransfer (),                                                                                    //              (terminated)
		.av_writebyteenable    (),                                                                                    //              (terminated)
		.av_lock               (),                                                                                    //              (terminated)
		.av_chipselect         (),                                                                                    //              (terminated)
		.av_clken              (),                                                                                    //              (terminated)
		.uav_clken             (1'b0),                                                                                //              (terminated)
		.av_outputenable       ()                                                                                     //              (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (9),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (9),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) clock_crossing_bridge_m0_translator (
		.clk                   (pll_io),                                                                      //                       clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                          //                     reset.reset
		.uav_address           (clock_crossing_bridge_m0_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (clock_crossing_bridge_m0_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (clock_crossing_bridge_m0_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (clock_crossing_bridge_m0_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (clock_crossing_bridge_m0_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (clock_crossing_bridge_m0_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (clock_crossing_bridge_m0_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (clock_crossing_bridge_m0_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (clock_crossing_bridge_m0_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (clock_crossing_bridge_m0_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (clock_crossing_bridge_m0_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (clock_crossing_bridge_m0_burstcount),                                         //                          .burstcount
		.av_byteenable         (clock_crossing_bridge_m0_byteenable),                                         //                          .byteenable
		.av_read               (clock_crossing_bridge_m0_read),                                               //                          .read
		.av_readdata           (clock_crossing_bridge_m0_readdata),                                           //                          .readdata
		.av_readdatavalid      (clock_crossing_bridge_m0_readdatavalid),                                      //                          .readdatavalid
		.av_write              (clock_crossing_bridge_m0_write),                                              //                          .write
		.av_writedata          (clock_crossing_bridge_m0_writedata),                                          //                          .writedata
		.av_debugaccess        (clock_crossing_bridge_m0_debugaccess),                                        //                          .debugaccess
		.av_beginbursttransfer (1'b0),                                                                        //               (terminated)
		.av_begintransfer      (1'b0),                                                                        //               (terminated)
		.av_chipselect         (1'b0),                                                                        //               (terminated)
		.av_lock               (1'b0),                                                                        //               (terminated)
		.uav_clken             (),                                                                            //               (terminated)
		.av_clken              (1'b1)                                                                         //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) timer_s1_translator (
		.clk                   (pll_io),                                                              //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                  //                    reset.reset
		.uav_address           (timer_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (timer_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (timer_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (timer_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (timer_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (timer_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (timer_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (timer_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (timer_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (timer_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (timer_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (timer_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (timer_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (timer_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (timer_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (timer_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                    //              (terminated)
		.av_begintransfer      (),                                                                    //              (terminated)
		.av_beginbursttransfer (),                                                                    //              (terminated)
		.av_burstcount         (),                                                                    //              (terminated)
		.av_byteenable         (),                                                                    //              (terminated)
		.av_readdatavalid      (1'b0),                                                                //              (terminated)
		.av_waitrequest        (1'b0),                                                                //              (terminated)
		.av_writebyteenable    (),                                                                    //              (terminated)
		.av_lock               (),                                                                    //              (terminated)
		.av_clken              (),                                                                    //              (terminated)
		.uav_clken             (1'b0),                                                                //              (terminated)
		.av_debugaccess        (),                                                                    //              (terminated)
		.av_outputenable       ()                                                                     //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_tx_i2c_scl_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_tx_i2c_scl_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_tx_i2c_sda_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_tx_i2c_sda_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_i2c_scl_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx_i2c_scl_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_i2c_sda_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx_i2c_sda_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_tx_reset_n_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_tx_reset_n_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_tx_irq_n_s1_translator (
		.clk                   (pll_io),                                                                      //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                          //                    reset.reset
		.uav_address           (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_tx_irq_n_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                            //              (terminated)
		.av_begintransfer      (),                                                                            //              (terminated)
		.av_beginbursttransfer (),                                                                            //              (terminated)
		.av_burstcount         (),                                                                            //              (terminated)
		.av_byteenable         (),                                                                            //              (terminated)
		.av_readdatavalid      (1'b0),                                                                        //              (terminated)
		.av_waitrequest        (1'b0),                                                                        //              (terminated)
		.av_writebyteenable    (),                                                                            //              (terminated)
		.av_lock               (),                                                                            //              (terminated)
		.av_clken              (),                                                                            //              (terminated)
		.uav_clken             (1'b0),                                                                        //              (terminated)
		.av_debugaccess        (),                                                                            //              (terminated)
		.av_outputenable       ()                                                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_reset_n_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx_reset_n_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pio_led_s1_translator (
		.clk                   (pll_io),                                                                //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                    //                    reset.reset
		.uav_address           (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (pio_led_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (pio_led_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (pio_led_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (pio_led_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (pio_led_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                      //              (terminated)
		.av_begintransfer      (),                                                                      //              (terminated)
		.av_beginbursttransfer (),                                                                      //              (terminated)
		.av_burstcount         (),                                                                      //              (terminated)
		.av_byteenable         (),                                                                      //              (terminated)
		.av_readdatavalid      (1'b0),                                                                  //              (terminated)
		.av_waitrequest        (1'b0),                                                                  //              (terminated)
		.av_writebyteenable    (),                                                                      //              (terminated)
		.av_lock               (),                                                                      //              (terminated)
		.av_clken              (),                                                                      //              (terminated)
		.uav_clken             (1'b0),                                                                  //              (terminated)
		.av_debugaccess        (),                                                                      //              (terminated)
		.av_outputenable       ()                                                                       //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) pio_button_s1_translator (
		.clk                   (pll_io),                                                                   //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                       //                    reset.reset
		.uav_address           (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (pio_button_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (pio_button_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (pio_button_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (pio_button_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (pio_button_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                         //              (terminated)
		.av_begintransfer      (),                                                                         //              (terminated)
		.av_beginbursttransfer (),                                                                         //              (terminated)
		.av_burstcount         (),                                                                         //              (terminated)
		.av_byteenable         (),                                                                         //              (terminated)
		.av_readdatavalid      (1'b0),                                                                     //              (terminated)
		.av_waitrequest        (1'b0),                                                                     //              (terminated)
		.av_writebyteenable    (),                                                                         //              (terminated)
		.av_lock               (),                                                                         //              (terminated)
		.av_clken              (),                                                                         //              (terminated)
		.uav_clken             (1'b0),                                                                     //              (terminated)
		.av_debugaccess        (),                                                                         //              (terminated)
		.av_outputenable       ()                                                                          //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sysid_control_slave_translator (
		.clk                   (pll_io),                                                                         //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                             //                    reset.reset
		.uav_address           (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (sysid_control_slave_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_readdata           (sysid_control_slave_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_write              (),                                                                               //              (terminated)
		.av_read               (),                                                                               //              (terminated)
		.av_writedata          (),                                                                               //              (terminated)
		.av_begintransfer      (),                                                                               //              (terminated)
		.av_beginbursttransfer (),                                                                               //              (terminated)
		.av_burstcount         (),                                                                               //              (terminated)
		.av_byteenable         (),                                                                               //              (terminated)
		.av_readdatavalid      (1'b0),                                                                           //              (terminated)
		.av_waitrequest        (1'b0),                                                                           //              (terminated)
		.av_writebyteenable    (),                                                                               //              (terminated)
		.av_lock               (),                                                                               //              (terminated)
		.av_chipselect         (),                                                                               //              (terminated)
		.av_clken              (),                                                                               //              (terminated)
		.uav_clken             (1'b0),                                                                           //              (terminated)
		.av_debugaccess        (),                                                                               //              (terminated)
		.av_outputenable       ()                                                                                //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_irq_n_s1_translator (
		.clk                   (pll_io),                                                                      //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                          //                    reset.reset
		.uav_address           (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_irq_n_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_readdata           (hdmi_rx_irq_n_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_write              (),                                                                            //              (terminated)
		.av_read               (),                                                                            //              (terminated)
		.av_writedata          (),                                                                            //              (terminated)
		.av_begintransfer      (),                                                                            //              (terminated)
		.av_beginbursttransfer (),                                                                            //              (terminated)
		.av_burstcount         (),                                                                            //              (terminated)
		.av_byteenable         (),                                                                            //              (terminated)
		.av_readdatavalid      (1'b0),                                                                        //              (terminated)
		.av_waitrequest        (1'b0),                                                                        //              (terminated)
		.av_writebyteenable    (),                                                                            //              (terminated)
		.av_lock               (),                                                                            //              (terminated)
		.av_chipselect         (),                                                                            //              (terminated)
		.av_clken              (),                                                                            //              (terminated)
		.uav_clken             (1'b0),                                                                        //              (terminated)
		.av_debugaccess        (),                                                                            //              (terminated)
		.av_outputenable       ()                                                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_hpd_n_s1_translator (
		.clk                   (pll_io),                                                                      //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                          //                    reset.reset
		.uav_address           (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx_hpd_n_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                            //              (terminated)
		.av_begintransfer      (),                                                                            //              (terminated)
		.av_beginbursttransfer (),                                                                            //              (terminated)
		.av_burstcount         (),                                                                            //              (terminated)
		.av_byteenable         (),                                                                            //              (terminated)
		.av_readdatavalid      (1'b0),                                                                        //              (terminated)
		.av_waitrequest        (1'b0),                                                                        //              (terminated)
		.av_writebyteenable    (),                                                                            //              (terminated)
		.av_lock               (),                                                                            //              (terminated)
		.av_clken              (),                                                                            //              (terminated)
		.uav_clken             (1'b0),                                                                        //              (terminated)
		.av_debugaccess        (),                                                                            //              (terminated)
		.av_outputenable       ()                                                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_cec_s1_translator (
		.clk                   (pll_io),                                                                    //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                        //                    reset.reset
		.uav_address           (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx_cec_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                          //              (terminated)
		.av_begintransfer      (),                                                                          //              (terminated)
		.av_beginbursttransfer (),                                                                          //              (terminated)
		.av_burstcount         (),                                                                          //              (terminated)
		.av_byteenable         (),                                                                          //              (terminated)
		.av_readdatavalid      (1'b0),                                                                      //              (terminated)
		.av_waitrequest        (1'b0),                                                                      //              (terminated)
		.av_writebyteenable    (),                                                                          //              (terminated)
		.av_lock               (),                                                                          //              (terminated)
		.av_clken              (),                                                                          //              (terminated)
		.uav_clken             (1'b0),                                                                      //              (terminated)
		.av_debugaccess        (),                                                                          //              (terminated)
		.av_outputenable       ()                                                                           //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx0_ep_scl_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx0_ep_scl_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx0_ep_sda_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx0_ep_sda_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx1_ep_scl_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx1_ep_scl_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx1_ep_sda_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx1_ep_sda_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_sync_s1_translator (
		.clk                   (pll_io),                                                                     //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                         //                    reset.reset
		.uav_address           (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx_sync_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                           //              (terminated)
		.av_begintransfer      (),                                                                           //              (terminated)
		.av_beginbursttransfer (),                                                                           //              (terminated)
		.av_burstcount         (),                                                                           //              (terminated)
		.av_byteenable         (),                                                                           //              (terminated)
		.av_readdatavalid      (1'b0),                                                                       //              (terminated)
		.av_waitrequest        (1'b0),                                                                       //              (terminated)
		.av_writebyteenable    (),                                                                           //              (terminated)
		.av_lock               (),                                                                           //              (terminated)
		.av_clken              (),                                                                           //              (terminated)
		.uav_clken             (1'b0),                                                                       //              (terminated)
		.av_debugaccess        (),                                                                           //              (terminated)
		.av_outputenable       ()                                                                            //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_tx_disp_mode_s1_translator (
		.clk                   (pll_io),                                                                          //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                              //                    reset.reset
		.uav_address           (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_tx_disp_mode_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                                //              (terminated)
		.av_begintransfer      (),                                                                                //              (terminated)
		.av_beginbursttransfer (),                                                                                //              (terminated)
		.av_burstcount         (),                                                                                //              (terminated)
		.av_byteenable         (),                                                                                //              (terminated)
		.av_readdatavalid      (1'b0),                                                                            //              (terminated)
		.av_waitrequest        (1'b0),                                                                            //              (terminated)
		.av_writebyteenable    (),                                                                                //              (terminated)
		.av_lock               (),                                                                                //              (terminated)
		.av_clken              (),                                                                                //              (terminated)
		.uav_clken             (1'b0),                                                                            //              (terminated)
		.av_debugaccess        (),                                                                                //              (terminated)
		.av_outputenable       ()                                                                                 //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_tx_mode_change_s1_translator (
		.clk                   (pll_io),                                                                            //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                                //                    reset.reset
		.uav_address           (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_tx_mode_change_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                                  //              (terminated)
		.av_begintransfer      (),                                                                                  //              (terminated)
		.av_beginbursttransfer (),                                                                                  //              (terminated)
		.av_burstcount         (),                                                                                  //              (terminated)
		.av_byteenable         (),                                                                                  //              (terminated)
		.av_readdatavalid      (1'b0),                                                                              //              (terminated)
		.av_waitrequest        (1'b0),                                                                              //              (terminated)
		.av_writebyteenable    (),                                                                                  //              (terminated)
		.av_lock               (),                                                                                  //              (terminated)
		.av_clken              (),                                                                                  //              (terminated)
		.uav_clken             (1'b0),                                                                              //              (terminated)
		.av_debugaccess        (),                                                                                  //              (terminated)
		.av_outputenable       ()                                                                                   //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_tx_vpg_color_s1_translator (
		.clk                   (pll_io),                                                                          //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                              //                    reset.reset
		.uav_address           (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_tx_vpg_color_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                                //              (terminated)
		.av_begintransfer      (),                                                                                //              (terminated)
		.av_beginbursttransfer (),                                                                                //              (terminated)
		.av_burstcount         (),                                                                                //              (terminated)
		.av_byteenable         (),                                                                                //              (terminated)
		.av_readdatavalid      (1'b0),                                                                            //              (terminated)
		.av_waitrequest        (1'b0),                                                                            //              (terminated)
		.av_writebyteenable    (),                                                                                //              (terminated)
		.av_lock               (),                                                                                //              (terminated)
		.av_clken              (),                                                                                //              (terminated)
		.uav_clken             (1'b0),                                                                            //              (terminated)
		.av_debugaccess        (),                                                                                //              (terminated)
		.av_outputenable       ()                                                                                 //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) hdmi_rx_edid_wp_s1_translator (
		.clk                   (pll_io),                                                                        //                      clk.clk
		.reset                 (rst_controller_002_reset_out_reset),                                            //                    reset.reset
		.uav_address           (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_chipselect         (hdmi_rx_edid_wp_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_read               (),                                                                              //              (terminated)
		.av_begintransfer      (),                                                                              //              (terminated)
		.av_beginbursttransfer (),                                                                              //              (terminated)
		.av_burstcount         (),                                                                              //              (terminated)
		.av_byteenable         (),                                                                              //              (terminated)
		.av_readdatavalid      (1'b0),                                                                          //              (terminated)
		.av_waitrequest        (1'b0),                                                                          //              (terminated)
		.av_writebyteenable    (),                                                                              //              (terminated)
		.av_lock               (),                                                                              //              (terminated)
		.av_clken              (),                                                                              //              (terminated)
		.uav_clken             (1'b0),                                                                          //              (terminated)
		.av_debugaccess        (),                                                                              //              (terminated)
		.av_outputenable       ()                                                                               //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.PKT_BEGIN_BURST           (72),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.ST_DATA_W                 (80),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (3)
	) cpu_instruction_master_translator_avalon_universal_master_0_agent (
		.clk              (pll_cpu),                                                                            //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                     // clk_reset.reset
		.av_address       (cpu_instruction_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (cpu_instruction_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (cpu_instruction_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (cpu_instruction_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (cpu_instruction_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (cpu_instruction_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (cpu_instruction_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (cpu_instruction_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (limiter_rsp_src_valid),                                                              //        rp.valid
		.rp_data          (limiter_rsp_src_data),                                                               //          .data
		.rp_channel       (limiter_rsp_src_channel),                                                            //          .channel
		.rp_startofpacket (limiter_rsp_src_startofpacket),                                                      //          .startofpacket
		.rp_endofpacket   (limiter_rsp_src_endofpacket),                                                        //          .endofpacket
		.rp_ready         (limiter_rsp_src_ready)                                                               //          .ready
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.PKT_BEGIN_BURST           (72),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.ST_DATA_W                 (80),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (2),
		.BURSTWRAP_VALUE           (7)
	) cpu_data_master_translator_avalon_universal_master_0_agent (
		.clk              (pll_cpu),                                                                     //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                              // clk_reset.reset
		.av_address       (cpu_data_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (cpu_data_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (cpu_data_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (cpu_data_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (cpu_data_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (cpu_data_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (cpu_data_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (cpu_data_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (cpu_data_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (cpu_data_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (limiter_001_rsp_src_valid),                                                   //        rp.valid
		.rp_data          (limiter_001_rsp_src_data),                                                    //          .data
		.rp_channel       (limiter_001_rsp_src_channel),                                                 //          .channel
		.rp_startofpacket (limiter_001_rsp_src_startofpacket),                                           //          .startofpacket
		.rp_endofpacket   (limiter_001_rsp_src_endofpacket),                                             //          .endofpacket
		.rp_ready         (limiter_001_rsp_src_ready)                                                    //          .ready
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (72),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (80),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_cpu),                                                                                    //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                             //       clk_reset.reset
		.m0_address              (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_src_ready),                                                                     //              cp.ready
		.cp_valid                (cmd_xbar_mux_src_valid),                                                                     //                .valid
		.cp_data                 (cmd_xbar_mux_src_data),                                                                      //                .data
		.cp_startofpacket        (cmd_xbar_mux_src_startofpacket),                                                             //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_src_endofpacket),                                                               //                .endofpacket
		.cp_channel              (cmd_xbar_mux_src_channel),                                                                   //                .channel
		.rf_sink_ready           (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (81),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_cpu),                                                                                    //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                             // clk_reset.reset
		.in_data           (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                      // (terminated)
		.csr_read          (1'b0),                                                                                       // (terminated)
		.csr_write         (1'b0),                                                                                       // (terminated)
		.csr_readdata      (),                                                                                           // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                       // (terminated)
		.almost_full_data  (),                                                                                           // (terminated)
		.almost_empty_data (),                                                                                           // (terminated)
		.in_empty          (1'b0),                                                                                       // (terminated)
		.out_empty         (),                                                                                           // (terminated)
		.in_error          (1'b0),                                                                                       // (terminated)
		.out_error         (),                                                                                           // (terminated)
		.in_channel        (1'b0),                                                                                       // (terminated)
		.out_channel       ()                                                                                            // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (72),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (80),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) onchip_memory2_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_cpu),                                                                                //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                         //       clk_reset.reset
		.m0_address              (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_001_src_ready),                                                             //              cp.ready
		.cp_valid                (cmd_xbar_mux_001_src_valid),                                                             //                .valid
		.cp_data                 (cmd_xbar_mux_001_src_data),                                                              //                .data
		.cp_startofpacket        (cmd_xbar_mux_001_src_startofpacket),                                                     //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_001_src_endofpacket),                                                       //                .endofpacket
		.cp_channel              (cmd_xbar_mux_001_src_channel),                                                           //                .channel
		.rf_sink_ready           (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (81),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_cpu),                                                                                //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                         // clk_reset.reset
		.in_data           (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                  // (terminated)
		.csr_read          (1'b0),                                                                                   // (terminated)
		.csr_write         (1'b0),                                                                                   // (terminated)
		.csr_readdata      (),                                                                                       // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                   // (terminated)
		.almost_full_data  (),                                                                                       // (terminated)
		.almost_empty_data (),                                                                                       // (terminated)
		.in_empty          (1'b0),                                                                                   // (terminated)
		.out_empty         (),                                                                                       // (terminated)
		.in_error          (1'b0),                                                                                   // (terminated)
		.out_error         (),                                                                                       // (terminated)
		.in_channel        (1'b0),                                                                                   // (terminated)
		.out_channel       ()                                                                                        // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (72),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (80),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_cpu),                                                                                          //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                   //       clk_reset.reset
		.m0_address              (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_001_src2_ready),                                                                    //              cp.ready
		.cp_valid                (cmd_xbar_demux_001_src2_valid),                                                                    //                .valid
		.cp_data                 (cmd_xbar_demux_001_src2_data),                                                                     //                .data
		.cp_startofpacket        (cmd_xbar_demux_001_src2_startofpacket),                                                            //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_001_src2_endofpacket),                                                              //                .endofpacket
		.cp_channel              (cmd_xbar_demux_001_src2_channel),                                                                  //                .channel
		.rf_sink_ready           (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (81),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_cpu),                                                                                          //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                   // clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                            // (terminated)
		.csr_read          (1'b0),                                                                                             // (terminated)
		.csr_write         (1'b0),                                                                                             // (terminated)
		.csr_readdata      (),                                                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                             // (terminated)
		.almost_full_data  (),                                                                                                 // (terminated)
		.almost_empty_data (),                                                                                                 // (terminated)
		.in_empty          (1'b0),                                                                                             // (terminated)
		.out_empty         (),                                                                                                 // (terminated)
		.in_error          (1'b0),                                                                                             // (terminated)
		.out_error         (),                                                                                                 // (terminated)
		.in_channel        (1'b0),                                                                                             // (terminated)
		.out_channel       ()                                                                                                  // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (72),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (80),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) pll_pll_slave_translator_avalon_universal_slave_0_agent (
		.clk                     (clk),                                                                                //             clk.clk
		.reset                   (rst_controller_001_reset_out_reset),                                                 //       clk_reset.reset
		.m0_address              (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (pll_pll_slave_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (crosser_out_ready),                                                                  //              cp.ready
		.cp_valid                (crosser_out_valid),                                                                  //                .valid
		.cp_data                 (crosser_out_data),                                                                   //                .data
		.cp_startofpacket        (crosser_out_startofpacket),                                                          //                .startofpacket
		.cp_endofpacket          (crosser_out_endofpacket),                                                            //                .endofpacket
		.cp_channel              (crosser_out_channel),                                                                //                .channel
		.rf_sink_ready           (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (81),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (clk),                                                                                //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                                 // clk_reset.reset
		.in_data           (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pll_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pll_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                              // (terminated)
		.csr_read          (1'b0),                                                                               // (terminated)
		.csr_write         (1'b0),                                                                               // (terminated)
		.csr_readdata      (),                                                                                   // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                               // (terminated)
		.almost_full_data  (),                                                                                   // (terminated)
		.almost_empty_data (),                                                                                   // (terminated)
		.in_empty          (1'b0),                                                                               // (terminated)
		.out_empty         (),                                                                                   // (terminated)
		.in_error          (1'b0),                                                                               // (terminated)
		.out_error         (),                                                                                   // (terminated)
		.in_channel        (1'b0),                                                                               // (terminated)
		.out_channel       ()                                                                                    // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (32),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo (
		.clk               (clk),                                                                          //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                           // clk_reset.reset
		.in_data           (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                                        // (terminated)
		.csr_read          (1'b0),                                                                         // (terminated)
		.csr_write         (1'b0),                                                                         // (terminated)
		.csr_readdata      (),                                                                             // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                         // (terminated)
		.almost_full_data  (),                                                                             // (terminated)
		.almost_empty_data (),                                                                             // (terminated)
		.in_startofpacket  (1'b0),                                                                         // (terminated)
		.in_endofpacket    (1'b0),                                                                         // (terminated)
		.out_startofpacket (),                                                                             // (terminated)
		.out_endofpacket   (),                                                                             // (terminated)
		.in_empty          (1'b0),                                                                         // (terminated)
		.out_empty         (),                                                                             // (terminated)
		.in_error          (1'b0),                                                                         // (terminated)
		.out_error         (),                                                                             // (terminated)
		.in_channel        (1'b0),                                                                         // (terminated)
		.out_channel       ()                                                                              // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (72),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (80),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) i2s_tx_slave_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_cpu),                                                                           //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                    //       clk_reset.reset
		.m0_address              (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (i2s_tx_slave_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_001_src4_ready),                                                     //              cp.ready
		.cp_valid                (cmd_xbar_demux_001_src4_valid),                                                     //                .valid
		.cp_data                 (cmd_xbar_demux_001_src4_data),                                                      //                .data
		.cp_startofpacket        (cmd_xbar_demux_001_src4_startofpacket),                                             //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_001_src4_endofpacket),                                               //                .endofpacket
		.cp_channel              (cmd_xbar_demux_001_src4_channel),                                                   //                .channel
		.rf_sink_ready           (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (81),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_cpu),                                                                           //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                    // clk_reset.reset
		.in_data           (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                             // (terminated)
		.csr_read          (1'b0),                                                                              // (terminated)
		.csr_write         (1'b0),                                                                              // (terminated)
		.csr_readdata      (),                                                                                  // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                              // (terminated)
		.almost_full_data  (),                                                                                  // (terminated)
		.almost_empty_data (),                                                                                  // (terminated)
		.in_empty          (1'b0),                                                                              // (terminated)
		.out_empty         (),                                                                                  // (terminated)
		.in_error          (1'b0),                                                                              // (terminated)
		.out_error         (),                                                                                  // (terminated)
		.in_channel        (1'b0),                                                                              // (terminated)
		.out_channel       ()                                                                                   // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (72),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (60),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (61),
		.PKT_TRANS_POSTED          (62),
		.PKT_TRANS_WRITE           (63),
		.PKT_TRANS_READ            (64),
		.PKT_TRANS_LOCK            (65),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (73),
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_BURSTWRAP_H           (71),
		.PKT_BURSTWRAP_L           (69),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_PROTECTION_H          (79),
		.PKT_PROTECTION_L          (79),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (80),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_cpu),                                                                                       //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                //       clk_reset.reset
		.m0_address              (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_001_src5_ready),                                                                 //              cp.ready
		.cp_valid                (cmd_xbar_demux_001_src5_valid),                                                                 //                .valid
		.cp_data                 (cmd_xbar_demux_001_src5_data),                                                                  //                .data
		.cp_startofpacket        (cmd_xbar_demux_001_src5_startofpacket),                                                         //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_001_src5_endofpacket),                                                           //                .endofpacket
		.cp_channel              (cmd_xbar_demux_001_src5_channel),                                                               //                .channel
		.rf_sink_ready           (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (81),
		.FIFO_DEPTH          (2081),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_cpu),                                                                                       //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                // clk_reset.reset
		.in_data           (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                         // (terminated)
		.csr_read          (1'b0),                                                                                          // (terminated)
		.csr_write         (1'b0),                                                                                          // (terminated)
		.csr_readdata      (),                                                                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                          // (terminated)
		.almost_full_data  (),                                                                                              // (terminated)
		.almost_empty_data (),                                                                                              // (terminated)
		.in_empty          (1'b0),                                                                                          // (terminated)
		.out_empty         (),                                                                                              // (terminated)
		.in_error          (1'b0),                                                                                          // (terminated)
		.out_error         (),                                                                                              // (terminated)
		.in_channel        (1'b0),                                                                                          // (terminated)
		.out_channel       ()                                                                                               // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.PKT_BEGIN_BURST           (56),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.ST_DATA_W                 (68),
		.ST_CHANNEL_W              (23),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (7)
	) clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent (
		.clk              (pll_io),                                                                               //       clk.clk
		.reset            (rst_controller_002_reset_out_reset),                                                   // clk_reset.reset
		.av_address       (clock_crossing_bridge_m0_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (clock_crossing_bridge_m0_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (clock_crossing_bridge_m0_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (clock_crossing_bridge_m0_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (clock_crossing_bridge_m0_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (clock_crossing_bridge_m0_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (clock_crossing_bridge_m0_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (clock_crossing_bridge_m0_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (clock_crossing_bridge_m0_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (clock_crossing_bridge_m0_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (limiter_002_rsp_src_valid),                                                            //        rp.valid
		.rp_data          (limiter_002_rsp_src_data),                                                             //          .data
		.rp_channel       (limiter_002_rsp_src_channel),                                                          //          .channel
		.rp_startofpacket (limiter_002_rsp_src_startofpacket),                                                    //          .startofpacket
		.rp_endofpacket   (limiter_002_rsp_src_endofpacket),                                                      //          .endofpacket
		.rp_ready         (limiter_002_rsp_src_ready)                                                             //          .ready
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) timer_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                        //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                            //       clk_reset.reset
		.m0_address              (timer_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (timer_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (timer_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (timer_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (timer_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (timer_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (timer_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (timer_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (timer_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (timer_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (timer_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (timer_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (timer_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (timer_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (timer_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (timer_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src0_ready),                                                 //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src0_valid),                                                 //                .valid
		.cp_data                 (cmd_xbar_demux_002_src0_data),                                                  //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src0_startofpacket),                                         //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src0_endofpacket),                                           //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src0_channel),                                               //                .channel
		.rf_sink_ready           (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                        //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.in_data           (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (timer_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                         // (terminated)
		.csr_read          (1'b0),                                                                          // (terminated)
		.csr_write         (1'b0),                                                                          // (terminated)
		.csr_readdata      (),                                                                              // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                          // (terminated)
		.almost_full_data  (),                                                                              // (terminated)
		.almost_empty_data (),                                                                              // (terminated)
		.in_empty          (1'b0),                                                                          // (terminated)
		.out_empty         (),                                                                              // (terminated)
		.in_error          (1'b0),                                                                          // (terminated)
		.out_error         (),                                                                              // (terminated)
		.in_channel        (1'b0),                                                                          // (terminated)
		.out_channel       ()                                                                               // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src1_ready),                                                           //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src1_valid),                                                           //                .valid
		.cp_data                 (cmd_xbar_demux_002_src1_data),                                                            //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src1_startofpacket),                                                   //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src1_endofpacket),                                                     //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src1_channel),                                                         //                .channel
		.rf_sink_ready           (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src2_ready),                                                           //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src2_valid),                                                           //                .valid
		.cp_data                 (cmd_xbar_demux_002_src2_data),                                                            //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src2_startofpacket),                                                   //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src2_endofpacket),                                                     //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src2_channel),                                                         //                .channel
		.rf_sink_ready           (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src3_ready),                                                           //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src3_valid),                                                           //                .valid
		.cp_data                 (cmd_xbar_demux_002_src3_data),                                                            //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src3_startofpacket),                                                   //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src3_endofpacket),                                                     //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src3_channel),                                                         //                .channel
		.rf_sink_ready           (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src4_ready),                                                           //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src4_valid),                                                           //                .valid
		.cp_data                 (cmd_xbar_demux_002_src4_data),                                                            //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src4_startofpacket),                                                   //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src4_endofpacket),                                                     //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src4_channel),                                                         //                .channel
		.rf_sink_ready           (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src5_ready),                                                           //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src5_valid),                                                           //                .valid
		.cp_data                 (cmd_xbar_demux_002_src5_data),                                                            //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src5_startofpacket),                                                   //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src5_endofpacket),                                                     //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src5_channel),                                                         //                .channel
		.rf_sink_ready           (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                    //       clk_reset.reset
		.m0_address              (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src6_ready),                                                         //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src6_valid),                                                         //                .valid
		.cp_data                 (cmd_xbar_demux_002_src6_data),                                                          //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src6_startofpacket),                                                 //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src6_endofpacket),                                                   //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src6_channel),                                                       //                .channel
		.rf_sink_ready           (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                    // clk_reset.reset
		.in_data           (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                 // (terminated)
		.csr_read          (1'b0),                                                                                  // (terminated)
		.csr_write         (1'b0),                                                                                  // (terminated)
		.csr_readdata      (),                                                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                  // (terminated)
		.almost_full_data  (),                                                                                      // (terminated)
		.almost_empty_data (),                                                                                      // (terminated)
		.in_empty          (1'b0),                                                                                  // (terminated)
		.out_empty         (),                                                                                      // (terminated)
		.in_error          (1'b0),                                                                                  // (terminated)
		.out_error         (),                                                                                      // (terminated)
		.in_channel        (1'b0),                                                                                  // (terminated)
		.out_channel       ()                                                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src7_ready),                                                           //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src7_valid),                                                           //                .valid
		.cp_data                 (cmd_xbar_demux_002_src7_data),                                                            //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src7_startofpacket),                                                   //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src7_endofpacket),                                                     //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src7_channel),                                                         //                .channel
		.rf_sink_ready           (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) pio_led_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                          //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                              //       clk_reset.reset
		.m0_address              (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src8_ready),                                                   //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src8_valid),                                                   //                .valid
		.cp_data                 (cmd_xbar_demux_002_src8_data),                                                    //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src8_startofpacket),                                           //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src8_endofpacket),                                             //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src8_channel),                                                 //                .channel
		.rf_sink_ready           (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                          //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                              // clk_reset.reset
		.in_data           (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                           // (terminated)
		.csr_read          (1'b0),                                                                            // (terminated)
		.csr_write         (1'b0),                                                                            // (terminated)
		.csr_readdata      (),                                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                            // (terminated)
		.almost_full_data  (),                                                                                // (terminated)
		.almost_empty_data (),                                                                                // (terminated)
		.in_empty          (1'b0),                                                                            // (terminated)
		.out_empty         (),                                                                                // (terminated)
		.in_error          (1'b0),                                                                            // (terminated)
		.out_error         (),                                                                                // (terminated)
		.in_channel        (1'b0),                                                                            // (terminated)
		.out_channel       ()                                                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) pio_button_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                             //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                 //       clk_reset.reset
		.m0_address              (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (pio_button_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src9_ready),                                                      //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src9_valid),                                                      //                .valid
		.cp_data                 (cmd_xbar_demux_002_src9_data),                                                       //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src9_startofpacket),                                              //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src9_endofpacket),                                                //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src9_channel),                                                    //                .channel
		.rf_sink_ready           (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (pio_button_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                             //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                 // clk_reset.reset
		.in_data           (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (pio_button_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (pio_button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                              // (terminated)
		.csr_read          (1'b0),                                                                               // (terminated)
		.csr_write         (1'b0),                                                                               // (terminated)
		.csr_readdata      (),                                                                                   // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                               // (terminated)
		.almost_full_data  (),                                                                                   // (terminated)
		.almost_empty_data (),                                                                                   // (terminated)
		.in_empty          (1'b0),                                                                               // (terminated)
		.out_empty         (),                                                                                   // (terminated)
		.in_error          (1'b0),                                                                               // (terminated)
		.out_error         (),                                                                                   // (terminated)
		.in_channel        (1'b0),                                                                               // (terminated)
		.out_channel       ()                                                                                    // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) sysid_control_slave_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                   //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                       //       clk_reset.reset
		.m0_address              (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src10_ready),                                                           //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src10_valid),                                                           //                .valid
		.cp_data                 (cmd_xbar_demux_002_src10_data),                                                            //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src10_startofpacket),                                                   //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src10_endofpacket),                                                     //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src10_channel),                                                         //                .channel
		.rf_sink_ready           (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                   //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                       // clk_reset.reset
		.in_data           (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                    // (terminated)
		.csr_read          (1'b0),                                                                                     // (terminated)
		.csr_write         (1'b0),                                                                                     // (terminated)
		.csr_readdata      (),                                                                                         // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                     // (terminated)
		.almost_full_data  (),                                                                                         // (terminated)
		.almost_empty_data (),                                                                                         // (terminated)
		.in_empty          (1'b0),                                                                                     // (terminated)
		.out_empty         (),                                                                                         // (terminated)
		.in_error          (1'b0),                                                                                     // (terminated)
		.out_error         (),                                                                                         // (terminated)
		.in_channel        (1'b0),                                                                                     // (terminated)
		.out_channel       ()                                                                                          // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                    //       clk_reset.reset
		.m0_address              (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src11_ready),                                                        //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src11_valid),                                                        //                .valid
		.cp_data                 (cmd_xbar_demux_002_src11_data),                                                         //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src11_startofpacket),                                                //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src11_endofpacket),                                                  //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src11_channel),                                                      //                .channel
		.rf_sink_ready           (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                    // clk_reset.reset
		.in_data           (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                 // (terminated)
		.csr_read          (1'b0),                                                                                  // (terminated)
		.csr_write         (1'b0),                                                                                  // (terminated)
		.csr_readdata      (),                                                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                  // (terminated)
		.almost_full_data  (),                                                                                      // (terminated)
		.almost_empty_data (),                                                                                      // (terminated)
		.in_empty          (1'b0),                                                                                  // (terminated)
		.out_empty         (),                                                                                      // (terminated)
		.in_error          (1'b0),                                                                                  // (terminated)
		.out_error         (),                                                                                      // (terminated)
		.in_channel        (1'b0),                                                                                  // (terminated)
		.out_channel       ()                                                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                    //       clk_reset.reset
		.m0_address              (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src12_ready),                                                        //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src12_valid),                                                        //                .valid
		.cp_data                 (cmd_xbar_demux_002_src12_data),                                                         //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src12_startofpacket),                                                //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src12_endofpacket),                                                  //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src12_channel),                                                      //                .channel
		.rf_sink_ready           (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                    // clk_reset.reset
		.in_data           (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                 // (terminated)
		.csr_read          (1'b0),                                                                                  // (terminated)
		.csr_write         (1'b0),                                                                                  // (terminated)
		.csr_readdata      (),                                                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                  // (terminated)
		.almost_full_data  (),                                                                                      // (terminated)
		.almost_empty_data (),                                                                                      // (terminated)
		.in_empty          (1'b0),                                                                                  // (terminated)
		.out_empty         (),                                                                                      // (terminated)
		.in_error          (1'b0),                                                                                  // (terminated)
		.out_error         (),                                                                                      // (terminated)
		.in_channel        (1'b0),                                                                                  // (terminated)
		.out_channel       ()                                                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                              //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                  //       clk_reset.reset
		.m0_address              (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src13_ready),                                                      //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src13_valid),                                                      //                .valid
		.cp_data                 (cmd_xbar_demux_002_src13_data),                                                       //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src13_startofpacket),                                              //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src13_endofpacket),                                                //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src13_channel),                                                    //                .channel
		.rf_sink_ready           (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                              //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                  // clk_reset.reset
		.in_data           (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                               // (terminated)
		.csr_read          (1'b0),                                                                                // (terminated)
		.csr_write         (1'b0),                                                                                // (terminated)
		.csr_readdata      (),                                                                                    // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                // (terminated)
		.almost_full_data  (),                                                                                    // (terminated)
		.almost_empty_data (),                                                                                    // (terminated)
		.in_empty          (1'b0),                                                                                // (terminated)
		.out_empty         (),                                                                                    // (terminated)
		.in_error          (1'b0),                                                                                // (terminated)
		.out_error         (),                                                                                    // (terminated)
		.in_channel        (1'b0),                                                                                // (terminated)
		.out_channel       ()                                                                                     // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src14_ready),                                                          //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src14_valid),                                                          //                .valid
		.cp_data                 (cmd_xbar_demux_002_src14_data),                                                           //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src14_startofpacket),                                                  //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src14_endofpacket),                                                    //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src14_channel),                                                        //                .channel
		.rf_sink_ready           (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src15_ready),                                                          //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src15_valid),                                                          //                .valid
		.cp_data                 (cmd_xbar_demux_002_src15_data),                                                           //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src15_startofpacket),                                                  //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src15_endofpacket),                                                    //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src15_channel),                                                        //                .channel
		.rf_sink_ready           (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src16_ready),                                                          //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src16_valid),                                                          //                .valid
		.cp_data                 (cmd_xbar_demux_002_src16_data),                                                           //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src16_startofpacket),                                                  //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src16_endofpacket),                                                    //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src16_channel),                                                        //                .channel
		.rf_sink_ready           (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src17_ready),                                                          //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src17_valid),                                                          //                .valid
		.cp_data                 (cmd_xbar_demux_002_src17_data),                                                           //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src17_startofpacket),                                                  //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src17_endofpacket),                                                    //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src17_channel),                                                        //                .channel
		.rf_sink_ready           (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                               //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                   //       clk_reset.reset
		.m0_address              (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src18_ready),                                                       //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src18_valid),                                                       //                .valid
		.cp_data                 (cmd_xbar_demux_002_src18_data),                                                        //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src18_startofpacket),                                               //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src18_endofpacket),                                                 //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src18_channel),                                                     //                .channel
		.rf_sink_ready           (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                               //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                   // clk_reset.reset
		.in_data           (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                // (terminated)
		.csr_read          (1'b0),                                                                                 // (terminated)
		.csr_write         (1'b0),                                                                                 // (terminated)
		.csr_readdata      (),                                                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                 // (terminated)
		.almost_full_data  (),                                                                                     // (terminated)
		.almost_empty_data (),                                                                                     // (terminated)
		.in_empty          (1'b0),                                                                                 // (terminated)
		.out_empty         (),                                                                                     // (terminated)
		.in_error          (1'b0),                                                                                 // (terminated)
		.out_error         (),                                                                                     // (terminated)
		.in_channel        (1'b0),                                                                                 // (terminated)
		.out_channel       ()                                                                                      // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                    //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                        //       clk_reset.reset
		.m0_address              (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src19_ready),                                                            //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src19_valid),                                                            //                .valid
		.cp_data                 (cmd_xbar_demux_002_src19_data),                                                             //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src19_startofpacket),                                                    //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src19_endofpacket),                                                      //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src19_channel),                                                          //                .channel
		.rf_sink_ready           (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                    //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                        // clk_reset.reset
		.in_data           (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                     // (terminated)
		.csr_read          (1'b0),                                                                                      // (terminated)
		.csr_write         (1'b0),                                                                                      // (terminated)
		.csr_readdata      (),                                                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                      // (terminated)
		.almost_full_data  (),                                                                                          // (terminated)
		.almost_empty_data (),                                                                                          // (terminated)
		.in_empty          (1'b0),                                                                                      // (terminated)
		.out_empty         (),                                                                                          // (terminated)
		.in_error          (1'b0),                                                                                      // (terminated)
		.out_error         (),                                                                                          // (terminated)
		.in_channel        (1'b0),                                                                                      // (terminated)
		.out_channel       ()                                                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                      //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                          //       clk_reset.reset
		.m0_address              (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src20_ready),                                                              //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src20_valid),                                                              //                .valid
		.cp_data                 (cmd_xbar_demux_002_src20_data),                                                               //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src20_startofpacket),                                                      //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src20_endofpacket),                                                        //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src20_channel),                                                            //                .channel
		.rf_sink_ready           (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                      //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                          // clk_reset.reset
		.in_data           (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                       // (terminated)
		.csr_read          (1'b0),                                                                                        // (terminated)
		.csr_write         (1'b0),                                                                                        // (terminated)
		.csr_readdata      (),                                                                                            // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                        // (terminated)
		.almost_full_data  (),                                                                                            // (terminated)
		.almost_empty_data (),                                                                                            // (terminated)
		.in_empty          (1'b0),                                                                                        // (terminated)
		.out_empty         (),                                                                                            // (terminated)
		.in_error          (1'b0),                                                                                        // (terminated)
		.out_error         (),                                                                                            // (terminated)
		.in_channel        (1'b0),                                                                                        // (terminated)
		.out_channel       ()                                                                                             // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                    //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                        //       clk_reset.reset
		.m0_address              (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src21_ready),                                                            //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src21_valid),                                                            //                .valid
		.cp_data                 (cmd_xbar_demux_002_src21_data),                                                             //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src21_startofpacket),                                                    //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src21_endofpacket),                                                      //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src21_channel),                                                          //                .channel
		.rf_sink_ready           (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                    //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                        // clk_reset.reset
		.in_data           (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                     // (terminated)
		.csr_read          (1'b0),                                                                                      // (terminated)
		.csr_write         (1'b0),                                                                                      // (terminated)
		.csr_readdata      (),                                                                                          // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                      // (terminated)
		.almost_full_data  (),                                                                                          // (terminated)
		.almost_empty_data (),                                                                                          // (terminated)
		.in_empty          (1'b0),                                                                                      // (terminated)
		.out_empty         (),                                                                                          // (terminated)
		.in_error          (1'b0),                                                                                      // (terminated)
		.out_error         (),                                                                                          // (terminated)
		.in_channel        (1'b0),                                                                                      // (terminated)
		.out_channel       ()                                                                                           // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (56),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_TRANS_LOCK            (49),
		.PKT_SRC_ID_H              (61),
		.PKT_SRC_ID_L              (57),
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_BURSTWRAP_H           (55),
		.PKT_BURSTWRAP_L           (53),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_PROTECTION_H          (67),
		.PKT_PROTECTION_L          (67),
		.ST_CHANNEL_W              (23),
		.ST_DATA_W                 (68),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (pll_io),                                                                                  //             clk.clk
		.reset                   (rst_controller_002_reset_out_reset),                                                      //       clk_reset.reset
		.m0_address              (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_002_src22_ready),                                                          //              cp.ready
		.cp_valid                (cmd_xbar_demux_002_src22_valid),                                                          //                .valid
		.cp_data                 (cmd_xbar_demux_002_src22_data),                                                           //                .data
		.cp_startofpacket        (cmd_xbar_demux_002_src22_startofpacket),                                                  //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_002_src22_endofpacket),                                                    //                .endofpacket
		.cp_channel              (cmd_xbar_demux_002_src22_channel),                                                        //                .channel
		.rf_sink_ready           (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (69),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (pll_io),                                                                                  //       clk.clk
		.reset             (rst_controller_002_reset_out_reset),                                                      // clk_reset.reset
		.in_data           (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                   // (terminated)
		.csr_read          (1'b0),                                                                                    // (terminated)
		.csr_write         (1'b0),                                                                                    // (terminated)
		.csr_readdata      (),                                                                                        // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                    // (terminated)
		.almost_full_data  (),                                                                                        // (terminated)
		.almost_empty_data (),                                                                                        // (terminated)
		.in_empty          (1'b0),                                                                                    // (terminated)
		.out_empty         (),                                                                                        // (terminated)
		.in_error          (1'b0),                                                                                    // (terminated)
		.out_error         (),                                                                                        // (terminated)
		.in_channel        (1'b0),                                                                                    // (terminated)
		.out_channel       ()                                                                                         // (terminated)
	);

	TR4_HDMI_TX_RX_SOPC_addr_router addr_router (
		.sink_ready         (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pll_cpu),                                                                            //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                     // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                                              //       src.ready
		.src_valid          (addr_router_src_valid),                                                              //          .valid
		.src_data           (addr_router_src_data),                                                               //          .data
		.src_channel        (addr_router_src_channel),                                                            //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                                      //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                                         //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_addr_router_001 addr_router_001 (
		.sink_ready         (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pll_cpu),                                                                     //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                              // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                                   //       src.ready
		.src_valid          (addr_router_001_src_valid),                                                   //          .valid
		.src_data           (addr_router_001_src_data),                                                    //          .data
		.src_channel        (addr_router_001_src_channel),                                                 //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                           //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                              //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router id_router (
		.sink_ready         (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_cpu),                                                                          //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                   // clk_reset.reset
		.src_ready          (id_router_src_ready),                                                              //       src.ready
		.src_valid          (id_router_src_valid),                                                              //          .valid
		.src_data           (id_router_src_data),                                                               //          .data
		.src_channel        (id_router_src_channel),                                                            //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                                      //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                                         //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router id_router_001 (
		.sink_ready         (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_cpu),                                                                      //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                               // clk_reset.reset
		.src_ready          (id_router_001_src_ready),                                                      //       src.ready
		.src_valid          (id_router_001_src_valid),                                                      //          .valid
		.src_data           (id_router_001_src_data),                                                       //          .data
		.src_channel        (id_router_001_src_channel),                                                    //          .channel
		.src_startofpacket  (id_router_001_src_startofpacket),                                              //          .startofpacket
		.src_endofpacket    (id_router_001_src_endofpacket)                                                 //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_002 id_router_002 (
		.sink_ready         (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_cpu),                                                                                //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                         // clk_reset.reset
		.src_ready          (id_router_002_src_ready),                                                                //       src.ready
		.src_valid          (id_router_002_src_valid),                                                                //          .valid
		.src_data           (id_router_002_src_data),                                                                 //          .data
		.src_channel        (id_router_002_src_channel),                                                              //          .channel
		.src_startofpacket  (id_router_002_src_startofpacket),                                                        //          .startofpacket
		.src_endofpacket    (id_router_002_src_endofpacket)                                                           //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_002 id_router_003 (
		.sink_ready         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (pll_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (clk),                                                                      //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),                                       // clk_reset.reset
		.src_ready          (id_router_003_src_ready),                                                  //       src.ready
		.src_valid          (id_router_003_src_valid),                                                  //          .valid
		.src_data           (id_router_003_src_data),                                                   //          .data
		.src_channel        (id_router_003_src_channel),                                                //          .channel
		.src_startofpacket  (id_router_003_src_startofpacket),                                          //          .startofpacket
		.src_endofpacket    (id_router_003_src_endofpacket)                                             //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_002 id_router_004 (
		.sink_ready         (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (i2s_tx_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_cpu),                                                                 //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                          // clk_reset.reset
		.src_ready          (id_router_004_src_ready),                                                 //       src.ready
		.src_valid          (id_router_004_src_valid),                                                 //          .valid
		.src_data           (id_router_004_src_data),                                                  //          .data
		.src_channel        (id_router_004_src_channel),                                               //          .channel
		.src_startofpacket  (id_router_004_src_startofpacket),                                         //          .startofpacket
		.src_endofpacket    (id_router_004_src_endofpacket)                                            //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_002 id_router_005 (
		.sink_ready         (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_cpu),                                                                             //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                      // clk_reset.reset
		.src_ready          (id_router_005_src_ready),                                                             //       src.ready
		.src_valid          (id_router_005_src_valid),                                                             //          .valid
		.src_data           (id_router_005_src_data),                                                              //          .data
		.src_channel        (id_router_005_src_channel),                                                           //          .channel
		.src_startofpacket  (id_router_005_src_startofpacket),                                                     //          .startofpacket
		.src_endofpacket    (id_router_005_src_endofpacket)                                                        //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_addr_router_002 addr_router_002 (
		.sink_ready         (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                               //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                                   // clk_reset.reset
		.src_ready          (addr_router_002_src_ready),                                                            //       src.ready
		.src_valid          (addr_router_002_src_valid),                                                            //          .valid
		.src_data           (addr_router_002_src_data),                                                             //          .data
		.src_channel        (addr_router_002_src_channel),                                                          //          .channel
		.src_startofpacket  (addr_router_002_src_startofpacket),                                                    //          .startofpacket
		.src_endofpacket    (addr_router_002_src_endofpacket)                                                       //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_006 (
		.sink_ready         (timer_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (timer_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (timer_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (timer_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (timer_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                              //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                  // clk_reset.reset
		.src_ready          (id_router_006_src_ready),                                             //       src.ready
		.src_valid          (id_router_006_src_valid),                                             //          .valid
		.src_data           (id_router_006_src_data),                                              //          .data
		.src_channel        (id_router_006_src_channel),                                           //          .channel
		.src_startofpacket  (id_router_006_src_startofpacket),                                     //          .startofpacket
		.src_endofpacket    (id_router_006_src_endofpacket)                                        //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_007 (
		.sink_ready         (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_tx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_007_src_ready),                                                       //       src.ready
		.src_valid          (id_router_007_src_valid),                                                       //          .valid
		.src_data           (id_router_007_src_data),                                                        //          .data
		.src_channel        (id_router_007_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_007_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_007_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_008 (
		.sink_ready         (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_tx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_008_src_ready),                                                       //       src.ready
		.src_valid          (id_router_008_src_valid),                                                       //          .valid
		.src_data           (id_router_008_src_data),                                                        //          .data
		.src_channel        (id_router_008_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_008_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_008_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_009 (
		.sink_ready         (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_009_src_ready),                                                       //       src.ready
		.src_valid          (id_router_009_src_valid),                                                       //          .valid
		.src_data           (id_router_009_src_data),                                                        //          .data
		.src_channel        (id_router_009_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_009_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_009_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_010 (
		.sink_ready         (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_010_src_ready),                                                       //       src.ready
		.src_valid          (id_router_010_src_valid),                                                       //          .valid
		.src_data           (id_router_010_src_data),                                                        //          .data
		.src_channel        (id_router_010_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_010_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_010_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_011 (
		.sink_ready         (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_tx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_011_src_ready),                                                       //       src.ready
		.src_valid          (id_router_011_src_valid),                                                       //          .valid
		.src_data           (id_router_011_src_data),                                                        //          .data
		.src_channel        (id_router_011_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_011_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_011_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_012 (
		.sink_ready         (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_tx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                      //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                          // clk_reset.reset
		.src_ready          (id_router_012_src_ready),                                                     //       src.ready
		.src_valid          (id_router_012_src_valid),                                                     //          .valid
		.src_data           (id_router_012_src_data),                                                      //          .data
		.src_channel        (id_router_012_src_channel),                                                   //          .channel
		.src_startofpacket  (id_router_012_src_startofpacket),                                             //          .startofpacket
		.src_endofpacket    (id_router_012_src_endofpacket)                                                //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_013 (
		.sink_ready         (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_reset_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_013_src_ready),                                                       //       src.ready
		.src_valid          (id_router_013_src_valid),                                                       //          .valid
		.src_data           (id_router_013_src_data),                                                        //          .data
		.src_channel        (id_router_013_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_013_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_013_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_014 (
		.sink_ready         (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                    // clk_reset.reset
		.src_ready          (id_router_014_src_ready),                                               //       src.ready
		.src_valid          (id_router_014_src_valid),                                               //          .valid
		.src_data           (id_router_014_src_data),                                                //          .data
		.src_channel        (id_router_014_src_channel),                                             //          .channel
		.src_startofpacket  (id_router_014_src_startofpacket),                                       //          .startofpacket
		.src_endofpacket    (id_router_014_src_endofpacket)                                          //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_015 (
		.sink_ready         (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (pio_button_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                   //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                       // clk_reset.reset
		.src_ready          (id_router_015_src_ready),                                                  //       src.ready
		.src_valid          (id_router_015_src_valid),                                                  //          .valid
		.src_data           (id_router_015_src_data),                                                   //          .data
		.src_channel        (id_router_015_src_channel),                                                //          .channel
		.src_startofpacket  (id_router_015_src_startofpacket),                                          //          .startofpacket
		.src_endofpacket    (id_router_015_src_endofpacket)                                             //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_016 (
		.sink_ready         (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                         //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                             // clk_reset.reset
		.src_ready          (id_router_016_src_ready),                                                        //       src.ready
		.src_valid          (id_router_016_src_valid),                                                        //          .valid
		.src_data           (id_router_016_src_data),                                                         //          .data
		.src_channel        (id_router_016_src_channel),                                                      //          .channel
		.src_startofpacket  (id_router_016_src_startofpacket),                                                //          .startofpacket
		.src_endofpacket    (id_router_016_src_endofpacket)                                                   //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_017 (
		.sink_ready         (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_irq_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                      //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                          // clk_reset.reset
		.src_ready          (id_router_017_src_ready),                                                     //       src.ready
		.src_valid          (id_router_017_src_valid),                                                     //          .valid
		.src_data           (id_router_017_src_data),                                                      //          .data
		.src_channel        (id_router_017_src_channel),                                                   //          .channel
		.src_startofpacket  (id_router_017_src_startofpacket),                                             //          .startofpacket
		.src_endofpacket    (id_router_017_src_endofpacket)                                                //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_018 (
		.sink_ready         (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_hpd_n_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                      //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                          // clk_reset.reset
		.src_ready          (id_router_018_src_ready),                                                     //       src.ready
		.src_valid          (id_router_018_src_valid),                                                     //          .valid
		.src_data           (id_router_018_src_data),                                                      //          .data
		.src_channel        (id_router_018_src_channel),                                                   //          .channel
		.src_startofpacket  (id_router_018_src_startofpacket),                                             //          .startofpacket
		.src_endofpacket    (id_router_018_src_endofpacket)                                                //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_019 (
		.sink_ready         (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_cec_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                    //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                        // clk_reset.reset
		.src_ready          (id_router_019_src_ready),                                                   //       src.ready
		.src_valid          (id_router_019_src_valid),                                                   //          .valid
		.src_data           (id_router_019_src_data),                                                    //          .data
		.src_channel        (id_router_019_src_channel),                                                 //          .channel
		.src_startofpacket  (id_router_019_src_startofpacket),                                           //          .startofpacket
		.src_endofpacket    (id_router_019_src_endofpacket)                                              //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_020 (
		.sink_ready         (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx0_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_020_src_ready),                                                       //       src.ready
		.src_valid          (id_router_020_src_valid),                                                       //          .valid
		.src_data           (id_router_020_src_data),                                                        //          .data
		.src_channel        (id_router_020_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_020_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_020_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_021 (
		.sink_ready         (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx0_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_021_src_ready),                                                       //       src.ready
		.src_valid          (id_router_021_src_valid),                                                       //          .valid
		.src_data           (id_router_021_src_data),                                                        //          .data
		.src_channel        (id_router_021_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_021_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_021_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_022 (
		.sink_ready         (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx1_ep_scl_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_022_src_ready),                                                       //       src.ready
		.src_valid          (id_router_022_src_valid),                                                       //          .valid
		.src_data           (id_router_022_src_data),                                                        //          .data
		.src_channel        (id_router_022_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_022_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_022_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_023 (
		.sink_ready         (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx1_ep_sda_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_023_src_ready),                                                       //       src.ready
		.src_valid          (id_router_023_src_valid),                                                       //          .valid
		.src_data           (id_router_023_src_data),                                                        //          .data
		.src_channel        (id_router_023_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_023_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_023_src_endofpacket)                                                  //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_024 (
		.sink_ready         (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_sync_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                     //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                         // clk_reset.reset
		.src_ready          (id_router_024_src_ready),                                                    //       src.ready
		.src_valid          (id_router_024_src_valid),                                                    //          .valid
		.src_data           (id_router_024_src_data),                                                     //          .data
		.src_channel        (id_router_024_src_channel),                                                  //          .channel
		.src_startofpacket  (id_router_024_src_startofpacket),                                            //          .startofpacket
		.src_endofpacket    (id_router_024_src_endofpacket)                                               //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_025 (
		.sink_ready         (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_tx_disp_mode_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                          //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                              // clk_reset.reset
		.src_ready          (id_router_025_src_ready),                                                         //       src.ready
		.src_valid          (id_router_025_src_valid),                                                         //          .valid
		.src_data           (id_router_025_src_data),                                                          //          .data
		.src_channel        (id_router_025_src_channel),                                                       //          .channel
		.src_startofpacket  (id_router_025_src_startofpacket),                                                 //          .startofpacket
		.src_endofpacket    (id_router_025_src_endofpacket)                                                    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_026 (
		.sink_ready         (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_tx_mode_change_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                            //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                                // clk_reset.reset
		.src_ready          (id_router_026_src_ready),                                                           //       src.ready
		.src_valid          (id_router_026_src_valid),                                                           //          .valid
		.src_data           (id_router_026_src_data),                                                            //          .data
		.src_channel        (id_router_026_src_channel),                                                         //          .channel
		.src_startofpacket  (id_router_026_src_startofpacket),                                                   //          .startofpacket
		.src_endofpacket    (id_router_026_src_endofpacket)                                                      //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_027 (
		.sink_ready         (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_tx_vpg_color_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                          //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                              // clk_reset.reset
		.src_ready          (id_router_027_src_ready),                                                         //       src.ready
		.src_valid          (id_router_027_src_valid),                                                         //          .valid
		.src_data           (id_router_027_src_data),                                                          //          .data
		.src_channel        (id_router_027_src_channel),                                                       //          .channel
		.src_startofpacket  (id_router_027_src_startofpacket),                                                 //          .startofpacket
		.src_endofpacket    (id_router_027_src_endofpacket)                                                    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_id_router_006 id_router_028 (
		.sink_ready         (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (hdmi_rx_edid_wp_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (pll_io),                                                                        //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),                                            // clk_reset.reset
		.src_ready          (id_router_028_src_ready),                                                       //       src.ready
		.src_valid          (id_router_028_src_valid),                                                       //          .valid
		.src_data           (id_router_028_src_data),                                                        //          .data
		.src_channel        (id_router_028_src_channel),                                                     //          .channel
		.src_startofpacket  (id_router_028_src_startofpacket),                                               //          .startofpacket
		.src_endofpacket    (id_router_028_src_endofpacket)                                                  //          .endofpacket
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_TRANS_POSTED          (62),
		.MAX_OUTSTANDING_RESPONSES (5),
		.PIPELINED                 (0),
		.ST_DATA_W                 (80),
		.ST_CHANNEL_W              (6),
		.VALID_WIDTH               (6),
		.ENFORCE_ORDER             (1),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32)
	) limiter (
		.clk                    (pll_cpu),                        //       clk.clk
		.reset                  (rst_controller_reset_out_reset), // clk_reset.reset
		.cmd_sink_ready         (addr_router_src_ready),          //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_src_valid),          //          .valid
		.cmd_sink_data          (addr_router_src_data),           //          .data
		.cmd_sink_channel       (addr_router_src_channel),        //          .channel
		.cmd_sink_startofpacket (addr_router_src_startofpacket),  //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_src_endofpacket),    //          .endofpacket
		.cmd_src_ready          (limiter_cmd_src_ready),          //   cmd_src.ready
		.cmd_src_data           (limiter_cmd_src_data),           //          .data
		.cmd_src_channel        (limiter_cmd_src_channel),        //          .channel
		.cmd_src_startofpacket  (limiter_cmd_src_startofpacket),  //          .startofpacket
		.cmd_src_endofpacket    (limiter_cmd_src_endofpacket),    //          .endofpacket
		.rsp_sink_ready         (rsp_xbar_mux_src_ready),         //  rsp_sink.ready
		.rsp_sink_valid         (rsp_xbar_mux_src_valid),         //          .valid
		.rsp_sink_channel       (rsp_xbar_mux_src_channel),       //          .channel
		.rsp_sink_data          (rsp_xbar_mux_src_data),          //          .data
		.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), //          .startofpacket
		.rsp_sink_endofpacket   (rsp_xbar_mux_src_endofpacket),   //          .endofpacket
		.rsp_src_ready          (limiter_rsp_src_ready),          //   rsp_src.ready
		.rsp_src_valid          (limiter_rsp_src_valid),          //          .valid
		.rsp_src_data           (limiter_rsp_src_data),           //          .data
		.rsp_src_channel        (limiter_rsp_src_channel),        //          .channel
		.rsp_src_startofpacket  (limiter_rsp_src_startofpacket),  //          .startofpacket
		.rsp_src_endofpacket    (limiter_rsp_src_endofpacket),    //          .endofpacket
		.cmd_src_valid          (limiter_cmd_valid_data)          // cmd_valid.data
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (78),
		.PKT_DEST_ID_L             (76),
		.PKT_TRANS_POSTED          (62),
		.MAX_OUTSTANDING_RESPONSES (2084),
		.PIPELINED                 (0),
		.ST_DATA_W                 (80),
		.ST_CHANNEL_W              (6),
		.VALID_WIDTH               (6),
		.ENFORCE_ORDER             (0),
		.PKT_BYTE_CNT_H            (68),
		.PKT_BYTE_CNT_L            (66),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32)
	) limiter_001 (
		.clk                    (pll_cpu),                            //       clk.clk
		.reset                  (rst_controller_reset_out_reset),     // clk_reset.reset
		.cmd_sink_ready         (addr_router_001_src_ready),          //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_001_src_valid),          //          .valid
		.cmd_sink_data          (addr_router_001_src_data),           //          .data
		.cmd_sink_channel       (addr_router_001_src_channel),        //          .channel
		.cmd_sink_startofpacket (addr_router_001_src_startofpacket),  //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_001_src_endofpacket),    //          .endofpacket
		.cmd_src_ready          (limiter_001_cmd_src_ready),          //   cmd_src.ready
		.cmd_src_data           (limiter_001_cmd_src_data),           //          .data
		.cmd_src_channel        (limiter_001_cmd_src_channel),        //          .channel
		.cmd_src_startofpacket  (limiter_001_cmd_src_startofpacket),  //          .startofpacket
		.cmd_src_endofpacket    (limiter_001_cmd_src_endofpacket),    //          .endofpacket
		.rsp_sink_ready         (rsp_xbar_mux_001_src_ready),         //  rsp_sink.ready
		.rsp_sink_valid         (rsp_xbar_mux_001_src_valid),         //          .valid
		.rsp_sink_channel       (rsp_xbar_mux_001_src_channel),       //          .channel
		.rsp_sink_data          (rsp_xbar_mux_001_src_data),          //          .data
		.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), //          .startofpacket
		.rsp_sink_endofpacket   (rsp_xbar_mux_001_src_endofpacket),   //          .endofpacket
		.rsp_src_ready          (limiter_001_rsp_src_ready),          //   rsp_src.ready
		.rsp_src_valid          (limiter_001_rsp_src_valid),          //          .valid
		.rsp_src_data           (limiter_001_rsp_src_data),           //          .data
		.rsp_src_channel        (limiter_001_rsp_src_channel),        //          .channel
		.rsp_src_startofpacket  (limiter_001_rsp_src_startofpacket),  //          .startofpacket
		.rsp_src_endofpacket    (limiter_001_rsp_src_endofpacket),    //          .endofpacket
		.cmd_src_valid          (limiter_001_cmd_valid_data)          // cmd_valid.data
	);

	altera_merlin_traffic_limiter #(
		.PKT_DEST_ID_H             (66),
		.PKT_DEST_ID_L             (62),
		.PKT_TRANS_POSTED          (46),
		.MAX_OUTSTANDING_RESPONSES (5),
		.PIPELINED                 (0),
		.ST_DATA_W                 (68),
		.ST_CHANNEL_W              (23),
		.VALID_WIDTH               (23),
		.ENFORCE_ORDER             (1),
		.PKT_BYTE_CNT_H            (52),
		.PKT_BYTE_CNT_L            (50),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32)
	) limiter_002 (
		.clk                    (pll_io),                             //       clk.clk
		.reset                  (rst_controller_002_reset_out_reset), // clk_reset.reset
		.cmd_sink_ready         (addr_router_002_src_ready),          //  cmd_sink.ready
		.cmd_sink_valid         (addr_router_002_src_valid),          //          .valid
		.cmd_sink_data          (addr_router_002_src_data),           //          .data
		.cmd_sink_channel       (addr_router_002_src_channel),        //          .channel
		.cmd_sink_startofpacket (addr_router_002_src_startofpacket),  //          .startofpacket
		.cmd_sink_endofpacket   (addr_router_002_src_endofpacket),    //          .endofpacket
		.cmd_src_ready          (limiter_002_cmd_src_ready),          //   cmd_src.ready
		.cmd_src_data           (limiter_002_cmd_src_data),           //          .data
		.cmd_src_channel        (limiter_002_cmd_src_channel),        //          .channel
		.cmd_src_startofpacket  (limiter_002_cmd_src_startofpacket),  //          .startofpacket
		.cmd_src_endofpacket    (limiter_002_cmd_src_endofpacket),    //          .endofpacket
		.rsp_sink_ready         (rsp_xbar_mux_002_src_ready),         //  rsp_sink.ready
		.rsp_sink_valid         (rsp_xbar_mux_002_src_valid),         //          .valid
		.rsp_sink_channel       (rsp_xbar_mux_002_src_channel),       //          .channel
		.rsp_sink_data          (rsp_xbar_mux_002_src_data),          //          .data
		.rsp_sink_startofpacket (rsp_xbar_mux_002_src_startofpacket), //          .startofpacket
		.rsp_sink_endofpacket   (rsp_xbar_mux_002_src_endofpacket),   //          .endofpacket
		.rsp_src_ready          (limiter_002_rsp_src_ready),          //   rsp_src.ready
		.rsp_src_valid          (limiter_002_rsp_src_valid),          //          .valid
		.rsp_src_data           (limiter_002_rsp_src_data),           //          .data
		.rsp_src_channel        (limiter_002_rsp_src_channel),        //          .channel
		.rsp_src_startofpacket  (limiter_002_rsp_src_startofpacket),  //          .startofpacket
		.rsp_src_endofpacket    (limiter_002_rsp_src_endofpacket),    //          .endofpacket
		.cmd_src_valid          (limiter_002_cmd_valid_data)          // cmd_valid.data
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (2),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~reset_n),                          // reset_in0.reset
		.reset_in1  (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
		.clk        (pll_cpu),                           //       clk.clk
		.reset_out  (rst_controller_reset_out_reset),    // reset_out.reset
		.reset_in2  (1'b0),                              // (terminated)
		.reset_in3  (1'b0),                              // (terminated)
		.reset_in4  (1'b0),                              // (terminated)
		.reset_in5  (1'b0),                              // (terminated)
		.reset_in6  (1'b0),                              // (terminated)
		.reset_in7  (1'b0),                              // (terminated)
		.reset_in8  (1'b0),                              // (terminated)
		.reset_in9  (1'b0),                              // (terminated)
		.reset_in10 (1'b0),                              // (terminated)
		.reset_in11 (1'b0),                              // (terminated)
		.reset_in12 (1'b0),                              // (terminated)
		.reset_in13 (1'b0),                              // (terminated)
		.reset_in14 (1'b0),                              // (terminated)
		.reset_in15 (1'b0)                               // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (2),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller_001 (
		.reset_in0  (~reset_n),                           // reset_in0.reset
		.reset_in1  (cpu_jtag_debug_module_reset_reset),  // reset_in1.reset
		.clk        (clk),                                //       clk.clk
		.reset_out  (rst_controller_001_reset_out_reset), // reset_out.reset
		.reset_in2  (1'b0),                               // (terminated)
		.reset_in3  (1'b0),                               // (terminated)
		.reset_in4  (1'b0),                               // (terminated)
		.reset_in5  (1'b0),                               // (terminated)
		.reset_in6  (1'b0),                               // (terminated)
		.reset_in7  (1'b0),                               // (terminated)
		.reset_in8  (1'b0),                               // (terminated)
		.reset_in9  (1'b0),                               // (terminated)
		.reset_in10 (1'b0),                               // (terminated)
		.reset_in11 (1'b0),                               // (terminated)
		.reset_in12 (1'b0),                               // (terminated)
		.reset_in13 (1'b0),                               // (terminated)
		.reset_in14 (1'b0),                               // (terminated)
		.reset_in15 (1'b0)                                // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (2),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller_002 (
		.reset_in0  (~reset_n),                           // reset_in0.reset
		.reset_in1  (cpu_jtag_debug_module_reset_reset),  // reset_in1.reset
		.clk        (pll_io),                             //       clk.clk
		.reset_out  (rst_controller_002_reset_out_reset), // reset_out.reset
		.reset_in2  (1'b0),                               // (terminated)
		.reset_in3  (1'b0),                               // (terminated)
		.reset_in4  (1'b0),                               // (terminated)
		.reset_in5  (1'b0),                               // (terminated)
		.reset_in6  (1'b0),                               // (terminated)
		.reset_in7  (1'b0),                               // (terminated)
		.reset_in8  (1'b0),                               // (terminated)
		.reset_in9  (1'b0),                               // (terminated)
		.reset_in10 (1'b0),                               // (terminated)
		.reset_in11 (1'b0),                               // (terminated)
		.reset_in12 (1'b0),                               // (terminated)
		.reset_in13 (1'b0),                               // (terminated)
		.reset_in14 (1'b0),                               // (terminated)
		.reset_in15 (1'b0)                                // (terminated)
	);

	TR4_HDMI_TX_RX_SOPC_cmd_xbar_demux cmd_xbar_demux (
		.clk                (pll_cpu),                           //        clk.clk
		.reset              (rst_controller_reset_out_reset),    //  clk_reset.reset
		.sink_ready         (limiter_cmd_src_ready),             //       sink.ready
		.sink_channel       (limiter_cmd_src_channel),           //           .channel
		.sink_data          (limiter_cmd_src_data),              //           .data
		.sink_startofpacket (limiter_cmd_src_startofpacket),     //           .startofpacket
		.sink_endofpacket   (limiter_cmd_src_endofpacket),       //           .endofpacket
		.sink_valid         (limiter_cmd_valid_data),            // sink_valid.data
		.src0_ready         (cmd_xbar_demux_src0_ready),         //       src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),         //           .valid
		.src0_data          (cmd_xbar_demux_src0_data),          //           .data
		.src0_channel       (cmd_xbar_demux_src0_channel),       //           .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), //           .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket),   //           .endofpacket
		.src1_ready         (cmd_xbar_demux_src1_ready),         //       src1.ready
		.src1_valid         (cmd_xbar_demux_src1_valid),         //           .valid
		.src1_data          (cmd_xbar_demux_src1_data),          //           .data
		.src1_channel       (cmd_xbar_demux_src1_channel),       //           .channel
		.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), //           .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_src1_endofpacket)    //           .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_cmd_xbar_demux_001 cmd_xbar_demux_001 (
		.clk                (pll_cpu),                               //        clk.clk
		.reset              (rst_controller_reset_out_reset),        //  clk_reset.reset
		.sink_ready         (limiter_001_cmd_src_ready),             //       sink.ready
		.sink_channel       (limiter_001_cmd_src_channel),           //           .channel
		.sink_data          (limiter_001_cmd_src_data),              //           .data
		.sink_startofpacket (limiter_001_cmd_src_startofpacket),     //           .startofpacket
		.sink_endofpacket   (limiter_001_cmd_src_endofpacket),       //           .endofpacket
		.sink_valid         (limiter_001_cmd_valid_data),            // sink_valid.data
		.src0_ready         (cmd_xbar_demux_001_src0_ready),         //       src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),         //           .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),          //           .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),       //           .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //           .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket),   //           .endofpacket
		.src1_ready         (cmd_xbar_demux_001_src1_ready),         //       src1.ready
		.src1_valid         (cmd_xbar_demux_001_src1_valid),         //           .valid
		.src1_data          (cmd_xbar_demux_001_src1_data),          //           .data
		.src1_channel       (cmd_xbar_demux_001_src1_channel),       //           .channel
		.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), //           .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket),   //           .endofpacket
		.src2_ready         (cmd_xbar_demux_001_src2_ready),         //       src2.ready
		.src2_valid         (cmd_xbar_demux_001_src2_valid),         //           .valid
		.src2_data          (cmd_xbar_demux_001_src2_data),          //           .data
		.src2_channel       (cmd_xbar_demux_001_src2_channel),       //           .channel
		.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), //           .startofpacket
		.src2_endofpacket   (cmd_xbar_demux_001_src2_endofpacket),   //           .endofpacket
		.src3_ready         (cmd_xbar_demux_001_src3_ready),         //       src3.ready
		.src3_valid         (cmd_xbar_demux_001_src3_valid),         //           .valid
		.src3_data          (cmd_xbar_demux_001_src3_data),          //           .data
		.src3_channel       (cmd_xbar_demux_001_src3_channel),       //           .channel
		.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), //           .startofpacket
		.src3_endofpacket   (cmd_xbar_demux_001_src3_endofpacket),   //           .endofpacket
		.src4_ready         (cmd_xbar_demux_001_src4_ready),         //       src4.ready
		.src4_valid         (cmd_xbar_demux_001_src4_valid),         //           .valid
		.src4_data          (cmd_xbar_demux_001_src4_data),          //           .data
		.src4_channel       (cmd_xbar_demux_001_src4_channel),       //           .channel
		.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), //           .startofpacket
		.src4_endofpacket   (cmd_xbar_demux_001_src4_endofpacket),   //           .endofpacket
		.src5_ready         (cmd_xbar_demux_001_src5_ready),         //       src5.ready
		.src5_valid         (cmd_xbar_demux_001_src5_valid),         //           .valid
		.src5_data          (cmd_xbar_demux_001_src5_data),          //           .data
		.src5_channel       (cmd_xbar_demux_001_src5_channel),       //           .channel
		.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), //           .startofpacket
		.src5_endofpacket   (cmd_xbar_demux_001_src5_endofpacket)    //           .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (pll_cpu),                               //       clk.clk
		.reset               (rst_controller_reset_out_reset),        // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),                //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),                //          .valid
		.src_data            (cmd_xbar_mux_src_data),                 //          .data
		.src_channel         (cmd_xbar_mux_src_channel),              //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),        //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),          //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src0_ready),             //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src0_valid),             //          .valid
		.sink0_channel       (cmd_xbar_demux_src0_channel),           //          .channel
		.sink0_data          (cmd_xbar_demux_src0_data),              //          .data
		.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src0_endofpacket),       //          .endofpacket
		.sink1_ready         (cmd_xbar_demux_001_src0_ready),         //     sink1.ready
		.sink1_valid         (cmd_xbar_demux_001_src0_valid),         //          .valid
		.sink1_channel       (cmd_xbar_demux_001_src0_channel),       //          .channel
		.sink1_data          (cmd_xbar_demux_001_src0_data),          //          .data
		.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_cmd_xbar_mux cmd_xbar_mux_001 (
		.clk                 (pll_cpu),                               //       clk.clk
		.reset               (rst_controller_reset_out_reset),        // clk_reset.reset
		.src_ready           (cmd_xbar_mux_001_src_ready),            //       src.ready
		.src_valid           (cmd_xbar_mux_001_src_valid),            //          .valid
		.src_data            (cmd_xbar_mux_001_src_data),             //          .data
		.src_channel         (cmd_xbar_mux_001_src_channel),          //          .channel
		.src_startofpacket   (cmd_xbar_mux_001_src_startofpacket),    //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_001_src_endofpacket),      //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src1_ready),             //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src1_valid),             //          .valid
		.sink0_channel       (cmd_xbar_demux_src1_channel),           //          .channel
		.sink0_data          (cmd_xbar_demux_src1_data),              //          .data
		.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src1_endofpacket),       //          .endofpacket
		.sink1_ready         (cmd_xbar_demux_001_src1_ready),         //     sink1.ready
		.sink1_valid         (cmd_xbar_demux_001_src1_valid),         //          .valid
		.sink1_channel       (cmd_xbar_demux_001_src1_channel),       //          .channel
		.sink1_data          (cmd_xbar_demux_001_src1_data),          //          .data
		.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), //          .startofpacket
		.sink1_endofpacket   (cmd_xbar_demux_001_src1_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux rsp_xbar_demux (
		.clk                (pll_cpu),                           //       clk.clk
		.reset              (rst_controller_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_src_ready),               //      sink.ready
		.sink_channel       (id_router_src_channel),             //          .channel
		.sink_data          (id_router_src_data),                //          .data
		.sink_startofpacket (id_router_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket),   //          .endofpacket
		.src1_ready         (rsp_xbar_demux_src1_ready),         //      src1.ready
		.src1_valid         (rsp_xbar_demux_src1_valid),         //          .valid
		.src1_data          (rsp_xbar_demux_src1_data),          //          .data
		.src1_channel       (rsp_xbar_demux_src1_channel),       //          .channel
		.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_src1_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux rsp_xbar_demux_001 (
		.clk                (pll_cpu),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_001_src_ready),               //      sink.ready
		.sink_channel       (id_router_001_src_channel),             //          .channel
		.sink_data          (id_router_001_src_data),                //          .data
		.sink_startofpacket (id_router_001_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_001_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_001_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_001_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_001_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_001_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_001_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_001_src0_endofpacket),   //          .endofpacket
		.src1_ready         (rsp_xbar_demux_001_src1_ready),         //      src1.ready
		.src1_valid         (rsp_xbar_demux_001_src1_valid),         //          .valid
		.src1_data          (rsp_xbar_demux_001_src1_data),          //          .data
		.src1_channel       (rsp_xbar_demux_001_src1_channel),       //          .channel
		.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_001_src1_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_002 rsp_xbar_demux_002 (
		.clk                (pll_cpu),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_002_src_ready),               //      sink.ready
		.sink_channel       (id_router_002_src_channel),             //          .channel
		.sink_data          (id_router_002_src_data),                //          .data
		.sink_startofpacket (id_router_002_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_002_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_002_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_002_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_002_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_002_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_002_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_002_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_002 rsp_xbar_demux_003 (
		.clk                (clk),                                   //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_003_src_ready),               //      sink.ready
		.sink_channel       (id_router_003_src_channel),             //          .channel
		.sink_data          (id_router_003_src_data),                //          .data
		.sink_startofpacket (id_router_003_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_003_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_003_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_003_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_003_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_003_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_003_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_003_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_002 rsp_xbar_demux_004 (
		.clk                (pll_cpu),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_004_src_ready),               //      sink.ready
		.sink_channel       (id_router_004_src_channel),             //          .channel
		.sink_data          (id_router_004_src_data),                //          .data
		.sink_startofpacket (id_router_004_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_004_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_004_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_004_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_004_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_004_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_004_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_004_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_002 rsp_xbar_demux_005 (
		.clk                (pll_cpu),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_005_src_ready),               //      sink.ready
		.sink_channel       (id_router_005_src_channel),             //          .channel
		.sink_data          (id_router_005_src_data),                //          .data
		.sink_startofpacket (id_router_005_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_005_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_005_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_005_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_005_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_005_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_005_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_005_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_mux rsp_xbar_mux (
		.clk                 (pll_cpu),                               //       clk.clk
		.reset               (rst_controller_reset_out_reset),        // clk_reset.reset
		.src_ready           (rsp_xbar_mux_src_ready),                //       src.ready
		.src_valid           (rsp_xbar_mux_src_valid),                //          .valid
		.src_data            (rsp_xbar_mux_src_data),                 //          .data
		.src_channel         (rsp_xbar_mux_src_channel),              //          .channel
		.src_startofpacket   (rsp_xbar_mux_src_startofpacket),        //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_src_endofpacket),          //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_src0_ready),             //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_src0_valid),             //          .valid
		.sink0_channel       (rsp_xbar_demux_src0_channel),           //          .channel
		.sink0_data          (rsp_xbar_demux_src0_data),              //          .data
		.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_src0_endofpacket),       //          .endofpacket
		.sink1_ready         (rsp_xbar_demux_001_src0_ready),         //     sink1.ready
		.sink1_valid         (rsp_xbar_demux_001_src0_valid),         //          .valid
		.sink1_channel       (rsp_xbar_demux_001_src0_channel),       //          .channel
		.sink1_data          (rsp_xbar_demux_001_src0_data),          //          .data
		.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (rsp_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_mux_001 rsp_xbar_mux_001 (
		.clk                 (pll_cpu),                               //       clk.clk
		.reset               (rst_controller_reset_out_reset),        // clk_reset.reset
		.src_ready           (rsp_xbar_mux_001_src_ready),            //       src.ready
		.src_valid           (rsp_xbar_mux_001_src_valid),            //          .valid
		.src_data            (rsp_xbar_mux_001_src_data),             //          .data
		.src_channel         (rsp_xbar_mux_001_src_channel),          //          .channel
		.src_startofpacket   (rsp_xbar_mux_001_src_startofpacket),    //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_001_src_endofpacket),      //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_src1_ready),             //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_src1_valid),             //          .valid
		.sink0_channel       (rsp_xbar_demux_src1_channel),           //          .channel
		.sink0_data          (rsp_xbar_demux_src1_data),              //          .data
		.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_src1_endofpacket),       //          .endofpacket
		.sink1_ready         (rsp_xbar_demux_001_src1_ready),         //     sink1.ready
		.sink1_valid         (rsp_xbar_demux_001_src1_valid),         //          .valid
		.sink1_channel       (rsp_xbar_demux_001_src1_channel),       //          .channel
		.sink1_data          (rsp_xbar_demux_001_src1_data),          //          .data
		.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), //          .startofpacket
		.sink1_endofpacket   (rsp_xbar_demux_001_src1_endofpacket),   //          .endofpacket
		.sink2_ready         (rsp_xbar_demux_002_src0_ready),         //     sink2.ready
		.sink2_valid         (rsp_xbar_demux_002_src0_valid),         //          .valid
		.sink2_channel       (rsp_xbar_demux_002_src0_channel),       //          .channel
		.sink2_data          (rsp_xbar_demux_002_src0_data),          //          .data
		.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), //          .startofpacket
		.sink2_endofpacket   (rsp_xbar_demux_002_src0_endofpacket),   //          .endofpacket
		.sink3_ready         (crosser_001_out_ready),                 //     sink3.ready
		.sink3_valid         (crosser_001_out_valid),                 //          .valid
		.sink3_channel       (crosser_001_out_channel),               //          .channel
		.sink3_data          (crosser_001_out_data),                  //          .data
		.sink3_startofpacket (crosser_001_out_startofpacket),         //          .startofpacket
		.sink3_endofpacket   (crosser_001_out_endofpacket),           //          .endofpacket
		.sink4_ready         (rsp_xbar_demux_004_src0_ready),         //     sink4.ready
		.sink4_valid         (rsp_xbar_demux_004_src0_valid),         //          .valid
		.sink4_channel       (rsp_xbar_demux_004_src0_channel),       //          .channel
		.sink4_data          (rsp_xbar_demux_004_src0_data),          //          .data
		.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), //          .startofpacket
		.sink4_endofpacket   (rsp_xbar_demux_004_src0_endofpacket),   //          .endofpacket
		.sink5_ready         (rsp_xbar_demux_005_src0_ready),         //     sink5.ready
		.sink5_valid         (rsp_xbar_demux_005_src0_valid),         //          .valid
		.sink5_channel       (rsp_xbar_demux_005_src0_channel),       //          .channel
		.sink5_data          (rsp_xbar_demux_005_src0_data),          //          .data
		.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), //          .startofpacket
		.sink5_endofpacket   (rsp_xbar_demux_005_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_cmd_xbar_demux_002 cmd_xbar_demux_002 (
		.clk                 (pll_io),                                 //        clk.clk
		.reset               (rst_controller_002_reset_out_reset),     //  clk_reset.reset
		.sink_ready          (limiter_002_cmd_src_ready),              //       sink.ready
		.sink_channel        (limiter_002_cmd_src_channel),            //           .channel
		.sink_data           (limiter_002_cmd_src_data),               //           .data
		.sink_startofpacket  (limiter_002_cmd_src_startofpacket),      //           .startofpacket
		.sink_endofpacket    (limiter_002_cmd_src_endofpacket),        //           .endofpacket
		.sink_valid          (limiter_002_cmd_valid_data),             // sink_valid.data
		.src0_ready          (cmd_xbar_demux_002_src0_ready),          //       src0.ready
		.src0_valid          (cmd_xbar_demux_002_src0_valid),          //           .valid
		.src0_data           (cmd_xbar_demux_002_src0_data),           //           .data
		.src0_channel        (cmd_xbar_demux_002_src0_channel),        //           .channel
		.src0_startofpacket  (cmd_xbar_demux_002_src0_startofpacket),  //           .startofpacket
		.src0_endofpacket    (cmd_xbar_demux_002_src0_endofpacket),    //           .endofpacket
		.src1_ready          (cmd_xbar_demux_002_src1_ready),          //       src1.ready
		.src1_valid          (cmd_xbar_demux_002_src1_valid),          //           .valid
		.src1_data           (cmd_xbar_demux_002_src1_data),           //           .data
		.src1_channel        (cmd_xbar_demux_002_src1_channel),        //           .channel
		.src1_startofpacket  (cmd_xbar_demux_002_src1_startofpacket),  //           .startofpacket
		.src1_endofpacket    (cmd_xbar_demux_002_src1_endofpacket),    //           .endofpacket
		.src2_ready          (cmd_xbar_demux_002_src2_ready),          //       src2.ready
		.src2_valid          (cmd_xbar_demux_002_src2_valid),          //           .valid
		.src2_data           (cmd_xbar_demux_002_src2_data),           //           .data
		.src2_channel        (cmd_xbar_demux_002_src2_channel),        //           .channel
		.src2_startofpacket  (cmd_xbar_demux_002_src2_startofpacket),  //           .startofpacket
		.src2_endofpacket    (cmd_xbar_demux_002_src2_endofpacket),    //           .endofpacket
		.src3_ready          (cmd_xbar_demux_002_src3_ready),          //       src3.ready
		.src3_valid          (cmd_xbar_demux_002_src3_valid),          //           .valid
		.src3_data           (cmd_xbar_demux_002_src3_data),           //           .data
		.src3_channel        (cmd_xbar_demux_002_src3_channel),        //           .channel
		.src3_startofpacket  (cmd_xbar_demux_002_src3_startofpacket),  //           .startofpacket
		.src3_endofpacket    (cmd_xbar_demux_002_src3_endofpacket),    //           .endofpacket
		.src4_ready          (cmd_xbar_demux_002_src4_ready),          //       src4.ready
		.src4_valid          (cmd_xbar_demux_002_src4_valid),          //           .valid
		.src4_data           (cmd_xbar_demux_002_src4_data),           //           .data
		.src4_channel        (cmd_xbar_demux_002_src4_channel),        //           .channel
		.src4_startofpacket  (cmd_xbar_demux_002_src4_startofpacket),  //           .startofpacket
		.src4_endofpacket    (cmd_xbar_demux_002_src4_endofpacket),    //           .endofpacket
		.src5_ready          (cmd_xbar_demux_002_src5_ready),          //       src5.ready
		.src5_valid          (cmd_xbar_demux_002_src5_valid),          //           .valid
		.src5_data           (cmd_xbar_demux_002_src5_data),           //           .data
		.src5_channel        (cmd_xbar_demux_002_src5_channel),        //           .channel
		.src5_startofpacket  (cmd_xbar_demux_002_src5_startofpacket),  //           .startofpacket
		.src5_endofpacket    (cmd_xbar_demux_002_src5_endofpacket),    //           .endofpacket
		.src6_ready          (cmd_xbar_demux_002_src6_ready),          //       src6.ready
		.src6_valid          (cmd_xbar_demux_002_src6_valid),          //           .valid
		.src6_data           (cmd_xbar_demux_002_src6_data),           //           .data
		.src6_channel        (cmd_xbar_demux_002_src6_channel),        //           .channel
		.src6_startofpacket  (cmd_xbar_demux_002_src6_startofpacket),  //           .startofpacket
		.src6_endofpacket    (cmd_xbar_demux_002_src6_endofpacket),    //           .endofpacket
		.src7_ready          (cmd_xbar_demux_002_src7_ready),          //       src7.ready
		.src7_valid          (cmd_xbar_demux_002_src7_valid),          //           .valid
		.src7_data           (cmd_xbar_demux_002_src7_data),           //           .data
		.src7_channel        (cmd_xbar_demux_002_src7_channel),        //           .channel
		.src7_startofpacket  (cmd_xbar_demux_002_src7_startofpacket),  //           .startofpacket
		.src7_endofpacket    (cmd_xbar_demux_002_src7_endofpacket),    //           .endofpacket
		.src8_ready          (cmd_xbar_demux_002_src8_ready),          //       src8.ready
		.src8_valid          (cmd_xbar_demux_002_src8_valid),          //           .valid
		.src8_data           (cmd_xbar_demux_002_src8_data),           //           .data
		.src8_channel        (cmd_xbar_demux_002_src8_channel),        //           .channel
		.src8_startofpacket  (cmd_xbar_demux_002_src8_startofpacket),  //           .startofpacket
		.src8_endofpacket    (cmd_xbar_demux_002_src8_endofpacket),    //           .endofpacket
		.src9_ready          (cmd_xbar_demux_002_src9_ready),          //       src9.ready
		.src9_valid          (cmd_xbar_demux_002_src9_valid),          //           .valid
		.src9_data           (cmd_xbar_demux_002_src9_data),           //           .data
		.src9_channel        (cmd_xbar_demux_002_src9_channel),        //           .channel
		.src9_startofpacket  (cmd_xbar_demux_002_src9_startofpacket),  //           .startofpacket
		.src9_endofpacket    (cmd_xbar_demux_002_src9_endofpacket),    //           .endofpacket
		.src10_ready         (cmd_xbar_demux_002_src10_ready),         //      src10.ready
		.src10_valid         (cmd_xbar_demux_002_src10_valid),         //           .valid
		.src10_data          (cmd_xbar_demux_002_src10_data),          //           .data
		.src10_channel       (cmd_xbar_demux_002_src10_channel),       //           .channel
		.src10_startofpacket (cmd_xbar_demux_002_src10_startofpacket), //           .startofpacket
		.src10_endofpacket   (cmd_xbar_demux_002_src10_endofpacket),   //           .endofpacket
		.src11_ready         (cmd_xbar_demux_002_src11_ready),         //      src11.ready
		.src11_valid         (cmd_xbar_demux_002_src11_valid),         //           .valid
		.src11_data          (cmd_xbar_demux_002_src11_data),          //           .data
		.src11_channel       (cmd_xbar_demux_002_src11_channel),       //           .channel
		.src11_startofpacket (cmd_xbar_demux_002_src11_startofpacket), //           .startofpacket
		.src11_endofpacket   (cmd_xbar_demux_002_src11_endofpacket),   //           .endofpacket
		.src12_ready         (cmd_xbar_demux_002_src12_ready),         //      src12.ready
		.src12_valid         (cmd_xbar_demux_002_src12_valid),         //           .valid
		.src12_data          (cmd_xbar_demux_002_src12_data),          //           .data
		.src12_channel       (cmd_xbar_demux_002_src12_channel),       //           .channel
		.src12_startofpacket (cmd_xbar_demux_002_src12_startofpacket), //           .startofpacket
		.src12_endofpacket   (cmd_xbar_demux_002_src12_endofpacket),   //           .endofpacket
		.src13_ready         (cmd_xbar_demux_002_src13_ready),         //      src13.ready
		.src13_valid         (cmd_xbar_demux_002_src13_valid),         //           .valid
		.src13_data          (cmd_xbar_demux_002_src13_data),          //           .data
		.src13_channel       (cmd_xbar_demux_002_src13_channel),       //           .channel
		.src13_startofpacket (cmd_xbar_demux_002_src13_startofpacket), //           .startofpacket
		.src13_endofpacket   (cmd_xbar_demux_002_src13_endofpacket),   //           .endofpacket
		.src14_ready         (cmd_xbar_demux_002_src14_ready),         //      src14.ready
		.src14_valid         (cmd_xbar_demux_002_src14_valid),         //           .valid
		.src14_data          (cmd_xbar_demux_002_src14_data),          //           .data
		.src14_channel       (cmd_xbar_demux_002_src14_channel),       //           .channel
		.src14_startofpacket (cmd_xbar_demux_002_src14_startofpacket), //           .startofpacket
		.src14_endofpacket   (cmd_xbar_demux_002_src14_endofpacket),   //           .endofpacket
		.src15_ready         (cmd_xbar_demux_002_src15_ready),         //      src15.ready
		.src15_valid         (cmd_xbar_demux_002_src15_valid),         //           .valid
		.src15_data          (cmd_xbar_demux_002_src15_data),          //           .data
		.src15_channel       (cmd_xbar_demux_002_src15_channel),       //           .channel
		.src15_startofpacket (cmd_xbar_demux_002_src15_startofpacket), //           .startofpacket
		.src15_endofpacket   (cmd_xbar_demux_002_src15_endofpacket),   //           .endofpacket
		.src16_ready         (cmd_xbar_demux_002_src16_ready),         //      src16.ready
		.src16_valid         (cmd_xbar_demux_002_src16_valid),         //           .valid
		.src16_data          (cmd_xbar_demux_002_src16_data),          //           .data
		.src16_channel       (cmd_xbar_demux_002_src16_channel),       //           .channel
		.src16_startofpacket (cmd_xbar_demux_002_src16_startofpacket), //           .startofpacket
		.src16_endofpacket   (cmd_xbar_demux_002_src16_endofpacket),   //           .endofpacket
		.src17_ready         (cmd_xbar_demux_002_src17_ready),         //      src17.ready
		.src17_valid         (cmd_xbar_demux_002_src17_valid),         //           .valid
		.src17_data          (cmd_xbar_demux_002_src17_data),          //           .data
		.src17_channel       (cmd_xbar_demux_002_src17_channel),       //           .channel
		.src17_startofpacket (cmd_xbar_demux_002_src17_startofpacket), //           .startofpacket
		.src17_endofpacket   (cmd_xbar_demux_002_src17_endofpacket),   //           .endofpacket
		.src18_ready         (cmd_xbar_demux_002_src18_ready),         //      src18.ready
		.src18_valid         (cmd_xbar_demux_002_src18_valid),         //           .valid
		.src18_data          (cmd_xbar_demux_002_src18_data),          //           .data
		.src18_channel       (cmd_xbar_demux_002_src18_channel),       //           .channel
		.src18_startofpacket (cmd_xbar_demux_002_src18_startofpacket), //           .startofpacket
		.src18_endofpacket   (cmd_xbar_demux_002_src18_endofpacket),   //           .endofpacket
		.src19_ready         (cmd_xbar_demux_002_src19_ready),         //      src19.ready
		.src19_valid         (cmd_xbar_demux_002_src19_valid),         //           .valid
		.src19_data          (cmd_xbar_demux_002_src19_data),          //           .data
		.src19_channel       (cmd_xbar_demux_002_src19_channel),       //           .channel
		.src19_startofpacket (cmd_xbar_demux_002_src19_startofpacket), //           .startofpacket
		.src19_endofpacket   (cmd_xbar_demux_002_src19_endofpacket),   //           .endofpacket
		.src20_ready         (cmd_xbar_demux_002_src20_ready),         //      src20.ready
		.src20_valid         (cmd_xbar_demux_002_src20_valid),         //           .valid
		.src20_data          (cmd_xbar_demux_002_src20_data),          //           .data
		.src20_channel       (cmd_xbar_demux_002_src20_channel),       //           .channel
		.src20_startofpacket (cmd_xbar_demux_002_src20_startofpacket), //           .startofpacket
		.src20_endofpacket   (cmd_xbar_demux_002_src20_endofpacket),   //           .endofpacket
		.src21_ready         (cmd_xbar_demux_002_src21_ready),         //      src21.ready
		.src21_valid         (cmd_xbar_demux_002_src21_valid),         //           .valid
		.src21_data          (cmd_xbar_demux_002_src21_data),          //           .data
		.src21_channel       (cmd_xbar_demux_002_src21_channel),       //           .channel
		.src21_startofpacket (cmd_xbar_demux_002_src21_startofpacket), //           .startofpacket
		.src21_endofpacket   (cmd_xbar_demux_002_src21_endofpacket),   //           .endofpacket
		.src22_ready         (cmd_xbar_demux_002_src22_ready),         //      src22.ready
		.src22_valid         (cmd_xbar_demux_002_src22_valid),         //           .valid
		.src22_data          (cmd_xbar_demux_002_src22_data),          //           .data
		.src22_channel       (cmd_xbar_demux_002_src22_channel),       //           .channel
		.src22_startofpacket (cmd_xbar_demux_002_src22_startofpacket), //           .startofpacket
		.src22_endofpacket   (cmd_xbar_demux_002_src22_endofpacket)    //           .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_006 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_006_src_ready),               //      sink.ready
		.sink_channel       (id_router_006_src_channel),             //          .channel
		.sink_data          (id_router_006_src_data),                //          .data
		.sink_startofpacket (id_router_006_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_006_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_006_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_006_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_006_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_006_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_006_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_006_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_007 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_007_src_ready),               //      sink.ready
		.sink_channel       (id_router_007_src_channel),             //          .channel
		.sink_data          (id_router_007_src_data),                //          .data
		.sink_startofpacket (id_router_007_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_007_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_007_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_007_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_007_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_007_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_007_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_007_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_008 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_008_src_ready),               //      sink.ready
		.sink_channel       (id_router_008_src_channel),             //          .channel
		.sink_data          (id_router_008_src_data),                //          .data
		.sink_startofpacket (id_router_008_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_008_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_008_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_008_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_008_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_008_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_008_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_008_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_009 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_009_src_ready),               //      sink.ready
		.sink_channel       (id_router_009_src_channel),             //          .channel
		.sink_data          (id_router_009_src_data),                //          .data
		.sink_startofpacket (id_router_009_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_009_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_009_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_009_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_009_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_009_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_009_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_009_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_010 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_010_src_ready),               //      sink.ready
		.sink_channel       (id_router_010_src_channel),             //          .channel
		.sink_data          (id_router_010_src_data),                //          .data
		.sink_startofpacket (id_router_010_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_010_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_010_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_010_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_010_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_010_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_010_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_010_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_011 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_011_src_ready),               //      sink.ready
		.sink_channel       (id_router_011_src_channel),             //          .channel
		.sink_data          (id_router_011_src_data),                //          .data
		.sink_startofpacket (id_router_011_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_011_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_011_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_011_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_011_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_011_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_011_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_011_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_011_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_012 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_012_src_ready),               //      sink.ready
		.sink_channel       (id_router_012_src_channel),             //          .channel
		.sink_data          (id_router_012_src_data),                //          .data
		.sink_startofpacket (id_router_012_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_012_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_012_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_012_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_012_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_012_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_012_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_012_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_012_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_013 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_013_src_ready),               //      sink.ready
		.sink_channel       (id_router_013_src_channel),             //          .channel
		.sink_data          (id_router_013_src_data),                //          .data
		.sink_startofpacket (id_router_013_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_013_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_013_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_013_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_013_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_013_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_013_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_013_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_013_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_014 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_014_src_ready),               //      sink.ready
		.sink_channel       (id_router_014_src_channel),             //          .channel
		.sink_data          (id_router_014_src_data),                //          .data
		.sink_startofpacket (id_router_014_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_014_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_014_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_014_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_014_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_014_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_014_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_014_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_014_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_015 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_015_src_ready),               //      sink.ready
		.sink_channel       (id_router_015_src_channel),             //          .channel
		.sink_data          (id_router_015_src_data),                //          .data
		.sink_startofpacket (id_router_015_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_015_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_015_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_015_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_015_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_015_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_015_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_015_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_015_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_016 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_016_src_ready),               //      sink.ready
		.sink_channel       (id_router_016_src_channel),             //          .channel
		.sink_data          (id_router_016_src_data),                //          .data
		.sink_startofpacket (id_router_016_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_016_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_016_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_016_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_016_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_016_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_016_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_016_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_016_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_017 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_017_src_ready),               //      sink.ready
		.sink_channel       (id_router_017_src_channel),             //          .channel
		.sink_data          (id_router_017_src_data),                //          .data
		.sink_startofpacket (id_router_017_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_017_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_017_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_017_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_017_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_017_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_017_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_017_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_017_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_018 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_018_src_ready),               //      sink.ready
		.sink_channel       (id_router_018_src_channel),             //          .channel
		.sink_data          (id_router_018_src_data),                //          .data
		.sink_startofpacket (id_router_018_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_018_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_018_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_018_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_018_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_018_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_018_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_018_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_018_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_019 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_019_src_ready),               //      sink.ready
		.sink_channel       (id_router_019_src_channel),             //          .channel
		.sink_data          (id_router_019_src_data),                //          .data
		.sink_startofpacket (id_router_019_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_019_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_019_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_019_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_019_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_019_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_019_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_019_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_019_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_020 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_020_src_ready),               //      sink.ready
		.sink_channel       (id_router_020_src_channel),             //          .channel
		.sink_data          (id_router_020_src_data),                //          .data
		.sink_startofpacket (id_router_020_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_020_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_020_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_020_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_020_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_020_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_020_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_020_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_020_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_021 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_021_src_ready),               //      sink.ready
		.sink_channel       (id_router_021_src_channel),             //          .channel
		.sink_data          (id_router_021_src_data),                //          .data
		.sink_startofpacket (id_router_021_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_021_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_021_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_021_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_021_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_021_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_021_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_021_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_021_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_022 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_022_src_ready),               //      sink.ready
		.sink_channel       (id_router_022_src_channel),             //          .channel
		.sink_data          (id_router_022_src_data),                //          .data
		.sink_startofpacket (id_router_022_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_022_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_022_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_022_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_022_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_022_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_022_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_022_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_022_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_023 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_023_src_ready),               //      sink.ready
		.sink_channel       (id_router_023_src_channel),             //          .channel
		.sink_data          (id_router_023_src_data),                //          .data
		.sink_startofpacket (id_router_023_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_023_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_023_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_023_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_023_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_023_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_023_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_023_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_023_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_024 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_024_src_ready),               //      sink.ready
		.sink_channel       (id_router_024_src_channel),             //          .channel
		.sink_data          (id_router_024_src_data),                //          .data
		.sink_startofpacket (id_router_024_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_024_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_024_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_024_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_024_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_024_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_024_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_024_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_024_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_025 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_025_src_ready),               //      sink.ready
		.sink_channel       (id_router_025_src_channel),             //          .channel
		.sink_data          (id_router_025_src_data),                //          .data
		.sink_startofpacket (id_router_025_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_025_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_025_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_025_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_025_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_025_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_025_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_025_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_025_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_026 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_026_src_ready),               //      sink.ready
		.sink_channel       (id_router_026_src_channel),             //          .channel
		.sink_data          (id_router_026_src_data),                //          .data
		.sink_startofpacket (id_router_026_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_026_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_026_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_026_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_026_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_026_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_026_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_026_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_026_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_027 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_027_src_ready),               //      sink.ready
		.sink_channel       (id_router_027_src_channel),             //          .channel
		.sink_data          (id_router_027_src_data),                //          .data
		.sink_startofpacket (id_router_027_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_027_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_027_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_027_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_027_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_027_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_027_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_027_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_027_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_demux_006 rsp_xbar_demux_028 (
		.clk                (pll_io),                                //       clk.clk
		.reset              (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_028_src_ready),               //      sink.ready
		.sink_channel       (id_router_028_src_channel),             //          .channel
		.sink_data          (id_router_028_src_data),                //          .data
		.sink_startofpacket (id_router_028_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_028_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_028_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_028_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_028_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_028_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_028_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_028_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_028_src0_endofpacket)    //          .endofpacket
	);

	TR4_HDMI_TX_RX_SOPC_rsp_xbar_mux_002 rsp_xbar_mux_002 (
		.clk                  (pll_io),                                //       clk.clk
		.reset                (rst_controller_002_reset_out_reset),    // clk_reset.reset
		.src_ready            (rsp_xbar_mux_002_src_ready),            //       src.ready
		.src_valid            (rsp_xbar_mux_002_src_valid),            //          .valid
		.src_data             (rsp_xbar_mux_002_src_data),             //          .data
		.src_channel          (rsp_xbar_mux_002_src_channel),          //          .channel
		.src_startofpacket    (rsp_xbar_mux_002_src_startofpacket),    //          .startofpacket
		.src_endofpacket      (rsp_xbar_mux_002_src_endofpacket),      //          .endofpacket
		.sink0_ready          (rsp_xbar_demux_006_src0_ready),         //     sink0.ready
		.sink0_valid          (rsp_xbar_demux_006_src0_valid),         //          .valid
		.sink0_channel        (rsp_xbar_demux_006_src0_channel),       //          .channel
		.sink0_data           (rsp_xbar_demux_006_src0_data),          //          .data
		.sink0_startofpacket  (rsp_xbar_demux_006_src0_startofpacket), //          .startofpacket
		.sink0_endofpacket    (rsp_xbar_demux_006_src0_endofpacket),   //          .endofpacket
		.sink1_ready          (rsp_xbar_demux_007_src0_ready),         //     sink1.ready
		.sink1_valid          (rsp_xbar_demux_007_src0_valid),         //          .valid
		.sink1_channel        (rsp_xbar_demux_007_src0_channel),       //          .channel
		.sink1_data           (rsp_xbar_demux_007_src0_data),          //          .data
		.sink1_startofpacket  (rsp_xbar_demux_007_src0_startofpacket), //          .startofpacket
		.sink1_endofpacket    (rsp_xbar_demux_007_src0_endofpacket),   //          .endofpacket
		.sink2_ready          (rsp_xbar_demux_008_src0_ready),         //     sink2.ready
		.sink2_valid          (rsp_xbar_demux_008_src0_valid),         //          .valid
		.sink2_channel        (rsp_xbar_demux_008_src0_channel),       //          .channel
		.sink2_data           (rsp_xbar_demux_008_src0_data),          //          .data
		.sink2_startofpacket  (rsp_xbar_demux_008_src0_startofpacket), //          .startofpacket
		.sink2_endofpacket    (rsp_xbar_demux_008_src0_endofpacket),   //          .endofpacket
		.sink3_ready          (rsp_xbar_demux_009_src0_ready),         //     sink3.ready
		.sink3_valid          (rsp_xbar_demux_009_src0_valid),         //          .valid
		.sink3_channel        (rsp_xbar_demux_009_src0_channel),       //          .channel
		.sink3_data           (rsp_xbar_demux_009_src0_data),          //          .data
		.sink3_startofpacket  (rsp_xbar_demux_009_src0_startofpacket), //          .startofpacket
		.sink3_endofpacket    (rsp_xbar_demux_009_src0_endofpacket),   //          .endofpacket
		.sink4_ready          (rsp_xbar_demux_010_src0_ready),         //     sink4.ready
		.sink4_valid          (rsp_xbar_demux_010_src0_valid),         //          .valid
		.sink4_channel        (rsp_xbar_demux_010_src0_channel),       //          .channel
		.sink4_data           (rsp_xbar_demux_010_src0_data),          //          .data
		.sink4_startofpacket  (rsp_xbar_demux_010_src0_startofpacket), //          .startofpacket
		.sink4_endofpacket    (rsp_xbar_demux_010_src0_endofpacket),   //          .endofpacket
		.sink5_ready          (rsp_xbar_demux_011_src0_ready),         //     sink5.ready
		.sink5_valid          (rsp_xbar_demux_011_src0_valid),         //          .valid
		.sink5_channel        (rsp_xbar_demux_011_src0_channel),       //          .channel
		.sink5_data           (rsp_xbar_demux_011_src0_data),          //          .data
		.sink5_startofpacket  (rsp_xbar_demux_011_src0_startofpacket), //          .startofpacket
		.sink5_endofpacket    (rsp_xbar_demux_011_src0_endofpacket),   //          .endofpacket
		.sink6_ready          (rsp_xbar_demux_012_src0_ready),         //     sink6.ready
		.sink6_valid          (rsp_xbar_demux_012_src0_valid),         //          .valid
		.sink6_channel        (rsp_xbar_demux_012_src0_channel),       //          .channel
		.sink6_data           (rsp_xbar_demux_012_src0_data),          //          .data
		.sink6_startofpacket  (rsp_xbar_demux_012_src0_startofpacket), //          .startofpacket
		.sink6_endofpacket    (rsp_xbar_demux_012_src0_endofpacket),   //          .endofpacket
		.sink7_ready          (rsp_xbar_demux_013_src0_ready),         //     sink7.ready
		.sink7_valid          (rsp_xbar_demux_013_src0_valid),         //          .valid
		.sink7_channel        (rsp_xbar_demux_013_src0_channel),       //          .channel
		.sink7_data           (rsp_xbar_demux_013_src0_data),          //          .data
		.sink7_startofpacket  (rsp_xbar_demux_013_src0_startofpacket), //          .startofpacket
		.sink7_endofpacket    (rsp_xbar_demux_013_src0_endofpacket),   //          .endofpacket
		.sink8_ready          (rsp_xbar_demux_014_src0_ready),         //     sink8.ready
		.sink8_valid          (rsp_xbar_demux_014_src0_valid),         //          .valid
		.sink8_channel        (rsp_xbar_demux_014_src0_channel),       //          .channel
		.sink8_data           (rsp_xbar_demux_014_src0_data),          //          .data
		.sink8_startofpacket  (rsp_xbar_demux_014_src0_startofpacket), //          .startofpacket
		.sink8_endofpacket    (rsp_xbar_demux_014_src0_endofpacket),   //          .endofpacket
		.sink9_ready          (rsp_xbar_demux_015_src0_ready),         //     sink9.ready
		.sink9_valid          (rsp_xbar_demux_015_src0_valid),         //          .valid
		.sink9_channel        (rsp_xbar_demux_015_src0_channel),       //          .channel
		.sink9_data           (rsp_xbar_demux_015_src0_data),          //          .data
		.sink9_startofpacket  (rsp_xbar_demux_015_src0_startofpacket), //          .startofpacket
		.sink9_endofpacket    (rsp_xbar_demux_015_src0_endofpacket),   //          .endofpacket
		.sink10_ready         (rsp_xbar_demux_016_src0_ready),         //    sink10.ready
		.sink10_valid         (rsp_xbar_demux_016_src0_valid),         //          .valid
		.sink10_channel       (rsp_xbar_demux_016_src0_channel),       //          .channel
		.sink10_data          (rsp_xbar_demux_016_src0_data),          //          .data
		.sink10_startofpacket (rsp_xbar_demux_016_src0_startofpacket), //          .startofpacket
		.sink10_endofpacket   (rsp_xbar_demux_016_src0_endofpacket),   //          .endofpacket
		.sink11_ready         (rsp_xbar_demux_017_src0_ready),         //    sink11.ready
		.sink11_valid         (rsp_xbar_demux_017_src0_valid),         //          .valid
		.sink11_channel       (rsp_xbar_demux_017_src0_channel),       //          .channel
		.sink11_data          (rsp_xbar_demux_017_src0_data),          //          .data
		.sink11_startofpacket (rsp_xbar_demux_017_src0_startofpacket), //          .startofpacket
		.sink11_endofpacket   (rsp_xbar_demux_017_src0_endofpacket),   //          .endofpacket
		.sink12_ready         (rsp_xbar_demux_018_src0_ready),         //    sink12.ready
		.sink12_valid         (rsp_xbar_demux_018_src0_valid),         //          .valid
		.sink12_channel       (rsp_xbar_demux_018_src0_channel),       //          .channel
		.sink12_data          (rsp_xbar_demux_018_src0_data),          //          .data
		.sink12_startofpacket (rsp_xbar_demux_018_src0_startofpacket), //          .startofpacket
		.sink12_endofpacket   (rsp_xbar_demux_018_src0_endofpacket),   //          .endofpacket
		.sink13_ready         (rsp_xbar_demux_019_src0_ready),         //    sink13.ready
		.sink13_valid         (rsp_xbar_demux_019_src0_valid),         //          .valid
		.sink13_channel       (rsp_xbar_demux_019_src0_channel),       //          .channel
		.sink13_data          (rsp_xbar_demux_019_src0_data),          //          .data
		.sink13_startofpacket (rsp_xbar_demux_019_src0_startofpacket), //          .startofpacket
		.sink13_endofpacket   (rsp_xbar_demux_019_src0_endofpacket),   //          .endofpacket
		.sink14_ready         (rsp_xbar_demux_020_src0_ready),         //    sink14.ready
		.sink14_valid         (rsp_xbar_demux_020_src0_valid),         //          .valid
		.sink14_channel       (rsp_xbar_demux_020_src0_channel),       //          .channel
		.sink14_data          (rsp_xbar_demux_020_src0_data),          //          .data
		.sink14_startofpacket (rsp_xbar_demux_020_src0_startofpacket), //          .startofpacket
		.sink14_endofpacket   (rsp_xbar_demux_020_src0_endofpacket),   //          .endofpacket
		.sink15_ready         (rsp_xbar_demux_021_src0_ready),         //    sink15.ready
		.sink15_valid         (rsp_xbar_demux_021_src0_valid),         //          .valid
		.sink15_channel       (rsp_xbar_demux_021_src0_channel),       //          .channel
		.sink15_data          (rsp_xbar_demux_021_src0_data),          //          .data
		.sink15_startofpacket (rsp_xbar_demux_021_src0_startofpacket), //          .startofpacket
		.sink15_endofpacket   (rsp_xbar_demux_021_src0_endofpacket),   //          .endofpacket
		.sink16_ready         (rsp_xbar_demux_022_src0_ready),         //    sink16.ready
		.sink16_valid         (rsp_xbar_demux_022_src0_valid),         //          .valid
		.sink16_channel       (rsp_xbar_demux_022_src0_channel),       //          .channel
		.sink16_data          (rsp_xbar_demux_022_src0_data),          //          .data
		.sink16_startofpacket (rsp_xbar_demux_022_src0_startofpacket), //          .startofpacket
		.sink16_endofpacket   (rsp_xbar_demux_022_src0_endofpacket),   //          .endofpacket
		.sink17_ready         (rsp_xbar_demux_023_src0_ready),         //    sink17.ready
		.sink17_valid         (rsp_xbar_demux_023_src0_valid),         //          .valid
		.sink17_channel       (rsp_xbar_demux_023_src0_channel),       //          .channel
		.sink17_data          (rsp_xbar_demux_023_src0_data),          //          .data
		.sink17_startofpacket (rsp_xbar_demux_023_src0_startofpacket), //          .startofpacket
		.sink17_endofpacket   (rsp_xbar_demux_023_src0_endofpacket),   //          .endofpacket
		.sink18_ready         (rsp_xbar_demux_024_src0_ready),         //    sink18.ready
		.sink18_valid         (rsp_xbar_demux_024_src0_valid),         //          .valid
		.sink18_channel       (rsp_xbar_demux_024_src0_channel),       //          .channel
		.sink18_data          (rsp_xbar_demux_024_src0_data),          //          .data
		.sink18_startofpacket (rsp_xbar_demux_024_src0_startofpacket), //          .startofpacket
		.sink18_endofpacket   (rsp_xbar_demux_024_src0_endofpacket),   //          .endofpacket
		.sink19_ready         (rsp_xbar_demux_025_src0_ready),         //    sink19.ready
		.sink19_valid         (rsp_xbar_demux_025_src0_valid),         //          .valid
		.sink19_channel       (rsp_xbar_demux_025_src0_channel),       //          .channel
		.sink19_data          (rsp_xbar_demux_025_src0_data),          //          .data
		.sink19_startofpacket (rsp_xbar_demux_025_src0_startofpacket), //          .startofpacket
		.sink19_endofpacket   (rsp_xbar_demux_025_src0_endofpacket),   //          .endofpacket
		.sink20_ready         (rsp_xbar_demux_026_src0_ready),         //    sink20.ready
		.sink20_valid         (rsp_xbar_demux_026_src0_valid),         //          .valid
		.sink20_channel       (rsp_xbar_demux_026_src0_channel),       //          .channel
		.sink20_data          (rsp_xbar_demux_026_src0_data),          //          .data
		.sink20_startofpacket (rsp_xbar_demux_026_src0_startofpacket), //          .startofpacket
		.sink20_endofpacket   (rsp_xbar_demux_026_src0_endofpacket),   //          .endofpacket
		.sink21_ready         (rsp_xbar_demux_027_src0_ready),         //    sink21.ready
		.sink21_valid         (rsp_xbar_demux_027_src0_valid),         //          .valid
		.sink21_channel       (rsp_xbar_demux_027_src0_channel),       //          .channel
		.sink21_data          (rsp_xbar_demux_027_src0_data),          //          .data
		.sink21_startofpacket (rsp_xbar_demux_027_src0_startofpacket), //          .startofpacket
		.sink21_endofpacket   (rsp_xbar_demux_027_src0_endofpacket),   //          .endofpacket
		.sink22_ready         (rsp_xbar_demux_028_src0_ready),         //    sink22.ready
		.sink22_valid         (rsp_xbar_demux_028_src0_valid),         //          .valid
		.sink22_channel       (rsp_xbar_demux_028_src0_channel),       //          .channel
		.sink22_data          (rsp_xbar_demux_028_src0_data),          //          .data
		.sink22_startofpacket (rsp_xbar_demux_028_src0_startofpacket), //          .startofpacket
		.sink22_endofpacket   (rsp_xbar_demux_028_src0_endofpacket)    //          .endofpacket
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (80),
		.BITS_PER_SYMBOL     (80),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (pll_cpu),                               //        in_clk.clk
		.in_reset          (rst_controller_reset_out_reset),        //  in_clk_reset.reset
		.out_clk           (clk),                                   //       out_clk.clk
		.out_reset         (rst_controller_001_reset_out_reset),    // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_001_src3_ready),         //            in.ready
		.in_valid          (cmd_xbar_demux_001_src3_valid),         //              .valid
		.in_startofpacket  (cmd_xbar_demux_001_src3_startofpacket), //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_001_src3_endofpacket),   //              .endofpacket
		.in_channel        (cmd_xbar_demux_001_src3_channel),       //              .channel
		.in_data           (cmd_xbar_demux_001_src3_data),          //              .data
		.out_ready         (crosser_out_ready),                     //           out.ready
		.out_valid         (crosser_out_valid),                     //              .valid
		.out_startofpacket (crosser_out_startofpacket),             //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),               //              .endofpacket
		.out_channel       (crosser_out_channel),                   //              .channel
		.out_data          (crosser_out_data),                      //              .data
		.in_empty          (1'b0),                                  //   (terminated)
		.in_error          (1'b0),                                  //   (terminated)
		.out_empty         (),                                      //   (terminated)
		.out_error         ()                                       //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (80),
		.BITS_PER_SYMBOL     (80),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (6),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (clk),                                   //        in_clk.clk
		.in_reset          (rst_controller_001_reset_out_reset),    //  in_clk_reset.reset
		.out_clk           (pll_cpu),                               //       out_clk.clk
		.out_reset         (rst_controller_reset_out_reset),        // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_003_src0_ready),         //            in.ready
		.in_valid          (rsp_xbar_demux_003_src0_valid),         //              .valid
		.in_startofpacket  (rsp_xbar_demux_003_src0_startofpacket), //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_003_src0_endofpacket),   //              .endofpacket
		.in_channel        (rsp_xbar_demux_003_src0_channel),       //              .channel
		.in_data           (rsp_xbar_demux_003_src0_data),          //              .data
		.out_ready         (crosser_001_out_ready),                 //           out.ready
		.out_valid         (crosser_001_out_valid),                 //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),         //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),           //              .endofpacket
		.out_channel       (crosser_001_out_channel),               //              .channel
		.out_data          (crosser_001_out_data),                  //              .data
		.in_empty          (1'b0),                                  //   (terminated)
		.in_error          (1'b0),                                  //   (terminated)
		.out_empty         (),                                      //   (terminated)
		.out_error         ()                                       //   (terminated)
	);

	TR4_HDMI_TX_RX_SOPC_irq_mapper irq_mapper (
		.clk           (pll_cpu),                        //       clk.clk
		.reset         (rst_controller_reset_out_reset), // clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),       // receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),       // receiver1.irq
		.receiver2_irq (irq_mapper_receiver2_irq),       // receiver2.irq
		.receiver3_irq (irq_mapper_receiver3_irq),       // receiver3.irq
		.receiver4_irq (irq_mapper_receiver4_irq),       // receiver4.irq
		.sender_irq    (cpu_d_irq_irq)                   //    sender.irq
	);

	altera_irq_clock_crosser #(
		.IRQ_WIDTH (1)
	) irq_synchronizer (
		.receiver_clk   (pll_io),                             //       receiver_clk.clk
		.sender_clk     (pll_cpu),                            //         sender_clk.clk
		.receiver_reset (rst_controller_002_reset_out_reset), // receiver_clk_reset.reset
		.sender_reset   (rst_controller_reset_out_reset),     //   sender_clk_reset.reset
		.receiver_irq   (irq_synchronizer_receiver_irq),      //           receiver.irq
		.sender_irq     (irq_mapper_receiver1_irq)            //             sender.irq
	);

	altera_irq_clock_crosser #(
		.IRQ_WIDTH (1)
	) irq_synchronizer_001 (
		.receiver_clk   (pll_io),                             //       receiver_clk.clk
		.sender_clk     (pll_cpu),                            //         sender_clk.clk
		.receiver_reset (rst_controller_002_reset_out_reset), // receiver_clk_reset.reset
		.sender_reset   (rst_controller_reset_out_reset),     //   sender_clk_reset.reset
		.receiver_irq   (irq_synchronizer_001_receiver_irq),  //           receiver.irq
		.sender_irq     (irq_mapper_receiver2_irq)            //             sender.irq
	);

	altera_irq_clock_crosser #(
		.IRQ_WIDTH (1)
	) irq_synchronizer_002 (
		.receiver_clk   (pll_io),                             //       receiver_clk.clk
		.sender_clk     (pll_cpu),                            //         sender_clk.clk
		.receiver_reset (rst_controller_002_reset_out_reset), // receiver_clk_reset.reset
		.sender_reset   (rst_controller_reset_out_reset),     //   sender_clk_reset.reset
		.receiver_irq   (irq_synchronizer_002_receiver_irq),  //           receiver.irq
		.sender_irq     (irq_mapper_receiver3_irq)            //             sender.irq
	);

endmodule
