/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'cpu_0' in SOPC Builder design 'system'
 * SOPC Builder design path: D:/Project/tr4_daught_card/tmp/test/TR4_ICB/system.sopcinfo
 *
 * Generated: Thu Dec 22 10:45:07 CST 2011
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x2100820
#define ALT_CPU_CPU_FREQ 100000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "fast"
#define ALT_CPU_DATA_ADDR_WIDTH 0x1a
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_DCACHE_SIZE 2048
#define ALT_CPU_EXCEPTION_ADDR 0x2080020
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 100000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1
#define ALT_CPU_HARDWARE_MULX_PRESENT 1
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INITDA_SUPPORTED
#define ALT_CPU_INST_ADDR_WIDTH 0x1a
#define ALT_CPU_NAME "cpu_0"
#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0
#define ALT_CPU_RESET_ADDR 0x2080000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x2100820
#define NIOS2_CPU_FREQ 100000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_DATA_ADDR_WIDTH 0x1a
#define NIOS2_DCACHE_LINE_SIZE 32
#define NIOS2_DCACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_SIZE 2048
#define NIOS2_EXCEPTION_ADDR 0x2080020
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1
#define NIOS2_HARDWARE_MULX_PRESENT 1
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_INITDA_SUPPORTED
#define NIOS2_INST_ADDR_WIDTH 0x1a
#define NIOS2_NUM_OF_SHADOW_REG_SETS 0
#define NIOS2_RESET_ADDR 0x2080000


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_UART
#define __ALTERA_NIOS2_QSYS
#define __ALTPLL


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Stratix IV"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x0
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x0
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x0
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "system"


/*
 * altpll_0 configuration
 *
 */

#define ALTPLL_0_BASE 0x2101000
#define ALTPLL_0_IRQ -1
#define ALTPLL_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ALTPLL_0_NAME "/dev/altpll_0"
#define ALTPLL_0_SPAN 16
#define ALTPLL_0_TYPE "altpll"
#define ALT_MODULE_CLASS_altpll_0 altpll


/*
 * can_0 configuration
 *
 */

#define ALT_MODULE_CLASS_can_0 altera_avalon_uart
#define CAN_0_BASE 0x10000a0
#define CAN_0_BAUD 9600
#define CAN_0_DATA_BITS 8
#define CAN_0_FIXED_BAUD 1
#define CAN_0_FREQ 10000000u
#define CAN_0_IRQ 5
#define CAN_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define CAN_0_NAME "/dev/can_0"
#define CAN_0_PARITY 'N'
#define CAN_0_SIM_CHAR_STREAM ""
#define CAN_0_SIM_TRUE_BAUD 0
#define CAN_0_SPAN 32
#define CAN_0_STOP_BITS 1
#define CAN_0_SYNC_REG_DEPTH 2
#define CAN_0_TYPE "altera_avalon_uart"
#define CAN_0_USE_CTS_RTS 1
#define CAN_0_USE_EOP_REGISTER 0


/*
 * can_1 configuration
 *
 */

#define ALT_MODULE_CLASS_can_1 altera_avalon_uart
#define CAN_1_BASE 0x10000c0
#define CAN_1_BAUD 9600
#define CAN_1_DATA_BITS 8
#define CAN_1_FIXED_BAUD 1
#define CAN_1_FREQ 10000000u
#define CAN_1_IRQ 6
#define CAN_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define CAN_1_NAME "/dev/can_1"
#define CAN_1_PARITY 'N'
#define CAN_1_SIM_CHAR_STREAM ""
#define CAN_1_SIM_TRUE_BAUD 0
#define CAN_1_SPAN 32
#define CAN_1_STOP_BITS 1
#define CAN_1_SYNC_REG_DEPTH 2
#define CAN_1_TYPE "altera_avalon_uart"
#define CAN_1_USE_CTS_RTS 0
#define CAN_1_USE_EOP_REGISTER 0


/*
 * hal configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER_1
#define ALT_TIMESTAMP_CLK none


/*
 * jtag_uart_0 configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x0
#define JTAG_UART_0_IRQ 7
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
#define JTAG_UART_0_READ_DEPTH 64
#define JTAG_UART_0_READ_THRESHOLD 8
#define JTAG_UART_0_SPAN 8
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_0_WRITE_DEPTH 64
#define JTAG_UART_0_WRITE_THRESHOLD 8


/*
 * onchip_memory2_0 configuration
 *
 */

#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_BASE 0x2080000
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "Automatic"
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "onchip_memory2_0"
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
#define ONCHIP_MEMORY2_0_IRQ -1
#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "Auto"
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 350000u
#define ONCHIP_MEMORY2_0_SPAN 350000
#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
#define ONCHIP_MEMORY2_0_WRITABLE 1


/*
 * rs485_0 configuration
 *
 */

#define ALT_MODULE_CLASS_rs485_0 altera_avalon_uart
#define RS485_0_BASE 0x1000020
#define RS485_0_BAUD 115200
#define RS485_0_DATA_BITS 8
#define RS485_0_FIXED_BAUD 1
#define RS485_0_FREQ 10000000u
#define RS485_0_IRQ 1
#define RS485_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define RS485_0_NAME "/dev/rs485_0"
#define RS485_0_PARITY 'N'
#define RS485_0_SIM_CHAR_STREAM ""
#define RS485_0_SIM_TRUE_BAUD 0
#define RS485_0_SPAN 32
#define RS485_0_STOP_BITS 1
#define RS485_0_SYNC_REG_DEPTH 2
#define RS485_0_TYPE "altera_avalon_uart"
#define RS485_0_USE_CTS_RTS 1
#define RS485_0_USE_EOP_REGISTER 0


/*
 * rs485_1 configuration
 *
 */

#define ALT_MODULE_CLASS_rs485_1 altera_avalon_uart
#define RS485_1_BASE 0x1000040
#define RS485_1_BAUD 115200
#define RS485_1_DATA_BITS 8
#define RS485_1_FIXED_BAUD 1
#define RS485_1_FREQ 10000000u
#define RS485_1_IRQ 2
#define RS485_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define RS485_1_NAME "/dev/rs485_1"
#define RS485_1_PARITY 'N'
#define RS485_1_SIM_CHAR_STREAM ""
#define RS485_1_SIM_TRUE_BAUD 0
#define RS485_1_SPAN 32
#define RS485_1_STOP_BITS 1
#define RS485_1_SYNC_REG_DEPTH 2
#define RS485_1_TYPE "altera_avalon_uart"
#define RS485_1_USE_CTS_RTS 1
#define RS485_1_USE_EOP_REGISTER 0


/*
 * rs485_2 configuration
 *
 */

#define ALT_MODULE_CLASS_rs485_2 altera_avalon_uart
#define RS485_2_BASE 0x1000060
#define RS485_2_BAUD 115200
#define RS485_2_DATA_BITS 8
#define RS485_2_FIXED_BAUD 1
#define RS485_2_FREQ 10000000u
#define RS485_2_IRQ 3
#define RS485_2_IRQ_INTERRUPT_CONTROLLER_ID 0
#define RS485_2_NAME "/dev/rs485_2"
#define RS485_2_PARITY 'N'
#define RS485_2_SIM_CHAR_STREAM ""
#define RS485_2_SIM_TRUE_BAUD 0
#define RS485_2_SPAN 32
#define RS485_2_STOP_BITS 1
#define RS485_2_SYNC_REG_DEPTH 2
#define RS485_2_TYPE "altera_avalon_uart"
#define RS485_2_USE_CTS_RTS 1
#define RS485_2_USE_EOP_REGISTER 0


/*
 * rs485_3 configuration
 *
 */

#define ALT_MODULE_CLASS_rs485_3 altera_avalon_uart
#define RS485_3_BASE 0x1000080
#define RS485_3_BAUD 115200
#define RS485_3_DATA_BITS 8
#define RS485_3_FIXED_BAUD 1
#define RS485_3_FREQ 10000000u
#define RS485_3_IRQ 4
#define RS485_3_IRQ_INTERRUPT_CONTROLLER_ID 0
#define RS485_3_NAME "/dev/rs485_3"
#define RS485_3_PARITY 'N'
#define RS485_3_SIM_CHAR_STREAM ""
#define RS485_3_SIM_TRUE_BAUD 0
#define RS485_3_SPAN 32
#define RS485_3_STOP_BITS 1
#define RS485_3_SYNC_REG_DEPTH 2
#define RS485_3_TYPE "altera_avalon_uart"
#define RS485_3_USE_CTS_RTS 1
#define RS485_3_USE_EOP_REGISTER 0


/*
 * sw configuration
 *
 */

#define ALT_MODULE_CLASS_sw altera_avalon_pio
#define SW_BASE 0x10000e0
#define SW_BIT_CLEARING_EDGE_REGISTER 0
#define SW_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SW_CAPTURE 0
#define SW_DATA_WIDTH 4
#define SW_DO_TEST_BENCH_WIRING 0
#define SW_DRIVEN_SIM_VALUE 0x0
#define SW_EDGE_TYPE "NONE"
#define SW_FREQ 10000000u
#define SW_HAS_IN 1
#define SW_HAS_OUT 0
#define SW_HAS_TRI 0
#define SW_IRQ -1
#define SW_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SW_IRQ_TYPE "NONE"
#define SW_NAME "/dev/sw"
#define SW_RESET_VALUE 0x0
#define SW_SPAN 16
#define SW_TYPE "altera_avalon_pio"


/*
 * timer_1 configuration
 *
 */

#define ALT_MODULE_CLASS_timer_1 altera_avalon_timer
#define TIMER_1_ALWAYS_RUN 0
#define TIMER_1_BASE 0x1000000
#define TIMER_1_COUNTER_SIZE 32
#define TIMER_1_FIXED_PERIOD 0
#define TIMER_1_FREQ 10000000u
#define TIMER_1_IRQ 0
#define TIMER_1_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_1_LOAD_VALUE 9999ull
#define TIMER_1_MULT 0.0010
#define TIMER_1_NAME "/dev/timer_1"
#define TIMER_1_PERIOD 1
#define TIMER_1_PERIOD_UNITS "ms"
#define TIMER_1_RESET_OUTPUT 0
#define TIMER_1_SNAPSHOT 1
#define TIMER_1_SPAN 32
#define TIMER_1_TICKS_PER_SEC 1000u
#define TIMER_1_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_1_TYPE "altera_avalon_timer"

#endif /* __SYSTEM_H_ */
