module Tr4_ICB_TOP
(
                  CLK_50,
                  RESET_N,
						SW,
                 //rs2323
                  ICBRS232_TXD,
                  ICBRS232_RXD,
                 //rs485
  		        		ICBRS485_0_RTS,
		          	ICBRS485_0_RXD,
		        		ICBRS485_0_TXD,
		          	ICBRS485_1_RTS,
		          	ICBRS485_1_RXD,
		          	ICBRS485_1_TXD,
		          	ICBRS485_2_RTS,
		          	ICBRS485_2_RXD,
		          	ICBRS485_2_TXD,
		        		ICBRS485_3_RTS,
		          	ICBRS485_3_RXD,
		          	ICBRS485_3_TXD,
						//can
                  ICBPOWER_VALID,
						ICBCAN0_T,
						ICBCAN0_R,
						ICBCAN1_T,
						ICBCAN1_R
  );
input              CLK_50;
input              RESET_N;
input   [3:0]      SW;
//rs232
input         ICBRS232_RXD;
output        ICBRS232_TXD; 
//rs485
output		        		ICBRS485_0_RTS;
input		          		ICBRS485_0_RXD;
output		        		ICBRS485_0_TXD;
output		          	ICBRS485_1_RTS;
input		          		ICBRS485_1_RXD;
output		          	ICBRS485_1_TXD;
output		          	ICBRS485_2_RTS;
input		          		ICBRS485_2_RXD;
output		          	ICBRS485_2_TXD;
output		        		ICBRS485_3_RTS;
input		          		ICBRS485_3_RXD;
output		          	ICBRS485_3_TXD;
//can
output                  ICBCAN0_T;
input                   ICBCAN0_R;
output                  ICBCAN1_T;
input                   ICBCAN1_R;
output		        		ICBPOWER_VALID;	 
//=======================================================
//  REG/WIRE declarations
//=======================================================
//RS232 WIRE and regist
wire	 [7:0]   uart_data;
wire	         rdempty;
wire	         write;
reg	     	   read;
reg	         cnt;
//=======================================================
//  Structural coding
//=======================================================
// UART Controller
uart_control UART0(

	.clk(CLK_50),
	.reset_n(RESET_N),
	// tx
	.write(write),
	.writedata(uart_data),

	// rx
	.read(read),
	.readdata(uart_data),
	.rdempty(rdempty),
	//
	.uart_clk_25m(cnt),
	.uart_tx(ICBRS232_TXD),
	.uart_rx(ICBRS232_RXD)
	
);	
//read
always@(posedge CLK_50)
	begin
		if (~rdempty)
			read <= 1;
		else
			read <= 0;
	end

assign	write = ( read & (~rdempty) );
always@(posedge CLK_50)
	cnt <= cnt + 1;
assign       		ICBPOWER_VALID=1'b1;	

system u0 (
        .clk_50                      (CLK_50),                      //               clk_50_clk_in.clk
        .uart_sys                    (),                    //                 altpll_0_c1.clk
        .rts_n_from_the_can_0        (),        //   can_0_external_connection.rts_n
        .cts_n_to_the_can_0          (),          //                            .cts_n
        .rxd_to_the_can_0            (ICBCAN0_R),            //                            .rxd
        .txd_from_the_can_0          (ICBCAN0_T),          //                            .txd
        .phasedone_from_the_altpll_0 (), //  altpll_0_phasedone_conduit.export
        .reset_n                     (RESET_N),                     //         clk_50_clk_in_reset.reset_n
        .txd_from_the_can_1          (ICBCAN1_T),          //   can_1_external_connection.txd
        .rxd_to_the_can_1            (ICBCAN1_R),            //                            .rxd
        .low_clk                     (),                     //                  c2_out_clk.clk
        .rxd_to_the_rs485_3          (ICBRS485_3_RXD),          // rs485_3_external_connection.rxd
        .rts_n_from_the_rs485_3      (ICBRS485_3_RTS),      //                            .rts_n
        .cts_n_to_the_rs485_3        (),        //                            .cts_n
        .txd_from_the_rs485_3        (ICBRS485_3_TXD),        //                            .txd
        .rxd_to_the_rs485_1          (ICBRS485_1_RXD),          // rs485_1_external_connection.rxd
        .rts_n_from_the_rs485_1      (ICBRS485_1_RTS),      //                            .rts_n
        .cts_n_to_the_rs485_1        (),        //                            .cts_n
        .txd_from_the_rs485_1        (ICBRS485_1_TXD),        //                            .txd
        .cts_n_to_the_rs485_0        (),        // rs485_0_external_connection.cts_n
        .rts_n_from_the_rs485_0      (ICBRS485_0_RTS),      //                            .rts_n
        .txd_from_the_rs485_0        (ICBRS485_0_TXD),        //                            .txd
        .rxd_to_the_rs485_0          (ICBRS485_0_RXD),          //                            .rxd
        .txd_from_the_rs485_2        (ICBRS485_2_TXD),        // rs485_2_external_connection.txd
        .rts_n_from_the_rs485_2      (ICBRS485_2_RTS),      //                            .rts_n
        .rxd_to_the_rs485_2          (ICBRS485_2_RXD),          //                            .rxd
        .cts_n_to_the_rs485_2        (),        //                            .cts_n
        .locked_from_the_altpll_0    (),    //     altpll_0_locked_conduit.export
        .sys_clk                     (),                     //                  c0_out_clk.clk
        .areset_to_the_altpll_0      (),      //     altpll_0_areset_conduit.export
        .in_port_to_the_sw           (SW)            //      sw_external_connection.export
    );
endmodule