<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="System" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element $${FILENAME}
   {
   }
   element altpll_0
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
   }
   element jtag_uart_0.avalon_jtag_slave
   {
      datum baseAddress
      {
         value = "0";
         type = "long";
      }
   }
   element c0
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
   element altpll_0.c0
   {
      datum _clockDomain
      {
         value = "sys_clk";
         type = "String";
      }
   }
   element altpll_0.c1
   {
      datum _clockDomain
      {
         value = "uart_sys";
         type = "String";
      }
   }
   element altpll_0.c2
   {
      datum _clockDomain
      {
         value = "low_clk";
         type = "String";
      }
   }
   element c2
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
   }
   element can_0
   {
      datum _sortIndex
      {
         value = "13";
         type = "int";
      }
   }
   element can_1
   {
      datum _sortIndex
      {
         value = "14";
         type = "int";
      }
   }
   element clk_50
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element clock_crossing_low
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
   }
   element cpu_0
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
   }
   element cpu_0.jtag_debug_module
   {
      datum baseAddress
      {
         value = "34605056";
         type = "long";
      }
   }
   element jtag_uart_0
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
   }
   element onchip_memory2_0
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
   }
   element altpll_0.pll_slave
   {
      datum baseAddress
      {
         value = "34607104";
         type = "long";
      }
   }
   element rs485_0
   {
      datum _sortIndex
      {
         value = "9";
         type = "int";
      }
   }
   element rs485_1
   {
      datum _sortIndex
      {
         value = "10";
         type = "int";
      }
   }
   element rs485_2
   {
      datum _sortIndex
      {
         value = "11";
         type = "int";
      }
   }
   element rs485_3
   {
      datum _sortIndex
      {
         value = "12";
         type = "int";
      }
   }
   element sw.s1
   {
      datum baseAddress
      {
         value = "224";
         type = "long";
      }
   }
   element rs485_2.s1
   {
      datum baseAddress
      {
         value = "96";
         type = "long";
      }
   }
   element onchip_memory2_0.s1
   {
      datum baseAddress
      {
         value = "34078720";
         type = "long";
      }
   }
   element rs485_0.s1
   {
      datum baseAddress
      {
         value = "32";
         type = "long";
      }
   }
   element can_0.s1
   {
      datum baseAddress
      {
         value = "160";
         type = "long";
      }
   }
   element can_1.s1
   {
      datum baseAddress
      {
         value = "192";
         type = "long";
      }
   }
   element rs485_3.s1
   {
      datum baseAddress
      {
         value = "128";
         type = "long";
      }
   }
   element timer_1.s1
   {
      datum baseAddress
      {
         value = "0";
         type = "long";
      }
   }
   element rs485_1.s1
   {
      datum baseAddress
      {
         value = "64";
         type = "long";
      }
   }
   element sw
   {
      datum _sortIndex
      {
         value = "15";
         type = "int";
      }
   }
   element timer_1
   {
      datum _sortIndex
      {
         value = "8";
         type = "int";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="deviceFamily" value="STRATIXIV" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="maxAdditionalLatency" value="0" />
 <parameter name="projectName" value="Tr4_ICB.qpf" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="1" />
 <parameter name="timeStamp" value="1324521674109" />
 <interface name="clk_50_clk_in" internal="clk_50.clk_in" type="clock" dir="end">
  <port name="clk_50" internal="in_clk" />
 </interface>
 <interface name="altpll_0_c1" internal="altpll_0.c1" type="clock" dir="start">
  <port name="uart_sys" internal="c1" />
 </interface>
 <interface
   name="can_0_external_connection"
   internal="can_0.external_connection"
   type="conduit"
   dir="end">
  <port name="rxd_to_the_can_0" internal="rxd" />
  <port name="txd_from_the_can_0" internal="txd" />
  <port name="cts_n_to_the_can_0" internal="cts_n" />
  <port name="rts_n_from_the_can_0" internal="rts_n" />
 </interface>
 <interface
   name="altpll_0_phasedone_conduit"
   internal="altpll_0.phasedone_conduit"
   type="conduit"
   dir="end">
  <port name="phasedone_from_the_altpll_0" internal="phasedone" />
 </interface>
 <interface
   name="clk_50_clk_in_reset"
   internal="clk_50.clk_in_reset"
   type="reset"
   dir="end">
  <port name="reset_n" internal="reset_n" />
 </interface>
 <interface
   name="can_1_external_connection"
   internal="can_1.external_connection"
   type="conduit"
   dir="end">
  <port name="rxd_to_the_can_1" internal="rxd" />
  <port name="txd_from_the_can_1" internal="txd" />
 </interface>
 <interface name="c2_out_clk" internal="c2.out_clk" type="clock" dir="start">
  <port name="low_clk" internal="out_clk" />
 </interface>
 <interface
   name="rs485_3_external_connection"
   internal="rs485_3.external_connection"
   type="conduit"
   dir="end">
  <port name="rxd_to_the_rs485_3" internal="rxd" />
  <port name="txd_from_the_rs485_3" internal="txd" />
  <port name="cts_n_to_the_rs485_3" internal="cts_n" />
  <port name="rts_n_from_the_rs485_3" internal="rts_n" />
 </interface>
 <interface
   name="rs485_1_external_connection"
   internal="rs485_1.external_connection"
   type="conduit"
   dir="end">
  <port name="rxd_to_the_rs485_1" internal="rxd" />
  <port name="txd_from_the_rs485_1" internal="txd" />
  <port name="cts_n_to_the_rs485_1" internal="cts_n" />
  <port name="rts_n_from_the_rs485_1" internal="rts_n" />
 </interface>
 <interface
   name="rs485_0_external_connection"
   internal="rs485_0.external_connection"
   type="conduit"
   dir="end">
  <port name="rxd_to_the_rs485_0" internal="rxd" />
  <port name="txd_from_the_rs485_0" internal="txd" />
  <port name="cts_n_to_the_rs485_0" internal="cts_n" />
  <port name="rts_n_from_the_rs485_0" internal="rts_n" />
 </interface>
 <interface
   name="rs485_2_external_connection"
   internal="rs485_2.external_connection"
   type="conduit"
   dir="end">
  <port name="rxd_to_the_rs485_2" internal="rxd" />
  <port name="txd_from_the_rs485_2" internal="txd" />
  <port name="cts_n_to_the_rs485_2" internal="cts_n" />
  <port name="rts_n_from_the_rs485_2" internal="rts_n" />
 </interface>
 <interface
   name="altpll_0_locked_conduit"
   internal="altpll_0.locked_conduit"
   type="conduit"
   dir="end">
  <port name="locked_from_the_altpll_0" internal="locked" />
 </interface>
 <interface name="c0_out_clk" internal="c0.out_clk" type="clock" dir="start">
  <port name="sys_clk" internal="out_clk" />
 </interface>
 <interface
   name="altpll_0_areset_conduit"
   internal="altpll_0.areset_conduit"
   type="conduit"
   dir="end">
  <port name="areset_to_the_altpll_0" internal="areset" />
 </interface>
 <interface
   name="sw_external_connection"
   internal="sw.external_connection"
   type="conduit"
   dir="end">
  <port name="in_port_to_the_sw" internal="in_port" />
 </interface>
 <module kind="clock_source" version="11.0" enabled="1" name="clk_50">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   kind="altera_avalon_onchip_memory2"
   version="11.0"
   enabled="1"
   name="onchip_memory2_0">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="autoInitializationFileName" value="onchip_memory2_0" />
  <parameter name="blockType" value="AUTO" />
  <parameter name="dataWidth" value="32" />
  <parameter name="deviceFamily" value="Stratix IV" />
  <parameter name="dualPort" value="false" />
  <parameter name="initMemContent" value="true" />
  <parameter name="initializationFileName" value="onchip_memory2_0" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="350000" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module kind="altpll" version="11.0" enabled="1" name="altpll_0">
  <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
  <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
  <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
  <parameter name="WIDTH_CLOCK" value="10" />
  <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
  <parameter name="PRIMARY_CLOCK" value="" />
  <parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
  <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
  <parameter name="OPERATION_MODE" value="NORMAL" />
  <parameter name="PLL_TYPE" value="AUTO" />
  <parameter name="QUALIFY_CONF_DONE" value="" />
  <parameter name="COMPENSATE_CLOCK" value="CLK0" />
  <parameter name="SCAN_CHAIN" value="" />
  <parameter name="GATE_LOCK_SIGNAL" value="" />
  <parameter name="GATE_LOCK_COUNTER" value="" />
  <parameter name="LOCK_HIGH" value="" />
  <parameter name="LOCK_LOW" value="" />
  <parameter name="VALID_LOCK_MULTIPLIER" value="" />
  <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
  <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
  <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
  <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
  <parameter name="SKIP_VCO" value="" />
  <parameter name="SWITCH_OVER_COUNTER" value="" />
  <parameter name="SWITCH_OVER_TYPE" value="" />
  <parameter name="FEEDBACK_SOURCE" value="" />
  <parameter name="BANDWIDTH" value="" />
  <parameter name="BANDWIDTH_TYPE" value="AUTO" />
  <parameter name="SPREAD_FREQUENCY" value="" />
  <parameter name="DOWN_SPREAD" value="" />
  <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
  <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
  <parameter name="CLK0_MULTIPLY_BY" value="2" />
  <parameter name="CLK1_MULTIPLY_BY" value="1" />
  <parameter name="CLK2_MULTIPLY_BY" value="1" />
  <parameter name="CLK3_MULTIPLY_BY" value="" />
  <parameter name="CLK4_MULTIPLY_BY" value="" />
  <parameter name="CLK5_MULTIPLY_BY" value="" />
  <parameter name="CLK6_MULTIPLY_BY" value="" />
  <parameter name="CLK7_MULTIPLY_BY" value="" />
  <parameter name="CLK8_MULTIPLY_BY" value="" />
  <parameter name="CLK9_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
  <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
  <parameter name="CLK0_DIVIDE_BY" value="1" />
  <parameter name="CLK1_DIVIDE_BY" value="1" />
  <parameter name="CLK2_DIVIDE_BY" value="5" />
  <parameter name="CLK3_DIVIDE_BY" value="" />
  <parameter name="CLK4_DIVIDE_BY" value="" />
  <parameter name="CLK5_DIVIDE_BY" value="" />
  <parameter name="CLK6_DIVIDE_BY" value="" />
  <parameter name="CLK7_DIVIDE_BY" value="" />
  <parameter name="CLK8_DIVIDE_BY" value="" />
  <parameter name="CLK9_DIVIDE_BY" value="" />
  <parameter name="EXTCLK0_DIVIDE_BY" value="" />
  <parameter name="EXTCLK1_DIVIDE_BY" value="" />
  <parameter name="EXTCLK2_DIVIDE_BY" value="" />
  <parameter name="EXTCLK3_DIVIDE_BY" value="" />
  <parameter name="CLK0_PHASE_SHIFT" value="0" />
  <parameter name="CLK1_PHASE_SHIFT" value="0" />
  <parameter name="CLK2_PHASE_SHIFT" value="0" />
  <parameter name="CLK3_PHASE_SHIFT" value="" />
  <parameter name="CLK4_PHASE_SHIFT" value="" />
  <parameter name="CLK5_PHASE_SHIFT" value="" />
  <parameter name="CLK6_PHASE_SHIFT" value="" />
  <parameter name="CLK7_PHASE_SHIFT" value="" />
  <parameter name="CLK8_PHASE_SHIFT" value="" />
  <parameter name="CLK9_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
  <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
  <parameter name="CLK0_DUTY_CYCLE" value="50" />
  <parameter name="CLK1_DUTY_CYCLE" value="50" />
  <parameter name="CLK2_DUTY_CYCLE" value="50" />
  <parameter name="CLK3_DUTY_CYCLE" value="" />
  <parameter name="CLK4_DUTY_CYCLE" value="" />
  <parameter name="CLK5_DUTY_CYCLE" value="" />
  <parameter name="CLK6_DUTY_CYCLE" value="" />
  <parameter name="CLK7_DUTY_CYCLE" value="" />
  <parameter name="CLK8_DUTY_CYCLE" value="" />
  <parameter name="CLK9_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
  <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
  <parameter name="PORT_clkena0" value="PORT_UNUSED" />
  <parameter name="PORT_clkena1" value="PORT_UNUSED" />
  <parameter name="PORT_clkena2" value="PORT_UNUSED" />
  <parameter name="PORT_clkena3" value="PORT_UNUSED" />
  <parameter name="PORT_clkena4" value="PORT_UNUSED" />
  <parameter name="PORT_clkena5" value="PORT_UNUSED" />
  <parameter name="PORT_extclkena0" value="" />
  <parameter name="PORT_extclkena1" value="" />
  <parameter name="PORT_extclkena2" value="" />
  <parameter name="PORT_extclkena3" value="" />
  <parameter name="PORT_extclk0" value="" />
  <parameter name="PORT_extclk1" value="" />
  <parameter name="PORT_extclk2" value="" />
  <parameter name="PORT_extclk3" value="" />
  <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
  <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
  <parameter name="PORT_clk0" value="PORT_USED" />
  <parameter name="PORT_clk1" value="PORT_USED" />
  <parameter name="PORT_clk2" value="PORT_USED" />
  <parameter name="PORT_clk3" value="PORT_UNUSED" />
  <parameter name="PORT_clk4" value="PORT_UNUSED" />
  <parameter name="PORT_clk5" value="PORT_UNUSED" />
  <parameter name="PORT_clk6" value="PORT_UNUSED" />
  <parameter name="PORT_clk7" value="PORT_UNUSED" />
  <parameter name="PORT_clk8" value="PORT_UNUSED" />
  <parameter name="PORT_clk9" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
  <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
  <parameter name="PORT_SCLKOUT1" value="" />
  <parameter name="PORT_SCLKOUT0" value="" />
  <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
  <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
  <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
  <parameter name="PORT_INCLK0" value="PORT_USED" />
  <parameter name="PORT_FBIN" value="PORT_UNUSED" />
  <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
  <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
  <parameter name="PORT_ARESET" value="PORT_USED" />
  <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
  <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
  <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
  <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
  <parameter name="PORT_ENABLE0" value="" />
  <parameter name="PORT_ENABLE1" value="" />
  <parameter name="PORT_LOCKED" value="PORT_USED" />
  <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
  <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
  <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
  <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
  <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
  <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
  <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
  <parameter name="PORT_VCOOVERRANGE" value="" />
  <parameter name="PORT_VCOUNDERRANGE" value="" />
  <parameter name="DPA_MULTIPLY_BY" value="" />
  <parameter name="DPA_DIVIDE_BY" value="" />
  <parameter name="DPA_DIVIDER" value="" />
  <parameter name="VCO_MULTIPLY_BY" value="" />
  <parameter name="VCO_DIVIDE_BY" value="" />
  <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
  <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
  <parameter name="VCO_FREQUENCY_CONTROL" value="" />
  <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
  <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
  <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
  <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
  <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 5 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
  <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 10.00000000 PT#OUTPUT_FREQ1 50.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 10.000000 PT#EFF_OUTPUT_FREQ_VALUE1 50.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1311576424883634.mif PT#ACTIVECLK_CHECK 0</parameter>
  <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
  <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
  <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
  <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
  <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
  <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
 </module>
 <module kind="altera_avalon_timer" version="11.0" enabled="1" name="timer_1">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="1" />
  <parameter name="periodUnits" value="MSEC" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="true" />
  <parameter name="systemFrequency" value="10000000" />
  <parameter name="timeoutPulseOutput" value="false" />
  <parameter name="timerPreset" value="CUSTOM" />
 </module>
 <module kind="altera_avalon_uart" version="11.0" enabled="1" name="rs485_0">
  <parameter name="baud" value="115200" />
  <parameter name="clockRate" value="10000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="true" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module kind="altera_avalon_uart" version="11.0" enabled="1" name="rs485_1">
  <parameter name="baud" value="115200" />
  <parameter name="clockRate" value="10000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="true" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module kind="altera_avalon_uart" version="11.0" enabled="1" name="rs485_2">
  <parameter name="baud" value="115200" />
  <parameter name="clockRate" value="10000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="true" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module kind="altera_avalon_uart" version="11.0" enabled="1" name="rs485_3">
  <parameter name="baud" value="115200" />
  <parameter name="clockRate" value="10000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="true" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module kind="altera_avalon_uart" version="11.0" enabled="1" name="can_0">
  <parameter name="baud" value="9600" />
  <parameter name="clockRate" value="10000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="true" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module kind="altera_avalon_uart" version="11.0" enabled="1" name="can_1">
  <parameter name="baud" value="9600" />
  <parameter name="clockRate" value="10000000" />
  <parameter name="dataBits" value="8" />
  <parameter name="fixedBaud" value="true" />
  <parameter name="parity" value="NONE" />
  <parameter name="simCharStream" value="" />
  <parameter name="simInteractiveInputEnable" value="false" />
  <parameter name="simInteractiveOutputEnable" value="false" />
  <parameter name="simTrueBaud" value="false" />
  <parameter name="stopBits" value="1" />
  <parameter name="syncRegDepth" value="2" />
  <parameter name="useCtsRts" value="false" />
  <parameter name="useEopRegister" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
 </module>
 <module kind="altera_avalon_pio" version="11.0" enabled="1" name="sw">
  <parameter name="bitClearingEdgeCapReg" value="false" />
  <parameter name="bitModifyingOutReg" value="false" />
  <parameter name="captureEdge" value="false" />
  <parameter name="clockRate" value="10000000" />
  <parameter name="direction" value="Input" />
  <parameter name="edgeType" value="RISING" />
  <parameter name="generateIRQ" value="false" />
  <parameter name="irqType" value="LEVEL" />
  <parameter name="resetValue" value="0" />
  <parameter name="simDoTestBenchWiring" value="false" />
  <parameter name="simDrivenValue" value="0" />
  <parameter name="width" value="4" />
 </module>
 <module
   kind="altera_avalon_jtag_uart"
   version="11.0"
   enabled="1"
   name="jtag_uart_0">
  <parameter name="allowMultipleConnections" value="false" />
  <parameter name="hubInstanceID" value="0" />
  <parameter name="readBufferDepth" value="64" />
  <parameter name="readIRQThreshold" value="8" />
  <parameter name="simInputCharacterStream" value="" />
  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
  <parameter name="useRegistersForReadBuffer" value="false" />
  <parameter name="useRegistersForWriteBuffer" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
  <parameter name="writeBufferDepth" value="64" />
  <parameter name="writeIRQThreshold" value="8" />
 </module>
 <module
   kind="altera_avalon_mm_clock_crossing_bridge"
   version="11.0"
   enabled="1"
   name="clock_crossing_low">
  <parameter name="DATA_WIDTH" value="32" />
  <parameter name="SYMBOL_WIDTH" value="8" />
  <parameter name="ADDRESS_WIDTH" value="8" />
  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
  <parameter name="MAX_BURST_SIZE" value="1" />
  <parameter name="COMMAND_FIFO_DEPTH" value="8" />
  <parameter name="RESPONSE_FIFO_DEPTH" value="8" />
  <parameter name="MASTER_SYNC_DEPTH" value="3" />
  <parameter name="SLAVE_SYNC_DEPTH" value="3" />
  <parameter name="AUTO_M0_CLK_CLOCK_RATE" value="10000000" />
  <parameter name="AUTO_S0_CLK_CLOCK_RATE" value="100000000" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
 </module>
 <module kind="altera_nios2_qsys" version="11.0" enabled="1" name="cpu_0">
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="setting_preciseDivisionErrorException" value="false" />
  <parameter name="setting_performanceCounter" value="false" />
  <parameter name="setting_illegalMemAccessDetection" value="false" />
  <parameter name="setting_illegalInstructionsTrap" value="false" />
  <parameter name="setting_fullWaveformSignals" value="false" />
  <parameter name="setting_extraExceptionInfo" value="false" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_debugSimGen" value="false" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="setting_bhtIndexPcOnly" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_allowFullAddressRange" value="false" />
  <parameter name="setting_activateTrace" value="true" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="setting_activateModelChecker" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="muldiv_divider" value="false" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="manuallyAssignCpuID" value="false" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_embeddedPLL" value="true" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="dcache_omitDataMaster" value="false" />
  <parameter name="cpuReset" value="false" />
  <parameter name="is_hardcopy_compatible" value="false" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="resetOffset" value="0" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="cpuID" value="0" />
  <parameter name="breakOffset" value="32" />
  <parameter name="userDefinedSettings" value="" />
  <parameter name="resetSlave" value="onchip_memory2_0.s1" />
  <parameter name="mmu_TLBMissExcSlave" value="" />
  <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
  <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
  <parameter name="setting_perfCounterWidth" value="32" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="setting_branchPredictionType" value="Automatic" />
  <parameter name="setting_bhtPtrSz" value="8" />
  <parameter name="muldiv_multiplierType" value="DSPBlock" />
  <parameter name="mpu_minInstRegionSize" value="12" />
  <parameter name="mpu_minDataRegionSize" value="12" />
  <parameter name="mmu_uitlbNumEntries" value="4" />
  <parameter name="mmu_udtlbNumEntries" value="6" />
  <parameter name="mmu_tlbPtrSz" value="7" />
  <parameter name="mmu_tlbNumWays" value="16" />
  <parameter name="mmu_processIDNumBits" value="8" />
  <parameter name="impl" value="Fast" />
  <parameter name="icache_size" value="4096" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="icache_numTCIM" value="0" />
  <parameter name="icache_burstType" value="None" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="debug_level" value="Level1" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dcache_size" value="2048" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dcache_numTCDM" value="0" />
  <parameter name="dcache_lineSize" value="32" />
  <parameter name="instAddrWidth" value="26" />
  <parameter name="dataAddrWidth" value="26" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='timer_1.s1' start='0x1000000' end='0x1000020' /><slave name='rs485_0.s1' start='0x1000020' end='0x1000040' /><slave name='rs485_1.s1' start='0x1000040' end='0x1000060' /><slave name='rs485_2.s1' start='0x1000060' end='0x1000080' /><slave name='rs485_3.s1' start='0x1000080' end='0x10000A0' /><slave name='can_0.s1' start='0x10000A0' end='0x10000C0' /><slave name='can_1.s1' start='0x10000C0' end='0x10000E0' /><slave name='sw.s1' start='0x10000E0' end='0x10000F0' /><slave name='onchip_memory2_0.s1' start='0x2080000' end='0x20D5730' /><slave name='cpu_0.jtag_debug_module' start='0x2100800' end='0x2101000' /></address-map>]]></parameter>
  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='jtag_uart_0.avalon_jtag_slave' start='0x0' end='0x8' /><slave name='timer_1.s1' start='0x1000000' end='0x1000020' /><slave name='rs485_0.s1' start='0x1000020' end='0x1000040' /><slave name='rs485_1.s1' start='0x1000040' end='0x1000060' /><slave name='rs485_2.s1' start='0x1000060' end='0x1000080' /><slave name='rs485_3.s1' start='0x1000080' end='0x10000A0' /><slave name='can_0.s1' start='0x10000A0' end='0x10000C0' /><slave name='can_1.s1' start='0x10000C0' end='0x10000E0' /><slave name='sw.s1' start='0x10000E0' end='0x10000F0' /><slave name='onchip_memory2_0.s1' start='0x2080000' end='0x20D5730' /><slave name='cpu_0.jtag_debug_module' start='0x2100800' end='0x2101000' /><slave name='altpll_0.pll_slave' start='0x2101000' end='0x2101010' /></address-map>]]></parameter>
  <parameter name="clockFrequency" value="100000000" />
  <parameter name="deviceFamilyName" value="Stratix IV" />
  <parameter name="internalIrqMaskSystemInfo" value="255" />
  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
  <parameter name="deviceFeaturesSystemInfo">M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 1 MRAM_MEMORY 0 MLAB_MEMORY 1 ESB 0 EPCS 1 DSP 1 EMUL 0 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 DSP_SHIFTER_BLOCK 1</parameter>
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
 </module>
 <module kind="altera_clock_bridge" version="11.0" enabled="1" name="c0">
  <parameter name="DERIVED_CLOCK_RATE" value="100000000" />
  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
 </module>
 <module kind="altera_clock_bridge" version="11.0" enabled="1" name="c2">
  <parameter name="DERIVED_CLOCK_RATE" value="10000000" />
  <parameter name="EXPLICIT_CLOCK_RATE" value="0" />
  <parameter name="NUM_CLOCK_OUTPUTS" value="1" />
 </module>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.instruction_master"
   end="cpu_0.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x02100800" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.data_master"
   end="cpu_0.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x02100800" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.instruction_master"
   end="onchip_memory2_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x02080000" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.data_master"
   end="onchip_memory2_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x02080000" />
 </connection>
 <connection
   kind="clock"
   version="11.0"
   start="clk_50.clk"
   end="altpll_0.inclk_interface" />
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.data_master"
   end="altpll_0.pll_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x02101000" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu_0.d_irq" end="timer_1.irq">
  <parameter name="irqNumber" value="0" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu_0.d_irq" end="rs485_0.irq">
  <parameter name="irqNumber" value="1" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu_0.d_irq" end="rs485_1.irq">
  <parameter name="irqNumber" value="2" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu_0.d_irq" end="rs485_2.irq">
  <parameter name="irqNumber" value="3" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu_0.d_irq" end="rs485_3.irq">
  <parameter name="irqNumber" value="4" />
 </connection>
 <connection kind="clock" version="11.0" start="altpll_0.c0" end="cpu_0.clk" />
 <connection
   kind="clock"
   version="11.0"
   start="altpll_0.c0"
   end="onchip_memory2_0.clk1" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="timer_1.clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="rs485_0.clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="rs485_1.clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="rs485_2.clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="rs485_3.clk" />
 <connection kind="interrupt" version="11.0" start="cpu_0.d_irq" end="can_0.irq">
  <parameter name="irqNumber" value="5" />
 </connection>
 <connection kind="interrupt" version="11.0" start="cpu_0.d_irq" end="can_1.irq">
  <parameter name="irqNumber" value="6" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.data_master"
   end="jtag_uart_0.avalon_jtag_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
 <connection
   kind="interrupt"
   version="11.0"
   start="cpu_0.d_irq"
   end="jtag_uart_0.irq">
  <parameter name="irqNumber" value="7" />
 </connection>
 <connection kind="clock" version="11.0" start="altpll_0.c0" end="jtag_uart_0.clk" />
 <connection
   kind="clock"
   version="11.0"
   start="altpll_0.c2"
   end="clock_crossing_low.m0_clk" />
 <connection
   kind="clock"
   version="11.0"
   start="altpll_0.c0"
   end="clock_crossing_low.s0_clk" />
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.instruction_master"
   end="clock_crossing_low.s0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01000000" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="cpu_0.data_master"
   end="clock_crossing_low.s0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x01000000" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="timer_1.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="rs485_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0020" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="rs485_1.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0040" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="rs485_2.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0060" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="rs485_3.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0080" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="can_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00a0" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="can_1.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00c0" />
 </connection>
 <connection
   kind="avalon"
   version="11.0"
   start="clock_crossing_low.m0"
   end="sw.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x00e0" />
 </connection>
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="onchip_memory2_0.reset1" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="onchip_memory2_0.reset1" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="altpll_0.inclk_interface_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="altpll_0.inclk_interface_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="timer_1.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="timer_1.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="rs485_0.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="rs485_0.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="rs485_1.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="rs485_1.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="rs485_2.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="rs485_2.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="rs485_3.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="rs485_3.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="can_0.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="can_0.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="can_1.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="can_1.reset" />
 <connection kind="reset" version="11.0" start="clk_50.clk_reset" end="sw.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="sw.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="jtag_uart_0.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="jtag_uart_0.reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="clock_crossing_low.m0_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="clock_crossing_low.m0_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="clock_crossing_low.s0_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="clock_crossing_low.s0_reset" />
 <connection
   kind="reset"
   version="11.0"
   start="clk_50.clk_reset"
   end="cpu_0.reset_n" />
 <connection
   kind="reset"
   version="11.0"
   start="cpu_0.jtag_debug_module_reset"
   end="cpu_0.reset_n" />
 <connection kind="clock" version="11.0" start="altpll_0.c0" end="c0.in_clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="c2.in_clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="can_0.clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="can_1.clk" />
 <connection kind="clock" version="11.0" start="altpll_0.c2" end="sw.clk" />
</system>
