MTL_SOPC |

2012.01.14.15:42:59 | Datasheet

Overview

clk_50 | MTL_SOPC
| key
| in_port
| out_port

Processor
cpu Nios II 10.1
All Components
altpll_0 altpll 10.1
jtag_uart altera_avalon_jtag_uart 10.1
alt_vip_vfr_0 alt_vip_vfr 10.1
multi_touch TERASIC_MULTI_TOUCH 1.0
tristate_bridge_ssram altera_avalon_tri_state_bridge 10.1
clock_crossing_io altera_avalon_clock_crossing 10.1
sysid altera_avalon_sysid 10.1
timer altera_avalon_timer 10.1
key altera_avalon_pio 10.1
led altera_avalon_pio 10.1
cpu altera_nios2 10.1
Memory Map

| alt_vip_vfr_0 | cpu
avalon_master | instruction_master | data_master
altpll_0 |  |  |
pll_slave |  |  | 0x00201100
jtag_uart |  |  |
avalon_jtag_slave |  |  | 0x00201110
alt_vip_vfr_0 |  |  |
avalon_slave |  |  | 0x00201000
multi_touch |  |  |
avalon_slave |  |  | 0x00201080
sysid |  |  |
control_slave |  |  | 0x01000040
timer |  |  |
s1 |  |  | 0x01000000
key |  |  |
s1 |  |  | 0x01000020
led |  |  |
s1 |  |  | 0x01000030
cpu |  |  |
jtag_debug_module |  | 0x00200800 | 0x00200800
ssram |  |  |
s1 | 0x00000000 | 0x00000000 | 0x00000000

## clk_50

clock_source v10.1

## Parameters

clockFrequency | 50000000
clockFrequencyKnown | true
inputClockFrequency | 0
resetSynchronousEdges | NONE
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## altpll_0

altpll v10.1

cpu | data_master | altpll_0
pll_slave
clk_50 | clk
inclk_interface
|  | c0 | cpu
|  | clk
|  | c0 | tristate_bridge_ssram
|  | clk
|  | c0 | jtag_uart
|  | clk
|  | c0 | alt_vip_vfr_0
|  | clock_reset
|  | c0
|  | clock_master
|  | c0 | alt_vip_itc_0
|  | is_clk_rst
|  | c2 | multi_touch
|  | clock
|  | c0 | clock_crossing_io
|  | clk_s1
|  | c0 | ssram
|  | clk

## Parameters

HIDDEN_CUSTOM_ELABORATION | altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT | altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY | Stratix IV
WIDTH_CLOCK | 10
WIDTH_PHASECOUNTERSELECT |
PRIMARY_CLOCK |
INCLK0_INPUT_FREQUENCY | 20000
INCLK1_INPUT_FREQUENCY |
OPERATION_MODE | NORMAL
PLL_TYPE | AUTO
QUALIFY_CONF_DONE |
COMPENSATE_CLOCK | CLK0
SCAN_CHAIN |
GATE_LOCK_SIGNAL |
GATE_LOCK_COUNTER |
LOCK_HIGH |
LOCK_LOW |
VALID_LOCK_MULTIPLIER |
INVALID_LOCK_MULTIPLIER |
SWITCH_OVER_ON_LOSSCLK |
SWITCH_OVER_ON_GATED_LOCK |
ENABLE_SWITCH_OVER_COUNTER |
SKIP_VCO |
SWITCH_OVER_COUNTER |
SWITCH_OVER_TYPE |
FEEDBACK_SOURCE |
BANDWIDTH |
BANDWIDTH_TYPE | AUTO
SPREAD_FREQUENCY |
DOWN_SPREAD |
SELF_RESET_ON_GATED_LOSS_LOCK |
SELF_RESET_ON_LOSS_LOCK |
CLK0_MULTIPLY_BY | 2
CLK1_MULTIPLY_BY | 2
CLK2_MULTIPLY_BY | 1
CLK3_MULTIPLY_BY |
CLK4_MULTIPLY_BY |
CLK5_MULTIPLY_BY |
CLK6_MULTIPLY_BY |
CLK7_MULTIPLY_BY |
CLK8_MULTIPLY_BY |
CLK9_MULTIPLY_BY |
EXTCLK0_MULTIPLY_BY |
EXTCLK1_MULTIPLY_BY |
EXTCLK2_MULTIPLY_BY |
EXTCLK3_MULTIPLY_BY |
CLK0_DIVIDE_BY | 1
CLK1_DIVIDE_BY | 1
CLK2_DIVIDE_BY | 1
CLK3_DIVIDE_BY |
CLK4_DIVIDE_BY |
CLK5_DIVIDE_BY |
CLK6_DIVIDE_BY |
CLK7_DIVIDE_BY |
CLK8_DIVIDE_BY |
CLK9_DIVIDE_BY |
EXTCLK0_DIVIDE_BY |
EXTCLK1_DIVIDE_BY |
EXTCLK2_DIVIDE_BY |
EXTCLK3_DIVIDE_BY |
CLK0_PHASE_SHIFT | 0
CLK1_PHASE_SHIFT | 0
CLK2_PHASE_SHIFT | 0
CLK3_PHASE_SHIFT |
CLK4_PHASE_SHIFT |
CLK5_PHASE_SHIFT |
CLK6_PHASE_SHIFT |
CLK7_PHASE_SHIFT |
CLK8_PHASE_SHIFT |
CLK9_PHASE_SHIFT |
EXTCLK0_PHASE_SHIFT |
EXTCLK1_PHASE_SHIFT |
EXTCLK2_PHASE_SHIFT |
EXTCLK3_PHASE_SHIFT |
CLK0_DUTY_CYCLE | 50
CLK1_DUTY_CYCLE | 50
CLK2_DUTY_CYCLE | 50
CLK3_DUTY_CYCLE |
CLK4_DUTY_CYCLE |
CLK5_DUTY_CYCLE |
CLK6_DUTY_CYCLE |
CLK7_DUTY_CYCLE |
CLK8_DUTY_CYCLE |
CLK9_DUTY_CYCLE |
EXTCLK0_DUTY_CYCLE |
EXTCLK1_DUTY_CYCLE |
EXTCLK2_DUTY_CYCLE |
EXTCLK3_DUTY_CYCLE |
PORT_clkena0 | PORT_UNUSED
PORT_clkena1 | PORT_UNUSED
PORT_clkena2 | PORT_UNUSED
PORT_clkena3 | PORT_UNUSED
PORT_clkena4 | PORT_UNUSED
PORT_clkena5 | PORT_UNUSED
PORT_extclkena0 |
PORT_extclkena1 |
PORT_extclkena2 |
PORT_extclkena3 |
PORT_extclk0 |
PORT_extclk1 |
PORT_extclk2 |
PORT_extclk3 |
PORT_CLKBAD0 | PORT_UNUSED
PORT_CLKBAD1 | PORT_UNUSED
PORT_clk0 | PORT_USED
PORT_clk1 | PORT_USED
PORT_clk2 | PORT_USED
PORT_clk3 | PORT_UNUSED
PORT_clk4 | PORT_UNUSED
PORT_clk5 | PORT_UNUSED
PORT_clk6 | PORT_UNUSED
PORT_clk7 | PORT_UNUSED
PORT_clk8 | PORT_UNUSED
PORT_clk9 | PORT_UNUSED
PORT_SCANDATA | PORT_UNUSED
PORT_SCANDATAOUT | PORT_UNUSED
PORT_SCANDONE | PORT_UNUSED
PORT_SCLKOUT1 |
PORT_SCLKOUT0 |
PORT_ACTIVECLOCK | PORT_UNUSED
PORT_CLKLOSS | PORT_UNUSED
PORT_INCLK1 | PORT_UNUSED
PORT_INCLK0 | PORT_USED
PORT_FBIN | PORT_UNUSED
PORT_PLLENA | PORT_UNUSED
PORT_CLKSWITCH | PORT_UNUSED
PORT_ARESET | PORT_USED
PORT_PFDENA | PORT_UNUSED
PORT_SCANCLK | PORT_UNUSED
PORT_SCANACLR | PORT_UNUSED
PORT_SCANREAD | PORT_UNUSED
PORT_SCANWRITE | PORT_UNUSED
PORT_ENABLE0 |
PORT_ENABLE1 |
PORT_LOCKED | PORT_USED
PORT_CONFIGUPDATE | PORT_UNUSED
PORT_FBOUT | PORT_UNUSED
PORT_PHASEDONE | PORT_UNUSED
PORT_PHASESTEP | PORT_UNUSED
PORT_PHASEUPDOWN | PORT_UNUSED
PORT_SCANCLKENA | PORT_UNUSED
PORT_PHASECOUNTERSELECT | PORT_UNUSED
PORT_VCOOVERRANGE |
PORT_VCOUNDERRANGE |
DPA_MULTIPLY_BY |
DPA_DIVIDE_BY |
DPA_DIVIDER |
VCO_MULTIPLY_BY |
VCO_DIVIDE_BY |
SCLKOUT0_PHASE_SHIFT |
SCLKOUT1_PHASE_SHIFT |
VCO_FREQUENCY_CONTROL |
VCO_PHASE_SHIFT_STEP |
USING_FBMIMICBIDIR_PORT | OFF
SCAN_CHAIN_MIF_FILE |
AVALON_USE_SEPARATE_SYSCLK | NO
HIDDEN_CONSTANTS | CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 1 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES | PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 0 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT2 0.00000000 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE2 50.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1313128064040112.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS | UP#locked used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC | IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS | MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS | IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0}
HIDDEN_IS_FIRST_EDIT | 0
AUTO_INCLK_INTERFACE_CLOCK_RATE | 50000000
AUTO_DEVICE_FAMILY | Stratix IV
deviceFamily | Stratix IV
generateLegacySim | false

## Software Assignments

(none)

## jtag_uart

altera_avalon_jtag_uart v10.1

cpu | data_master | jtag_uart
avalon_jtag_slave
d_irq
irq
altpll_0 | c0
clk

## Parameters

allowMultipleConnections | false
hubInstanceID | 0
readBufferDepth | 512
readIRQThreshold | 8
simInputCharacterStream |
simInteractiveOptions | INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer | false
useRegistersForWriteBuffer | false
useRelativePathForSimFile | false
writeBufferDepth | 512
writeIRQThreshold | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

WRITE_DEPTH | 512
READ_DEPTH | 512
WRITE_THRESHOLD | 8
READ_THRESHOLD | 8

## alt_vip_vfr_0

alt_vip_vfr v10.1

cpu | data_master | alt_vip_vfr_0
avalon_slave
d_irq
interrupt_sender
altpll_0 | c0
clock_reset
c0
clock_master
|  | avalon_streaming_source | alt_vip_itc_0
|  | din
|  | avalon_master | tristate_bridge_ssram
|  | avalon_slave

## Parameters

BITS_PER_PIXEL_PER_COLOR_PLANE | 8
NUMBER_OF_CHANNELS_IN_PARALLEL | 3
NUMBER_OF_CHANNELS_IN_SEQUENCE | 1
MAX_IMAGE_WIDTH | 800
MAX_IMAGE_HEIGHT | 480
MEM_PORT_WIDTH | 32
RMASTER_FIFO_DEPTH | 128
RMASTER_BURST_TARGET | 32
CLOCKS_ARE_SEPARATE | 0
AUTO_CLOCK_RESET_CLOCK_RATE | 100000000
AUTO_CLOCK_MASTER_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## alt_vip_itc_0

alt_vip_itc v10.1

alt_vip_vfr_0 | avalon_streaming_source | alt_vip_itc_0
din
altpll_0 | c0
is_clk_rst

## Parameters

NUMBER_OF_COLOUR_PLANES | 3
COLOUR_PLANES_ARE_IN_PARALLEL | 1
BPS | 8
INTERLACED | 0
H_ACTIVE_PIXELS | 800
V_ACTIVE_LINES | 480
ACCEPT_COLOURS_IN_SEQ | 0
FIFO_DEPTH | 800
CLOCKS_ARE_SAME | 0
USE_CONTROL | 0
NO_OF_MODES | 1
THRESHOLD | 799
STD_WIDTH | 1
GENERATE_SYNC | 0
USE_EMBEDDED_SYNCS | 0
AP_LINE | 0
V_BLANK | 0
H_BLANK | 0
H_SYNC_LENGTH | 30
H_FRONT_PORCH | 210
H_BACK_PORCH | 16
V_SYNC_LENGTH | 13
V_FRONT_PORCH | 22
V_BACK_PORCH | 10
F_RISING_EDGE | 0
F_FALLING_EDGE | 0
FIELD0_V_RISING_EDGE | 0
FIELD0_V_BLANK | 0
FIELD0_V_SYNC_LENGTH | 0
FIELD0_V_FRONT_PORCH | 0
FIELD0_V_BACK_PORCH | 0
ANC_LINE | 0
FIELD0_ANC_LINE | 0
AUTO_IS_CLK_RST_CLOCK_RATE | 100000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## multi_touch

TERASIC_MULTI_TOUCH v1.0

cpu | data_master | multi_touch
avalon_slave
d_irq
interrupt_sender
altpll_0 | c2
clock

## Parameters

AUTO_CLOCK_CLOCK_RATE | 50000000
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## tristate_bridge_ssram

altera_avalon_tri_state_bridge v10.1

cpu | instruction_master | tristate_bridge_ssram
avalon_slave
data_master
avalon_slave
alt_vip_vfr_0 | avalon_master
avalon_slave
altpll_0 | c0
clk
|  | tristate_master | ssram
|  | s1

## Parameters

registerIncomingSignals | true
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## clock_crossing_io

altera_avalon_clock_crossing v10.1

clk_50 | clk | clock_crossing_io
clk_m1
cpu | data_master
s1
altpll_0 | c0
clk_s1
|  | m1 | sysid
|  | control_slave
|  | m1 | timer
|  | s1
|  | m1 | key
|  | s1
|  | m1 | led
|  | s1

## Parameters

dataWidth | 32
downstreamFIFODepth | 32
downstreamUseRegister | false
masterSyncDepth | 3
maxBurstSize | 8
slaveAddressWidth | 5
slaveSyncDepth | 3
upstreamFIFODepth | 256
upstreamUseRegister | false
useBurstCount | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

(none)

## sysid

altera_avalon_sysid v10.1

clk_50 | clk | sysid
clk
clock_crossing_io | m1
control_slave

## Parameters

id | 0
timestamp | 1326526829
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ID | 0u
TIMESTAMP | 1326526829u

## timer

altera_avalon_timer v10.1

clk_50 | clk | timer
clk
clock_crossing_io | m1
s1
cpu | d_irq
irq

## Parameters

alwaysRun | false
counterSize | 32
fixedPeriod | false
period | 1
periodUnits | MSEC
resetOutput | false
snapshot | true
systemFrequency | 50000000
timeoutPulseOutput | false
timerPreset | CUSTOM
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

ALWAYS_RUN | 0
FIXED_PERIOD | 0
SNAPSHOT | 1
PERIOD | 1
PERIOD_UNITS | "ms"
RESET_OUTPUT | 0
TIMEOUT_PULSE_OUTPUT | 0
FREQ | 50000000u
LOAD_VALUE | 49999ULL
COUNTER_SIZE | 32
MULT | 0.0010
TICKS_PER_SEC | 1000u

## key

altera_avalon_pio v10.1

clk_50 | clk | key
clk
clock_crossing_io | m1
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 4
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## led

altera_avalon_pio v10.1

clk_50 | clk | led
clk
clock_crossing_io | m1
s1

## Parameters

bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 50000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 4
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 4
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 50000000u

## cpu

altera_nios2 v10.1

altpll_0 | c0 | cpu
clk
|  | instruction_master | tristate_bridge_ssram
|  | avalon_slave
|  | data_master
|  | avalon_slave
|  | data_master | altpll_0
|  | pll_slave
|  | data_master | jtag_uart
|  | avalon_jtag_slave
|  | d_irq
|  | irq
|  | data_master | alt_vip_vfr_0
|  | avalon_slave
|  | d_irq
|  | interrupt_sender
|  | data_master | multi_touch
|  | avalon_slave
|  | d_irq
|  | interrupt_sender
|  | data_master | clock_crossing_io
|  | s1
|  | d_irq | timer
|  | irq

## Parameters

userDefinedSettings |
tightlyCoupledInstructionMaster3MapParam |
tightlyCoupledInstructionMaster3AddrWidth | 1
tightlyCoupledInstructionMaster2MapParam |
tightlyCoupledInstructionMaster2AddrWidth | 1
tightlyCoupledInstructionMaster1MapParam |
tightlyCoupledInstructionMaster1AddrWidth | 1
tightlyCoupledInstructionMaster0MapParam |
tightlyCoupledInstructionMaster0AddrWidth | 1
tightlyCoupledDataMaster3MapParam |
tightlyCoupledDataMaster3AddrWidth | 1
tightlyCoupledDataMaster2MapParam |
tightlyCoupledDataMaster2AddrWidth | 1
tightlyCoupledDataMaster1MapParam |
tightlyCoupledDataMaster1AddrWidth | 1
tightlyCoupledDataMaster0MapParam |
tightlyCoupledDataMaster0AddrWidth | 1
setting_showUnpublishedSettings | false
setting_showInternalSettings | false
setting_shadowRegisterSets | 0
setting_preciseSlaveAccessErrorException | false
setting_preciseIllegalMemAccessException | false
setting_preciseDivisionErrorException | false
setting_performanceCounter | false
setting_perfCounterWidth | _32
setting_interruptControllerType | Internal
setting_illegalMemAccessDetection | false
setting_illegalInstructionsTrap | false
setting_fullWaveformSignals | false
setting_extraExceptionInfo | false
setting_exportPCB | false
setting_debugSimGen | false
setting_clearXBitsLDNonBypass | true
setting_branchPredictionType | Automatic
setting_bit31BypassDCache | true
setting_bigEndian | false
setting_bhtPtrSz | _8
setting_bhtIndexPcOnly | false
setting_avalonDebugPortPresent | false
setting_alwaysEncrypt | true
setting_allowFullAddressRange | false
setting_activateTrace | true
setting_activateTestEndChecker | false
setting_activateMonitors | true
setting_activateModelChecker | false
setting_HDLSimCachesCleared | true
setting_HBreakTest | false
resetSlave | ssram.s1
resetOffset | 0
muldiv_multiplierType | DSPBlock
muldiv_divider | false
mpu_useLimit | false
mpu_numOfInstRegion | 8
mpu_numOfDataRegion | 8
mpu_minInstRegionSize | _12
mpu_minDataRegionSize | _12
mpu_enabled | false
mmu_uitlbNumEntries | _4
mmu_udtlbNumEntries | _6
mmu_tlbPtrSz | _7
mmu_tlbNumWays | _16
mmu_processIDNumBits | _8
mmu_enabled | false
mmu_autoAssignTlbPtrSz | true
mmu_TLBMissExcSlave |
mmu_TLBMissExcOffset | 0
manuallyAssignCpuID | false
internalIrqMaskSystemInfo | 15
instSlaveMapParam | <address-map><slave name='ssram.s1' start='0x0' end='0x200000' /><slave name='cpu.jtag_debug_module' start='0x200800' end='0x201000' /></address-map>
instAddrWidth | 22
impl | Fast
icache_size | _4096
icache_ramBlockType | Automatic
icache_numTCIM | _0
icache_burstType | None
exceptionSlave | ssram.s1
exceptionOffset | 32
deviceFeaturesSystemInfo | M512_MEMORY 0 M4K_MEMORY 0 M9K_MEMORY 1 M20K_MEMORY 0 M144K_MEMORY 1 MRAM_MEMORY 0 MLAB_MEMORY 1 ESB 0 EPCS 1 DSP 1 EMUL 0 HARDCOPY 0 LVDS_IO 1 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 DSP_SHIFTER_BLOCK 1
deviceFamilyName | Stratix IV
debug_triggerArming | true
debug_level | Level1
debug_jtagInstanceID | 0
debug_embeddedPLL | true
debug_debugReqSignals | false
debug_assignJtagInstanceID | false
debug_OCIOnchipTrace | _128
dcache_size | _2048
dcache_ramBlockType | Automatic
dcache_omitDataMaster | false
dcache_numTCDM | _0
dcache_lineSize | _32
dcache_bursts | false
dataSlaveMapParam | <address-map><slave name='ssram.s1' start='0x0' end='0x200000' /><slave name='cpu.jtag_debug_module' start='0x200800' end='0x201000' /><slave name='alt_vip_vfr_0.avalon_slave' start='0x201000' end='0x201080' /><slave name='multi_touch.avalon_slave' start='0x201080' end='0x201100' /><slave name='altpll_0.pll_slave' start='0x201100' end='0x201110' /><slave name='jtag_uart.avalon_jtag_slave' start='0x201110' end='0x201118' /><slave name='timer.s1' start='0x1000000' end='0x1000020' /><slave name='key.s1' start='0x1000020' end='0x1000030' /><slave name='led.s1' start='0x1000030' end='0x1000040' /><slave name='sysid.control_slave' start='0x1000040' end='0x1000048' /></address-map>
dataAddrWidth | 25
customInstSlavesSystemInfo | <info/>
cpuReset | false
cpuID | 0
clockFrequency | 100000000
breakSlave | cpu.jtag_debug_module
breakOffset | 32
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

CPU_IMPLEMENTATION | "fast"
BIG_ENDIAN | 0
CPU_FREQ | 100000000u
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 2048
INITDA_SUPPORTED |
FLUSHDA_SUPPORTED |
HAS_JMPI_INSTRUCTION |
EXCEPTION_ADDR | 0x20
RESET_ADDR | 0x0
BREAK_ADDR | 0x200820
HAS_DEBUG_STUB |
HAS_DEBUG_CORE | 1
CPU_ID_SIZE | 1
CPU_ID_VALUE | 0x0
HARDWARE_DIVIDE_PRESENT | 0
HARDWARE_MULTIPLY_PRESENT | 1
HARDWARE_MULX_PRESENT | 1
INST_ADDR_WIDTH | 22
DATA_ADDR_WIDTH | 25
NUM_OF_SHADOW_REG_SETS | 0

## ssram

altera_avalon_cy7c1380_ssram v10.1

tristate_bridge_ssram | tristate_master | ssram
s1
altpll_0 | c0
clk

## Parameters

readLatency | 2
sharedPorts | s1/address,s1/bwe_n,s1/data,s1/outputenable_n
simMakeModel | true
size | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments

SRAM_MEMORY_SIZE | 2
SRAM_MEMORY_UNITS | 1048576
SSRAM_DATA_WIDTH | 32
SSRAM_READ_LATENCY | 2

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