
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module TR4_MTL_Painter(

	//////////// CLOCK //////////
	OSC_50_BANK1,
	OSC_50_BANK3,
	OSC_50_BANK4,
	OSC_50_BANK7,
	OSC_50_BANK8,

	//////////// Loop //////////
	LOOP_CLKIN0,
	LOOP_CLKIN1,
	LOOP_CLKOUT0,
	LOOP_CLKOUT1,

	//////////// LED x 4 //////////
	LED,

	//////////// BUTTON x 4 //////////
	BUTTON,

	//////////// SWITCH x 4 //////////
	SW,

	//////////// Flash and SRAM Address/Data/OE/WM Share Bus //////////
	FSM_A,
	FSM_D,
	FSM_OE_n,
	FSM_WE_n,

	//////////// SSRAM Control //////////
	SSRAM_ADSC_n,
	SSRAM_ADSP_n,
	SSRAM_ADV_n,
	SSRAM_BE_n,
	SSRAM_CE1_n,
	SSRAM_CLK,

	//////////// GPIO_1, GPIO_1 connect to MTL - Multi-Touch LCD Panel //////////
	MTL_B,
	MTL_DCLK,
	MTL_G,
	MTL_HSD,
	MTL_R,
	MTL_TOUCH_I2C_SCL,
	MTL_TOUCH_I2C_SDA,
	MTL_TOUCH_INT_n,
	MTL_VSD 
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input 		          		OSC_50_BANK1;
input 		          		OSC_50_BANK3;
input 		          		OSC_50_BANK4;
input 		          		OSC_50_BANK7;
input 		          		OSC_50_BANK8;

//////////// Loop //////////
input 		          		LOOP_CLKIN0;
input 		          		LOOP_CLKIN1;
output		          		LOOP_CLKOUT0;
output		          		LOOP_CLKOUT1;

//////////// LED x 4 //////////
output		     [3:0]		LED;

//////////// BUTTON x 4 //////////
input 		     [3:0]		BUTTON;

//////////// SWITCH x 4 //////////
input 		     [3:0]		SW;

//////////// Flash and SRAM Address/Data/OE/WM Share Bus //////////
output		    [20:1]		FSM_A;
inout 		    [31:0]		FSM_D;
output		          		FSM_OE_n;
output		          		FSM_WE_n;

//////////// SSRAM Control //////////
output		          		SSRAM_ADSC_n;
output		          		SSRAM_ADSP_n;
output		          		SSRAM_ADV_n;
output		     [3:0]		SSRAM_BE_n;
output		          		SSRAM_CE1_n;
output		          		SSRAM_CLK;

//////////// GPIO_1, GPIO_1 connect to MTL - Multi-Touch LCD Panel //////////
output		     [7:0]		MTL_B;
output		          		MTL_DCLK;
output		     [7:0]		MTL_G;
output		          		MTL_HSD;
output		     [7:0]		MTL_R;
output		          		MTL_TOUCH_I2C_SCL;
inout 		          		MTL_TOUCH_I2C_SDA;
input 		          		MTL_TOUCH_INT_n;
output		          		MTL_VSD;


//=======================================================
//  REG/WIRE declarations
//=======================================================
wire reset_n;
wire video_hs;
wire video_vs;
wire video_clk;
wire [7:0]	video_r;
wire [7:0]	video_g;
wire [7:0]	video_b;

wire dummy_a0;
//=======================================================
//  Structural coding
//=======================================================
// MTL - display
assign {MTL_R,MTL_G,MTL_B} = {video_r, video_g, video_b};
assign MTL_DCLK = video_clk;
assign MTL_HSD = ~video_hs;
assign MTL_VSD = ~video_vs;	

assign FAN_CTRL = 1'b1;
assign FLASH_CE_n = 1'b1;
assign FLASH_RESET_n = 1'b1;

assign SSRAM_ADSP_n = 1'b1;
assign SSRAM_ADV_n  = 1'b1;

vga_pll	vga_pll_inst (
	.areset ( 1'b0 ),
	.inclk0 ( OSC_50_BANK7 ),
	.c0 ( video_clk ),
	.locked ( reset_n )
	);
	
  MTL_SOPC MTL_SOPC_inst
    (
		.clk_50                                    (OSC_50_BANK8),
		
		.altpll_ssram                              (SSRAM_CLK),
      .altpll_sys                                (),
      .altpll_touch                              (),
		.locked_from_the_altpll_0                  (),
		.phasedone_from_the_altpll_0               (),
		
		//touch
      .TOUCH_I2C_SCL_from_the_multi_touch        (MTL_TOUCH_I2C_SCL),
      .TOUCH_I2C_SDA_to_and_from_the_multi_touch (MTL_TOUCH_I2C_SDA),
      .TOUCH_INT_n_to_the_multi_touch            (MTL_TOUCH_INT_n),
		
      .in_port_to_the_key                        (BUTTON),
      .out_port_from_the_led                     (LED),
      
      .reset_n                                   (reset_n),
		
		.adsc_n_to_the_ssram                 		 (SSRAM_ADSC_n),
      .bw_n_to_the_ssram                   		 (SSRAM_BE_n),
      .chipenable1_n_to_the_ssram                (SSRAM_CE1_n),
      .reset_n_to_the_ssram                      (1'b1),
      .tristate_bridge_ssram_address             ({FSM_A,dummy_a0}),
      .tristate_bridge_ssram_data                (FSM_D),
      .tristate_bridge_ssram_outputenablen       (FSM_OE_n),
      .tristate_bridge_ssram_writen              (FSM_WE_n),
		
	  //vip
      .underflow_from_the_alt_vip_itc_0          (),
      .vid_clk_to_the_alt_vip_itc_0              (video_clk),
      .vid_data_from_the_alt_vip_itc_0           ({video_r, video_g, video_b}),
      .vid_datavalid_from_the_alt_vip_itc_0      (),
      .vid_f_from_the_alt_vip_itc_0              (),
      .vid_h_from_the_alt_vip_itc_0              (),
      .vid_h_sync_from_the_alt_vip_itc_0         (video_hs),
      .vid_v_from_the_alt_vip_itc_0              (),
      .vid_v_sync_from_the_alt_vip_itc_0         (video_vs)
    );


endmodule
