# TCL File Generated by Component Editor 7.2sp1 on:
# Thu Mar 06 15:00:27 MYT 2008
# DO NOT MODIFY

set_module_property NAME maxII_interface
set_module_property VERSION 9.1
set_module_property GROUP ""
set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
set_module_property EDITABLE false
set_module_property SIMULATION_MODEL_IN_VERILOG false
set_module_property SIMULATION_MODEL_IN_VHDL false
set_module_property SIMULATION_MODEL_HAS_TULIPS false
set_module_property SIMULATION_MODEL_IS_OBFUSCATED false

# Interface clock_sink, 
add_interface clock_sink clock sink asynchronous 
# Ports in interface clock_sink, no port declaration needed
# add_port_to_interface clock_sink reset_n reset_n 
# add_port_to_interface clock_sink clock clk 
# Ports directions and widths in interface clock_sink
# set_port_direction_and_width reset_n input 1
# set_port_direction_and_width clock input 1

# Interface s1
add_interface s1 avalon_tristate slave clock_sink 
set_interface_property s1 isNonVolatileStorage false 
set_interface_property s1 readLatency 0 
set_interface_property s1 readWaitStates 100 
set_interface_property s1 holdTime 0 
set_interface_property s1 printableDevice false 
set_interface_property s1 readWaitTime 100 
set_interface_property s1 setupTime 0 
set_interface_property s1 writeWaitTime 100 
set_interface_property s1 timingUnits Nanoseconds 
set_interface_property s1 minimumUninterruptedRunLength 1 
set_interface_property s1 activeCSThroughReadLatency false 
set_interface_property s1 isMemoryDevice false 
set_interface_property s1 writeWaitStates 100 
set_interface_property s1 maximumPendingReadTransactions 0 
# Ports in interface s1
add_interface_port s1 we_n write_n input 1
add_interface_port s1 cs_n chipselect_n input 1
add_interface_port s1 oe_n read_n input 1
add_interface_port s1 address address input 1
add_interface_port s1 data data input 1
#Ports directions and widths in interface s1
set_port_property we_n width 1 
set_port_property we_n direction input
set_port_property cs_n width 1
set_port_property cs_n direction input
set_port_property oe_n width 1
set_port_property oe_n direction input
set_port_property address width 3
set_port_property address direction input
set_port_property data width 32
set_port_property data direction bidir
