# TCL File Generated by Component Editor 9.1sp2
# Thu May 20 17:46:55 CST 2010
# DO NOT MODIFY


# +-----------------------------------
# | 
# | TERASIC_TRISTATE_SSRAM "TERASIC_TRISTATE_SSRAM" v1.0
# | null 2010.05.20.17:46:55
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 9.1
# | 
package require -exact sopc 9.1
# | 
# +-----------------------------------

# +-----------------------------------
# | module TERASIC_TRISTATE_SSRAM
# | 
set_module_property NAME TERASIC_TRISTATE_SSRAM
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP "Terasic Technologies Inc."
set_module_property DISPLAY_NAME TERASIC_TRISTATE_SSRAM
set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
set_module_property EDITABLE false
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
add_parameter DATA_WIDTH INTEGER 16
set_parameter_property DATA_WIDTH DEFAULT_VALUE 16
set_parameter_property DATA_WIDTH DISPLAY_NAME DATA_WIDTH
set_parameter_property DATA_WIDTH UNITS None
set_parameter_property DATA_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property DATA_WIDTH DISPLAY_HINT ""
set_parameter_property DATA_WIDTH AFFECTS_GENERATION false
set_parameter_property DATA_WIDTH HDL_PARAMETER true
add_parameter ADDR_WIDTH INTEGER 20
set_parameter_property ADDR_WIDTH DEFAULT_VALUE 20
set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
set_parameter_property ADDR_WIDTH UNITS None
set_parameter_property ADDR_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property ADDR_WIDTH DISPLAY_HINT ""
set_parameter_property ADDR_WIDTH AFFECTS_GENERATION false
set_parameter_property ADDR_WIDTH HDL_PARAMETER true
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock
# | 
add_interface clock clock end

set_interface_property clock ENABLED true

add_interface_port clock clk clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point slave
# | 
add_interface slave avalon_tristate end
set_interface_property slave activeCSThroughReadLatency true
set_interface_property slave explicitAddressSpan 0
set_interface_property slave holdTime 2
set_interface_property slave isMemoryDevice true
set_interface_property slave isNonVolatileStorage false
set_interface_property slave maximumPendingReadTransactions 0
set_interface_property slave printableDevice false
set_interface_property slave readLatency 2
set_interface_property slave readWaitStates 0
set_interface_property slave readWaitTime 0
set_interface_property slave setupTime 1
set_interface_property slave timingUnits Cycles
set_interface_property slave writeWaitTime 0

set_interface_property slave ASSOCIATED_CLOCK clock
set_interface_property slave ENABLED true

add_interface_port slave ssram_cen chipselect_n Input 1
add_interface_port slave ssram_wen write_n Input 1
add_interface_port slave ssram_oen outputenable_n Input 1
add_interface_port slave ssram_bwn byteenable_n Input DATA_WIDTH/8
add_interface_port slave ssram_data data Bidir DATA_WIDTH
add_interface_port slave ssram_address address Input ADDR_WIDTH
# | 
# +-----------------------------------
