SYSTEM MTL_SOPC
{
   # 
   # Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
   # Date: 2012.01.14.15:43:53
   # 
   #    clock_source "clk_50"
   #    altpll "altpll_0"
   #    altera_avalon_jtag_uart "jtag_uart"
   #    alt_vip_vfr "alt_vip_vfr_0"
   #    alt_vip_itc "alt_vip_itc_0"
   #    TERASIC_MULTI_TOUCH "multi_touch"
   #    altera_avalon_tri_state_bridge "tristate_bridge_ssram"
   #    altera_avalon_clock_crossing "clock_crossing_io"
   #    altera_avalon_sysid "sysid"
   #    altera_avalon_timer "timer"
   #    altera_avalon_pio "key"
   #    altera_avalon_pio "led"
   #    altera_nios2 "cpu"
   #    altera_avalon_cy7c1380_ssram "ssram"
   # 
   #    Contains 35 connections.
   # 
   System_Wizard_Version = "8.0";
   Builder_Application = "sopc_builder_ca";
   #. values for Builder_Application are:
   #.    sopc_builder_preview --> 6.1p, 7.0p prerelease versions
   #.    sopc_builder_ca      --> 7.1 and later
   #.    (missing) --> 6.0 or earlier
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_language = "verilog";
      device_family = "STRATIXIV";
      device_family_id = "STRATIXIV";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      CLOCKS 
      {
         CLOCK clk_50
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "clk_50";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "clk_50.clk";
         }
         CLOCK altpll_0_c0
         {
            frequency = "100000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from altpll_0";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "altpll_0.c0";
         }
         CLOCK altpll_sys
         {
            frequency = "100000000";
            source = "altpll_0_c0";
            Is_Clock_Source = "0";
            display_name = "altpll_sys";
         }
         CLOCK altpll_0_c1
         {
            frequency = "100000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c1 from altpll_0";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "altpll_0.c1";
         }
         CLOCK altpll_ssram
         {
            frequency = "100000000";
            source = "altpll_0_c1";
            Is_Clock_Source = "0";
            display_name = "altpll_ssram";
         }
         CLOCK altpll_0_c2
         {
            frequency = "50000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c2 from altpll_0";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "altpll_0.c2";
         }
         CLOCK altpll_touch
         {
            frequency = "50000000";
            source = "altpll_0_c2";
            Is_Clock_Source = "0";
            display_name = "altpll_touch";
         }
      }
   }
   MODULE altpll_0
   {
      SLAVE pll_slave
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "0cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "16";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00201100";
            }
            Clock_Source = "clk_50";
            Has_Clock = "1";
            Base_Address = "0x00201100";
         }
      }
      PORT_WIRING 
      {
         PORT c0
         {
            type = "out_clk";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT c1
         {
            type = "out_clk";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT c2
         {
            type = "out_clk";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT phasedone
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT locked
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "no_legacy_module";
      class_version = "10.1";
      gtf_class_name = "altpll";
      gtf_class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "E:\\yq_share\\TR4_MTL_Painter/altpll_0.vo";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE jtag_uart
   {
      SLAVE avalon_jtag_slave
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT rst_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_read_n
            {
               type = "read_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT av_write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT av_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dataavailable
            {
               type = "dataavailable";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "1";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            JTAG_Hub_Base_Id = "262254";
            JTAG_Hub_Instance_Id = "0";
            Connection_Limit = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00201110";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "0";
            }
            Base_Address = "0x00201110";
         }
      }
      class = "altera_avalon_jtag_uart";
      class_version = "10.1";
      iss_model_name = "altera_avalon_jtag_uart";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         write_depth = "512";
         read_depth = "512";
         write_threshold = "8";
         read_threshold = "8";
         read_char_stream = "";
         showascii = "1";
         relativepath = "1";
         read_le = "0";
         write_le = "0";
         altera_show_unreleased_jtag_uart_features = "0";
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL av_chipselect
            {
               name = "av_chipselect";
            }
            SIGNAL av_address
            {
               name = "av_address";
            }
            SIGNAL av_read_n
            {
               name = "av_read_n";
            }
            SIGNAL av_readdata
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL av_write_n
            {
               name = "av_write_n";
            }
            SIGNAL av_writedata
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL av_waitrequest
            {
               name = "av_waitrequest";
            }
            SIGNAL dataavailable
            {
               name = "dataavailable";
            }
            SIGNAL readyfordata
            {
               name = "readyfordata";
            }
         }
         INTERACTIVE_IN drive
         {
            enable = "0";
            file = "_input_data_stream.dat";
            mutex = "_input_data_mutex.dat";
            log = "_in.log";
            rate = "100";
            signals = "temp,list";
            exe = "nios2-terminal";
         }
         INTERACTIVE_OUT log
         {
            enable = "1";
            exe = "perl -- atail-f.pl";
            file = "_output_stream.dat";
            radix = "ascii";
            signals = "temp,list";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "altpll_sys";
         Has_Clock = "1";
      }
   }
   MODULE alt_vip_vfr_0
   {
      SLAVE avalon_slave
      {
         PORT_WIRING 
         {
            PORT clock
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT slave_address
            {
               type = "address";
               width = "5";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "0cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "1";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "5";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00201000";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "1";
            }
            Clock_Source = "altpll_sys";
            Has_Clock = "1";
            Base_Address = "0x00201000";
         }
      }
      MASTER avalon_master
      {
         PORT_WIRING 
         {
            PORT master_clock
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_reset
            {
               type = "reset";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_address
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_burstcount
            {
               type = "burstcount";
               width = "6";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "32";
            Maximum_Burst_Size = "32";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Clock_Source = "altpll_sys";
            Has_Clock = "1";
         }
         MEMORY_MAP 
         {
            Entry ssram/s1
            {
               address = "0x00000000";
               span = "0x00200000";
               is_bridge = "0";
            }
         }
      }
      MASTER avalon_streaming_source
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Clock_Source = "altpll_sys";
            Has_Clock = "1";
         }
         PORT_WIRING 
         {
            PORT dout_data
            {
               type = "data";
               width = "24";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dout_valid
            {
               type = "valid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dout_ready
            {
               type = "ready";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dout_startofpacket
            {
               type = "startofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dout_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
      }
      class = "no_legacy_module";
      class_version = "10.1";
      gtf_class_name = "alt_vip_vfr";
      gtf_class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "E:\\yq_share\\TR4_MTL_Painter/alt_vip_vfr_0.vo";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE alt_vip_itc_0
   {
      SLAVE din
      {
         PORT_WIRING 
         {
            PORT is_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT rst
            {
               type = "reset";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT is_data
            {
               type = "data";
               width = "24";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT is_valid
            {
               type = "valid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT is_ready
            {
               type = "ready";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT is_sop
            {
               type = "startofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT is_eop
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "atlantic";
            Accepts_Internal_Connections = "1";
            MASTERED_BY alt_vip_vfr_0/avalon_streaming_source
            {
               priority = "0";
            }
         }
      }
      PORT_WIRING 
      {
         PORT vid_clk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT vid_data
         {
            type = "export";
            width = "24";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT underflow
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT vid_datavalid
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT vid_v_sync
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT vid_h_sync
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT vid_f
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT vid_h
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT vid_v
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "no_legacy_module";
      class_version = "10.1";
      gtf_class_name = "alt_vip_itc";
      gtf_class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "altpll_sys";
         Has_Clock = "1";
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "E:\\yq_share\\TR4_MTL_Painter/alt_vip_itc_0.vo";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE multi_touch
   {
      SLAVE avalon_slave
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq_n
            {
               type = "irq_n";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT s_cs
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s_address
            {
               type = "address";
               width = "5";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s_readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT s_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT s_writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "5";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00201080";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "2";
            }
            Base_Address = "0x00201080";
         }
      }
      PORT_WIRING 
      {
         PORT TOUCH_I2C_SDA
         {
            type = "export";
            width = "1";
            direction = "inout";
            Is_Enabled = "1";
         }
         PORT TOUCH_I2C_SCL
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT TOUCH_INT_n
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
      }
      class = "no_legacy_module";
      class_version = "1.0";
      gtf_class_name = "TERASIC_MULTI_TOUCH";
      gtf_class_version = "1.0";
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "0";
         Is_Enabled = "1";
         Clock_Source = "altpll_touch";
         Has_Clock = "1";
      }
      HDL_INFO 
      {
         Simulation_HDL_Files = "E:/yq_share/TR4_MTL_Painter/ip/TERASIC_MULTI_TOUCH/TERASIC_MULTI_TOUCH.v,E:/yq_share/TR4_MTL_Painter/ip/TERASIC_MULTI_TOUCH/i2c_touch_config.v,E:/yq_share/TR4_MTL_Painter/ip/TERASIC_MULTI_TOUCH/i2c_touch_controller.v,E:/yq_share/TR4_MTL_Painter/ip/TERASIC_MULTI_TOUCH/touch_fifo.v,E:/yq_share/TR4_MTL_Painter/multi_touch.v";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
   }
   MODULE tristate_bridge_ssram
   {
      SLAVE avalon_slave
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "1";
            Register_Outgoing_Signals = "1";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "N/A";
               Base_Address = "N/A";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "N/A";
               Base_Address = "N/A";
            }
            MASTERED_BY alt_vip_vfr_0/avalon_master
            {
               priority = "4";
               Offset_Address = "N/A";
               Base_Address = "N/A";
            }
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
         }
         MEMORY_MAP 
         {
            Entry ssram/s1
            {
               address = "0x00000000";
               span = "0x00200000";
               is_bridge = "0";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      class = "altera_avalon_tri_state_bridge";
      class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "altpll_sys";
         Has_Clock = "1";
      }
   }
   MODULE clock_crossing_io
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT slave_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_address
            {
               type = "address";
               width = "5";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_nativeaddress
            {
               type = "nativeaddress";
               width = "5";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_read
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT slave_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT slave_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT slave_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT slave_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "128";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "64";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "5";
            Opaque_Bridges_To = "m1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x01000000";
            }
            Clock_Source = "altpll_sys";
            Has_Clock = "1";
            Base_Address = "0x01000000";
         }
      }
      MASTER m1
      {
         PORT_WIRING 
         {
            PORT master_clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_address
            {
               type = "address";
               width = "7";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_nativeaddress
            {
               type = "nativeaddress";
               width = "5";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT master_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT master_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "7";
            Opaque_Bridges_To = "s1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Clock_Source = "clk_50";
            Has_Clock = "1";
         }
         MEMORY_MAP 
         {
            Entry sysid/control_slave
            {
               address = "0x00000040";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry timer/s1
            {
               address = "0x00000000";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry key/s1
            {
               address = "0x00000020";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry led/s1
            {
               address = "0x00000030";
               span = "0x00000010";
               is_bridge = "0";
            }
         }
      }
      class = "altera_avalon_clock_crossing";
      class_version = "10.1";
      iss_model_name = "altera_avalon_clock_crossing";
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Upstream_FIFO_Depth = "256";
         Downstream_FIFO_Depth = "32";
         Data_Width = "32";
         Native_Address_Width = "5";
         Use_Byte_Enable = "1";
         Use_Burst_Count = "0";
         Maximum_Burst_Size = "8";
         Upstream_Use_Register = "0";
         Downstream_Use_Register = "0";
         Slave_Synchronizer_Depth = "3";
         Master_Synchronizer_Depth = "3";
         Device_Family = "STRATIXIV";
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Has_Clock = "0";
         Is_Bridge = "1";
      }
   }
   MODULE sysid
   {
      SLAVE control_slave
      {
         PORT_WIRING 
         {
            PORT clock
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "1";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY clock_crossing_io/m1
            {
               priority = "1";
               Offset_Address = "0x00000040";
            }
            Base_Address = "0x01000040";
         }
      }
      class = "altera_avalon_sysid";
      class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Date_Modified = "";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Fixed_Module_Name = "sysid";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk_50";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         id = "0";
         timestamp = "1326526829";
         regenerate_values = "0";
      }
   }
   MODULE timer
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "16";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "16";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "16";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY clock_crossing_io/m1
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            IRQ_MASTER cpu/data_master
            {
               IRQ_Number = "3";
            }
            Base_Address = "0x01000000";
         }
      }
      class = "altera_avalon_timer";
      class_version = "10.1";
      iss_model_name = "altera_avalon_timer";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            Settings_Summary = "Timer with 1 ms timeout period.";
            Is_Collapsed = "1";
         }
         Clock_Source = "clk_50";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         always_run = "0";
         fixed_period = "0";
         snapshot = "1";
         period = "1";
         period_units = "ms";
         reset_output = "0";
         timeout_pulse_output = "0";
         load_value = "49999";
         counter_size = "32";
         mult = "0.0010";
         ticks_per_sec = "1000";
      }
   }
   MODULE key
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "4";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY clock_crossing_io/m1
            {
               priority = "1";
               Offset_Address = "0x00000020";
            }
            Base_Address = "0x01000020";
         }
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            type = "export";
            width = "4";
            direction = "input";
            Is_Enabled = "1";
         }
      }
      class = "altera_avalon_pio";
      class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk_50";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "0";
         has_in = "1";
         capture = "0";
         Data_Width = "4";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
   }
   MODULE led
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "4";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY clock_crossing_io/m1
            {
               priority = "1";
               Offset_Address = "0x00000030";
            }
            Base_Address = "0x01000030";
         }
      }
      PORT_WIRING 
      {
         PORT out_port
         {
            type = "export";
            width = "4";
            direction = "output";
            Is_Enabled = "1";
         }
      }
      class = "altera_avalon_pio";
      class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk_50";
         Has_Clock = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         Data_Width = "4";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
   }
   MODULE cpu
   {
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_address
            {
               type = "address";
               width = "22";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_resetrequest
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "22";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Instruction_Master = "1";
         }
         MEMORY_MAP 
         {
            Entry cpu/jtag_debug_module
            {
               address = "0x00200800";
               span = "0x00000800";
               is_bridge = "0";
            }
            Entry ssram/s1
            {
               address = "0x00000000";
               span = "0x00200000";
               is_bridge = "0";
            }
         }
      }
      MASTER custom_instruction_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Is_Custom_Instruction = "1";
            Is_Enabled = "0";
            Max_Address_Width = "8";
         }
         PORT_WIRING 
         {
            PORT dataa
            {
               type = "dataa";
               width = "32";
               direction = "output";
            }
            PORT datab
            {
               type = "datab";
               width = "32";
               direction = "output";
            }
            PORT result
            {
               type = "result";
               width = "32";
               direction = "input";
            }
            PORT clk_en
            {
               type = "clk_en";
               width = "1";
               direction = "output";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "output";
            }
            PORT start
            {
               type = "start";
               width = "1";
               direction = "output";
            }
            PORT done
            {
               type = "done";
               width = "1";
               direction = "input";
            }
            PORT n
            {
               type = "n";
               width = "8";
               direction = "output";
            }
            PORT a
            {
               type = "a";
               width = "5";
               direction = "output";
            }
            PORT b
            {
               type = "b";
               width = "5";
               direction = "output";
            }
            PORT c
            {
               type = "c";
               width = "5";
               direction = "output";
            }
            PORT readra
            {
               type = "readra";
               width = "1";
               direction = "output";
            }
            PORT readrb
            {
               type = "readrb";
               width = "1";
               direction = "output";
            }
            PORT writerc
            {
               type = "writerc";
               width = "1";
               direction = "output";
            }
         }
      }
      SLAVE jtag_debug_module
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "2048";
            Read_Latency = "0";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "9";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Accepts_External_Connections = "1";
            Requires_Internal_Connections = "";
            MASTERED_BY cpu/instruction_master
            {
               priority = "1";
               Offset_Address = "0x00200800";
            }
            MASTERED_BY cpu/data_master
            {
               priority = "1";
               Offset_Address = "0x00200800";
            }
            Base_Address = "0x00200800";
         }
         PORT_WIRING 
         {
            PORT jtag_debug_module_address
            {
               type = "address";
               width = "9";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_begintransfer
            {
               type = "begintransfer";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess
            {
               type = "debugaccess";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_readdata
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_select
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_write
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_writedata
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
         }
      }
      MASTER data_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Irq_Scheme = "individual_requests";
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "25";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Data_Master = "1";
         }
         PORT_WIRING 
         {
            PORT d_irq
            {
               type = "irq";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_address
            {
               type = "address";
               width = "25";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_byteenable
            {
               type = "byteenable";
               width = "4";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT d_write
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT d_writedata
            {
               type = "writedata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT jtag_debug_module_debugaccess_to_roms
            {
               type = "debugaccess";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry cpu/jtag_debug_module
            {
               address = "0x00200800";
               span = "0x00000800";
               is_bridge = "0";
            }
            Entry altpll_0/pll_slave
            {
               address = "0x00201100";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry jtag_uart/avalon_jtag_slave
            {
               address = "0x00201110";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry alt_vip_vfr_0/avalon_slave
            {
               address = "0x00201000";
               span = "0x00000080";
               is_bridge = "0";
            }
            Entry multi_touch/avalon_slave
            {
               address = "0x00201080";
               span = "0x00000080";
               is_bridge = "0";
            }
            Entry ssram/s1
            {
               address = "0x00000000";
               span = "0x00200000";
               is_bridge = "0";
            }
            Entry clock_crossing_io/s1
            {
               address = "0x01000000";
               span = "0x00000080";
               is_bridge = "1";
            }
            Entry sysid/control_slave
            {
               address = "0x01000040";
               span = "0x00000008";
               is_bridge = "0";
            }
            Entry timer/s1
            {
               address = "0x01000000";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry key/s1
            {
               address = "0x01000020";
               span = "0x00000010";
               is_bridge = "0";
            }
            Entry led/s1
            {
               address = "0x01000030";
               span = "0x00000010";
               is_bridge = "0";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         cache_has_dcache = "1";
         cache_dcache_size = "2048";
         cache_dcache_line_size = "32";
         cache_dcache_bursts = "0";
         cache_dcache_ram_block_type = "AUTO";
         num_tightly_coupled_data_masters = "0";
         gui_num_tightly_coupled_data_masters = "0";
         gui_include_tightly_coupled_data_masters = "0";
         gui_omit_avalon_data_master = "0";
         cache_has_icache = "1";
         cache_icache_size = "4096";
         cache_icache_line_size = "32";
         cache_icache_ram_block_type = "AUTO";
         cache_icache_bursts = "0";
         num_tightly_coupled_instruction_masters = "0";
         gui_num_tightly_coupled_instruction_masters = "0";
         gui_include_tightly_coupled_instruction_masters = "0";
         debug_level = "2";
         include_oci = "1";
         oci_num_xbrk = "0";
         oci_num_dbrk = "0";
         oci_dbrk_trace = "0";
         oci_dbrk_pairs = "0";
         oci_onchip_trace = "0";
         oci_offchip_trace = "0";
         oci_data_trace = "0";
         include_third_party_debug_port = "0";
         oci_trace_addr_width = "7";
         oci_debugreq_signals = "0";
         oci_trigger_arming = "1";
         oci_embedded_pll = "0";
         oci_assign_jtag_instance_id = "0";
         oci_jtag_instance_id = "0";
         oci_num_pm = "0";
         oci_pm_width = "32";
         performance_counters_present = "0";
         performance_counters_width = "32";
         always_encrypt = "1";
         debug_simgen = "0";
         activate_model_checker = "0";
         activate_test_end_checker = "0";
         activate_trace = "1";
         activate_monitors = "1";
         clear_x_bits_ld_non_bypass = "1";
         bit_31_bypass_dcache = "1";
         hdl_sim_caches_cleared = "1";
         hbreak_test = "0";
         allow_full_address_range = "0";
         extra_exc_info = "0";
         branch_prediction_type = "Dynamic";
         bht_ptr_sz = "8";
         bht_index_pc_only = "0";
         gui_branch_prediction_type = "Automatic";
         full_waveform_signals = "0";
         export_pcb = "0";
         big_endian = "0";
         avalon_debug_port_present = "0";
         illegal_instructions_trap = "0";
         illegal_memory_access_detection = "0";
         illegal_mem_exc = "0";
         slave_access_error_exc = "0";
         division_error_exc = "0";
         eic_present = "0";
         num_shadow_reg_sets = "0";
         gui_mmu_present = "0";
         mmu_present = "0";
         process_id_num_bits = "8";
         tlb_ptr_sz = "7";
         tlb_num_ways = "16";
         udtlb_num_entries = "6";
         uitlb_num_entries = "4";
         fast_tlb_miss_exc_slave = "";
         fast_tlb_miss_exc_offset = "0x00000000";
         mpu_present = "0";
         mpu_num_data_regions = "8";
         mpu_num_inst_regions = "8";
         mpu_min_data_region_size_log2 = "12";
         mpu_min_inst_region_size_log2 = "12";
         mpu_use_limit = "0";
         hardware_divide_present = "0";
         gui_hardware_divide_setting = "0";
         hardware_multiply_present = "1";
         hardware_multiply_impl = "dsp_mul";
         shift_rot_impl = "dsp_shift";
         gui_hardware_multiply_setting = "dsp_mul_dsp_shift";
         reset_slave = "ssram/s1";
         break_slave = "cpu/jtag_debug_module";
         exc_slave = "ssram/s1";
         reset_offset = "0x00000000";
         break_offset = "0x00000020";
         exc_offset = "0x00000020";
         cpu_reset = "0";
         CPU_Implementation = "fast";
         cpu_selection = "f";
         device_family_id = "STRATIXIV";
         address_stall_present = "1";
         dsp_block_supports_shift = "1";
         mrams_present = "0";
         cpuid_value = "0";
         dont_overwrite_cpuid = "1";
         allow_legacy_sdk = "1";
         legacy_sdk_support = "1";
         inst_addr_width = "22";
         data_addr_width = "25";
      }
      class = "altera_nios2";
      class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "altpll_sys";
         Has_Clock = "1";
      }
   }
   MODULE ssram
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "19";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "1";
            }
            PORT adsc_n
            {
               type = "begintransfer_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT bw_n
            {
               type = "byteenable_n";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT bwe_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "1";
            }
            PORT chipenable1_n
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT data
            {
               type = "data";
               width = "32";
               direction = "inout";
               Is_Enabled = "1";
               is_shared = "1";
            }
            PORT outputenable_n
            {
               type = "outputenable_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "0cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "2097152";
            Read_Latency = "2";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Active_CS_Through_Read_Latency = "1";
            Data_Width = "32";
            Address_Width = "19";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY tristate_bridge_ssram/tristate_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            Base_Address = "0x00000000";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         sram_memory_size = "2";
         sram_memory_units = "1048576";
         ssram_data_width = "32";
         ssram_read_latency = "2";
      }
      class = "altera_avalon_cy7c1380_ssram";
      class_version = "10.1";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "altpll_sys";
         Has_Clock = "1";
      }
   }
}
