module xcvr_test0 (

cal_blk_clk,
xcvr_refclk,
irst_n,
xcvr_tx,
xcvr_rx,
error_insert,
test_error,
tx_clock,

);

input			cal_blk_clk;
input			xcvr_refclk;	
input			irst_n;	
input			xcvr_rx;
output			xcvr_tx;
input			error_insert;
output			test_error;		
output 			tx_clock;


/////////////////////////////////////////

wire			rst_n;
wire			gxb_powerdown_ctrl_n;
reg				gxb_powerdown;					
reg				rx_d_reset;	
reg				rx_a_reset;				
reg				tx_d_reset;				
wire	[7:0]	tx_datain;	
wire			tx_ctrl_en;
				
wire			pll_locked;				
wire			rx_clkout;
wire	[1:0]	rx_ctrl_det;

wire	[7:0]	rx_dataout;
wire	[7:0]	rx_dataout1;
wire	[7:0]	rx_dataout2;
wire	[7:0]	rx_dataout3;

wire			rx_freqlocked;
wire			rx_pll_locked;
wire			tx_clkout;

reg				rx_enapatternalign;

wire			rx_test_error1;
wire			rx_test_error2;
wire			rx_test_error3;
wire			rx_test_error4;

wire 			tx_clk_sma;
wire			test_error;
reg				test_error_status;
reg	[28:0]		test_cnt;

wire			rx_verify_start1;
wire			rx_verify_start2;
wire			rx_verify_start3;
wire			rx_verify_start4;

/////////////////////////////////////////

//============================
//  Altera XCVR IP 
//============================


gx_alt4gxb0 x
	( 
	.cal_blk_clk(cal_blk_clk),
	.gxb_powerdown(),
	.pll_inclk(xcvr_refclk),
	.pll_locked(pll_locked),
	.reconfig_clk(),
	.reconfig_fromgxb(),
	.reconfig_togxb(),
	.rx_analogreset(rx_a_reset),
	.rx_bitslip(),
	.rx_clkout(rx_clkout),
	.rx_cruclk(),
	.rx_ctrldetect(rx_ctrldetect),
	.rx_datain(xcvr_rx),
	.rx_dataout({rx_dataout,rx_dataout1,rx_dataout2,rx_dataout3}),
	.rx_digitalreset(rx_d_reset),
	.rx_errdetect(),
	.rx_freqlocked(rx_freqlocked),
	.rx_locktodata(),
	.rx_locktorefclk(),
	.rx_pll_locked(rx_pll_locked),
	.tx_clkout(tx_clkout),
	.tx_ctrlenable({tx_ctrl_en,tx_ctrl_en,tx_ctrl_en,tx_ctrl_en}),
	.tx_datain({tx_datain,tx_datain,tx_datain,tx_datain}),
	.tx_dataout(xcvr_tx),
	.tx_digitalreset(tx_d_reset),
	.rx_syncstatus(),
	.rx_patterndetect(),
	.rx_enapatternalign(rx_enapatternalign),
	) ;

//	rx_enapatternalign

always@(posedge tx_clkout)
	begin
		if (~rst_n)
			rx_enapatternalign <= 1'b0;
		else if (rx_d_reset == 1'b0)
			rx_enapatternalign <= 	1'b1;
	end

	
//	Reset control 1	
	always@(posedge cal_blk_clk)
		begin
			if (~rst_n)
				begin
					gxb_powerdown <= 1;
					tx_d_reset <= 1;
					rx_a_reset <= 1;
					
				end
			else if (gxb_powerdown_ctrl_n)
				begin
					gxb_powerdown <= 0;
				end
			else if (pll_locked)
				begin
					tx_d_reset <= 0;
					rx_a_reset <= 0;
				end
		end
		
//	Reset control 2			
	always@(posedge cal_blk_clk)
		begin
			if (~rst_n)
				rx_d_reset <= 1;
			else if (rx_freqlocked)
				rx_d_reset <= 0;
				
		end

//	tx pattern generator
tx_pattern0 tx_pat(
.iclk(tx_clkout),
.rst_n(rst_n),
.tx_data(tx_datain),
.tx_ctrl_en(tx_ctrl_en),
.error_insert(error_insert),
);


//	rx verify block

rx_data_verify0 rx_verify(
.iclk(rx_clkout),
.rst_n(rst_n),
.rx_pll_locked(rx_pll_locked),
.rx_data(rx_dataout),
.test_error(rx_test_error1),
.rx_state(),
.rx_verify_start(rx_verify_start1),
);

rx_data_verify0 rx_verify1(
.iclk(rx_clkout),
.rst_n(rst_n),
.rx_pll_locked(rx_pll_locked),
.rx_data(rx_dataout1),
.test_error(rx_test_error2),
.rx_state(),
.rx_verify_start(rx_verify_start2),
);

rx_data_verify0 rx_verify2(
.iclk(rx_clkout),
.rst_n(rst_n),
.rx_pll_locked(rx_pll_locked),
.rx_data(rx_dataout2),
.test_error(rx_test_error3),
.rx_state(),
.rx_verify_start(rx_verify_start3),
);

rx_data_verify0 rx_verify3(
.iclk(rx_clkout),
.rst_n(rst_n),
.rx_pll_locked(rx_pll_locked),
.rx_data(rx_dataout3),
.test_error(rx_test_error4),
.rx_state(),
.rx_verify_start(rx_verify_start4),
);


always@(posedge rx_clkout or negedge rst_n)
	begin
		if (!rst_n)
			begin
				test_error_status <= 1'b0;
				test_cnt <= 0;
			end	
		else if (   rx_test_error1 | rx_test_error2 |	
					rx_test_error3 | rx_test_error4)	
			begin
				test_error_status <= 1'b1;
				test_cnt <= 0;
			end
		else if (rx_verify_start1 | rx_verify_start2 |
		         rx_verify_start3 | rx_verify_start4 )
		    begin
				test_cnt <= test_cnt + 1;
			end	
	end			

assign test_error = test_error_status ? 1'b1 : test_cnt[26];


reset_ctrl0 rst_ctl(
.iclk(cal_blk_clk),
.irst_n(irst_n),
.orst_n(gxb_powerdown_ctrl_n),
.orst_n1(rst_n)
);



endmodule
