# PIN MAP for core < TR4_QSYS_uniphy_ddr3_p0 >
#
# Generated by TR4_QSYS_uniphy_ddr3_p0_pin_assignments.tcl
#
# This file is for reference only and is not used by Quartus II
#

INSTANCE: u0|uniphy_ddr3|p0
DQS: {mem_dqs[0]} {mem_dqs[1]} {mem_dqs[2]} {mem_dqs[3]} {mem_dqs[4]} {mem_dqs[5]} {mem_dqs[6]} {mem_dqs[7]}
DQSn: {mem_dqs_n[0]} {mem_dqs_n[1]} {mem_dqs_n[2]} {mem_dqs_n[3]} {mem_dqs_n[4]} {mem_dqs_n[5]} {mem_dqs_n[6]} {mem_dqs_n[7]}
DQ: {{mem_dq[0]} {mem_dq[1]} {mem_dq[2]} {mem_dq[3]} {mem_dq[4]} {mem_dq[5]} {mem_dq[6]} {mem_dq[7]}} {{mem_dq[8]} {mem_dq[9]} {mem_dq[10]} {mem_dq[11]} {mem_dq[12]} {mem_dq[13]} {mem_dq[14]} {mem_dq[15]}} {{mem_dq[16]} {mem_dq[17]} {mem_dq[18]} {mem_dq[19]} {mem_dq[20]} {mem_dq[21]} {mem_dq[22]} {mem_dq[23]}} {{mem_dq[24]} {mem_dq[25]} {mem_dq[26]} {mem_dq[27]} {mem_dq[28]} {mem_dq[29]} {mem_dq[30]} {mem_dq[31]}} {{mem_dq[32]} {mem_dq[33]} {mem_dq[34]} {mem_dq[35]} {mem_dq[36]} {mem_dq[37]} {mem_dq[38]} {mem_dq[39]}} {{mem_dq[40]} {mem_dq[41]} {mem_dq[42]} {mem_dq[43]} {mem_dq[44]} {mem_dq[45]} {mem_dq[46]} {mem_dq[47]}} {{mem_dq[48]} {mem_dq[49]} {mem_dq[50]} {mem_dq[51]} {mem_dq[52]} {mem_dq[53]} {mem_dq[54]} {mem_dq[55]}} {{mem_dq[56]} {mem_dq[57]} {mem_dq[58]} {mem_dq[59]} {mem_dq[60]} {mem_dq[61]} {mem_dq[62]} {mem_dq[63]}}
DM {mem_dm[0]} {mem_dm[1]} {mem_dm[2]} {mem_dm[3]} {mem_dm[4]} {mem_dm[5]} {mem_dm[6]} {mem_dm[7]}
CK: {mem_ck[0]} {mem_ck[1]}
CKn: {mem_ck_n[0]} {mem_ck_n[1]}
ADD: {mem_a[0]} {mem_a[10]} {mem_a[11]} {mem_a[12]} {mem_a[13]} {mem_a[1]} {mem_a[2]} {mem_a[3]} {mem_a[4]} {mem_a[5]} {mem_a[6]} {mem_a[7]} {mem_a[8]} {mem_a[9]}
CMD: {mem_cs_n[0]} mem_we_n mem_ras_n mem_cas_n {mem_cke[0]} {mem_odt[0]}
RESET: mem_reset_n
BA: {mem_ba[0]} {mem_ba[1]} {mem_ba[2]}
REF CLK: OSC_50_BANK8
PLL AFI: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[0]
PLL CK: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[1]
PLL WRITE: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[2]
PLL AC: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[3]
PLL AFI HALF: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[4]
PLL AVL: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[5]
PLL CONFIG: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|upll_memphy|altpll_component|auto_generated|pll1|clk[6]
DQS_IN_CLOCK DQS_PIN (0): mem_dqs[0]
DQS_IN_CLOCK DQS_SHIFTED_PIN (0): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (0): u0|uniphy_ddr3|p0|div_clock_0
DQS_IN_CLOCK DIV_PIN (0): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[0]
DQS_IN_CLOCK DQS_PIN (1): mem_dqs[1]
DQS_IN_CLOCK DQS_SHIFTED_PIN (1): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (1): u0|uniphy_ddr3|p0|div_clock_1
DQS_IN_CLOCK DIV_PIN (1): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[1]
DQS_IN_CLOCK DQS_PIN (2): mem_dqs[2]
DQS_IN_CLOCK DQS_SHIFTED_PIN (2): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (2): u0|uniphy_ddr3|p0|div_clock_2
DQS_IN_CLOCK DIV_PIN (2): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[2]
DQS_IN_CLOCK DQS_PIN (3): mem_dqs[3]
DQS_IN_CLOCK DQS_SHIFTED_PIN (3): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (3): u0|uniphy_ddr3|p0|div_clock_3
DQS_IN_CLOCK DIV_PIN (3): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[3]
DQS_IN_CLOCK DQS_PIN (4): mem_dqs[4]
DQS_IN_CLOCK DQS_SHIFTED_PIN (4): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (4): u0|uniphy_ddr3|p0|div_clock_4
DQS_IN_CLOCK DIV_PIN (4): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[4]
DQS_IN_CLOCK DQS_PIN (5): mem_dqs[5]
DQS_IN_CLOCK DQS_SHIFTED_PIN (5): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (5): u0|uniphy_ddr3|p0|div_clock_5
DQS_IN_CLOCK DIV_PIN (5): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[5]
DQS_IN_CLOCK DQS_PIN (6): mem_dqs[6]
DQS_IN_CLOCK DQS_SHIFTED_PIN (6): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (6): u0|uniphy_ddr3|p0|div_clock_6
DQS_IN_CLOCK DIV_PIN (6): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[6]
DQS_IN_CLOCK DQS_PIN (7): mem_dqs[7]
DQS_IN_CLOCK DQS_SHIFTED_PIN (7): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_delay_chain|dqsbusout
DQS_IN_CLOCK DIV_NAME (7): u0|uniphy_ddr3|p0|div_clock_7
DQS_IN_CLOCK DIV_PIN (7): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uread_datapath|read_capture_clk_div2[7]
DQS_OUT_CLOCK SRC (0): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (0): mem_dqs[0]
DQS_OUT_CLOCK DM (0): mem_dm[0]
DQS_OUT_CLOCK SRC (1): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (1): mem_dqs[1]
DQS_OUT_CLOCK DM (1): mem_dm[1]
DQS_OUT_CLOCK SRC (2): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (2): mem_dqs[2]
DQS_OUT_CLOCK DM (2): mem_dm[2]
DQS_OUT_CLOCK SRC (3): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (3): mem_dqs[3]
DQS_OUT_CLOCK DM (3): mem_dm[3]
DQS_OUT_CLOCK SRC (4): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (4): mem_dqs[4]
DQS_OUT_CLOCK DM (4): mem_dm[4]
DQS_OUT_CLOCK SRC (5): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (5): mem_dqs[5]
DQS_OUT_CLOCK DM (5): mem_dm[5]
DQS_OUT_CLOCK SRC (6): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (6): mem_dqs[6]
DQS_OUT_CLOCK DM (6): mem_dm[6]
DQS_OUT_CLOCK SRC (7): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_0|o
DQS_OUT_CLOCK DST (7): mem_dqs[7]
DQS_OUT_CLOCK DM (7): mem_dm[7]
DQSN_OUT_CLOCK SRC (0): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (0): mem_dqs_n[0]
DQSN_OUT_CLOCK DM (0): mem_dm[0]
DQSN_OUT_CLOCK SRC (1): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (1): mem_dqs_n[1]
DQSN_OUT_CLOCK DM (1): mem_dm[1]
DQSN_OUT_CLOCK SRC (2): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (2): mem_dqs_n[2]
DQSN_OUT_CLOCK DM (2): mem_dm[2]
DQSN_OUT_CLOCK SRC (3): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (3): mem_dqs_n[3]
DQSN_OUT_CLOCK DM (3): mem_dm[3]
DQSN_OUT_CLOCK SRC (4): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (4): mem_dqs_n[4]
DQSN_OUT_CLOCK DM (4): mem_dm[4]
DQSN_OUT_CLOCK SRC (5): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (5): mem_dqs_n[5]
DQSN_OUT_CLOCK DM (5): mem_dm[5]
DQSN_OUT_CLOCK SRC (6): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (6): mem_dqs_n[6]
DQSN_OUT_CLOCK DM (6): mem_dm[6]
DQSN_OUT_CLOCK SRC (7): u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|obuf_os_bar_0|o
DQSN_OUT_CLOCK DST (7): mem_dqs_n[7]
DQSN_OUT_CLOCK DM (7): mem_dm[7]
LEVELING PINS: u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[2].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[4].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[5].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[6].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oe_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|dqs_oct_bar_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|extra_output_pad_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[0].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[1].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[2].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[3].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[4].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[5].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[6].oct_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].data_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oe_alignment|clk u0|uniphy_ddr3|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|dq_ddio[7].ubidir_dq_dqs|altdq_dqs2_inst|output_path_gen[7].oct_alignment|clk
READ CAPTURE DDIO: {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*input_path_gen[*].capture_reg*} {*:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uio_pads|*:dq_ddio[*].ubidir_dq_dqs|*:altdq_dqs2_inst|*read_data_out[*]}
AFI RESET REGISTERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:ureset|*:ureset_afi_clk|reset_reg[3]
SEQ  RESET REGISTERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:usequencer|*:sequencer_inst|*
SYNCHRONIZERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|read_buffering[*].seq_read_fifo_reset_sync
SYNCHRONIZATION FIFO WRITE ADDRESS REGISTERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|read_buffering[*].read_subgroup[*].wraddress[*]
SYNCHRONIZATION FIFO WRITE REGISTERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_buffering[*].read_subgroup[*].uread_fifo*|data_stored[*][*]
SYNCHRONIZATION FIFO READ REGISTERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_buffering[*].uread_fifo*|rd_data[*]
VALID PREDICTION FIFO WRITE REGISTERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_valid_predict[*].uread_valid_fifo|data_stored[*][*]
VALID PREDICTION FIFO READ REGISTERS: *:u0|*:uniphy_ddr3|*:p0|*:controller_phy_inst|*:memphy_top_inst|*:umemphy|*:uread_datapath|*:read_valid_predict[*].uread_valid_fifo|rd_data[*]

#
# END OF INSTANCE: u0|uniphy_ddr3|p0

