module rx_data_verify0 (

iclk,
rst_n,
rx_data,
test_error,
rx_state,
rx_pll_locked,
rx_verify_start,

);

input			iclk;
input			rst_n;
input	[7:0]	rx_data;
input			rx_pll_locked;

output			test_error;
output	[4:0]	rx_state;
output			rx_verify_start;

//=======================================================
//  PARAMETER declarations
//=======================================================

parameter rx_idle_state						=	5'd0;
parameter rx_phase_detect1_state			=	5'd1;
parameter rx_phase_detect2_state			=	5'd2;
parameter rx_phase_detect3_state			=	5'd3;
parameter rx_preamable_d1_verify_state		=	5'd4;
parameter rx_pattern_d1_verify_state		=	5'd7;
parameter rx_pattern_d2_verify_state		=	5'd8;
parameter rx_pattern_d3_verify_state		=	5'd9;
parameter rx_pattern_d4_verify_state		=	5'd10;
parameter rx_pattern_d5_verify_state		=	5'd11;
parameter rx_pattern_d6_verify_state		=	5'd12;
parameter rx_pattern_d7_verify_state		=	5'd13;
parameter rx_pattern_d8_verify_state		=	5'd14;
parameter rx_pattern_d9_verify_state		=	5'd15;
parameter rx_pattern_d10_verify_state		=	5'd16;
parameter rx_pattern_d11_verify_state		=	5'd17;
parameter rx_pattern_d12_verify_state		=	5'd18;
parameter rx_pattern_d13_verify_state		=	5'd19;
parameter rx_pattern_d14_verify_state		=	5'd20;
parameter rx_pattern_d15_verify_state		=	5'd21;
parameter rx_pattern_d16_verify_state		=	5'd22;


parameter rx_pattern_d1			= 	8'hf1;
parameter rx_pattern_d2			= 	8'he2;
parameter rx_pattern_d3			= 	8'hd3;
parameter rx_pattern_d4			= 	8'hc4;
parameter rx_pattern_d5			= 	8'hb5;
parameter rx_pattern_d6			= 	8'ha6;
parameter rx_pattern_d7			= 	8'h97;
parameter rx_pattern_d8			= 	8'h8a;
parameter rx_pattern_d9			= 	8'h7b;
parameter rx_pattern_d10		= 	8'h6c;
parameter rx_pattern_d11		= 	8'h5d;
parameter rx_pattern_d12		= 	8'h4e;
parameter rx_pattern_d13		= 	8'h3f;
parameter rx_pattern_d14		= 	8'h29;
parameter rx_pattern_d15		= 	8'h18;
parameter rx_pattern_d16		= 	8'h0d;

parameter peamable_d1			=	8'hbc;

//=======================================================
//  REG/WIRE declarations
//=======================================================
reg		[4:0]	rx_state;
wire	[7:0]	rx_data;
reg		[4:0]	byte_cnt;
reg				test_error;
reg				rx_verify_start;

//=======================================================
//  Structural coding
//=======================================================


always@(posedge iclk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				rx_state <= 5'h0;
				test_error <= 1'b0;
				rx_verify_start <= 1'b0;
			end	
		else
			begin
				case(rx_state)
				rx_idle_state : 			
					begin
						
						if (rx_pll_locked)
							begin
								rx_state <= rx_phase_detect1_state;
							end
						else
							begin
								rx_state <= rx_idle_state;
								
							end
	
					end
				rx_phase_detect1_state:
					begin
						if (rx_data == peamable_d1)
							begin
								rx_state <= rx_pattern_d1_verify_state;
							end
						else
							begin
								rx_state <= rx_phase_detect1_state;
																
								if (rx_pll_unlocked_cnt == 24'hffffff)
									begin
										test_error <= 1'b1;
									end	
								else
									begin
										test_error <= 1'b0;
									end		
								
							end
					end
			
				rx_preamable_d1_verify_state:
					begin
						if (rx_data == peamable_d1)
							begin
								rx_state <= rx_pattern_d1_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								
								if (rx_verify_start)
									begin
										test_error <= 1'b1;
										rx_state <= rx_pattern_d1_verify_state;									
									end	
								else
									begin
										test_error <= 1'b0;
										rx_state <= rx_phase_detect1_state;								
									end											
							end					
					end	
					
				rx_pattern_d1_verify_state:
					begin
						if (rx_data == rx_pattern_d1)
							begin
								rx_state <= rx_pattern_d2_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin

								if (rx_verify_start)
									begin
										test_error <= 1'b1;
										rx_state <= rx_pattern_d2_verify_state;										
									end	
								else
									begin
										test_error <= 1'b0;
										rx_state <= rx_phase_detect1_state;								
									end									
							end	
					end					
				rx_pattern_d2_verify_state:
					begin
						if (rx_data == rx_pattern_d2)
							begin
								rx_state <= rx_pattern_d3_verify_state;
								test_error <= 1'b0;	
	
							end	
						else
							begin
								if (rx_verify_start)
									begin
										test_error <= 1'b1;
										rx_state <= rx_pattern_d3_verify_state;										
									end	
								else
									begin
										test_error <= 1'b0;
										rx_state <= rx_phase_detect1_state;					
									end								
							end	
					end	
				rx_pattern_d3_verify_state:
					begin
						if (rx_data == rx_pattern_d3)
							begin
								rx_state <= rx_pattern_d4_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								if (rx_verify_start)
									begin
										test_error <= 1'b1;
										rx_state <= rx_pattern_d4_verify_state;										
									end	
								else
									begin
										test_error <= 1'b0;
										rx_state <= rx_phase_detect1_state;					
									end								
							end	
					end		
				rx_pattern_d4_verify_state:
					begin
						if (rx_data == rx_pattern_d4)
							begin
								rx_state <= rx_pattern_d5_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								if (rx_verify_start)
									begin
										test_error <= 1'b1;
										rx_state <= rx_pattern_d5_verify_state;										
									end	
								else
									begin
										test_error <= 1'b0;
										rx_state <= rx_phase_detect1_state;					
									end								
							end	
					end			
				rx_pattern_d5_verify_state:
					begin
						if (rx_data == rx_pattern_d5)
							begin
								rx_state <= rx_pattern_d6_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								if (rx_verify_start)
									begin
										test_error <= 1'b1;
										rx_state <= rx_pattern_d6_verify_state;										
									end	
								else
									begin
										test_error <= 1'b0;
										rx_state <= rx_phase_detect1_state;					
									end								
							end	
					end		
				rx_pattern_d6_verify_state:
					begin
						if (rx_data == rx_pattern_d6)
							begin
								rx_state <= rx_pattern_d7_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								if (rx_verify_start)
									begin
										test_error <= 1'b1;
										rx_state <= rx_pattern_d7_verify_state;										
									end	
								else
									begin
										test_error <= 1'b0;
										rx_state <= rx_phase_detect1_state;					
									end								
							end	
					end		
				rx_pattern_d7_verify_state:
					begin
						if (rx_data == rx_pattern_d7)
							begin
								rx_state <= rx_pattern_d8_verify_state;
								test_error <= 1'b0;	
								rx_verify_start <= 1'b1;
							end	
						else
							begin
								rx_state <= rx_pattern_d8_verify_state;	
								test_error <= 1'b1;								
							end	
					end			
				rx_pattern_d8_verify_state:
					begin
						if (rx_data == rx_pattern_d8)
							begin
								rx_state <= rx_pattern_d9_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d9_verify_state;	
								test_error <= 1'b1;								
							end	
					end			
				rx_pattern_d9_verify_state:
					begin
						if (rx_data == rx_pattern_d9)
							begin
								rx_state <= rx_pattern_d10_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d10_verify_state;	
								test_error <= 1'b1;								
							end	
					end			
				rx_pattern_d10_verify_state:
					begin
						if (rx_data == rx_pattern_d10)
							begin
								rx_state <= rx_pattern_d11_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d11_verify_state;	
								test_error <= 1'b1;								
							end	
					end		
				rx_pattern_d11_verify_state:
					begin
						if (rx_data == rx_pattern_d11)
							begin
								rx_state <= rx_pattern_d12_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d12_verify_state;	
								test_error <= 1'b1;								
							end	
					end						

				rx_pattern_d12_verify_state:
					begin
						if (rx_data == rx_pattern_d12)
							begin
								rx_state <= rx_pattern_d13_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d13_verify_state;	
								test_error <= 1'b1;								
							end	
					end	
				rx_pattern_d13_verify_state:
					begin
						if (rx_data == rx_pattern_d13)
							begin
								rx_state <= rx_pattern_d14_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d14_verify_state;	
								test_error <= 1'b1;								
							end	
					end	

				rx_pattern_d14_verify_state:
					begin
						if (rx_data == rx_pattern_d14)
							begin
								rx_state <= rx_pattern_d15_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d15_verify_state;	
								test_error <= 1'b1;								
							end	
					end	
				rx_pattern_d15_verify_state:
					begin
						if (rx_data == rx_pattern_d15)
							begin
								rx_state <= rx_pattern_d16_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_pattern_d16_verify_state;	
								test_error <= 1'b1;								
							end	
					end	
				rx_pattern_d16_verify_state:
					begin
						if (rx_data == rx_pattern_d16)
							begin
								rx_state <= rx_preamable_d1_verify_state;
								test_error <= 1'b0;	
							end	
						else
							begin
								rx_state <= rx_preamable_d1_verify_state;	
								test_error <= 1'b1;								
							end	
					end	

				endcase	
			end
	end
	
reg	[23:0] rx_pll_unlocked_cnt;	

always@(posedge iclk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				rx_pll_unlocked_cnt <= 0;
			end
		else if (rx_state == rx_phase_detect1_state)
			begin
				rx_pll_unlocked_cnt <= rx_pll_unlocked_cnt + 1;
			end
		else
			begin
				rx_pll_unlocked_cnt <= 0;
			end
	end		
			
				

endmodule
