// --------------------------------------------------------------------
// Copyright (c) 2010 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/   
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
//Date:  Thu Jul  7 16:45:45 2011
//---------------------------------------------------------------------


module tr4_golden_top(

							///////////BUTTON/////////////
							BUTTON,

							/////////FAN/////////
							FAN_CTRL,
							FAN_SPEED,

							/////////FLASH/////////
							FLASH_ADV_n,
							FLASH_CE_n,
							FLASH_CLK,
							FLASH_RDY_BSY_n,
							FLASH_RESET_n,
							FLASH_WP_n,

							/////////FSM/////////
							FSM_A,
							FSM_D,
							FSM_OE_n,
							FSM_WE_n,

							/////////HSMA/////////
							HSMA_CLKIN0,
							HSMA_CLKIN_n1,
							HSMA_CLKIN_n2,
							HSMA_CLKIN_p1,
							HSMA_CLKIN_p2,
							HSMA_D,
//							HSMA_GXB_RX_p,
//							HSMA_GXB_TX_p,
							HSMA_OUT0,
							HSMA_OUT_n1,
							HSMA_OUT_n2,
							HSMA_OUT_p1,
							HSMA_OUT_p2,
//							HSMA_REFCLK_p,
							HSMA_RX_n,
							HSMA_RX_p,
							HSMA_TX_n,
							HSMA_TX_p,

							/////////HSMB/////////
							HSMB_CLKIN0,
							HSMB_CLKIN_n1,
							HSMB_CLKIN_n2,
							HSMB_CLKIN_p1,
							HSMB_CLKIN_p2,
							HSMB_D,
							HSMB_OUT0,
							HSMB_OUT_n1,
							HSMB_OUT_n2,
							HSMB_OUT_p1,
							HSMB_OUT_p2,
							HSMB_RX_n,
							HSMB_RX_p,
							HSMB_SCL,
							HSMB_SDA,
							HSMB_TX_n,
							HSMB_TX_p,

							/////////HSMC/////////
							HSMC_CLKIN0,
							HSMC_CLKIN_n1,
							HSMC_CLKIN_n2,
							HSMC_CLKIN_p1,
							HSMC_CLKIN_p2,
							HSMC_CLKOUT_n1,
							HSMC_CLKOUT_p1,
							HSMC_D,
							HSMC_OUT0,
							HSMC_OUT_n2,
							HSMC_OUT_p2,
							HSMC_RX_n,
							HSMC_RX_p,
							HSMC_TX_n,
							HSMC_TX_p,

							/////////HSMD/////////
							HSMD_CLKIN0,
							HSMD_CLKIN_n1,
							HSMD_CLKIN_n2,
							HSMD_CLKIN_p1,
							HSMD_CLKIN_p2,
							HSMD_CLKOUT_n1,
							HSMD_CLKOUT_p1,
							HSMD_D,
							HSMD_OUT0,
							HSMD_OUT_n2,
							HSMD_OUT_p2,
							HSMD_RX_n,
							HSMD_RX_p,
							HSMD_SCL,
							HSMD_SDA,
							HSMD_TX_n,
							HSMD_TX_p,

							/////////HSME/////////
							HSME_CLKIN0,
							HSME_CLKIN_n1,
							HSME_CLKIN_n2,
							HSME_CLKIN_p1,
							HSME_CLKIN_p2,
							HSME_CLKOUT_n1,
							HSME_CLKOUT_p1,
							HSME_D,
//							HSME_GXB_RX_p,
//							HSME_GXB_TX_p,
							HSME_OUT0,
							HSME_OUT_n2,
							HSME_OUT_p2,
//							HSME_REFCLK_p,
							HSME_RX_n,
							HSME_RX_p,
							HSME_TX_n,
							HSME_TX_p,

							/////////HSMF/////////
							HSMF_CLKIN0,
							HSMF_CLKIN_n1,
							HSMF_CLKIN_n2,
							HSMF_CLKIN_p1,
							HSMF_CLKIN_p2,
							HSMF_CLKOUT_n1,
							HSMF_CLKOUT_n2,
							HSMF_CLKOUT_p1,
							HSMF_CLKOUT_p2,
							HSMF_D,
							HSMF_OUT0,
							HSMF_RX_n,
							HSMF_RX_p,
							HSMF_TX_n,
							HSMF_TX_p,

							/////////LED/////////
							LED,

							/////////LOOP/////////
							LOOP_CLKIN0,
							LOOP_CLKOUT0,
							LOOP_CLKIN1,
							LOOP_CLKOUT1,

							/////////MAX2/////////
							MAX2_CS_n,
							MAX2_I2C_SCL,
							MAX2_I2C_SDA,

							/////////mem/////////
//							mem_a,
//							mem_ba,
//							mem_cas_n,
//							mem_cke,
//							mem_ck,
//							mem_ck_n,
//							mem_cs_n,
//							mem_dm,
//							mem_dq,
//							mem_dqs,
//							mem_dqs_n,
//							mem_event_n,
//							mem_odt,
//							mem_ras_n,
//							mem_reset_n,
//							mem_scl,
//							mem_sda,
//							mem_we_n,

							/////////OSC/////////
							OSC_50_BANK1,
							OSC_50_BANK3,
							OSC_50_BANK4,
							OSC_50_BANK7,
							OSC_50_BANK8,

							/////////PCIE0/////////
							PCIE0_pREST_n,
							PCIE0_REFCLK_p,
							PCIE0_RX_p,
							PCIE0_TX_p,
							PCIE0_WAKE_n,

							/////////PCIE1/////////
							PCIE1_pREST_n,
							PCIE1_REFCLK_p,
							PCIE1_RX_p,
							PCIE1_TX_p,
							PCIE1_WAKE_n,

							/////////PGM/////////
//							PGM_GXBCLK_p1,

							/////////mem_oct_rdn/////////
							mem_oct_rdn,

							/////////mem_oct_rup/////////
							mem_oct_rup,

							/////////SMA/////////
							SMA_CLKIN,
							SMA_CLKOUT,
							SMA_CLKOUT_n,
							SMA_CLKOUT_p,
//							SMA_GXBCLK_p,

							/////////SSRAM/////////
							SSRAM_ADSC_n,
							SSRAM_ADSP_n,
							SSRAM_ADV_n,
							SSRAM_BE_n,
							SSRAM_CE1_n,
							SSRAM_CLK,

							/////////SW/////////
							SW,

							/////////TEMP/////////
							TEMP_CLK,
							TEMP_DATA,
							TEMP_INT_n,
							TEMP_OVERT_n,
);

//=======================================================
//  PORT declarations
//=======================================================

							///////////BUTTON/////////////

input							[3:0]							BUTTON;

///////// FAN /////////
output																FAN_CTRL;
input															FAN_SPEED;

///////// FLASH /////////
output																FLASH_ADV_n;
output															FLASH_CE_n;
output															FLASH_CLK;
input															FLASH_RDY_BSY_n;
output															FLASH_RESET_n;
output															FLASH_WP_n;

///////// FSM /////////
output							[25:1]							FSM_A;
inout							[31:0]							FSM_D;
output															FSM_OE_n;
output															FSM_WE_n;

///////// HSMA /////////
input																HSMA_CLKIN0;
input															HSMA_CLKIN_n1;
input															HSMA_CLKIN_n2;
input															HSMA_CLKIN_p1;
input															HSMA_CLKIN_p2;
inout							[3:0]							HSMA_D;
//input							[7:0]							HSMA_GXB_RX_p;
//output							[7:0]							HSMA_GXB_TX_p;
inout															HSMA_OUT0;
inout															HSMA_OUT_n1;
inout															HSMA_OUT_n2;
inout															HSMA_OUT_p1;
inout															HSMA_OUT_p2;
//input															HSMA_REFCLK_p;
inout							[16:0]							HSMA_RX_n;
inout							[16:0]							HSMA_RX_p;
inout							[16:0]							HSMA_TX_n;
inout							[16:0]							HSMA_TX_p;

///////// HSMB /////////
input																HSMB_CLKIN0;
input															HSMB_CLKIN_n1;
input															HSMB_CLKIN_n2;
input															HSMB_CLKIN_p1;
input															HSMB_CLKIN_p2;
inout							[3:0]							HSMB_D;
inout															HSMB_OUT0;
inout															HSMB_OUT_n1;
inout															HSMB_OUT_n2;
inout															HSMB_OUT_p1;
inout															HSMB_OUT_p2;
inout							[16:0]							HSMB_RX_n;
inout							[16:0]							HSMB_RX_p;
output															HSMB_SCL;
inout															HSMB_SDA;
inout							[16:0]							HSMB_TX_n;
inout							[16:0]							HSMB_TX_p;

///////// HSMC /////////
input																HSMC_CLKIN0;
input															HSMC_CLKIN_n1;
input															HSMC_CLKIN_n2;
input															HSMC_CLKIN_p1;
input															HSMC_CLKIN_p2;
inout															HSMC_CLKOUT_n1;
inout															HSMC_CLKOUT_p1;
inout							[3:0]							HSMC_D;
inout															HSMC_OUT0;
inout															HSMC_OUT_n2;
inout															HSMC_OUT_p2;
inout							[16:0]							HSMC_RX_n;
inout							[16:0]							HSMC_RX_p;
inout							[16:0]							HSMC_TX_n;
inout							[16:0]							HSMC_TX_p;

///////// HSMD /////////
input																HSMD_CLKIN0;
input															HSMD_CLKIN_n1;
input															HSMD_CLKIN_n2;
input															HSMD_CLKIN_p1;
input															HSMD_CLKIN_p2;
inout															HSMD_CLKOUT_n1;
inout															HSMD_CLKOUT_p1;
inout							[3:0]							HSMD_D;
inout															HSMD_OUT0;
inout															HSMD_OUT_n2;
inout															HSMD_OUT_p2;
inout							[16:0]							HSMD_RX_n;
inout							[16:0]							HSMD_RX_p;
output															HSMD_SCL;
inout															HSMD_SDA;
inout							[16:0]							HSMD_TX_n;
inout							[16:0]							HSMD_TX_p;

///////// HSME /////////
input																HSME_CLKIN0;
input															HSME_CLKIN_n1;
input															HSME_CLKIN_n2;
input															HSME_CLKIN_p1;
input															HSME_CLKIN_p2;
inout															HSME_CLKOUT_n1;
inout															HSME_CLKOUT_p1;
inout							[3:0]							HSME_D;
//input							[7:0]							HSME_GXB_RX_p;
//output							[7:0]							HSME_GXB_TX_p;
inout															HSME_OUT0;
inout															HSME_OUT_n2;
inout															HSME_OUT_p2;
//input															HSME_REFCLK_p;
inout							[16:0]							HSME_RX_n;
inout							[16:0]							HSME_RX_p;
inout							[16:0]							HSME_TX_n;
inout							[16:0]							HSME_TX_p;

///////// HSMF /////////
input																HSMF_CLKIN0;
input															HSMF_CLKIN_n1;
input															HSMF_CLKIN_n2;
input															HSMF_CLKIN_p1;
input															HSMF_CLKIN_p2;
inout															HSMF_CLKOUT_n1;
inout															HSMF_CLKOUT_n2;
inout															HSMF_CLKOUT_p1;
inout															HSMF_CLKOUT_p2;
inout							[3:0]							HSMF_D;
inout															HSMF_OUT0;
inout							[16:0]							HSMF_RX_n;
inout							[16:0]							HSMF_RX_p;
inout							[16:0]							HSMF_TX_n;
inout							[16:0]							HSMF_TX_p;

///////// LED /////////
output							[3:0]							LED;

///////// LOOP /////////
input																LOOP_CLKIN0;
output															LOOP_CLKOUT0;
input															LOOP_CLKIN1;
output															LOOP_CLKOUT1;

///////// MAX2 /////////
output																MAX2_CS_n;
output															MAX2_I2C_SCL;
inout															MAX2_I2C_SDA;

///////// mem /////////
//output							[15:0]							mem_a;
//output							[2:0]							mem_ba;
//output															mem_cas_n;
//output							[1:0]							mem_cke;
//output							[1:0]							mem_ck;
//output							[1:0]							mem_ck_n;
//output							[1:0]							mem_cs_n;
//output							[7:0]							mem_dm;
//inout							[63:0]							mem_dq;
//inout							[7:0]							mem_dqs;
//inout							[7:0]							mem_dqs_n;
//input															mem_event_n;
//output							[1:0]							mem_odt;
//output															mem_ras_n;
//output															mem_reset_n;
//output															mem_scl;
//inout															mem_sda;
//output															mem_we_n;

///////// OSC /////////
input																OSC_50_BANK1;
input															OSC_50_BANK3;
input															OSC_50_BANK4;
input															OSC_50_BANK7;
input															OSC_50_BANK8;

///////// PCIE0 /////////
input																PCIE0_pREST_n;
input															PCIE0_REFCLK_p;
input							[3:0]							PCIE0_RX_p;
output							[3:0]							PCIE0_TX_p;
output															PCIE0_WAKE_n;

/////// PCIE1 /////////
input																PCIE1_pREST_n;
input															PCIE1_REFCLK_p;
input							[3:0]							PCIE1_RX_p;
output							[3:0]							PCIE1_TX_p;
output															PCIE1_WAKE_n;

///////// PGM /////////
//input																PGM_GXBCLK_p1;

///////// mem_oct_rdn /////////
input																mem_oct_rdn;

///////// mem_oct_rup /////////
input																mem_oct_rup;

///////// SMA /////////
input																SMA_CLKIN;
output															SMA_CLKOUT;
output															SMA_CLKOUT_n;
output															SMA_CLKOUT_p;
//input															SMA_GXBCLK_p;

///////// SSRAM /////////
output																SSRAM_ADSC_n;
output															SSRAM_ADSP_n;
output															SSRAM_ADV_n;
output							[3:0]							SSRAM_BE_n;
output															SSRAM_CE1_n;
output															SSRAM_CLK;

///////// SW /////////
input							[3:0]							SW;

///////// TEMP /////////
output																TEMP_CLK;
inout															TEMP_DATA;
input															TEMP_INT_n;
input															TEMP_OVERT_n;

//=======================================================
//  REG/WIRE declarations
//=======================================================
wire	[7:0]		test_error;
//wire			cal_blk_clk;
//wire			CLK425;
//wire			CLK4250;
//=======================================================
//  Structural coding
//=======================================================

assign FAN_CTRL = 1;

/////////////////////////////////////////////////////////////////////

// PCIE 1 TX 0 ------ PCIE 0 ---RX   0
xcvr_test g1(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE0_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE0_TX_p[0]),
.xcvr_rx(PCIE0_RX_p[0]),
.error_insert(BUTTON[1]),
.test_error(test_error[0]),
.tx_clock(),

);

xcvr_test g2(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE0_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE0_TX_p[1]),
.xcvr_rx(PCIE0_RX_p[1]),
.error_insert(BUTTON[1]),
.test_error(test_error[1]),
.tx_clock(),

);

xcvr_test g3(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE0_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE0_TX_p[2]),
.xcvr_rx(PCIE0_RX_p[2]),
.error_insert(BUTTON[1]),
.test_error(test_error[2]),
.tx_clock(),

);

xcvr_test g4(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE0_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE0_TX_p[3]),
.xcvr_rx(PCIE0_RX_p[3]),
.error_insert(BUTTON[1]),
.test_error(test_error[3]),
.tx_clock(),

);

assign PCIE0_WAKE_n = SW[0];

//assign	LED[0]=!test_error[0];
//assign	LED[1]=!test_error[1];
//assign	LED[2]=!test_error[2];
//assign	LED[3]=!test_error[3];
assign LED[0] =  (!test_error[0])&(!test_error[1])&(!test_error[2])&(!test_error[3]);
assign LED[1] =   PCIE0_pREST_n; //xor

//PCIe1
xcvr_test g5(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE1_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE1_TX_p[0]),
.xcvr_rx(PCIE1_RX_p[0]),
.error_insert(BUTTON[1]),
.test_error(test_error[4]),
.tx_clock(),

);

xcvr_test g6(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE1_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE1_TX_p[1]),
.xcvr_rx(PCIE1_RX_p[1]),
.error_insert(BUTTON[1]),
.test_error(test_error[5]),
.tx_clock(),

);

xcvr_test g7(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE1_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE1_TX_p[2]),
.xcvr_rx(PCIE1_RX_p[2]),
.error_insert(BUTTON[1]),
.test_error(test_error[6]),
.tx_clock(),

);

xcvr_test g8(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(PCIE1_REFCLK_p),
.irst_n(BUTTON[0]),
.xcvr_tx(PCIE1_TX_p[3]),
.xcvr_rx(PCIE1_RX_p[3]),
.error_insert(BUTTON[1]),
.test_error(test_error[7]),
.tx_clock(),

);

assign PCIE1_WAKE_n = SW[1];


assign LED[2] =  (!test_error[4])&(!test_error[5])&(!test_error[6])&(!test_error[7]);
assign LED[3] =  !PCIE1_pREST_n;
endmodule
