// TR4_QSYS.v


`timescale 1 ps / 1 ps
module TR4_QSYS (
		output wire        alt_vip_itc_0_clocked_video_underflow,              // alt_vip_itc_0_clocked_video.underflow
		output wire [23:0] alt_vip_itc_0_clocked_video_vid_data,               //                            .vid_data
		output wire        alt_vip_itc_0_clocked_video_vid_v_sync,             //                            .vid_v_sync
		output wire        alt_vip_itc_0_clocked_video_vid_h,                  //                            .vid_h
		output wire        alt_vip_itc_0_clocked_video_vid_h_sync,             //                            .vid_h_sync
		input  wire        alt_vip_itc_0_clocked_video_vid_clk,                //                            .vid_clk
		output wire        alt_vip_itc_0_clocked_video_vid_f,                  //                            .vid_f
		output wire        alt_vip_itc_0_clocked_video_vid_datavalid,          //                            .vid_datavalid
		output wire        alt_vip_itc_0_clocked_video_vid_v,                  //                            .vid_v
		input  wire        oct_rup,                                            //                         oct.rup
		input  wire        oct_rdn,                                            //                            .rdn
		input  wire        external_reset_reset_n,                             //              external_reset.reset_n
		output wire [5:0]  uniphy_ddr3_dll_sharing_dll_delayctrl,              //     uniphy_ddr3_dll_sharing.dll_delayctrl
		output wire        uniphy_ddr3_local_powerdown_local_powerdn_ack,      // uniphy_ddr3_local_powerdown.local_powerdn_ack
		input  wire        uniphy_ddr3_local_powerdown_local_powerdn_req,      //                            .local_powerdn_req
		output wire [13:0] uniphy_ddr3_oct_sharing_parallelterminationcontrol, //     uniphy_ddr3_oct_sharing.parallelterminationcontrol
		output wire [13:0] uniphy_ddr3_oct_sharing_seriesterminationcontrol,   //                            .seriesterminationcontrol
		output wire        uniphy_ddr3_pll_sharing_pll_write_clk,              //     uniphy_ddr3_pll_sharing.pll_write_clk
		output wire        uniphy_ddr3_pll_sharing_pll_addr_cmd_clk,           //                            .pll_addr_cmd_clk
		output wire        uniphy_ddr3_pll_sharing_pll_config_clk,             //                            .pll_config_clk
		output wire        uniphy_ddr3_pll_sharing_pll_mem_clk,                //                            .pll_mem_clk
		output wire        uniphy_ddr3_pll_sharing_pll_locked,                 //                            .pll_locked
		output wire        uniphy_ddr3_pll_sharing_pll_avl_clk,                //                            .pll_avl_clk
		output wire        uniphy_ddr3_status_local_cal_fail,                  //          uniphy_ddr3_status.local_cal_fail
		output wire        uniphy_ddr3_status_local_init_done,                 //                            .local_init_done
		output wire        uniphy_ddr3_status_local_cal_success,               //                            .local_cal_success
		input  wire        external_clk50_clk,                                 //              external_clk50.clk
		output wire        memory_mem_cs_n,                                    //                      memory.mem_cs_n
		output wire        memory_mem_ras_n,                                   //                            .mem_ras_n
		output wire [1:0]  memory_mem_ck_n,                                    //                            .mem_ck_n
		output wire [13:0] memory_mem_a,                                       //                            .mem_a
		inout  wire [7:0]  memory_mem_dqs_n,                                   //                            .mem_dqs_n
		output wire        memory_mem_cke,                                     //                            .mem_cke
		inout  wire [63:0] memory_mem_dq,                                      //                            .mem_dq
		output wire [2:0]  memory_mem_ba,                                      //                            .mem_ba
		output wire        memory_mem_odt,                                     //                            .mem_odt
		inout  wire [7:0]  memory_mem_dqs,                                     //                            .mem_dqs
		output wire        memory_mem_cas_n,                                   //                            .mem_cas_n
		output wire [7:0]  memory_mem_dm,                                      //                            .mem_dm
		output wire        memory_mem_we_n,                                    //                            .mem_we_n
		output wire        memory_mem_reset_n,                                 //                            .mem_reset_n
		output wire [1:0]  memory_mem_ck,                                      //                            .mem_ck
		input  wire        alt_vip_cti_0_clocked_video_vid_clk,                // alt_vip_cti_0_clocked_video.vid_clk
		output wire        alt_vip_cti_0_clocked_video_overflow,               //                            .overflow
		input  wire        alt_vip_cti_0_clocked_video_vid_f,                  //                            .vid_f
		input  wire        alt_vip_cti_0_clocked_video_vid_h_sync,             //                            .vid_h_sync
		input  wire        alt_vip_cti_0_clocked_video_vid_datavalid,          //                            .vid_datavalid
		input  wire        alt_vip_cti_0_clocked_video_vid_v_sync,             //                            .vid_v_sync
		input  wire [23:0] alt_vip_cti_0_clocked_video_vid_data,               //                            .vid_data
		input  wire        alt_vip_cti_0_clocked_video_vid_locked              //                            .vid_locked
	);

	wire          alt_vip_cti_0_dout_endofpacket;                                                        // alt_vip_cti_0:is_eop -> frame_buffer:din_endofpacket
	wire          alt_vip_cti_0_dout_valid;                                                              // alt_vip_cti_0:is_valid -> frame_buffer:din_valid
	wire          alt_vip_cti_0_dout_startofpacket;                                                      // alt_vip_cti_0:is_sop -> frame_buffer:din_startofpacket
	wire   [23:0] alt_vip_cti_0_dout_data;                                                               // alt_vip_cti_0:is_data -> frame_buffer:din_data
	wire          alt_vip_cti_0_dout_ready;                                                              // frame_buffer:din_ready -> alt_vip_cti_0:is_ready
	wire          frame_buffer_dout_endofpacket;                                                         // frame_buffer:dout_endofpacket -> alt_vip_itc_0:is_eop
	wire          frame_buffer_dout_valid;                                                               // frame_buffer:dout_valid -> alt_vip_itc_0:is_valid
	wire          frame_buffer_dout_startofpacket;                                                       // frame_buffer:dout_startofpacket -> alt_vip_itc_0:is_sop
	wire   [23:0] frame_buffer_dout_data;                                                                // frame_buffer:dout_data -> alt_vip_itc_0:is_data
	wire          frame_buffer_dout_ready;                                                               // alt_vip_itc_0:is_ready -> frame_buffer:dout_ready
	wire          uniphy_ddr3_afi_half_clk_clk;                                                          // uniphy_ddr3:afi_half_clk -> [addr_router:clk, addr_router_001:clk, alt_vip_cti_0:is_clk, alt_vip_itc_0:is_clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, crosser:in_clk, crosser_001:in_clk, crosser_002:out_clk, crosser_003:out_clk, frame_buffer:clock, frame_buffer_read_master_translator:clk, frame_buffer_read_master_translator_avalon_universal_master_0_agent:clk, frame_buffer_write_master_translator:clk, frame_buffer_write_master_translator_avalon_universal_master_0_agent:clk, rst_controller:clk]
	wire    [6:0] frame_buffer_read_master_burstcount;                                                   // frame_buffer:read_master_av_burstcount -> frame_buffer_read_master_translator:av_burstcount
	wire          frame_buffer_read_master_waitrequest;                                                  // frame_buffer_read_master_translator:av_waitrequest -> frame_buffer:read_master_av_waitrequest
	wire   [31:0] frame_buffer_read_master_address;                                                      // frame_buffer:read_master_av_address -> frame_buffer_read_master_translator:av_address
	wire          frame_buffer_read_master_read;                                                         // frame_buffer:read_master_av_read -> frame_buffer_read_master_translator:av_read
	wire   [63:0] frame_buffer_read_master_readdata;                                                     // frame_buffer_read_master_translator:av_readdata -> frame_buffer:read_master_av_readdata
	wire          frame_buffer_read_master_readdatavalid;                                                // frame_buffer_read_master_translator:av_readdatavalid -> frame_buffer:read_master_av_readdatavalid
	wire    [6:0] frame_buffer_write_master_burstcount;                                                  // frame_buffer:write_master_av_burstcount -> frame_buffer_write_master_translator:av_burstcount
	wire          frame_buffer_write_master_waitrequest;                                                 // frame_buffer_write_master_translator:av_waitrequest -> frame_buffer:write_master_av_waitrequest
	wire   [63:0] frame_buffer_write_master_writedata;                                                   // frame_buffer:write_master_av_writedata -> frame_buffer_write_master_translator:av_writedata
	wire   [31:0] frame_buffer_write_master_address;                                                     // frame_buffer:write_master_av_address -> frame_buffer_write_master_translator:av_address
	wire          frame_buffer_write_master_write;                                                       // frame_buffer:write_master_av_write -> frame_buffer_write_master_translator:av_write
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_waitrequest;                            // uniphy_ddr3:avl_ready -> uniphy_ddr3_avl_translator:av_waitrequest
	wire    [3:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_burstcount;                             // uniphy_ddr3_avl_translator:av_burstcount -> uniphy_ddr3:avl_size
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_writedata;                              // uniphy_ddr3_avl_translator:av_writedata -> uniphy_ddr3:avl_wdata
	wire   [24:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_address;                                // uniphy_ddr3_avl_translator:av_address -> uniphy_ddr3:avl_addr
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_write;                                  // uniphy_ddr3_avl_translator:av_write -> uniphy_ddr3:avl_write_req
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_beginbursttransfer;                     // uniphy_ddr3_avl_translator:av_beginbursttransfer -> uniphy_ddr3:avl_burstbegin
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_read;                                   // uniphy_ddr3_avl_translator:av_read -> uniphy_ddr3:avl_read_req
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdata;                               // uniphy_ddr3:avl_rdata -> uniphy_ddr3_avl_translator:av_readdata
	wire          uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdatavalid;                          // uniphy_ddr3:avl_rdata_valid -> uniphy_ddr3_avl_translator:av_readdatavalid
	wire   [31:0] uniphy_ddr3_avl_translator_avalon_anti_slave_0_byteenable;                             // uniphy_ddr3_avl_translator:av_byteenable -> uniphy_ddr3:avl_be
	wire          uniphy_ddr3_afi_clk_clk;                                                               // uniphy_ddr3:afi_clk -> [burst_adapter:clk, cmd_xbar_mux:clk, crosser:out_clk, crosser_001:out_clk, crosser_002:in_clk, crosser_003:in_clk, id_router:clk, rsp_xbar_demux:clk, rst_controller_001:clk, uniphy_ddr3_avl_translator:clk, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:clk, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk]
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_waitrequest;             // frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_waitrequest -> frame_buffer_read_master_translator:uav_waitrequest
	wire    [9:0] frame_buffer_read_master_translator_avalon_universal_master_0_burstcount;              // frame_buffer_read_master_translator:uav_burstcount -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [63:0] frame_buffer_read_master_translator_avalon_universal_master_0_writedata;               // frame_buffer_read_master_translator:uav_writedata -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] frame_buffer_read_master_translator_avalon_universal_master_0_address;                 // frame_buffer_read_master_translator:uav_address -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_address
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_lock;                    // frame_buffer_read_master_translator:uav_lock -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_lock
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_write;                   // frame_buffer_read_master_translator:uav_write -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_write
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_read;                    // frame_buffer_read_master_translator:uav_read -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_read
	wire   [63:0] frame_buffer_read_master_translator_avalon_universal_master_0_readdata;                // frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_readdata -> frame_buffer_read_master_translator:uav_readdata
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_debugaccess;             // frame_buffer_read_master_translator:uav_debugaccess -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [7:0] frame_buffer_read_master_translator_avalon_universal_master_0_byteenable;              // frame_buffer_read_master_translator:uav_byteenable -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_readdatavalid;           // frame_buffer_read_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> frame_buffer_read_master_translator:uav_readdatavalid
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_waitrequest;            // frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_waitrequest -> frame_buffer_write_master_translator:uav_waitrequest
	wire    [9:0] frame_buffer_write_master_translator_avalon_universal_master_0_burstcount;             // frame_buffer_write_master_translator:uav_burstcount -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire   [63:0] frame_buffer_write_master_translator_avalon_universal_master_0_writedata;              // frame_buffer_write_master_translator:uav_writedata -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_writedata
	wire   [31:0] frame_buffer_write_master_translator_avalon_universal_master_0_address;                // frame_buffer_write_master_translator:uav_address -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_address
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_lock;                   // frame_buffer_write_master_translator:uav_lock -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_lock
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_write;                  // frame_buffer_write_master_translator:uav_write -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_write
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_read;                   // frame_buffer_write_master_translator:uav_read -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_read
	wire   [63:0] frame_buffer_write_master_translator_avalon_universal_master_0_readdata;               // frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_readdata -> frame_buffer_write_master_translator:uav_readdata
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_debugaccess;            // frame_buffer_write_master_translator:uav_debugaccess -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire    [7:0] frame_buffer_write_master_translator_avalon_universal_master_0_byteenable;             // frame_buffer_write_master_translator:uav_byteenable -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_readdatavalid;          // frame_buffer_write_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> frame_buffer_write_master_translator:uav_readdatavalid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;              // uniphy_ddr3_avl_translator:uav_waitrequest -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire    [8:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;               // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> uniphy_ddr3_avl_translator:uav_burstcount
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> uniphy_ddr3_avl_translator:uav_writedata
	wire   [31:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_address;                  // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_address -> uniphy_ddr3_avl_translator:uav_address
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_write;                    // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_write -> uniphy_ddr3_avl_translator:uav_write
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_lock;                     // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_lock -> uniphy_ddr3_avl_translator:uav_lock
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_read;                     // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_read -> uniphy_ddr3_avl_translator:uav_read
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                 // uniphy_ddr3_avl_translator:uav_readdata -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;            // uniphy_ddr3_avl_translator:uav_readdatavalid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;              // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> uniphy_ddr3_avl_translator:uav_debugaccess
	wire   [31:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;               // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> uniphy_ddr3_avl_translator:uav_byteenable
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;       // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;             // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;     // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [351:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_data;              // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;             // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;    // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;          // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;  // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [351:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;           // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;          // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;        // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;         // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;        // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid;        // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [255:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data;         // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready;        // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket;    // frame_buffer_read_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_valid;          // frame_buffer_read_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket;  // frame_buffer_read_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
	wire  [134:0] frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_data;           // frame_buffer_read_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
	wire          frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_ready;          // addr_router:sink_ready -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket;   // frame_buffer_write_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_valid;         // frame_buffer_write_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // frame_buffer_write_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
	wire  [134:0] frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_data;          // frame_buffer_write_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
	wire          frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_ready;         // addr_router_001:sink_ready -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:cp_ready
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;              // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_valid;                    // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;            // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
	wire  [350:0] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_data;                     // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
	wire          uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_ready;                    // id_router:sink_ready -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire          burst_adapter_source0_endofpacket;                                                     // burst_adapter:source0_endofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire          burst_adapter_source0_valid;                                                           // burst_adapter:source0_valid -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire          burst_adapter_source0_startofpacket;                                                   // burst_adapter:source0_startofpacket -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [350:0] burst_adapter_source0_data;                                                            // burst_adapter:source0_data -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire          burst_adapter_source0_ready;                                                           // uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
	wire    [1:0] burst_adapter_source0_channel;                                                         // burst_adapter:source0_channel -> uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire          rst_controller_reset_out_reset;                                                        // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, alt_vip_cti_0:rst, alt_vip_itc_0:rst, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, crosser:in_reset, crosser_001:in_reset, crosser_002:out_reset, crosser_003:out_reset, frame_buffer:reset, frame_buffer_read_master_translator:reset, frame_buffer_read_master_translator_avalon_universal_master_0_agent:reset, frame_buffer_write_master_translator:reset, frame_buffer_write_master_translator_avalon_universal_master_0_agent:reset]
	wire          uniphy_ddr3_afi_reset_reset;                                                           // uniphy_ddr3:afi_reset_n -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
	wire          rst_controller_001_reset_out_reset;                                                    // rst_controller_001:reset_out -> [burst_adapter:reset, cmd_xbar_mux:reset, crosser:out_reset, crosser_001:out_reset, crosser_002:in_reset, crosser_003:in_reset, id_router:reset, rsp_xbar_demux:reset, uniphy_ddr3_avl_translator:reset, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent:reset, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset]
	wire          addr_router_src_endofpacket;                                                           // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire          addr_router_src_valid;                                                                 // addr_router:src_valid -> cmd_xbar_demux:sink_valid
	wire          addr_router_src_startofpacket;                                                         // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [134:0] addr_router_src_data;                                                                  // addr_router:src_data -> cmd_xbar_demux:sink_data
	wire    [1:0] addr_router_src_channel;                                                               // addr_router:src_channel -> cmd_xbar_demux:sink_channel
	wire          addr_router_src_ready;                                                                 // cmd_xbar_demux:sink_ready -> addr_router:src_ready
	wire          crosser_002_out_ready;                                                                 // frame_buffer_read_master_translator_avalon_universal_master_0_agent:rp_ready -> crosser_002:out_ready
	wire          addr_router_001_src_endofpacket;                                                       // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire          addr_router_001_src_valid;                                                             // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
	wire          addr_router_001_src_startofpacket;                                                     // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire  [134:0] addr_router_001_src_data;                                                              // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
	wire    [1:0] addr_router_001_src_channel;                                                           // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
	wire          addr_router_001_src_ready;                                                             // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
	wire          crosser_003_out_ready;                                                                 // frame_buffer_write_master_translator_avalon_universal_master_0_agent:rp_ready -> crosser_003:out_ready
	wire          cmd_xbar_mux_src_endofpacket;                                                          // cmd_xbar_mux:src_endofpacket -> width_adapter:in_endofpacket
	wire          cmd_xbar_mux_src_valid;                                                                // cmd_xbar_mux:src_valid -> width_adapter:in_valid
	wire          cmd_xbar_mux_src_startofpacket;                                                        // cmd_xbar_mux:src_startofpacket -> width_adapter:in_startofpacket
	wire  [134:0] cmd_xbar_mux_src_data;                                                                 // cmd_xbar_mux:src_data -> width_adapter:in_data
	wire    [1:0] cmd_xbar_mux_src_channel;                                                              // cmd_xbar_mux:src_channel -> width_adapter:in_channel
	wire          cmd_xbar_mux_src_ready;                                                                // width_adapter:in_ready -> cmd_xbar_mux:src_ready
	wire          width_adapter_src_endofpacket;                                                         // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
	wire          width_adapter_src_valid;                                                               // width_adapter:out_valid -> burst_adapter:sink0_valid
	wire          width_adapter_src_startofpacket;                                                       // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
	wire  [350:0] width_adapter_src_data;                                                                // width_adapter:out_data -> burst_adapter:sink0_data
	wire          width_adapter_src_ready;                                                               // burst_adapter:sink0_ready -> width_adapter:out_ready
	wire    [1:0] width_adapter_src_channel;                                                             // width_adapter:out_channel -> burst_adapter:sink0_channel
	wire          id_router_src_endofpacket;                                                             // id_router:src_endofpacket -> width_adapter_001:in_endofpacket
	wire          id_router_src_valid;                                                                   // id_router:src_valid -> width_adapter_001:in_valid
	wire          id_router_src_startofpacket;                                                           // id_router:src_startofpacket -> width_adapter_001:in_startofpacket
	wire  [350:0] id_router_src_data;                                                                    // id_router:src_data -> width_adapter_001:in_data
	wire    [1:0] id_router_src_channel;                                                                 // id_router:src_channel -> width_adapter_001:in_channel
	wire          id_router_src_ready;                                                                   // width_adapter_001:in_ready -> id_router:src_ready
	wire          width_adapter_001_src_endofpacket;                                                     // width_adapter_001:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire          width_adapter_001_src_valid;                                                           // width_adapter_001:out_valid -> rsp_xbar_demux:sink_valid
	wire          width_adapter_001_src_startofpacket;                                                   // width_adapter_001:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [134:0] width_adapter_001_src_data;                                                            // width_adapter_001:out_data -> rsp_xbar_demux:sink_data
	wire          width_adapter_001_src_ready;                                                           // rsp_xbar_demux:sink_ready -> width_adapter_001:out_ready
	wire    [1:0] width_adapter_001_src_channel;                                                         // width_adapter_001:out_channel -> rsp_xbar_demux:sink_channel
	wire          crosser_out_endofpacket;                                                               // crosser:out_endofpacket -> cmd_xbar_mux:sink0_endofpacket
	wire          crosser_out_valid;                                                                     // crosser:out_valid -> cmd_xbar_mux:sink0_valid
	wire          crosser_out_startofpacket;                                                             // crosser:out_startofpacket -> cmd_xbar_mux:sink0_startofpacket
	wire  [134:0] crosser_out_data;                                                                      // crosser:out_data -> cmd_xbar_mux:sink0_data
	wire    [1:0] crosser_out_channel;                                                                   // crosser:out_channel -> cmd_xbar_mux:sink0_channel
	wire          crosser_out_ready;                                                                     // cmd_xbar_mux:sink0_ready -> crosser:out_ready
	wire          cmd_xbar_demux_src0_endofpacket;                                                       // cmd_xbar_demux:src0_endofpacket -> crosser:in_endofpacket
	wire          cmd_xbar_demux_src0_valid;                                                             // cmd_xbar_demux:src0_valid -> crosser:in_valid
	wire          cmd_xbar_demux_src0_startofpacket;                                                     // cmd_xbar_demux:src0_startofpacket -> crosser:in_startofpacket
	wire  [134:0] cmd_xbar_demux_src0_data;                                                              // cmd_xbar_demux:src0_data -> crosser:in_data
	wire    [1:0] cmd_xbar_demux_src0_channel;                                                           // cmd_xbar_demux:src0_channel -> crosser:in_channel
	wire          cmd_xbar_demux_src0_ready;                                                             // crosser:in_ready -> cmd_xbar_demux:src0_ready
	wire          crosser_001_out_endofpacket;                                                           // crosser_001:out_endofpacket -> cmd_xbar_mux:sink1_endofpacket
	wire          crosser_001_out_valid;                                                                 // crosser_001:out_valid -> cmd_xbar_mux:sink1_valid
	wire          crosser_001_out_startofpacket;                                                         // crosser_001:out_startofpacket -> cmd_xbar_mux:sink1_startofpacket
	wire  [134:0] crosser_001_out_data;                                                                  // crosser_001:out_data -> cmd_xbar_mux:sink1_data
	wire    [1:0] crosser_001_out_channel;                                                               // crosser_001:out_channel -> cmd_xbar_mux:sink1_channel
	wire          crosser_001_out_ready;                                                                 // cmd_xbar_mux:sink1_ready -> crosser_001:out_ready
	wire          cmd_xbar_demux_001_src0_endofpacket;                                                   // cmd_xbar_demux_001:src0_endofpacket -> crosser_001:in_endofpacket
	wire          cmd_xbar_demux_001_src0_valid;                                                         // cmd_xbar_demux_001:src0_valid -> crosser_001:in_valid
	wire          cmd_xbar_demux_001_src0_startofpacket;                                                 // cmd_xbar_demux_001:src0_startofpacket -> crosser_001:in_startofpacket
	wire  [134:0] cmd_xbar_demux_001_src0_data;                                                          // cmd_xbar_demux_001:src0_data -> crosser_001:in_data
	wire    [1:0] cmd_xbar_demux_001_src0_channel;                                                       // cmd_xbar_demux_001:src0_channel -> crosser_001:in_channel
	wire          cmd_xbar_demux_001_src0_ready;                                                         // crosser_001:in_ready -> cmd_xbar_demux_001:src0_ready
	wire          crosser_002_out_endofpacket;                                                           // crosser_002:out_endofpacket -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          crosser_002_out_valid;                                                                 // crosser_002:out_valid -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          crosser_002_out_startofpacket;                                                         // crosser_002:out_startofpacket -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [134:0] crosser_002_out_data;                                                                  // crosser_002:out_data -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [1:0] crosser_002_out_channel;                                                               // crosser_002:out_channel -> frame_buffer_read_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          rsp_xbar_demux_src0_endofpacket;                                                       // rsp_xbar_demux:src0_endofpacket -> crosser_002:in_endofpacket
	wire          rsp_xbar_demux_src0_valid;                                                             // rsp_xbar_demux:src0_valid -> crosser_002:in_valid
	wire          rsp_xbar_demux_src0_startofpacket;                                                     // rsp_xbar_demux:src0_startofpacket -> crosser_002:in_startofpacket
	wire  [134:0] rsp_xbar_demux_src0_data;                                                              // rsp_xbar_demux:src0_data -> crosser_002:in_data
	wire    [1:0] rsp_xbar_demux_src0_channel;                                                           // rsp_xbar_demux:src0_channel -> crosser_002:in_channel
	wire          rsp_xbar_demux_src0_ready;                                                             // crosser_002:in_ready -> rsp_xbar_demux:src0_ready
	wire          crosser_003_out_endofpacket;                                                           // crosser_003:out_endofpacket -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire          crosser_003_out_valid;                                                                 // crosser_003:out_valid -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:rp_valid
	wire          crosser_003_out_startofpacket;                                                         // crosser_003:out_startofpacket -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [134:0] crosser_003_out_data;                                                                  // crosser_003:out_data -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:rp_data
	wire    [1:0] crosser_003_out_channel;                                                               // crosser_003:out_channel -> frame_buffer_write_master_translator_avalon_universal_master_0_agent:rp_channel
	wire          rsp_xbar_demux_src1_endofpacket;                                                       // rsp_xbar_demux:src1_endofpacket -> crosser_003:in_endofpacket
	wire          rsp_xbar_demux_src1_valid;                                                             // rsp_xbar_demux:src1_valid -> crosser_003:in_valid
	wire          rsp_xbar_demux_src1_startofpacket;                                                     // rsp_xbar_demux:src1_startofpacket -> crosser_003:in_startofpacket
	wire  [134:0] rsp_xbar_demux_src1_data;                                                              // rsp_xbar_demux:src1_data -> crosser_003:in_data
	wire    [1:0] rsp_xbar_demux_src1_channel;                                                           // rsp_xbar_demux:src1_channel -> crosser_003:in_channel
	wire          rsp_xbar_demux_src1_ready;                                                             // crosser_003:in_ready -> rsp_xbar_demux:src1_ready

	TR4_QSYS_uniphy_ddr3 uniphy_ddr3 (
		.pll_ref_clk                (external_clk50_clk),                                                //     pll_ref_clk.clk
		.global_reset_n             (external_reset_reset_n),                                            //    global_reset.reset_n
		.soft_reset_n               (external_reset_reset_n),                                            //      soft_reset.reset_n
		.afi_clk                    (uniphy_ddr3_afi_clk_clk),                                           //         afi_clk.clk
		.afi_half_clk               (uniphy_ddr3_afi_half_clk_clk),                                      //    afi_half_clk.clk
		.afi_reset_n                (uniphy_ddr3_afi_reset_reset),                                       //       afi_reset.reset_n
		.mem_dqs_n                  (memory_mem_dqs_n),                                                  //          memory.mem_dqs_n
		.mem_cke                    (memory_mem_cke),                                                    //                .mem_cke
		.mem_reset_n                (memory_mem_reset_n),                                                //                .mem_reset_n
		.mem_a                      (memory_mem_a),                                                      //                .mem_a
		.mem_ras_n                  (memory_mem_ras_n),                                                  //                .mem_ras_n
		.mem_dqs                    (memory_mem_dqs),                                                    //                .mem_dqs
		.mem_dm                     (memory_mem_dm),                                                     //                .mem_dm
		.mem_ba                     (memory_mem_ba),                                                     //                .mem_ba
		.mem_odt                    (memory_mem_odt),                                                    //                .mem_odt
		.mem_we_n                   (memory_mem_we_n),                                                   //                .mem_we_n
		.mem_ck_n                   (memory_mem_ck_n),                                                   //                .mem_ck_n
		.mem_ck                     (memory_mem_ck),                                                     //                .mem_ck
		.mem_cs_n                   (memory_mem_cs_n),                                                   //                .mem_cs_n
		.mem_cas_n                  (memory_mem_cas_n),                                                  //                .mem_cas_n
		.mem_dq                     (memory_mem_dq),                                                     //                .mem_dq
		.avl_ready                  (uniphy_ddr3_avl_translator_avalon_anti_slave_0_waitrequest),        //             avl.waitrequest_n
		.avl_burstbegin             (uniphy_ddr3_avl_translator_avalon_anti_slave_0_beginbursttransfer), //                .beginbursttransfer
		.avl_addr                   (uniphy_ddr3_avl_translator_avalon_anti_slave_0_address),            //                .address
		.avl_rdata_valid            (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdatavalid),      //                .readdatavalid
		.avl_rdata                  (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdata),           //                .readdata
		.avl_wdata                  (uniphy_ddr3_avl_translator_avalon_anti_slave_0_writedata),          //                .writedata
		.avl_be                     (uniphy_ddr3_avl_translator_avalon_anti_slave_0_byteenable),         //                .byteenable
		.avl_read_req               (uniphy_ddr3_avl_translator_avalon_anti_slave_0_read),               //                .read
		.avl_write_req              (uniphy_ddr3_avl_translator_avalon_anti_slave_0_write),              //                .write
		.avl_size                   (uniphy_ddr3_avl_translator_avalon_anti_slave_0_burstcount),         //                .burstcount
		.local_cal_success          (uniphy_ddr3_status_local_cal_success),                              //          status.local_cal_success
		.local_init_done            (uniphy_ddr3_status_local_init_done),                                //                .local_init_done
		.local_cal_fail             (uniphy_ddr3_status_local_cal_fail),                                 //                .local_cal_fail
		.oct_rdn                    (oct_rdn),                                                           //             oct.rdn
		.oct_rup                    (oct_rup),                                                           //                .rup
		.seriesterminationcontrol   (uniphy_ddr3_oct_sharing_seriesterminationcontrol),                  //     oct_sharing.seriesterminationcontrol
		.parallelterminationcontrol (uniphy_ddr3_oct_sharing_parallelterminationcontrol),                //                .parallelterminationcontrol
		.pll_addr_cmd_clk           (uniphy_ddr3_pll_sharing_pll_addr_cmd_clk),                          //     pll_sharing.pll_addr_cmd_clk
		.pll_mem_clk                (uniphy_ddr3_pll_sharing_pll_mem_clk),                               //                .pll_mem_clk
		.pll_avl_clk                (uniphy_ddr3_pll_sharing_pll_avl_clk),                               //                .pll_avl_clk
		.pll_write_clk              (uniphy_ddr3_pll_sharing_pll_write_clk),                             //                .pll_write_clk
		.pll_config_clk             (uniphy_ddr3_pll_sharing_pll_config_clk),                            //                .pll_config_clk
		.pll_locked                 (uniphy_ddr3_pll_sharing_pll_locked),                                //                .pll_locked
		.dll_delayctrl              (uniphy_ddr3_dll_sharing_dll_delayctrl),                             //     dll_sharing.dll_delayctrl
		.local_powerdn_req          (uniphy_ddr3_local_powerdown_local_powerdn_req),                     // local_powerdown.local_powerdn_req
		.local_powerdn_ack          (uniphy_ddr3_local_powerdown_local_powerdn_ack)                      //                .local_powerdn_ack
	);

	alt_vipcti110_Vid2IS #(
		.BPS                           (8),
		.NUMBER_OF_COLOUR_PLANES       (3),
		.COLOUR_PLANES_ARE_IN_PARALLEL (1),
		.SYNC_TO                       (2),
		.USE_EMBEDDED_SYNCS            (0),
		.ACCEPT_COLOURS_IN_SEQ         (0),
		.USE_STD                       (0),
		.STD_WIDTH                     (1),
		.GENERATE_ANC                  (0),
		.INTERLACED                    (0),
		.H_ACTIVE_PIXELS_F0            (800),
		.V_ACTIVE_LINES_F0             (600),
		.V_ACTIVE_LINES_F1             (32),
		.FIFO_DEPTH                    (4800),
		.CLOCKS_ARE_SAME               (0),
		.USE_CONTROL                   (0),
		.GENERATE_SYNC                 (0)
	) alt_vip_cti_0 (
		.is_clk        (uniphy_ddr3_afi_half_clk_clk),              //       is_clk_rst.clk
		.rst           (rst_controller_reset_out_reset),            // is_clk_rst_reset.reset
		.is_data       (alt_vip_cti_0_dout_data),                   //             dout.data
		.is_valid      (alt_vip_cti_0_dout_valid),                  //                 .valid
		.is_ready      (alt_vip_cti_0_dout_ready),                  //                 .ready
		.is_sop        (alt_vip_cti_0_dout_startofpacket),          //                 .startofpacket
		.is_eop        (alt_vip_cti_0_dout_endofpacket),            //                 .endofpacket
		.vid_clk       (alt_vip_cti_0_clocked_video_vid_clk),       //    clocked_video.export
		.vid_data      (alt_vip_cti_0_clocked_video_vid_data),      //                 .export
		.overflow      (alt_vip_cti_0_clocked_video_overflow),      //                 .export
		.vid_datavalid (alt_vip_cti_0_clocked_video_vid_datavalid), //                 .export
		.vid_locked    (alt_vip_cti_0_clocked_video_vid_locked),    //                 .export
		.vid_v_sync    (alt_vip_cti_0_clocked_video_vid_v_sync),    //                 .export
		.vid_h_sync    (alt_vip_cti_0_clocked_video_vid_h_sync),    //                 .export
		.vid_f         (alt_vip_cti_0_clocked_video_vid_f)          //                 .export
	);

	alt_vipitc110_IS2Vid #(
		.NUMBER_OF_COLOUR_PLANES       (3),
		.COLOUR_PLANES_ARE_IN_PARALLEL (1),
		.BPS                           (8),
		.INTERLACED                    (0),
		.H_ACTIVE_PIXELS               (800),
		.V_ACTIVE_LINES                (480),
		.ACCEPT_COLOURS_IN_SEQ         (0),
		.FIFO_DEPTH                    (512),
		.CLOCKS_ARE_SAME               (0),
		.USE_CONTROL                   (0),
		.NO_OF_MODES                   (1),
		.THRESHOLD                     (0),
		.STD_WIDTH                     (1),
		.GENERATE_SYNC                 (0),
		.USE_EMBEDDED_SYNCS            (0),
		.AP_LINE                       (0),
		.V_BLANK                       (0),
		.H_BLANK                       (0),
		.H_SYNC_LENGTH                 (30),
		.H_FRONT_PORCH                 (210),
		.H_BACK_PORCH                  (16),
		.V_SYNC_LENGTH                 (13),
		.V_FRONT_PORCH                 (22),
		.V_BACK_PORCH                  (10),
		.F_RISING_EDGE                 (0),
		.F_FALLING_EDGE                (0),
		.FIELD0_V_RISING_EDGE          (0),
		.FIELD0_V_BLANK                (0),
		.FIELD0_V_SYNC_LENGTH          (0),
		.FIELD0_V_FRONT_PORCH          (0),
		.FIELD0_V_BACK_PORCH           (0),
		.ANC_LINE                      (0),
		.FIELD0_ANC_LINE               (0)
	) alt_vip_itc_0 (
		.is_clk        (uniphy_ddr3_afi_half_clk_clk),              //       is_clk_rst.clk
		.rst           (rst_controller_reset_out_reset),            // is_clk_rst_reset.reset
		.is_data       (frame_buffer_dout_data),                    //              din.data
		.is_valid      (frame_buffer_dout_valid),                   //                 .valid
		.is_ready      (frame_buffer_dout_ready),                   //                 .ready
		.is_sop        (frame_buffer_dout_startofpacket),           //                 .startofpacket
		.is_eop        (frame_buffer_dout_endofpacket),             //                 .endofpacket
		.vid_clk       (alt_vip_itc_0_clocked_video_vid_clk),       //    clocked_video.export
		.vid_data      (alt_vip_itc_0_clocked_video_vid_data),      //                 .export
		.underflow     (alt_vip_itc_0_clocked_video_underflow),     //                 .export
		.vid_datavalid (alt_vip_itc_0_clocked_video_vid_datavalid), //                 .export
		.vid_v_sync    (alt_vip_itc_0_clocked_video_vid_v_sync),    //                 .export
		.vid_h_sync    (alt_vip_itc_0_clocked_video_vid_h_sync),    //                 .export
		.vid_f         (alt_vip_itc_0_clocked_video_vid_f),         //                 .export
		.vid_h         (alt_vip_itc_0_clocked_video_vid_h),         //                 .export
		.vid_v         (alt_vip_itc_0_clocked_video_vid_v)          //                 .export
	);

	TR4_QSYS_frame_buffer #(
		.PARAMETERISATION                      ("<frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>800</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>480</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>0</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>1</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>1</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>64</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>64</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>64</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>0</VFB_DROP_INVALID_FIELDS></frameBufferParams>"),
		.AUTO_DEVICE_FAMILY                    ("Stratix IV"),
		.AUTO_READER_CONTROL_CLOCKS_SAME       ("0"),
		.AUTO_READ_MASTER_CLOCKS_SAME          ("2"),
		.AUTO_READ_MASTER_INTERRUPT_USED_MASK  ("0"),
		.AUTO_READ_MASTER_MAX_READ_LATENCY     ("2"),
		.AUTO_READ_MASTER_NEED_ADDR_WIDTH      ("35"),
		.AUTO_WRITER_CONTROL_CLOCKS_SAME       ("0"),
		.AUTO_WRITE_MASTER_CLOCKS_SAME         ("2"),
		.AUTO_WRITE_MASTER_INTERRUPT_USED_MASK ("0"),
		.AUTO_WRITE_MASTER_MAX_READ_LATENCY    ("2"),
		.AUTO_WRITE_MASTER_NEED_ADDR_WIDTH     ("35")
	) frame_buffer (
		.clock                        (uniphy_ddr3_afi_half_clk_clk),           //        clock.clk
		.reset                        (rst_controller_reset_out_reset),         //        reset.reset
		.din_ready                    (alt_vip_cti_0_dout_ready),               //          din.ready
		.din_valid                    (alt_vip_cti_0_dout_valid),               //             .valid
		.din_data                     (alt_vip_cti_0_dout_data),                //             .data
		.din_startofpacket            (alt_vip_cti_0_dout_startofpacket),       //             .startofpacket
		.din_endofpacket              (alt_vip_cti_0_dout_endofpacket),         //             .endofpacket
		.dout_ready                   (frame_buffer_dout_ready),                //         dout.ready
		.dout_valid                   (frame_buffer_dout_valid),                //             .valid
		.dout_data                    (frame_buffer_dout_data),                 //             .data
		.dout_startofpacket           (frame_buffer_dout_startofpacket),        //             .startofpacket
		.dout_endofpacket             (frame_buffer_dout_endofpacket),          //             .endofpacket
		.read_master_av_address       (frame_buffer_read_master_address),       //  read_master.address
		.read_master_av_read          (frame_buffer_read_master_read),          //             .read
		.read_master_av_waitrequest   (frame_buffer_read_master_waitrequest),   //             .waitrequest
		.read_master_av_readdatavalid (frame_buffer_read_master_readdatavalid), //             .readdatavalid
		.read_master_av_readdata      (frame_buffer_read_master_readdata),      //             .readdata
		.read_master_av_burstcount    (frame_buffer_read_master_burstcount),    //             .burstcount
		.write_master_av_address      (frame_buffer_write_master_address),      // write_master.address
		.write_master_av_write        (frame_buffer_write_master_write),        //             .write
		.write_master_av_writedata    (frame_buffer_write_master_writedata),    //             .writedata
		.write_master_av_waitrequest  (frame_buffer_write_master_waitrequest),  //             .waitrequest
		.write_master_av_burstcount   (frame_buffer_write_master_burstcount)    //             .burstcount
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) frame_buffer_read_master_translator (
		.clk                   (uniphy_ddr3_afi_half_clk_clk),                                                //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                              //                     reset.reset
		.uav_address           (frame_buffer_read_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (frame_buffer_read_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (frame_buffer_read_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (frame_buffer_read_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (frame_buffer_read_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (frame_buffer_read_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (frame_buffer_read_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (frame_buffer_read_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (frame_buffer_read_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (frame_buffer_read_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (frame_buffer_read_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (frame_buffer_read_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (frame_buffer_read_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (frame_buffer_read_master_burstcount),                                         //                          .burstcount
		.av_read               (frame_buffer_read_master_read),                                               //                          .read
		.av_readdata           (frame_buffer_read_master_readdata),                                           //                          .readdata
		.av_readdatavalid      (frame_buffer_read_master_readdatavalid),                                      //                          .readdatavalid
		.av_byteenable         (8'b11111111),                                                                 //               (terminated)
		.av_beginbursttransfer (1'b0),                                                                        //               (terminated)
		.av_begintransfer      (1'b0),                                                                        //               (terminated)
		.av_chipselect         (1'b0),                                                                        //               (terminated)
		.av_write              (1'b0),                                                                        //               (terminated)
		.av_writedata          (64'b0000000000000000000000000000000000000000000000000000000000000000),        //               (terminated)
		.av_lock               (1'b0),                                                                        //               (terminated)
		.av_debugaccess        (1'b0),                                                                        //               (terminated)
		.uav_clken             (),                                                                            //               (terminated)
		.av_clken              (1'b1)                                                                         //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (64),
		.AV_BURSTCOUNT_W             (7),
		.AV_BYTEENABLE_W             (8),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (10),
		.USE_READ                    (0),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (8),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) frame_buffer_write_master_translator (
		.clk                   (uniphy_ddr3_afi_half_clk_clk),                                                 //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                               //                     reset.reset
		.uav_address           (frame_buffer_write_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (frame_buffer_write_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (frame_buffer_write_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (frame_buffer_write_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (frame_buffer_write_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (frame_buffer_write_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (frame_buffer_write_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (frame_buffer_write_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (frame_buffer_write_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (frame_buffer_write_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (frame_buffer_write_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (frame_buffer_write_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (frame_buffer_write_master_waitrequest),                                        //                          .waitrequest
		.av_burstcount         (frame_buffer_write_master_burstcount),                                         //                          .burstcount
		.av_write              (frame_buffer_write_master_write),                                              //                          .write
		.av_writedata          (frame_buffer_write_master_writedata),                                          //                          .writedata
		.av_byteenable         (8'b11111111),                                                                  //               (terminated)
		.av_beginbursttransfer (1'b0),                                                                         //               (terminated)
		.av_begintransfer      (1'b0),                                                                         //               (terminated)
		.av_chipselect         (1'b0),                                                                         //               (terminated)
		.av_read               (1'b0),                                                                         //               (terminated)
		.av_readdata           (),                                                                             //               (terminated)
		.av_readdatavalid      (),                                                                             //               (terminated)
		.av_lock               (1'b0),                                                                         //               (terminated)
		.av_debugaccess        (1'b0),                                                                         //               (terminated)
		.uav_clken             (),                                                                             //               (terminated)
		.av_clken              (1'b1)                                                                          //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (25),
		.AV_DATA_W                      (256),
		.UAV_DATA_W                     (256),
		.AV_BURSTCOUNT_W                (4),
		.AV_BYTEENABLE_W                (32),
		.UAV_BYTEENABLE_W               (32),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (9),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (32),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) uniphy_ddr3_avl_translator (
		.clk                   (uniphy_ddr3_afi_clk_clk),                                                    //                      clk.clk
		.reset                 (rst_controller_001_reset_out_reset),                                         //                    reset.reset
		.uav_address           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (uniphy_ddr3_avl_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (uniphy_ddr3_avl_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (uniphy_ddr3_avl_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (uniphy_ddr3_avl_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_beginbursttransfer (uniphy_ddr3_avl_translator_avalon_anti_slave_0_beginbursttransfer),          //                         .beginbursttransfer
		.av_burstcount         (uniphy_ddr3_avl_translator_avalon_anti_slave_0_burstcount),                  //                         .burstcount
		.av_byteenable         (uniphy_ddr3_avl_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_readdatavalid      (uniphy_ddr3_avl_translator_avalon_anti_slave_0_readdatavalid),               //                         .readdatavalid
		.av_waitrequest        (~uniphy_ddr3_avl_translator_avalon_anti_slave_0_waitrequest),                //                         .waitrequest
		.av_begintransfer      (),                                                                           //              (terminated)
		.av_writebyteenable    (),                                                                           //              (terminated)
		.av_lock               (),                                                                           //              (terminated)
		.av_chipselect         (),                                                                           //              (terminated)
		.av_clken              (),                                                                           //              (terminated)
		.uav_clken             (1'b0),                                                                       //              (terminated)
		.av_debugaccess        (),                                                                           //              (terminated)
		.av_outputenable       ()                                                                            //              (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (134),
		.PKT_PROTECTION_L          (134),
		.PKT_BEGIN_BURST           (129),
		.PKT_BURSTWRAP_H           (128),
		.PKT_BURSTWRAP_L           (119),
		.PKT_BYTE_CNT_H            (118),
		.PKT_BYTE_CNT_L            (109),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.ST_DATA_W                 (135),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (1),
		.BURSTWRAP_VALUE           (1023)
	) frame_buffer_read_master_translator_avalon_universal_master_0_agent (
		.clk              (uniphy_ddr3_afi_half_clk_clk),                                                         //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                       // clk_reset.reset
		.av_address       (frame_buffer_read_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (frame_buffer_read_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (frame_buffer_read_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (frame_buffer_read_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (frame_buffer_read_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (frame_buffer_read_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (frame_buffer_read_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (frame_buffer_read_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (frame_buffer_read_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (frame_buffer_read_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (frame_buffer_read_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (crosser_002_out_valid),                                                                //        rp.valid
		.rp_data          (crosser_002_out_data),                                                                 //          .data
		.rp_channel       (crosser_002_out_channel),                                                              //          .channel
		.rp_startofpacket (crosser_002_out_startofpacket),                                                        //          .startofpacket
		.rp_endofpacket   (crosser_002_out_endofpacket),                                                          //          .endofpacket
		.rp_ready         (crosser_002_out_ready)                                                                 //          .ready
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (134),
		.PKT_PROTECTION_L          (134),
		.PKT_BEGIN_BURST           (129),
		.PKT_BURSTWRAP_H           (128),
		.PKT_BURSTWRAP_L           (119),
		.PKT_BYTE_CNT_H            (118),
		.PKT_BYTE_CNT_L            (109),
		.PKT_ADDR_H                (103),
		.PKT_ADDR_L                (72),
		.PKT_TRANS_COMPRESSED_READ (104),
		.PKT_TRANS_POSTED          (105),
		.PKT_TRANS_WRITE           (106),
		.PKT_TRANS_READ            (107),
		.PKT_TRANS_LOCK            (108),
		.PKT_DATA_H                (63),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (71),
		.PKT_BYTEEN_L              (64),
		.PKT_SRC_ID_H              (131),
		.PKT_SRC_ID_L              (130),
		.PKT_DEST_ID_H             (133),
		.PKT_DEST_ID_L             (132),
		.ST_DATA_W                 (135),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (10),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (2),
		.BURSTWRAP_VALUE           (1023)
	) frame_buffer_write_master_translator_avalon_universal_master_0_agent (
		.clk              (uniphy_ddr3_afi_half_clk_clk),                                                          //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                        // clk_reset.reset
		.av_address       (frame_buffer_write_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (frame_buffer_write_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (frame_buffer_write_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (frame_buffer_write_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (frame_buffer_write_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (frame_buffer_write_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (frame_buffer_write_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (frame_buffer_write_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (frame_buffer_write_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (frame_buffer_write_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (frame_buffer_write_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (crosser_003_out_valid),                                                                 //        rp.valid
		.rp_data          (crosser_003_out_data),                                                                  //          .data
		.rp_channel       (crosser_003_out_channel),                                                               //          .channel
		.rp_startofpacket (crosser_003_out_startofpacket),                                                         //          .startofpacket
		.rp_endofpacket   (crosser_003_out_endofpacket),                                                           //          .endofpacket
		.rp_ready         (crosser_003_out_ready)                                                                  //          .ready
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (345),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_TRANS_LOCK            (324),
		.PKT_SRC_ID_H              (347),
		.PKT_SRC_ID_L              (346),
		.PKT_DEST_ID_H             (349),
		.PKT_DEST_ID_L             (348),
		.PKT_BURSTWRAP_H           (344),
		.PKT_BURSTWRAP_L           (335),
		.PKT_BYTE_CNT_H            (334),
		.PKT_BYTE_CNT_L            (325),
		.PKT_PROTECTION_H          (350),
		.PKT_PROTECTION_L          (350),
		.ST_CHANNEL_W              (2),
		.ST_DATA_W                 (351),
		.AVS_BURSTCOUNT_W          (9),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (uniphy_ddr3_afi_clk_clk),                                                              //             clk.clk
		.reset                   (rst_controller_001_reset_out_reset),                                                   //       clk_reset.reset
		.m0_address              (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (burst_adapter_source0_ready),                                                          //              cp.ready
		.cp_valid                (burst_adapter_source0_valid),                                                          //                .valid
		.cp_data                 (burst_adapter_source0_data),                                                           //                .data
		.cp_startofpacket        (burst_adapter_source0_startofpacket),                                                  //                .startofpacket
		.cp_endofpacket          (burst_adapter_source0_endofpacket),                                                    //                .endofpacket
		.cp_channel              (burst_adapter_source0_channel),                                                        //                .channel
		.rf_sink_ready           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid),       //                .valid
		.rdata_fifo_sink_data    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),        //                .data
		.rdata_fifo_src_ready    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (352),
		.FIFO_DEPTH          (33),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (uniphy_ddr3_afi_clk_clk),                                                              //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                                   // clk_reset.reset
		.in_data           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                // (terminated)
		.csr_read          (1'b0),                                                                                 // (terminated)
		.csr_write         (1'b0),                                                                                 // (terminated)
		.csr_readdata      (),                                                                                     // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                 // (terminated)
		.almost_full_data  (),                                                                                     // (terminated)
		.almost_empty_data (),                                                                                     // (terminated)
		.in_empty          (1'b0),                                                                                 // (terminated)
		.out_empty         (),                                                                                     // (terminated)
		.in_error          (1'b0),                                                                                 // (terminated)
		.out_error         (),                                                                                     // (terminated)
		.in_channel        (1'b0),                                                                                 // (terminated)
		.out_channel       ()                                                                                      // (terminated)
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (256),
		.FIFO_DEPTH          (512),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (3),
		.USE_MEMORY_BLOCKS   (1),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo (
		.clk               (uniphy_ddr3_afi_clk_clk),                                                        //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),                                             // clk_reset.reset
		.in_data           (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),  //        in.data
		.in_valid          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), //          .valid
		.in_ready          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), //          .ready
		.out_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data),  //       out.data
		.out_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), //          .valid
		.out_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), //          .ready
		.csr_address       (2'b00),                                                                          // (terminated)
		.csr_read          (1'b0),                                                                           // (terminated)
		.csr_write         (1'b0),                                                                           // (terminated)
		.csr_readdata      (),                                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                           // (terminated)
		.almost_full_data  (),                                                                               // (terminated)
		.almost_empty_data (),                                                                               // (terminated)
		.in_startofpacket  (1'b0),                                                                           // (terminated)
		.in_endofpacket    (1'b0),                                                                           // (terminated)
		.out_startofpacket (),                                                                               // (terminated)
		.out_endofpacket   (),                                                                               // (terminated)
		.in_empty          (1'b0),                                                                           // (terminated)
		.out_empty         (),                                                                               // (terminated)
		.in_error          (1'b0),                                                                           // (terminated)
		.out_error         (),                                                                               // (terminated)
		.in_channel        (1'b0),                                                                           // (terminated)
		.out_channel       ()                                                                                // (terminated)
	);

	TR4_QSYS_addr_router addr_router (
		.sink_ready         (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (frame_buffer_read_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (uniphy_ddr3_afi_half_clk_clk),                                                         //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                       // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                                                //       src.ready
		.src_valid          (addr_router_src_valid),                                                                //          .valid
		.src_data           (addr_router_src_data),                                                                 //          .data
		.src_channel        (addr_router_src_channel),                                                              //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                                        //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                                           //          .endofpacket
	);

	TR4_QSYS_addr_router addr_router_001 (
		.sink_ready         (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (frame_buffer_write_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (uniphy_ddr3_afi_half_clk_clk),                                                          //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                        // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                                             //       src.ready
		.src_valid          (addr_router_001_src_valid),                                                             //          .valid
		.src_data           (addr_router_001_src_data),                                                              //          .data
		.src_channel        (addr_router_001_src_channel),                                                           //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                                     //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                                        //          .endofpacket
	);

	TR4_QSYS_id_router id_router (
		.sink_ready         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (uniphy_ddr3_afi_clk_clk),                                                    //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),                                         // clk_reset.reset
		.src_ready          (id_router_src_ready),                                                        //       src.ready
		.src_valid          (id_router_src_valid),                                                        //          .valid
		.src_data           (id_router_src_data),                                                         //          .data
		.src_channel        (id_router_src_channel),                                                      //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                                //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                                   //          .endofpacket
	);

	altera_merlin_burst_adapter #(
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_BEGIN_BURST           (345),
		.PKT_BYTE_CNT_H            (334),
		.PKT_BYTE_CNT_L            (325),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_BURSTWRAP_H           (344),
		.PKT_BURSTWRAP_L           (335),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.ST_DATA_W                 (351),
		.ST_CHANNEL_W              (2),
		.OUT_BYTE_CNT_H            (333),
		.OUT_BURSTWRAP_H           (344),
		.COMPRESSED_READ_SUPPORT   (1),
		.BURSTWRAP_CONST_MASK      (1023),
		.BURSTWRAP_CONST_VALUE     (1023)
	) burst_adapter (
		.clk                   (uniphy_ddr3_afi_clk_clk),             //       cr0.clk
		.reset                 (rst_controller_001_reset_out_reset),  // cr0_reset.reset
		.sink0_valid           (width_adapter_src_valid),             //     sink0.valid
		.sink0_data            (width_adapter_src_data),              //          .data
		.sink0_channel         (width_adapter_src_channel),           //          .channel
		.sink0_startofpacket   (width_adapter_src_startofpacket),     //          .startofpacket
		.sink0_endofpacket     (width_adapter_src_endofpacket),       //          .endofpacket
		.sink0_ready           (width_adapter_src_ready),             //          .ready
		.source0_valid         (burst_adapter_source0_valid),         //   source0.valid
		.source0_data          (burst_adapter_source0_data),          //          .data
		.source0_channel       (burst_adapter_source0_channel),       //          .channel
		.source0_startofpacket (burst_adapter_source0_startofpacket), //          .startofpacket
		.source0_endofpacket   (burst_adapter_source0_endofpacket),   //          .endofpacket
		.source0_ready         (burst_adapter_source0_ready)          //          .ready
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~uniphy_ddr3_afi_reset_reset),   // reset_in0.reset
		.clk        (uniphy_ddr3_afi_half_clk_clk),   //       clk.clk
		.reset_out  (rst_controller_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                           // (terminated)
		.reset_in2  (1'b0),                           // (terminated)
		.reset_in3  (1'b0),                           // (terminated)
		.reset_in4  (1'b0),                           // (terminated)
		.reset_in5  (1'b0),                           // (terminated)
		.reset_in6  (1'b0),                           // (terminated)
		.reset_in7  (1'b0),                           // (terminated)
		.reset_in8  (1'b0),                           // (terminated)
		.reset_in9  (1'b0),                           // (terminated)
		.reset_in10 (1'b0),                           // (terminated)
		.reset_in11 (1'b0),                           // (terminated)
		.reset_in12 (1'b0),                           // (terminated)
		.reset_in13 (1'b0),                           // (terminated)
		.reset_in14 (1'b0),                           // (terminated)
		.reset_in15 (1'b0)                            // (terminated)
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller_001 (
		.reset_in0  (~uniphy_ddr3_afi_reset_reset),       // reset_in0.reset
		.clk        (uniphy_ddr3_afi_clk_clk),            //       clk.clk
		.reset_out  (rst_controller_001_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                               // (terminated)
		.reset_in2  (1'b0),                               // (terminated)
		.reset_in3  (1'b0),                               // (terminated)
		.reset_in4  (1'b0),                               // (terminated)
		.reset_in5  (1'b0),                               // (terminated)
		.reset_in6  (1'b0),                               // (terminated)
		.reset_in7  (1'b0),                               // (terminated)
		.reset_in8  (1'b0),                               // (terminated)
		.reset_in9  (1'b0),                               // (terminated)
		.reset_in10 (1'b0),                               // (terminated)
		.reset_in11 (1'b0),                               // (terminated)
		.reset_in12 (1'b0),                               // (terminated)
		.reset_in13 (1'b0),                               // (terminated)
		.reset_in14 (1'b0),                               // (terminated)
		.reset_in15 (1'b0)                                // (terminated)
	);

	TR4_QSYS_cmd_xbar_demux cmd_xbar_demux (
		.clk                (uniphy_ddr3_afi_half_clk_clk),      //       clk.clk
		.reset              (rst_controller_reset_out_reset),    // clk_reset.reset
		.sink_ready         (addr_router_src_ready),             //      sink.ready
		.sink_channel       (addr_router_src_channel),           //          .channel
		.sink_data          (addr_router_src_data),              //          .data
		.sink_startofpacket (addr_router_src_startofpacket),     //          .startofpacket
		.sink_endofpacket   (addr_router_src_endofpacket),       //          .endofpacket
		.sink_valid         (addr_router_src_valid),             //          .valid
		.src0_ready         (cmd_xbar_demux_src0_ready),         //      src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),         //          .valid
		.src0_data          (cmd_xbar_demux_src0_data),          //          .data
		.src0_channel       (cmd_xbar_demux_src0_channel),       //          .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_cmd_xbar_demux cmd_xbar_demux_001 (
		.clk                (uniphy_ddr3_afi_half_clk_clk),          //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (addr_router_001_src_ready),             //      sink.ready
		.sink_channel       (addr_router_001_src_channel),           //          .channel
		.sink_data          (addr_router_001_src_data),              //          .data
		.sink_startofpacket (addr_router_001_src_startofpacket),     //          .startofpacket
		.sink_endofpacket   (addr_router_001_src_endofpacket),       //          .endofpacket
		.sink_valid         (addr_router_001_src_valid),             //          .valid
		.src0_ready         (cmd_xbar_demux_001_src0_ready),         //      src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),         //          .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),          //          .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),       //          .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_cmd_xbar_mux cmd_xbar_mux (
		.clk                 (uniphy_ddr3_afi_clk_clk),            //       clk.clk
		.reset               (rst_controller_001_reset_out_reset), // clk_reset.reset
		.src_ready           (cmd_xbar_mux_src_ready),             //       src.ready
		.src_valid           (cmd_xbar_mux_src_valid),             //          .valid
		.src_data            (cmd_xbar_mux_src_data),              //          .data
		.src_channel         (cmd_xbar_mux_src_channel),           //          .channel
		.src_startofpacket   (cmd_xbar_mux_src_startofpacket),     //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_src_endofpacket),       //          .endofpacket
		.sink0_ready         (crosser_out_ready),                  //     sink0.ready
		.sink0_valid         (crosser_out_valid),                  //          .valid
		.sink0_channel       (crosser_out_channel),                //          .channel
		.sink0_data          (crosser_out_data),                   //          .data
		.sink0_startofpacket (crosser_out_startofpacket),          //          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket),            //          .endofpacket
		.sink1_ready         (crosser_001_out_ready),              //     sink1.ready
		.sink1_valid         (crosser_001_out_valid),              //          .valid
		.sink1_channel       (crosser_001_out_channel),            //          .channel
		.sink1_data          (crosser_001_out_data),               //          .data
		.sink1_startofpacket (crosser_001_out_startofpacket),      //          .startofpacket
		.sink1_endofpacket   (crosser_001_out_endofpacket)         //          .endofpacket
	);

	TR4_QSYS_rsp_xbar_demux rsp_xbar_demux (
		.clk                (uniphy_ddr3_afi_clk_clk),             //       clk.clk
		.reset              (rst_controller_001_reset_out_reset),  // clk_reset.reset
		.sink_ready         (width_adapter_001_src_ready),         //      sink.ready
		.sink_channel       (width_adapter_001_src_channel),       //          .channel
		.sink_data          (width_adapter_001_src_data),          //          .data
		.sink_startofpacket (width_adapter_001_src_startofpacket), //          .startofpacket
		.sink_endofpacket   (width_adapter_001_src_endofpacket),   //          .endofpacket
		.sink_valid         (width_adapter_001_src_valid),         //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),           //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),           //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),            //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),         //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket),   //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket),     //          .endofpacket
		.src1_ready         (rsp_xbar_demux_src1_ready),           //      src1.ready
		.src1_valid         (rsp_xbar_demux_src1_valid),           //          .valid
		.src1_data          (rsp_xbar_demux_src1_data),            //          .data
		.src1_channel       (rsp_xbar_demux_src1_channel),         //          .channel
		.src1_startofpacket (rsp_xbar_demux_src1_startofpacket),   //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_src1_endofpacket)      //          .endofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (118),
		.IN_PKT_BYTE_CNT_L             (109),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_BURSTWRAP_H            (128),
		.IN_PKT_BURSTWRAP_L            (119),
		.IN_ST_DATA_W                  (135),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (334),
		.OUT_PKT_BYTE_CNT_L            (325),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_ST_DATA_W                 (351),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter (
		.clk               (uniphy_ddr3_afi_clk_clk),            //       clk.clk
		.reset             (rst_controller_001_reset_out_reset), // clk_reset.reset
		.in_valid          (cmd_xbar_mux_src_valid),             //      sink.valid
		.in_channel        (cmd_xbar_mux_src_channel),           //          .channel
		.in_startofpacket  (cmd_xbar_mux_src_startofpacket),     //          .startofpacket
		.in_endofpacket    (cmd_xbar_mux_src_endofpacket),       //          .endofpacket
		.in_ready          (cmd_xbar_mux_src_ready),             //          .ready
		.in_data           (cmd_xbar_mux_src_data),              //          .data
		.out_endofpacket   (width_adapter_src_endofpacket),      //       src.endofpacket
		.out_data          (width_adapter_src_data),             //          .data
		.out_channel       (width_adapter_src_channel),          //          .channel
		.out_valid         (width_adapter_src_valid),            //          .valid
		.out_ready         (width_adapter_src_ready),            //          .ready
		.out_startofpacket (width_adapter_src_startofpacket)     //          .startofpacket
	);

	altera_merlin_width_adapter #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (334),
		.IN_PKT_BYTE_CNT_L             (325),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_BURSTWRAP_H            (344),
		.IN_PKT_BURSTWRAP_L            (335),
		.IN_ST_DATA_W                  (351),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (118),
		.OUT_PKT_BYTE_CNT_L            (109),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_ST_DATA_W                 (135),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0)
	) width_adapter_001 (
		.clk               (uniphy_ddr3_afi_clk_clk),             //       clk.clk
		.reset             (rst_controller_001_reset_out_reset),  // clk_reset.reset
		.in_valid          (id_router_src_valid),                 //      sink.valid
		.in_channel        (id_router_src_channel),               //          .channel
		.in_startofpacket  (id_router_src_startofpacket),         //          .startofpacket
		.in_endofpacket    (id_router_src_endofpacket),           //          .endofpacket
		.in_ready          (id_router_src_ready),                 //          .ready
		.in_data           (id_router_src_data),                  //          .data
		.out_endofpacket   (width_adapter_001_src_endofpacket),   //       src.endofpacket
		.out_data          (width_adapter_001_src_data),          //          .data
		.out_channel       (width_adapter_001_src_channel),       //          .channel
		.out_valid         (width_adapter_001_src_valid),         //          .valid
		.out_ready         (width_adapter_001_src_ready),         //          .ready
		.out_startofpacket (width_adapter_001_src_startofpacket)  //          .startofpacket
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (135),
		.BITS_PER_SYMBOL     (135),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser (
		.in_clk            (uniphy_ddr3_afi_half_clk_clk),       //        in_clk.clk
		.in_reset          (rst_controller_reset_out_reset),     //  in_clk_reset.reset
		.out_clk           (uniphy_ddr3_afi_clk_clk),            //       out_clk.clk
		.out_reset         (rst_controller_001_reset_out_reset), // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_src0_ready),          //            in.ready
		.in_valid          (cmd_xbar_demux_src0_valid),          //              .valid
		.in_startofpacket  (cmd_xbar_demux_src0_startofpacket),  //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_src0_endofpacket),    //              .endofpacket
		.in_channel        (cmd_xbar_demux_src0_channel),        //              .channel
		.in_data           (cmd_xbar_demux_src0_data),           //              .data
		.out_ready         (crosser_out_ready),                  //           out.ready
		.out_valid         (crosser_out_valid),                  //              .valid
		.out_startofpacket (crosser_out_startofpacket),          //              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),            //              .endofpacket
		.out_channel       (crosser_out_channel),                //              .channel
		.out_data          (crosser_out_data),                   //              .data
		.in_empty          (1'b0),                               //   (terminated)
		.in_error          (1'b0),                               //   (terminated)
		.out_empty         (),                                   //   (terminated)
		.out_error         ()                                    //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (135),
		.BITS_PER_SYMBOL     (135),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_001 (
		.in_clk            (uniphy_ddr3_afi_half_clk_clk),          //        in_clk.clk
		.in_reset          (rst_controller_reset_out_reset),        //  in_clk_reset.reset
		.out_clk           (uniphy_ddr3_afi_clk_clk),               //       out_clk.clk
		.out_reset         (rst_controller_001_reset_out_reset),    // out_clk_reset.reset
		.in_ready          (cmd_xbar_demux_001_src0_ready),         //            in.ready
		.in_valid          (cmd_xbar_demux_001_src0_valid),         //              .valid
		.in_startofpacket  (cmd_xbar_demux_001_src0_startofpacket), //              .startofpacket
		.in_endofpacket    (cmd_xbar_demux_001_src0_endofpacket),   //              .endofpacket
		.in_channel        (cmd_xbar_demux_001_src0_channel),       //              .channel
		.in_data           (cmd_xbar_demux_001_src0_data),          //              .data
		.out_ready         (crosser_001_out_ready),                 //           out.ready
		.out_valid         (crosser_001_out_valid),                 //              .valid
		.out_startofpacket (crosser_001_out_startofpacket),         //              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),           //              .endofpacket
		.out_channel       (crosser_001_out_channel),               //              .channel
		.out_data          (crosser_001_out_data),                  //              .data
		.in_empty          (1'b0),                                  //   (terminated)
		.in_error          (1'b0),                                  //   (terminated)
		.out_empty         (),                                      //   (terminated)
		.out_error         ()                                       //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (135),
		.BITS_PER_SYMBOL     (135),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_002 (
		.in_clk            (uniphy_ddr3_afi_clk_clk),            //        in_clk.clk
		.in_reset          (rst_controller_001_reset_out_reset), //  in_clk_reset.reset
		.out_clk           (uniphy_ddr3_afi_half_clk_clk),       //       out_clk.clk
		.out_reset         (rst_controller_reset_out_reset),     // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_src0_ready),          //            in.ready
		.in_valid          (rsp_xbar_demux_src0_valid),          //              .valid
		.in_startofpacket  (rsp_xbar_demux_src0_startofpacket),  //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src0_endofpacket),    //              .endofpacket
		.in_channel        (rsp_xbar_demux_src0_channel),        //              .channel
		.in_data           (rsp_xbar_demux_src0_data),           //              .data
		.out_ready         (crosser_002_out_ready),              //           out.ready
		.out_valid         (crosser_002_out_valid),              //              .valid
		.out_startofpacket (crosser_002_out_startofpacket),      //              .startofpacket
		.out_endofpacket   (crosser_002_out_endofpacket),        //              .endofpacket
		.out_channel       (crosser_002_out_channel),            //              .channel
		.out_data          (crosser_002_out_data),               //              .data
		.in_empty          (1'b0),                               //   (terminated)
		.in_error          (1'b0),                               //   (terminated)
		.out_empty         (),                                   //   (terminated)
		.out_error         ()                                    //   (terminated)
	);

	altera_avalon_st_handshake_clock_crosser #(
		.DATA_WIDTH          (135),
		.BITS_PER_SYMBOL     (135),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (2),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0)
	) crosser_003 (
		.in_clk            (uniphy_ddr3_afi_clk_clk),            //        in_clk.clk
		.in_reset          (rst_controller_001_reset_out_reset), //  in_clk_reset.reset
		.out_clk           (uniphy_ddr3_afi_half_clk_clk),       //       out_clk.clk
		.out_reset         (rst_controller_reset_out_reset),     // out_clk_reset.reset
		.in_ready          (rsp_xbar_demux_src1_ready),          //            in.ready
		.in_valid          (rsp_xbar_demux_src1_valid),          //              .valid
		.in_startofpacket  (rsp_xbar_demux_src1_startofpacket),  //              .startofpacket
		.in_endofpacket    (rsp_xbar_demux_src1_endofpacket),    //              .endofpacket
		.in_channel        (rsp_xbar_demux_src1_channel),        //              .channel
		.in_data           (rsp_xbar_demux_src1_data),           //              .data
		.out_ready         (crosser_003_out_ready),              //           out.ready
		.out_valid         (crosser_003_out_valid),              //              .valid
		.out_startofpacket (crosser_003_out_startofpacket),      //              .startofpacket
		.out_endofpacket   (crosser_003_out_endofpacket),        //              .endofpacket
		.out_channel       (crosser_003_out_channel),            //              .channel
		.out_data          (crosser_003_out_data),               //              .data
		.in_empty          (1'b0),                               //   (terminated)
		.in_error          (1'b0),                               //   (terminated)
		.out_empty         (),                                   //   (terminated)
		.out_error         ()                                    //   (terminated)
	);

endmodule
