TR4_QSYS | TR4_QSYS 1.0

2011.10.27.16:01:32 | Generation Report

Output Directory | E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/
Files | E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/TR4_QSYS.v (124974 bytes VERILOG) E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3.v (13794 bytes VERILOG) E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_c0.v (19487 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd.v (25980 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v (51432 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v (19238 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v (10002 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v (16552 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_odt_gen.v (14757 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v (46253 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_arbiter.v (50108 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_burst_gen.v (64113 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_cmd_gen.v (121966 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_csr.v (53869 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_buffer.v (4779 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_buffer_manager.v (8991 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_burst_tracking.v (4707 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_dataid_manager.v (33821 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_fifo.v (8340 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_list.v (8754 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rdata_path.v (51877 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_wdata_path.v (44528 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_define.iv (2237 bytes VERILOG_INCLUDE)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v (13702 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v (32973 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v (59259 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v (10730 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v (14064 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v (22231 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v (49920 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_input_if.v (10699 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rank_timer.v (116132 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_sideband.v (57384 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_tbp.v (175785 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_timing_param.v (52437 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_controller.v (161675 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_controller_st_top.v (90484 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv (27695 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v (6961 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_clock_pair_generator.v (3520 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pll_memphy.v (23386 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_dll_memphy.v (6054 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_oct_control.v (3791 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_controller_phy.sv (16471 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_memphy_top.sv (25133 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_valid_selector.v (2379 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_datapath.v (6482 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset.v (4421 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_pads.v (13237 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_memphy.v (45568 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset_sync.v (1978 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_afi_mux.v (6280 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_new_io_pads.v (12210 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_fr_cycle_shifter.v (3943 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_datapath.v (26511 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_write_datapath.v (4314 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_hr_to_fr.v (1348 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_mux_bridge.sv (18324 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_phy_csr.sv (6105 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_iss_probe.v (1784 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_flop_mem.v (2755 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_nios_sequencer.sv (11285 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sv (13635 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_altdqdqs.v (5562 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altdq_dqs2_ddio_3reg_stratixiv.sv (53994 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/software/sequencer.c (131340 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/software/sequencer.h (10140 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer.v (352923 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v (32198 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv (9448 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10392 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv (8662 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv (16415 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv (17560 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv (15976 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv (13743 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_no_ifdef_params.v (10403 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_reg.v (1478 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_bitcheck.v (2624 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_core.sv (16455 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_datamux.v (1733 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_data_broadcast.v (2347 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_data_decoder.v (2892 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_ddr3.v (7707 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer.v (10123 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer_wrap.v (2076 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_dm_decoder.v (1735 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_generic.sv (7209 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_no_ifdef_params.v (10442 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_reg.v (1504 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_jumplogic.v (3333 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_lfsr12.v (1438 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_lfsr36.v (2097 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_lfsr72.v (1381 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_pattern_fifo.v (10125 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_ram.v (1317 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_ram_csr.v (2442 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_read_datapath.v (3610 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/rw_manager_write_decoder.v (2858 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/sequencer_data_mgr.sv (3779 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/sequencer_phy_mgr.sv (13764 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/sequencer_ptr_mgr.sv (3133 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/sequencer_scc_mgr.sv (17682 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/sequencer_scc_phase_decode.v (13160 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/sequencer_scc_reg_file.v (2631 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_addr_router.sv (6409 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_addr_router_001.sv (8029 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cmd_xbar_demux.sv (4169 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cmd_xbar_demux_001.sv (7987 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cmd_xbar_mux.sv (12302 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst.sdc (5808 bytes SDC)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst.v (208383 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk.v (7838 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck.v (9544 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper.v (12055 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_ociram_default_contents.mif (5878 bytes MIF)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_oci_test_bench.v (1713 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_rf_ram_a.mif (600 bytes MIF)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_rf_ram_b.mif (600 bytes MIF)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_cpu_inst_test_bench.v (32285 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_id_router.sv (5987 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_id_router_002.sv (5918 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_irq_mapper.sv (1714 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_demux.sv (4163 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_demux_002.sv (3539 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_mux.sv (12268 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_rsp_xbar_mux_001.sv (17364 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_sequencer_ram.v (4415 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_sequencer_rom.hex (86029 bytes HEX)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_qsys_sequencer_sequencer_rom.v (4563 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_rom.hex (86046 bytes HEX)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_AC_ROM.hex (1357 bytes HEX)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_inst_ROM.hex (2445 bytes HEX)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.ppf (60251 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sdc (29418 bytes SDC)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_timing.tcl (5728 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing.tcl (17168 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing_core.tcl (81477 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_map.tcl (78709 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_assignments.tcl (18913 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_parameters.tcl (3112 bytes OTHER)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_cpu.sdc (796 bytes SDC)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_Vid2IS.v (24737 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_Vid2IS_control.v (8555 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_Vid2IS_av_st_output.v (8763 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_Vid2IS_resolution_detection.v (10760 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_Vid2IS_write_buffer.v (3406 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_Vid2IS_embedded_sync_extractor.v (5665 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_Vid2IS_sync_polarity_convertor.v (887 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_common_fifo.v (2533 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_common_sync.v (994 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_common_sync_generation.v (4203 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_common_frame_counter.v (2390 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_common_sample_counter.v (1606 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipcti110_cvi.sdc (2434 bytes SDC)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid.v (43072 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_sync_compare.v (7112 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_calculate_mode.v (3850 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_control.v (5232 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_mode_banks.v (26347 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_IS2Vid_statemachine.v (9489 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_fifo.v (2533 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_generic_count.v (1843 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_to_binary.v (1208 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_sync.v (994 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_trigger_sync.v (1430 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_sync_generation.v (4203 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_frame_counter.v (2390 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_common_sample_counter.v (1606 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_vipitc110_cvo.sdc (6266 bytes SDC)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_frame_buffer.ocp (584 bytes unknown type)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_frame_buffer_vfb_writer_vfb_writer.trace (384365 bytes unknown type)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_frame_buffer_vfb_reader_vfb_reader.trace (280579 bytes unknown type)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_frame_buffer.vhd (424720 bytes VHDL_ENCRYPT)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_frame_buffer_tb.vhd (8605 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_muxbin2.vhd (862 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd (158228 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_au.vhd (5638 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_addsubcarry.vhd (11784 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_reg.vhd (2232 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_muxhot16.vhd (2866 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_avalon_st_input.vhd (12742 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_muxfast4.vhd (11574 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_avalon_st_output.vhd (5616 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_atlantic_reporter.vhd (3769 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_avalon_mm_bursting_master_fifo.vhd (36260 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_fifo.vhd (8942 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_fifo_usedw_calculator.vhd (14003 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_general_fifo.vhd (13672 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_gray_clock_crosser.vhd (3963 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_logic_fifo.vhd (5161 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_one_bit_delay.vhd (2313 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_ram_fifo.vhd (8174 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_std_logic_vector_delay.vhd (2610 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_pulling_width_adapter.vhd (6216 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_pushing_width_adapter.vhd (4878 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_pc.vhd (36289 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_cmp.vhd (3083 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_clock_reset.vhd (1791 bytes VHDL)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router.sv (6009 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router.sv (5906 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_burst_adapter.sv (36989 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux.sv (3476 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_mux.sv (11023 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux.sv (4110 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_width_adapter.sv (36187 bytes SYSTEM_VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v (7493 bytes VERILOG)
E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_avalon_st_clock_crosser.v (4900 bytes VERILOG)
Instantiations |

TR4_QSYS TR4_QSYS v1.0 | TR4_QSYS_uniphy_ddr3 as uniphy_ddr3 alt_vipcti110_Vid2IS as alt_vip_cti_0 alt_vipitc110_IS2Vid as alt_vip_itc_0 TR4_QSYS_frame_buffer as frame_buffer altera_merlin_master_translator as frame_buffer_read_master_translator, frame_buffer_write_master_translator
altera_merlin_slave_translator as uniphy_ddr3_avl_translator
altera_merlin_master_agent as frame_buffer_read_master_translator_avalon_universal_master_0_agent, frame_buffer_write_master_translator_avalon_universal_master_0_agent
altera_merlin_slave_agent as uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent
altera_avalon_sc_fifo as uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo
TR4_QSYS_addr_router as addr_router, addr_router_001
TR4_QSYS_id_router as id_router
altera_merlin_burst_adapter as burst_adapter
altera_reset_controller as rst_controller, rst_controller_001
TR4_QSYS_cmd_xbar_demux as cmd_xbar_demux, cmd_xbar_demux_001
TR4_QSYS_cmd_xbar_mux as cmd_xbar_mux
TR4_QSYS_rsp_xbar_demux as rsp_xbar_demux
altera_merlin_width_adapter as width_adapter, width_adapter_001
altera_avalon_st_handshake_clock_crosser as crosser, crosser_001, crosser_002, crosser_003
TR4_QSYS_uniphy_ddr3 altera_mem_if_ddr3_emif v11.0 | TR4_QSYS_uniphy_ddr3_c0 as c0 TR4_QSYS_uniphy_ddr3_p0 as p0
alt_vipcti110_Vid2IS alt_vip_cti v11.0 |
alt_vipitc110_IS2Vid alt_vip_itc v11.0 |
TR4_QSYS_frame_buffer alt_vip_vfb v11.0 | alt_cusp110_muxbin2 as vfb_writer_packet_write_address_au_l_muxinst, vfb_writer_packet_write_address_au_sload_muxinst, vfb_writer_first_packet_id_au_enable_muxinst, vfb_writer_first_packet_id_au_sload_muxinst, vfb_writer_next_to_last_packet_id_au_enable_muxinst, vfb_writer_overflow_trigger_au_sload_muxinst, vfb_writer_overflow_flag_reg_enable_muxinst, vfb_writer_word_counter_trigger_au_sload_muxinst, vfb_writer_field_interlace_reg_d_muxinst, vfb_writer_field_interlace_reg_enable_muxinst, vfb_writer_write_address_au_l_muxinst, vfb_reader_current_packet_id_au_l_muxinst, read_master_renable_trigger_muxinst, read_master_addr_muxinst, read_master_len_be_muxinst, write_master_len_be_muxinst, write_master_push_input_muxinst, vfb_writer_packets_sample_length_reg_d_muxinst, vfb_writer_packets_sample_length_reg_enable_muxinst, vfb_writer_packets_word_length_reg_d_muxinst, vfb_writer_packets_word_length_reg_enable_muxinst, packetdimensions_reg_d_muxinst, packetdimensions_reg_130_d_muxinst, packetdimensions_reg_1302_d_muxinst, packetdimensions_reg_1303_d_muxinst, output_reg_d_muxinst, output_reg_157_d_muxinst, output_reg_1572_d_muxinst, output_reg_1573_d_muxinst, output_reg_1574_d_muxinst, output_reg_1575_d_muxinst, msg_buffer_reply_id_3135_line154_d_muxinst, msg_buffer_id_3140_line162_d_muxinst, msg_field_width_id_3144_line164_d_muxinst, msg_field_height_id_3148_line166_d_muxinst, msg_field_interlace_id_3152_line168_d_muxinst, msg_samples_in_field_id_3156_line170_d_muxinst, msg_words_in_field_id_3160_line172_d_muxinst, msg_first_packet_id_3164_line214_d_muxinst, msg_next_to_last_packet_id_3168_line215_d_muxinst, vfb_reader_length_cnt_id_3239_line889_a_muxinst, vfb_reader_length_cnt_id_3248_line889_a_muxinst
alt_cusp110_au as vfb_writer_packet_write_address_au, vfb_writer_first_packet_id_au, vfb_writer_next_to_last_packet_id_au, vfb_writer_overflow_trigger_au, vfb_writer_length_counter_au, vfb_writer_word_counter_au, vfb_writer_word_counter_trigger_au, vfb_writer_write_address_au, vfb_reader_read_address_au, vfb_reader_packet_read_address_au, vfb_reader_current_packet_id_au, wrap_packet_id_id_3230_line1069, vfb_reader_length_cnt_4_id_3237_line889, vfb_reader_length_cnt_id_3239_line889, vfb_reader_length_cnt_id_3248_line889
alt_cusp110_reg as vfb_writer_overflow_flag_reg, vfb_writer_field_width_reg, vfb_writer_field_height_reg, vfb_writer_field_interlace_reg, vfb_writer_just_read_reg, vfb_writer_packets_sample_length_reg, vfb_writer_packets_word_length_reg, msg_packets_sample_length_reg, msg_packets_word_length_reg, packetdimensions_reg, packetdimensions_reg_130, packetdimensions_reg_1302, packetdimensions_reg_1303, output_reg, output_reg_157, output_reg_1572, output_reg_1573, output_reg_1574, output_reg_1575, output_reg_1576, output_reg_1577, output_reg_1578, msg_buffer_reply_id_3135_line154, msg_buffer_id_3140_line162, msg_field_width_id_3144_line164, msg_field_height_id_3148_line166, msg_field_interlace_id_3152_line168, msg_samples_in_field_id_3156_line170, msg_words_in_field_id_3160_line172, msg_first_packet_id_3164_line214, msg_next_to_last_packet_id_3168_line215, vfb_writer_buffer_id_3172_line220, write_to_read_buf_id_3175_line145, write_to_read_ack_id_3178_line156, vfb_writer_packet_base_address_0_id_3181_line196, isnotimagedata_0_id_3183_line144, iscontrolpacket_0_id_3185_line202, no_last_burst_0_id_3187_line301, no_last_burst_0_id_3191_line577, cond580_0_id_3193, drop_0_id_3195_line337, loop_repeat_0_id_3197_line359, burst_trigger_0_id_3199_line555, cond560_0_id_3201, vfb_reader_buffer_id_3203_line857, read_to_write_ack_id_3206_line148, read_to_write_buf_id_3209_line152, vfb_reader_field_width_0_id_3212_line765, vfb_reader_samples_in_field_0_id_3214_line881, vfb_reader_field_height_0_id_3216_line767, vfb_reader_words_in_field_0_id_3218_line883, vfb_reader_field_interlace_0_id_3220_line769, vfb_reader_next_to_last_packet_id_0_id_3222_line868, reader_packets_sample_length_0_id_3224_line870, reader_packets_word_length_0_id_3226_line872, vfb_reader_packet_base_address_0_id_3228_line865, vfb_reader_length_cnt_3_id_3233_line889, vfb_reader_word_cnt_0_id_3235_line890, repeat_0_id_3242_line1132, loop_repeat_0_id_3244_line1140, cond1195_0_id_3246, cond1105_0_id_3251, ispreviousendpacket_0_comb_id_7816, justreadqueue_1_1_comb_id_7819, justreadqueue_2_1_comb_id_7822, justreadqueue_1_2_comb_id_7825, ispreviousendpacket_1_comb_id_7828, justreadaccesswire_3_comb_id_7831, justreadaccesswire_4_comb_id_7834, justreadqueue_1_4_comb_id_7837, justreadqueue_2_2_comb_id_7840, justreadqueue_1_5_comb_id_7843, ispreviousendpacket_2_comb_id_7846, justreadaccesswire_6_comb_id_7849, justreadaccesswire_7_comb_id_7852, justreadqueue_1_7_comb_id_7855, justreadqueue_2_3_comb_id_7858, justreadqueue_1_8_comb_id_7861, word_counter_trigger_flag_0_comb_id_7864, op_2217_comb_id_7867, op_2217_comb_0_id_7870, op_4366_comb_id_7873, op_4368_comb_id_7876, op_3239_comb_id_7879, op_3239_comb_0_id_7882, op_4381_comb_id_7885, op_4382_comb_id_7888, cond1105_0_stage_1_id_7891, cond1105_0_stage_2_id_7894, cond1105_0_stage_3_id_7897, empty_image_0_comb_id_7900, cond1195_0_stage_1_id_7903, cond1195_0_stage_2_id_7906, cond1195_0_stage_3_id_7909
alt_cusp110_muxhot16 as vfb_writer_length_counter_au_enable_muxinst, vfb_writer_word_counter_au_enable_muxinst, vfb_writer_word_counter_au_enable_trigger_muxinst, vfb_writer_word_counter_trigger_au_enable_muxinst, vfb_writer_write_address_au_enable_trigger_muxinst, vfb_writer_just_read_reg_enable_muxinst, vfb_reader_packet_read_address_au_sload_muxinst, din_takeb_trigger_muxinst, dout_takeb_trigger_muxinst, dout_seteop_trigger_muxinst, dout_eop_muxinst, read_master_pull_pull_trigger_muxinst, write_master_cenable_trigger_muxinst, write_master_push_push_trigger_muxinst, pc0_usenextpc_trigger_muxinst, pc0_hold_trigger_muxinst, pc1_usenextpc_trigger_muxinst, pc1_hold_trigger_muxinst
alt_cusp110_avalon_st_input as din
alt_cusp110_muxfast4 as dout_wdata_muxinst
alt_cusp110_avalon_st_output as dout
alt_cusp110_avalon_mm_bursting_master_fifo as read_master, write_master
alt_cusp110_pulling_width_adapter as read_master_pull
alt_cusp110_pushing_width_adapter as write_master_push
alt_cusp110_pc as pc0, pc1
alt_cusp110_cmp as fu_id_4465_line317_93, fu_id_4481_line317_52, fu_id_4497_line201_52, fu_id_4667_line202_58, fu_id_4889_line330_94, fu_id_4898_line331_96, fu_id_5009_line631_55, fu_id_5237_line688_38, fu_id_5696_line502_66, fu_id_5824_line555_105, fu_id_6004_line925_38, fu_id_6242_line1054_114, fu_id_6258_line1055_112, fu_id_6274_line1070_53, fu_id_6283_line1086_53, fu_id_6340_line1180_29, fu_id_6468_line1240_53, fu_id_6714_line1118_52
alt_cusp110_clock_reset as clocksource
TR4_QSYS_frame_buffer as dut
altera_merlin_master_translator altera_merlin_master_translator v11.0 |
altera_merlin_slave_translator altera_merlin_slave_translator v11.0 |
altera_merlin_master_agent altera_merlin_master_agent v11.0 |
altera_merlin_slave_agent altera_merlin_slave_agent v11.0 |
altera_avalon_sc_fifo altera_avalon_sc_fifo v11.0 |
TR4_QSYS_addr_router altera_merlin_router v11.0 |
TR4_QSYS_id_router altera_merlin_router v11.0 |
altera_merlin_burst_adapter altera_merlin_burst_adapter v11.0 |
altera_reset_controller altera_reset_controller v11.0 |
TR4_QSYS_cmd_xbar_demux altera_merlin_demultiplexer v11.0 |
TR4_QSYS_cmd_xbar_mux altera_merlin_multiplexer v11.0 |
TR4_QSYS_rsp_xbar_demux altera_merlin_demultiplexer v11.0 |
altera_merlin_width_adapter altera_merlin_width_adapter v11.0 |
altera_avalon_st_handshake_clock_crosser altera_avalon_st_handshake_clock_crosser v11.0 |
TR4_QSYS_uniphy_ddr3_c0 altera_mem_if_nextgen_ddr3_controller v11.0 | alt_mem_if_nextgen_ddr3_controller_core as ng0 alt_mem_ddrx_mm_st_converter as a0
TR4_QSYS_uniphy_ddr3_p0 altera_mem_if_ddr3_phy v11.0 |
alt_cusp110_muxbin2 alt_cusp_muxbin2 v11.0 |
alt_cusp110_au alt_au v11.0 |
alt_cusp110_reg alt_reg v11.0 |
alt_cusp110_muxhot16 alt_cusp_muxhot16 v11.0 |
alt_cusp110_avalon_st_input alt_avalon_st_input v11.0 |
alt_cusp110_muxfast4 alt_cusp_muxfast4 v11.0 |
alt_cusp110_avalon_st_output alt_avalon_st_output v11.0 |
alt_cusp110_avalon_mm_bursting_master_fifo alt_avalon_mm_bursting_master_fifo v11.0 |
alt_cusp110_pulling_width_adapter alt_cusp_pulling_width_adapter v11.0 |
alt_cusp110_pushing_width_adapter alt_cusp_pushing_width_adapter v11.0 |
alt_cusp110_pc alt_pc v11.0 |
alt_cusp110_cmp alt_cmp v11.0 |
alt_cusp110_clock_reset alt_cusp_testbench_clock v11.0 |
alt_mem_if_nextgen_ddr3_controller_core altera_mem_if_nextgen_ddr3_controller_core v11.0 |
alt_mem_ddrx_mm_st_converter alt_mem_ddrx_mm_st_converter v11.0 |

Generation Messages
2011.10.27.15:56:14 [Info] TR4_QSYS.uniphy_ddr3: Auto interface leveling mode set to 'Leveling' 2011.10.27.15:52:58 [Debug] TR4_QSYS.uniphy_ddr3.c0.altera_mem_if_nextgen_ddr3_controller_core: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.c0.ng0: Timing: VAL:1/0.032s ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_reset: Timing: ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_clk: Timing: ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_half_clk: Timing: ELA:1/0.000s 2011.10.27.15:52:58 [Debug] TR4_QSYS.uniphy_ddr3.c0.alt_mem_ddrx_mm_st_converter: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.c0.a0: Timing: VAL:1/0.000s ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.c0: Timing: VAL:1/0.031s COM:1/0.125s 2011.10.27.15:52:57 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_phy: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.p0: Timing: VAL:1/0.250s ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.pll_ref_clk: Timing: ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.global_reset: Timing: ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.soft_reset: Timing: ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.afi_clk: Timing: ELA:2/0.000s/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.afi_half_clk: Timing: ELA:2/0.000s/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3.afi_reset: Timing: ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.uniphy_ddr3: Timing: VAL:1/0.250s COM:1/0.813s 2011.10.27.15:56:15 [Debug] TR4_QSYS.alt_vip_cti_0: Timing: ELA:1/0.000s 2011.10.27.15:56:15 [Debug] TR4_QSYS.alt_vip_itc_0: Timing: ELA:1/0.016s 2011.10.27.15:56:15 [Info] TR4_QSYS: Generating TR4_QSYS "TR4_QSYS" for QUARTUS_SYNTH 2011.10.27.15:56:16 [Debug] TR4_QSYS: queue size: 0 starting:TR4_QSYS "TR4_QSYS" 2011.10.27.15:56:17 [Debug] Transform: PipelineBridgeSwap 2011.10.27.15:56:18 [Info] pipeline_bridge_swap_transform: After transform: 5 modules, 13 connections 2011.10.27.15:56:18 [Debug] Transform: ClockCrossingBridgeSwap 2011.10.27.15:56:19 [Debug] Transform: QsysBetaIPSwap 2011.10.27.15:56:20 [Debug] Transform: CustomInstructionTransform 2011.10.27.15:56:22 [Info] No custom instruction connections, skipping transform 2011.10.27.15:56:22 [Debug] Transform: TristateConduitUpgradeTransform 2011.10.27.15:56:24 [Debug] Transform: TranslatorTransform 2011.10.27.15:56:25 [Progress] min: 0 2011.10.27.15:56:25 [Progress] max: 1 2011.10.27.15:56:25 [Progress] current: 1 2011.10.27.15:56:25 [Progress] min: 0 2011.10.27.15:56:25 [Progress] max: 1 2011.10.27.15:56:25 [Progress] current: 1 2011.10.27.15:56:25 [Progress] min: 0 2011.10.27.15:56:25 [Progress] max: 1 2011.10.27.15:56:25 [Progress] current: 1 2011.10.27.15:56:25 [Info] merlin_translator_transform: After transform: 8 modules, 22 connections 2011.10.27.15:56:25 [Debug] Transform: DomainTransform 2011.10.27.15:56:27 [Debug] Transform merlin_domain_transform not run on matched interfaces frame_buffer.read_master and frame_buffer_read_master_translator.avalon_anti_master_0 2011.10.27.15:56:27 [Debug] Transform merlin_domain_transform not run on matched interfaces frame_buffer.write_master and frame_buffer_write_master_translator.avalon_anti_master_0 2011.10.27.15:56:27 [Progress] min: 0 2011.10.27.15:56:27 [Progress] max: 1 2011.10.27.15:56:27 [Progress] current: 1 2011.10.27.15:56:27 [Progress] min: 0 2011.10.27.15:56:27 [Progress] max: 1 2011.10.27.15:56:27 [Progress] current: 1 2011.10.27.15:56:27 [Progress] min: 0 2011.10.27.15:56:27 [Progress] max: 1 2011.10.27.15:56:27 [Progress] current: 1 2011.10.27.15:56:27 [Progress] min: 0 2011.10.27.15:56:27 [Progress] max: 1 2011.10.27.15:56:27 [Progress] current: 1 2011.10.27.15:56:27 [Progress] min: 0 2011.10.27.15:56:27 [Progress] max: 1 2011.10.27.15:56:27 [Progress] current: 1 2011.10.27.15:56:27 [Debug] Transform merlin_domain_transform not run on matched interfaces uniphy_ddr3_avl_translator.avalon_anti_slave_0 and uniphy_ddr3.avl 2011.10.27.15:56:27 [Info] merlin_domain_transform: After transform: 14 modules, 49 connections 2011.10.27.15:56:27 [Debug] Transform: RouterTransform 2011.10.27.15:56:28 [Progress] min: 0 2011.10.27.15:56:28 [Progress] max: 1 2011.10.27.15:56:28 [Progress] current: 1 2011.10.27.15:56:28 [Progress] min: 0 2011.10.27.15:56:28 [Progress] max: 1 2011.10.27.15:56:28 [Progress] current: 1 2011.10.27.15:56:28 [Progress] min: 0 2011.10.27.15:56:28 [Progress] max: 1 2011.10.27.15:56:28 [Progress] current: 1 2011.10.27.15:56:28 [Info] merlin_router_transform: After transform: 17 modules, 58 connections 2011.10.27.15:56:28 [Debug] Transform: TrafficLimiterTransform 2011.10.27.15:56:29 [Debug] Transform: BurstTransform 2011.10.27.15:56:30 [Progress] min: 0 2011.10.27.15:56:30 [Progress] max: 1 2011.10.27.15:56:30 [Progress] current: 1 2011.10.27.15:56:31 [Info] merlin_burst_transform: After transform: 18 modules, 61 connections 2011.10.27.15:56:31 [Debug] Transform: ResetAdaptation 2011.10.27.15:56:32 [Progress] min: 0 2011.10.27.15:56:32 [Progress] max: 1 2011.10.27.15:56:32 [Progress] current: 1 2011.10.27.15:56:32 [Progress] min: 0 2011.10.27.15:56:32 [Progress] max: 1 2011.10.27.15:56:32 [Progress] current: 1 2011.10.27.15:56:32 [Info] reset_adaptation_transform: After transform: 20 modules, 65 connections 2011.10.27.15:56:32 [Debug] Transform: NetworkToSwitchTransform 2011.10.27.15:56:33 [Progress] min: 0 2011.10.27.15:56:33 [Progress] max: 1 2011.10.27.15:56:33 [Progress] current: 1 2011.10.27.15:56:33 [Progress] min: 0 2011.10.27.15:56:33 [Progress] max: 1 2011.10.27.15:56:33 [Progress] current: 1 2011.10.27.15:56:33 [Progress] min: 0 2011.10.27.15:56:33 [Progress] max: 1 2011.10.27.15:56:33 [Progress] current: 1 2011.10.27.15:56:33 [Progress] min: 0 2011.10.27.15:56:33 [Progress] max: 1 2011.10.27.15:56:33 [Progress] current: 1 2011.10.27.15:56:33 [Progress] min: 0 2011.10.27.15:56:33 [Progress] max: 1 2011.10.27.15:56:33 [Progress] current: 1 2011.10.27.15:56:33 [Progress] min: 0 2011.10.27.15:56:33 [Progress] max: 1 2011.10.27.15:56:33 [Progress] current: 1 2011.10.27.15:56:33 [Info] merlin_network_to_switch_transform: After transform: 25 modules, 75 connections 2011.10.27.15:56:33 [Debug] Transform: WidthTransform 2011.10.27.15:56:34 [Progress] min: 0 2011.10.27.15:56:34 [Progress] max: 1 2011.10.27.15:56:34 [Progress] current: 1 2011.10.27.15:56:34 [Progress] min: 0 2011.10.27.15:56:34 [Progress] max: 1 2011.10.27.15:56:34 [Progress] current: 1 2011.10.27.15:56:34 [Info] merlin_width_transform: After transform: 27 modules, 81 connections 2011.10.27.15:56:34 [Debug] Transform: RouterTableTransform 2011.10.27.15:56:36 [Debug] Transform: ClockCrossingTransform 2011.10.27.15:56:37 [Info] Inserting clock-crossing logic between cmd_xbar_demux.src0 and cmd_xbar_mux.sink0 2011.10.27.15:56:37 [Progress] min: 0 2011.10.27.15:56:37 [Progress] max: 1 2011.10.27.15:56:37 [Progress] current: 1 2011.10.27.15:56:37 [Info] Inserting clock-crossing logic between cmd_xbar_demux_001.src0 and cmd_xbar_mux.sink1 2011.10.27.15:56:37 [Progress] min: 0 2011.10.27.15:56:37 [Progress] max: 1 2011.10.27.15:56:37 [Progress] current: 1 2011.10.27.15:56:37 [Info] Inserting clock-crossing logic between rsp_xbar_demux.src0 and rsp_xbar_mux.sink0 2011.10.27.15:56:37 [Progress] min: 0 2011.10.27.15:56:37 [Progress] max: 1 2011.10.27.15:56:37 [Progress] current: 1 2011.10.27.15:56:37 [Info] Inserting clock-crossing logic between rsp_xbar_demux.src1 and rsp_xbar_mux_001.sink0 2011.10.27.15:56:37 [Progress] min: 0 2011.10.27.15:56:37 [Progress] max: 1 2011.10.27.15:56:37 [Progress] current: 1 2011.10.27.15:56:37 [Info] com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform: After transform: 31 modules, 101 connections 2011.10.27.15:56:37 [Debug] Transform: PipelineTransform 2011.10.27.15:56:38 [Debug] Transform: TrafficLimiterUpdateTransform 2011.10.27.15:56:39 [Debug] Transform: InterruptMapperTransform 2011.10.27.15:56:41 [Debug] Transform: InterruptSyncTransform 2011.10.27.15:56:42 [Debug] Transform: InterruptFanoutTransform 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses alt_vip_cti "submodules/alt_vipcti110_Vid2IS" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses alt_vip_itc "submodules/alt_vipitc110_IS2Vid" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses alt_vip_vfb "submodules/TR4_QSYS_frame_buffer" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.10.27.15:56:45 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.10.27.15:56:45 [Debug] TR4_QSYS: queue size: 27 starting:altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2011.10.27.15:56:45 [Info] uniphy_ddr3: Running transform AvalonTransform 2011.10.27.15:56:45 [Debug] Transform: PipelineBridgeSwap 2011.10.27.15:56:46 [Info] pipeline_bridge_swap_transform: After transform: 8 modules, 10 connections 2011.10.27.15:56:46 [Debug] Transform: ClockCrossingBridgeSwap 2011.10.27.15:56:46 [Debug] Transform: QsysBetaIPSwap 2011.10.27.15:56:47 [Debug] Transform: CustomInstructionTransform 2011.10.27.15:56:47 [Info] No custom instruction connections, skipping transform 2011.10.27.15:56:47 [Debug] Transform: TristateConduitUpgradeTransform 2011.10.27.15:56:48 [Debug] Transform: TranslatorTransform 2011.10.27.15:56:48 [Info] No Avalon connections, skipping transform 2011.10.27.15:56:48 [Debug] Transform: DomainTransform 2011.10.27.15:56:49 [Debug] Transform: RouterTransform 2011.10.27.15:56:49 [Debug] Transform: TrafficLimiterTransform 2011.10.27.15:56:50 [Debug] Transform: BurstTransform 2011.10.27.15:56:50 [Debug] Transform: ResetAdaptation 2011.10.27.15:56:51 [Debug] Transform: NetworkToSwitchTransform 2011.10.27.15:56:51 [Debug] Transform: WidthTransform 2011.10.27.15:56:51 [Debug] Transform: RouterTableTransform 2011.10.27.15:56:52 [Debug] Transform: ClockCrossingTransform 2011.10.27.15:56:52 [Debug] Transform: TrafficLimiterUpdateTransform 2011.10.27.15:56:53 [Debug] Transform: InterruptMapperTransform 2011.10.27.15:56:53 [Debug] Transform: InterruptSyncTransform 2011.10.27.15:56:54 [Debug] Transform: InterruptFanoutTransform 2011.10.27.15:56:55 [Info] uniphy_ddr3: Running transform AvalonTransform took 9.828s 2011.10.27.15:56:55 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2011.10.27.15:56:55 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_phy "submodules/TR4_QSYS_uniphy_ddr3_p0" 2011.10.27.15:56:55 [Info] uniphy_ddr3: "TR4_QSYS" instantiated altera_mem_if_ddr3_emif "uniphy_ddr3" 2011.10.27.15:56:55 [Debug] TR4_QSYS: queue size: 28 starting:alt_vip_cti "submodules/alt_vipcti110_Vid2IS" 2011.10.27.15:56:55 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.10.27.15:56:55 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0001_sopcqmap/not_a_project_setup.tcl 2011.10.27.15:56:55 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=C:/altera/11.0/ip/altera/clocked_video_input/src_hdl/alt_vipcti110_Vid2IS.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0001_sopcqmap/ 2011.10.27.15:57:28 [Debug] Command took 33.062s 2011.10.27.15:57:38 [Debug] Command took 9.766s 2011.10.27.15:57:38 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.10.27.15:57:38 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0002_sopcqmap/not_a_project_setup.tcl 2011.10.27.15:57:38 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe "not_a_project" "--generate_hdl_interface=C:\\altera\\11.0\\ip\\altera\\clocked_video_input\\src_hdl\\alt_vipcti110_Vid2IS.v" "--set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0002_sopcqmap/" "--set=HDL_INTERFACE_INSTANCE_NAME=inst" "--set=HDL_INTERFACE_INSTANCE_ENTITY=alt_vipcti110_Vid2IS" "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=BPS=D\"8\";NUMBER_OF_COLOUR_PLANES=D\"3\";COLOUR_PLANES_ARE_IN_PARALLEL=D\"1\";SYNC_TO=D\"2\";USE_EMBEDDED_SYNCS=D\"0\";ACCEPT_COLOURS_IN_SEQ=D\"0\";USE_STD=D\"0\";STD_WIDTH=D\"1\";GENERATE_ANC=D\"0\";INTERLACED=D\"0\";H_ACTIVE_PIXELS_F0=D\"800\";V_ACTIVE_LINES_F0=D\"600\";V_ACTIVE_LINES_F1=D\"32\";FIFO_DEPTH=D\"4800\";CLOCKS_ARE_SAME=D\"0\";USE_CONTROL=D\"0\";GENERATE_SYNC=D\"0\";" 2011.10.27.15:57:48 [Debug] Command took 10.203s 2011.10.27.15:57:55 [Debug] Command took 7.015s 2011.10.27.15:57:55 [Info] alt_vip_cti_0: "TR4_QSYS" instantiated alt_vip_cti "alt_vip_cti_0" 2011.10.27.15:57:55 [Debug] TR4_QSYS: queue size: 27 starting:alt_vip_itc "submodules/alt_vipitc110_IS2Vid" 2011.10.27.15:57:55 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.10.27.15:57:55 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0003_sopcqmap/not_a_project_setup.tcl 2011.10.27.15:57:55 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=C:/altera/11.0/ip/altera/clocked_video_output/src_hdl/alt_vipitc110_IS2Vid.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0003_sopcqmap/ 2011.10.27.15:58:05 [Debug] Command took 10.078s 2011.10.27.15:58:20 [Debug] Command took 15.250s 2011.10.27.15:58:20 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.10.27.15:58:20 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_sh.exe -t C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0004_sopcqmap/not_a_project_setup.tcl 2011.10.27.15:58:20 [Debug] Command: C:/altera/11.0/quartus/bin/quartus_map.exe "not_a_project" "--generate_hdl_interface=C:\\altera\\11.0\\ip\\altera\\clocked_video_output\\src_hdl\\alt_vipitc110_IS2Vid.v" "--set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5274_2939508332566261511.dir/0004_sopcqmap/" "--set=HDL_INTERFACE_INSTANCE_NAME=inst" "--set=HDL_INTERFACE_INSTANCE_ENTITY=alt_vipitc110_IS2Vid" "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=NUMBER_OF_COLOUR_PLANES=D\"3\";COLOUR_PLANES_ARE_IN_PARALLEL=D\"1\";BPS=D\"8\";INTERLACED=D\"0\";H_ACTIVE_PIXELS=D\"800\";V_ACTIVE_LINES=D\"480\";ACCEPT_COLOURS_IN_SEQ=D\"0\";FIFO_DEPTH=D\"512\";CLOCKS_ARE_SAME=D\"0\";USE_CONTROL=D\"0\";NO_OF_MODES=D\"1\";THRESHOLD=D\"0\";STD_WIDTH=D\"1\";GENERATE_SYNC=D\"0\";USE_EMBEDDED_SYNCS=D\"0\";AP_LINE=D\"0\";V_BLANK=D\"0\";H_BLANK=D\"0\";H_SYNC_LENGTH=D\"30\";H_FRONT_PORCH=D\"210\";H_BACK_PORCH=D\"16\";V_SYNC_LENGTH=D\"13\";V_FRONT_PORCH=D\"22\";V_BACK_PORCH=D\"10\";F_RISING_EDGE=D\"0\";F_FALLING_EDGE=D\"0\";FIELD0_V_RISING_EDGE=D\"0\";FIELD0_V_BLANK=D\"0\";FIELD0_V_SYNC_LENGTH=D\"0\";FIELD0_V_FRONT_PORCH=D\"0\";FIELD0_V_BACK_PORCH=D\"0\";ANC_LINE=D\"0\";FIELD0_ANC_LINE=D\"0\";" 2011.10.27.15:58:37 [Debug] Command took 16.953s 2011.10.27.15:58:46 [Debug] Command took 8.188s 2011.10.27.15:58:46 [Info] alt_vip_itc_0: "TR4_QSYS" instantiated alt_vip_itc "alt_vip_itc_0" 2011.10.27.15:58:46 [Debug] TR4_QSYS: queue size: 26 starting:alt_vip_vfb "submodules/TR4_QSYS_frame_buffer" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_avalon_st_input "submodules/alt_cusp110_avalon_st_input" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxfast4 "submodules/alt_cusp110_muxfast4" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_avalon_st_output "submodules/alt_cusp110_avalon_st_output" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp110_avalon_mm_bursting_master_fifo" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp110_pulling_width_adapter" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp110_avalon_mm_bursting_master_fifo" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp110_pushing_width_adapter" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_pc "submodules/alt_cusp110_pc" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_pc "submodules/alt_cusp110_pc" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_au "submodules/alt_cusp110_au" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:55 [Debug] frame_buffer: "frame_buffer" reuses alt_reg "submodules/alt_cusp110_reg" 2011.10.27.15:58:56 [Debug] dut: "dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp110_clock_reset" 2011.10.27.15:58:56 [Debug] dut: "dut" reuses alt_vip_vfb "submodules/TR4_QSYS_frame_buffer" 2011.10.27.15:58:56 [Info] frame_buffer: "TR4_QSYS" instantiated alt_vip_vfb "frame_buffer" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 223 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.10.27.15:58:57 [Info] frame_buffer_read_master_translator: "TR4_QSYS" instantiated altera_merlin_master_translator "frame_buffer_read_master_translator" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 221 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.10.27.15:58:57 [Info] uniphy_ddr3_avl_translator: "TR4_QSYS" instantiated altera_merlin_slave_translator "uniphy_ddr3_avl_translator" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 220 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.10.27.15:58:57 [Info] frame_buffer_read_master_translator_avalon_universal_master_0_agent: "TR4_QSYS" instantiated altera_merlin_master_agent "frame_buffer_read_master_translator_avalon_universal_master_0_agent" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 218 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.10.27.15:58:57 [Info] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent: "TR4_QSYS" instantiated altera_merlin_slave_agent "uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 217 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.10.27.15:58:57 [Info] uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo: "TR4_QSYS" instantiated altera_avalon_sc_fifo "uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 215 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router" 2011.10.27.15:58:57 [Info] addr_router: "TR4_QSYS" instantiated altera_merlin_router "addr_router" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 213 starting:altera_merlin_router "submodules/TR4_QSYS_id_router" 2011.10.27.15:58:57 [Info] id_router: "TR4_QSYS" instantiated altera_merlin_router "id_router" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 212 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" 2011.10.27.15:58:57 [Info] burst_adapter: "TR4_QSYS" instantiated altera_merlin_burst_adapter "burst_adapter" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 211 starting:altera_reset_controller "submodules/altera_reset_controller" 2011.10.27.15:58:57 [Info] rst_controller: "TR4_QSYS" instantiated altera_reset_controller "rst_controller" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 209 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2011.10.27.15:58:57 [Info] cmd_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 207 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2011.10.27.15:58:57 [Info] cmd_xbar_mux: "TR4_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 206 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2011.10.27.15:58:57 [Info] rsp_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 205 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.10.27.15:58:57 [Info] width_adapter: "TR4_QSYS" instantiated altera_merlin_width_adapter "width_adapter" 2011.10.27.15:58:57 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 203 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.10.27.15:58:57 [Info] crosser: "TR4_QSYS" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2011.10.27.15:58:57 [Debug] TR4_QSYS: queue size: 199 starting:altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2011.10.27.15:58:57 [Info] c0: Running transform AvalonTransform 2011.10.27.15:58:57 [Debug] Transform: PipelineBridgeSwap 2011.10.27.15:58:57 [Info] pipeline_bridge_swap_transform: After transform: 5 modules, 8 connections 2011.10.27.15:58:57 [Debug] Transform: ClockCrossingBridgeSwap 2011.10.27.15:58:57 [Debug] Transform: QsysBetaIPSwap 2011.10.27.15:58:57 [Debug] Transform: CustomInstructionTransform 2011.10.27.15:58:57 [Info] No custom instruction connections, skipping transform 2011.10.27.15:58:57 [Debug] Transform: TristateConduitUpgradeTransform 2011.10.27.15:58:58 [Debug] Transform: TranslatorTransform 2011.10.27.15:58:58 [Info] No Avalon connections, skipping transform 2011.10.27.15:58:58 [Debug] Transform: DomainTransform 2011.10.27.15:58:58 [Debug] Transform: RouterTransform 2011.10.27.15:58:58 [Debug] Transform: TrafficLimiterTransform 2011.10.27.15:58:58 [Debug] Transform: BurstTransform 2011.10.27.15:58:58 [Debug] Transform: ResetAdaptation 2011.10.27.15:58:58 [Debug] Transform: NetworkToSwitchTransform 2011.10.27.15:58:58 [Debug] Transform: WidthTransform 2011.10.27.15:58:58 [Debug] Transform: RouterTableTransform 2011.10.27.15:58:58 [Debug] Transform: ClockCrossingTransform 2011.10.27.15:58:58 [Debug] Transform: TrafficLimiterUpdateTransform 2011.10.27.15:58:58 [Debug] Transform: InterruptMapperTransform 2011.10.27.15:58:59 [Debug] Transform: InterruptSyncTransform 2011.10.27.15:58:59 [Debug] Transform: InterruptFanoutTransform 2011.10.27.15:58:59 [Info] c0: Running transform AvalonTransform took 1.813s 2011.10.27.15:58:59 [Debug] c0: "c0" reuses altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2011.10.27.15:58:59 [Debug] c0: "c0" reuses alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2011.10.27.15:58:59 [Info] c0: "uniphy_ddr3" instantiated altera_mem_if_nextgen_ddr3_controller "c0" 2011.10.27.15:58:59 [Debug] TR4_QSYS: queue size: 200 starting:altera_mem_if_ddr3_phy "submodules/TR4_QSYS_uniphy_ddr3_p0" 2011.10.27.16:01:30 [Info] p0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_phy "p0" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_reset_controller.v 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 199 starting:alt_cusp_muxbin2 "submodules/alt_cusp110_muxbin2" 2011.10.27.16:01:30 [Info] vfb_writer_packet_write_address_au_l_muxinst: "frame_buffer" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst" 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 197 starting:alt_au "submodules/alt_cusp110_au" 2011.10.27.16:01:30 [Info] vfb_writer_packet_write_address_au: "frame_buffer" instantiated alt_au "vfb_writer_packet_write_address_au" 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 188 starting:alt_reg "submodules/alt_cusp110_reg" 2011.10.27.16:01:30 [Info] vfb_writer_overflow_flag_reg: "frame_buffer" instantiated alt_reg "vfb_writer_overflow_flag_reg" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 187 starting:alt_cusp_muxhot16 "submodules/alt_cusp110_muxhot16" 2011.10.27.16:01:30 [Info] vfb_writer_length_counter_au_enable_muxinst: "frame_buffer" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst" 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 163 starting:alt_avalon_st_input "submodules/alt_cusp110_avalon_st_input" 2011.10.27.16:01:30 [Info] din: "frame_buffer" instantiated alt_avalon_st_input "din" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 161 starting:alt_cusp_muxfast4 "submodules/alt_cusp110_muxfast4" 2011.10.27.16:01:30 [Info] dout_wdata_muxinst: "frame_buffer" instantiated alt_cusp_muxfast4 "dout_wdata_muxinst" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 158 starting:alt_avalon_st_output "submodules/alt_cusp110_avalon_st_output" 2011.10.27.16:01:30 [Info] dout: "frame_buffer" instantiated alt_avalon_st_output "dout" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 154 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp110_avalon_mm_bursting_master_fifo" 2011.10.27.16:01:30 [Info] read_master: "frame_buffer" instantiated alt_avalon_mm_bursting_master_fifo "read_master" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 152 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp110_pulling_width_adapter" 2011.10.27.16:01:30 [Info] read_master_pull: "frame_buffer" instantiated alt_cusp_pulling_width_adapter "read_master_pull" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 146 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp110_pushing_width_adapter" 2011.10.27.16:01:30 [Info] write_master_push: "frame_buffer" instantiated alt_cusp_pushing_width_adapter "write_master_push" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 112 starting:alt_pc "submodules/alt_cusp110_pc" 2011.10.27.16:01:30 [Info] pc0: "frame_buffer" instantiated alt_pc "pc0" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:30 [Debug] TR4_QSYS: queue size: 53 starting:alt_cmp "submodules/alt_cusp110_cmp" 2011.10.27.16:01:30 [Info] fu_id_4465_line317_93: "frame_buffer" instantiated alt_cmp "fu_id_4465_line317_93" 2011.10.27.16:01:30 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:31 [Debug] TR4_QSYS: queue size: 3 starting:alt_cusp_testbench_clock "submodules/alt_cusp110_clock_reset" 2011.10.27.16:01:31 [Info] clocksource: "frame_buffer" instantiated alt_cusp_testbench_clock "clocksource" 2011.10.27.16:01:31 [Info] Reusing file E:/yq_share/TR4_DDR3_UniPHY_1G_QSYS_MTLC/TR4_QSYS/synthesis/submodules/alt_cusp110_package.vhd 2011.10.27.16:01:31 [Debug] TR4_QSYS: queue size: 1 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2011.10.27.16:01:31 [Info] ng0: "c0" instantiated altera_mem_if_nextgen_ddr3_controller_core "ng0" 2011.10.27.16:01:31 [Debug] TR4_QSYS: queue size: 0 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2011.10.27.16:01:31 [Info] a0: "c0" instantiated alt_mem_ddrx_mm_st_converter "a0" 2011.10.27.16:01:31 [Info] TR4_QSYS: Done TR4_QSYS" with 36 modules, 592 files, 27734180 bytes