module reset_ctrl (
iclk,
irst_n,
orst_n,
orst_n1,
);


input			iclk;
input			irst_n;
output			orst_n;
output			orst_n1;

reg	[27:0]		clk_cnt;
reg				orst_n;
wire			orst_n1;

always@(posedge iclk or negedge irst_n)
	begin
		if (!irst_n)
			begin
				orst_n <= 1'b0;
				clk_cnt <= 28'h0;
			end
		else if (clk_cnt == 500000)
			begin
				orst_n <= 1'b1;
				clk_cnt <= clk_cnt;
			end
		else
			begin
				orst_n <= 1'b0;
				clk_cnt <= clk_cnt + 1;
			end
	end

assign orst_n1 = (clk_cnt >= 250000) ? 1'b1 : 1'b0;

							 	
endmodule