// --------------------------------------------------------------------
// Copyright (c) 2011 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
//
// Major Functions:	TR4 DDR3 1G
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V1.0 :| Vic chang         :| 08/26/11  :| Initial Revision
// --------------------------------------------------------------------


module tr4_golden_top(

							///////////BUTTON/////////////
							BUTTON,

							/////////FAN/////////
							FAN_CTRL,
							FAN_SPEED,

							/////////FLASH/////////
							FLASH_ADV_n,
							FLASH_CE_n,
							FLASH_CLK,
							FLASH_RDY_BSY_n,
							FLASH_RESET_n,
							FLASH_WP_n,

							/////////FSM/////////
							FSM_A,
							FSM_D,
							FSM_OE_n,
							FSM_WE_n,

							/////////HSMA/////////
							HSMA_CLKIN0,
							HSMA_CLKIN_n1,
							HSMA_CLKIN_n2,
							HSMA_CLKIN_p1,
							HSMA_CLKIN_p2,
							HSMA_D,
							HSMA_OUT0,
							HSMA_OUT_n1,
							HSMA_OUT_n2,
							HSMA_OUT_p1,
							HSMA_OUT_p2,
							HSMA_RX_n,
							HSMA_RX_p,
							HSMA_TX_n,
							HSMA_TX_p,

							/////////HSMB/////////
							HSMB_CLKIN0,
							HSMB_CLKIN_n1,
							HSMB_CLKIN_n2,
							HSMB_CLKIN_p1,
							HSMB_CLKIN_p2,
							HSMB_D,
							HSMB_OUT0,
							HSMB_OUT_n1,
							HSMB_OUT_n2,
							HSMB_OUT_p1,
							HSMB_OUT_p2,
							HSMB_RX_n,
							HSMB_RX_p,
							HSMB_SCL,
							HSMB_SDA,
							HSMB_TX_n,
							HSMB_TX_p,

							/////////HSMC/////////
							HSMC_CLKIN0,
							HSMC_CLKIN_n1,
							HSMC_CLKIN_n2,
							HSMC_CLKIN_p1,
							HSMC_CLKIN_p2,
							HSMC_CLKOUT_n1,
							HSMC_CLKOUT_p1,
							HSMC_D,
							HSMC_OUT0,
							HSMC_OUT_n2,
							HSMC_OUT_p2,
							HSMC_RX_n,
							HSMC_RX_p,
							HSMC_TX_n,
							HSMC_TX_p,

							/////////HSMD/////////
							HSMD_CLKIN0,
							HSMD_CLKIN_n1,
							HSMD_CLKIN_n2,
							HSMD_CLKIN_p1,
							HSMD_CLKIN_p2,
							HSMD_CLKOUT_n1,
							HSMD_CLKOUT_p1,
							HSMD_D,
							HSMD_OUT0,
							HSMD_OUT_n2,
							HSMD_OUT_p2,
							HSMD_RX_n,
							HSMD_RX_p,
							HSMD_SCL,
							HSMD_SDA,
							HSMD_TX_n,
							HSMD_TX_p,

							/////////HSME/////////
							HSME_CLKIN0,
							HSME_CLKIN_n1,
							HSME_CLKIN_n2,
							HSME_CLKIN_p1,
							HSME_CLKIN_p2,
							HSME_CLKOUT_n1,
							HSME_CLKOUT_p1,
							HSME_D,
							HSME_OUT0,
							HSME_OUT_n2,
							HSME_OUT_p2,
							HSME_RX_n,
							HSME_RX_p,
							HSME_TX_n,
							HSME_TX_p,

//							/////////HSMF/////////
//							HSMF_CLKIN0,
//							HSMF_CLKIN_n1,
//							HSMF_CLKIN_n2,
//							HSMF_CLKIN_p1,
//							HSMF_CLKIN_p2,
//							HSMF_CLKOUT_n1,
//							HSMF_CLKOUT_n2,
//							HSMF_CLKOUT_p1,
//							HSMF_CLKOUT_p2,
//							HSMF_D,
//							HSMF_OUT0,
//							HSMF_RX_n,
//							HSMF_RX_p,
//							HSMF_TX_n,
//							HSMF_TX_p,

							/////////LED/////////
							LED,

							/////////LOOP/////////
							LOOP_CLKIN0,
							LOOP_CLKOUT0,
							LOOP_CLKIN1,
							LOOP_CLKOUT1,

							/////////MAX2/////////
							MAX2_CS_n,
							MAX2_I2C_SCL,
							MAX2_I2C_SDA,

							/////////mem/////////
							mem_a,
							mem_ba,
							mem_cas_n,
							mem_cke,
							mem_ck,
							mem_ck_n,
							mem_cs_n,
							mem_dm,
							mem_dq,
							mem_dqs,
							mem_dqs_n,
							mem_event_n,
							mem_odt,
							mem_ras_n,
							mem_reset_n,
							mem_scl,
							mem_sda,
							mem_we_n,

							/////////OSC/////////
							OSC_50_BANK1,
							OSC_50_BANK3,
							OSC_50_BANK4,
							OSC_50_BANK7,
							OSC_50_BANK8,

							/////////mem_oct_rdn/////////
							mem_oct_rdn,

							/////////mem_oct_rup/////////
							mem_oct_rup,

							/////////SMA/////////
							SMA_CLKIN,
							SMA_CLKOUT,
							SMA_CLKOUT_n,
							SMA_CLKOUT_p,

							/////////SSRAM/////////
							SSRAM_ADSC_n,
							SSRAM_ADSP_n,
							SSRAM_ADV_n,
							SSRAM_BE_n,
							SSRAM_CE1_n,
							SSRAM_CLK,

							/////////SW/////////
							SW,

							/////////TEMP/////////
							TEMP_CLK,
							TEMP_DATA,
							TEMP_INT_n,
							TEMP_OVERT_n,
							
							//////////MTLC/////
								CAMERA_D,
	CAMERA_FVAL,
	CAMERA_LVAL,
	CAMERA_PIXCLK,
	CAMERA_RESET_n,
	CAMERA_SCLK,
	CAMERA_SDATA,
	CAMERA_STROBE,
	CAMERA_TRIGGER,
	CAMERA_XCLKIN,
	GSENSOR_ALT_ADDR,
	GSENSOR_CS_n,
	GSENSOR_INT1,
	GSENSOR_INT2,
	GSENSOR_SCL_SCLK,
	GSENSOR_SDA_SDI_SDIO,
	LCD_B,
	LCD_DCLK,
	LCD_DE,
	LCD_DIM,
	LCD_DITH,
	LCD_G,
	LCD_HSD,
	LCD_MODE,
	LCD_POWER_CTL,
	LCD_R,
	LCD_RSTB,
	LCD_SHLR,
	LCD_UPDN,
	LCD_VSD,
	LSENSOR_ADDR_SEL,
	LSENSOR_INT,
	LSENSOR_SCL,
	LSENSOR_SDA,
	TOUCH_I2C_SCL,
	TOUCH_I2C_SDA,
	TOUCH_INT_n,
);

//=======================================================
//  PORT declarations
//=======================================================
///////////BUTTON/////////////
input							[3:0]							BUTTON;

///////// FAN /////////
output														FAN_CTRL;
input															FAN_SPEED;

///////// FLASH /////////
output														FLASH_ADV_n;
output														FLASH_CE_n;
output														FLASH_CLK;
input															FLASH_RDY_BSY_n;
output														FLASH_RESET_n;
output														FLASH_WP_n;

///////// FSM /////////
output							[25:1]					FSM_A;
inout							[31:0]						FSM_D;
output														FSM_OE_n;
output														FSM_WE_n;

///////// HSMA /////////
input															HSMA_CLKIN0;
input															HSMA_CLKIN_n1;
input															HSMA_CLKIN_n2;
input															HSMA_CLKIN_p1;
input															HSMA_CLKIN_p2;
inout							[3:0]							HSMA_D;
inout															HSMA_OUT0;
inout															HSMA_OUT_n1;
inout															HSMA_OUT_n2;
inout															HSMA_OUT_p1;
inout															HSMA_OUT_p2;
inout							[16:0]						HSMA_RX_n;
inout							[16:0]						HSMA_RX_p;
inout							[16:0]						HSMA_TX_n;
inout							[16:0]						HSMA_TX_p;

///////// HSMB /////////
input															HSMB_CLKIN0;
input															HSMB_CLKIN_n1;
input															HSMB_CLKIN_n2;
input															HSMB_CLKIN_p1;
input															HSMB_CLKIN_p2;
inout							[3:0]							HSMB_D;
inout															HSMB_OUT0;
inout															HSMB_OUT_n1;
inout															HSMB_OUT_n2;
inout															HSMB_OUT_p1;
inout															HSMB_OUT_p2;
inout							[16:0]						HSMB_RX_n;
inout							[16:0]						HSMB_RX_p;
output														HSMB_SCL;
inout															HSMB_SDA;
inout							[16:0]						HSMB_TX_n;
inout							[16:0]						HSMB_TX_p;

///////// HSMC /////////
input															HSMC_CLKIN0;
input															HSMC_CLKIN_n1;
input															HSMC_CLKIN_n2;
input															HSMC_CLKIN_p1;
input															HSMC_CLKIN_p2;
inout															HSMC_CLKOUT_n1;
inout															HSMC_CLKOUT_p1;
inout							[3:0]							HSMC_D;
inout															HSMC_OUT0;
inout															HSMC_OUT_n2;
inout															HSMC_OUT_p2;
inout							[16:0]						HSMC_RX_n;
inout							[16:0]						HSMC_RX_p;
inout							[16:0]						HSMC_TX_n;
inout							[16:0]						HSMC_TX_p;

///////// HSMD /////////
input															HSMD_CLKIN0;
input															HSMD_CLKIN_n1;
input															HSMD_CLKIN_n2;
input															HSMD_CLKIN_p1;
input															HSMD_CLKIN_p2;
inout															HSMD_CLKOUT_n1;
inout															HSMD_CLKOUT_p1;
inout							[3:0]							HSMD_D;
inout															HSMD_OUT0;
inout															HSMD_OUT_n2;
inout															HSMD_OUT_p2;
inout							[16:0]						HSMD_RX_n;
inout							[16:0]						HSMD_RX_p;
output														HSMD_SCL;
inout															HSMD_SDA;
inout							[16:0]						HSMD_TX_n;
inout							[16:0]						HSMD_TX_p;

///////// HSME /////////
input															HSME_CLKIN0;
input															HSME_CLKIN_n1;
input															HSME_CLKIN_n2;
input															HSME_CLKIN_p1;
input															HSME_CLKIN_p2;
inout															HSME_CLKOUT_n1;
inout															HSME_CLKOUT_p1;
inout							[3:0]							HSME_D;
inout															HSME_OUT0;
inout															HSME_OUT_n2;
inout															HSME_OUT_p2;
inout							[16:0]						HSME_RX_n;
inout							[16:0]						HSME_RX_p;
inout							[16:0]						HSME_TX_n;
inout							[16:0]						HSME_TX_p;

/////////// HSMF /////////
//input															HSMF_CLKIN0;
//input															HSMF_CLKIN_n1;
//input															HSMF_CLKIN_n2;
//input															HSMF_CLKIN_p1;
//input															HSMF_CLKIN_p2;
//inout															HSMF_CLKOUT_n1;
//inout															HSMF_CLKOUT_n2;
//inout															HSMF_CLKOUT_p1;
//inout															HSMF_CLKOUT_p2;
//inout							[3:0]							HSMF_D;
//inout															HSMF_OUT0;
//inout							[16:0]						HSMF_RX_n;
//inout							[16:0]						HSMF_RX_p;
//inout							[16:0]						HSMF_TX_n;
//inout							[16:0]						HSMF_TX_p;

///////// LED /////////
output							[3:0]						LED;

///////// LOOP /////////
input															LOOP_CLKIN0;
output														LOOP_CLKOUT0;
input															LOOP_CLKIN1;
output														LOOP_CLKOUT1;

///////// MAX2 /////////
output														MAX2_CS_n;
output														MAX2_I2C_SCL;
inout															MAX2_I2C_SDA;

///////// mem /////////
output							[15:0]					mem_a;
output							[2:0]						mem_ba;
output														mem_cas_n;
output							[1:0]						mem_cke;
output							[1:0]						mem_ck;
output							[1:0]						mem_ck_n;
output							[1:0]						mem_cs_n;
output							[7:0]						mem_dm;
inout								[63:0]					mem_dq;
inout								[7:0]						mem_dqs;
inout								[7:0]						mem_dqs_n;
input															mem_event_n;
output							[1:0]						mem_odt;
output														mem_ras_n;
output														mem_reset_n;
output														mem_scl;
inout															mem_sda;
output														mem_we_n;

///////// OSC /////////
input															OSC_50_BANK1;
input															OSC_50_BANK3;
input															OSC_50_BANK4;
input															OSC_50_BANK7;
input															OSC_50_BANK8;

///////// mem_oct_rdn /////////
input															mem_oct_rdn;

///////// mem_oct_rup /////////
input															mem_oct_rup;

///////// SMA /////////
input															SMA_CLKIN;
output														SMA_CLKOUT;
output														SMA_CLKOUT_n;
output														SMA_CLKOUT_p;

///////// SSRAM /////////
output														SSRAM_ADSC_n;
output														SSRAM_ADSP_n;
output														SSRAM_ADV_n;
output							[3:0]						SSRAM_BE_n;
output														SSRAM_CE1_n;
output														SSRAM_CLK;

///////// SW /////////
input							[3:0]							SW;

///////// TEMP /////////
output														TEMP_CLK;
inout															TEMP_DATA;
input															TEMP_INT_n;
input															TEMP_OVERT_n;

////////////MTLC/////////
input		     [11:0]		CAMERA_D;
input		        		CAMERA_FVAL;
input		        		CAMERA_LVAL;
input		        		CAMERA_PIXCLK;
output		        		CAMERA_RESET_n;
output		        		CAMERA_SCLK;
inout		        		CAMERA_SDATA;
input		        		CAMERA_STROBE;
output		        		CAMERA_TRIGGER;
output		        		CAMERA_XCLKIN;
output		        		GSENSOR_ALT_ADDR;
output		        		GSENSOR_CS_n;
input		        		GSENSOR_INT1;
input		        		GSENSOR_INT2;
output		        		GSENSOR_SCL_SCLK;
inout		        		GSENSOR_SDA_SDI_SDIO;
output		     [7:0]		LCD_B;
output		        		LCD_DCLK;
output		        		LCD_DE;
output		        		LCD_DIM;
output		        		LCD_DITH;
output		     [7:0]		LCD_G;
output		        		LCD_HSD;
output		        		LCD_MODE;
output		        		LCD_POWER_CTL;
output		     [7:0]		LCD_R;
output		        		LCD_RSTB;
output		        		LCD_SHLR;
output		        		LCD_UPDN;
output		        		LCD_VSD;
output		        		LSENSOR_ADDR_SEL;
input		        		LSENSOR_INT;
output		        		LSENSOR_SCL;
inout		        		LSENSOR_SDA;
output		        		TOUCH_I2C_SCL;
inout		        		TOUCH_I2C_SDA;
input		        		TOUCH_INT_n;


//=======================================================
//  REG/WIRE declarations
//=======================================================


wire system_reset;
assign system_reset = 1'b1;

  wire [23:0] LCD_DATA;
  wire clk_100;
  wire clk_mtlc;
  wire video_hs, video_vs;
  wire locked;
 
  //wire clk_touch;
assign LCD_MODE = 1'b0;  //HV sync mode
assign LCD_RSTB = locked &BUTTON[3]; //NO RESET
assign LCD_DIM  = 1'b1;
assign LCD_POWER_CTL = 1'b1;
assign LCD_SHLR  	= 1'b1;
assign LCD_UPDN 	= 1'b0;

pll_clk	pll_clk_inst (
	.areset ( 1'b0 ),
	.inclk0 ( OSC_50_BANK7 ),
	.c0 ( clk_mtlc ),   //33M
	.c1 ( CAMERA_XCLKIN ), //25M
	.locked ( locked )
	);

//=======================================================
//  Structural coding
//=======================================================
assign FAN_CTRL = 1'b1;

    TR4_QSYS u0 (
        .external_clk50_clk                                 (OSC_50_BANK8),                               
        .external_reset_reset_n                             (system_reset),  
		  
        .memory_mem_cs_n                                    (mem_cs_n),      
        .memory_mem_odt                                     (mem_odt), 
        .memory_mem_cas_n                                   (mem_cas_n), 
        .memory_mem_dm                                      (mem_dm),  
        .memory_mem_dqs                                     (mem_dqs), 
        .memory_mem_we_n                                    (mem_we_n),
        .memory_mem_ck                                      (mem_ck),   
        .memory_mem_ras_n                                   (mem_ras_n), 
        .memory_mem_dq                                      (mem_dq), 
        .memory_mem_ck_n                                    (mem_ck_n), 
        .memory_mem_cke                                     (mem_cke), 
        .memory_mem_dqs_n                                   (mem_dqs_n),  
        .memory_mem_reset_n                                 (mem_reset_n), 
        .memory_mem_a                                       (mem_a),    
        .memory_mem_ba                                      (mem_ba),   
        .oct_rup                                            (mem_oct_rup),      
        .oct_rdn                                            (mem_oct_rdn),      
		  
        .uniphy_ddr3_oct_sharing_parallelterminationcontrol (), 
        .uniphy_ddr3_oct_sharing_seriesterminationcontrol   (),   
        .uniphy_ddr3_pll_sharing_pll_addr_cmd_clk           (),  
        .uniphy_ddr3_pll_sharing_pll_config_clk             (),  
        .uniphy_ddr3_pll_sharing_pll_write_clk              (),   
        .uniphy_ddr3_pll_sharing_pll_avl_clk                (),    
        .uniphy_ddr3_pll_sharing_pll_mem_clk                (),     
        .uniphy_ddr3_pll_sharing_pll_locked                 (),     
        .uniphy_ddr3_dll_sharing_dll_delayctrl              (),    
        .uniphy_ddr3_local_powerdown_local_powerdn_ack      (),    
        .uniphy_ddr3_local_powerdown_local_powerdn_req      (),    
        .uniphy_ddr3_status_local_cal_success               (uniphy_ddr3_status_local_cal_success),       
        .uniphy_ddr3_status_local_cal_fail                  (uniphy_ddr3_status_local_cal_fail),     
        .uniphy_ddr3_status_local_init_done                 (uniphy_ddr3_status_local_init_done),
		  
		  //CAMERA
		  .alt_vip_cti_0_clocked_video_vid_v_sync             (rCCD_FVAL), 
        .alt_vip_cti_0_clocked_video_vid_datavalid          (rCCD_LVAL),
        .alt_vip_cti_0_clocked_video_vid_h_sync             (rCCD_LVAL),
        .alt_vip_cti_0_clocked_video_vid_locked             (DLY_RST_3),
        .alt_vip_cti_0_clocked_video_vid_data               ({sCCD_R[11:4],sCCD_G[11:4],sCCD_B[11:4]}),
        .alt_vip_cti_0_clocked_video_vid_f                  (1'b0),
        .alt_vip_cti_0_clocked_video_vid_clk                (CAMERA_PIXCLK),
        .alt_vip_cti_0_clocked_video_overflow               (),
        
		  //MTLC
		  .alt_vip_itc_0_clocked_video_vid_h_sync             (video_hs),
        .alt_vip_itc_0_clocked_video_underflow              (),
        .alt_vip_itc_0_clocked_video_vid_v_sync             (video_vs),
        .alt_vip_itc_0_clocked_video_vid_datavalid          (LCD_DE),
        .alt_vip_itc_0_clocked_video_vid_data               (LCD_DATA),
        .alt_vip_itc_0_clocked_video_vid_h                  (),
        .alt_vip_itc_0_clocked_video_vid_f                  (),
        .alt_vip_itc_0_clocked_video_vid_clk                (clk_mtlc),
        .alt_vip_itc_0_clocked_video_vid_v                  ()	  
    );
	 
wire uniphy_ddr3_status_local_cal_success,uniphy_ddr3_status_local_cal_fail,uniphy_ddr3_status_local_init_done;

assign LED = {1'b1,~uniphy_ddr3_status_local_cal_success,~uniphy_ddr3_status_local_cal_fail,~uniphy_ddr3_status_local_init_done};

assign LCD_HSD = ~video_hs;
assign LCD_VSD = ~video_vs;

assign LCD_R = LCD_DATA[23:16];
assign LCD_G = LCD_DATA[15:8];
assign LCD_B = LCD_DATA[7:0];

assign LCD_DCLK = clk_mtlc;

//////////////////////D5M//////////////////////////////
wire	[11:0]	mCCD_DATA;
wire			mCCD_DVAL;
wire			mCCD_DVAL_d;
wire	[15:0]	X_Cont;
wire	[15:0]	Y_Cont;
wire	[9:0]	X_ADDR;
wire	[31:0]	Frame_Cont;
wire			DLY_RST_0;
wire			DLY_RST_1;
wire			DLY_RST_2;
wire			DLY_RST_3;
wire			DLY_RST_4;

reg		[11:0]	rCCD_DATA;
reg				rCCD_LVAL;
reg				rCCD_FVAL;
wire	[11:0]	sCCD_R;
wire	[11:0]	sCCD_G;
wire	[11:0]	sCCD_B;
wire			sCCD_DVAL;
//power on start
wire             auto_start;

// D5M
assign	CAMERA_TRIGGER	    =	1'b1;  // tRIGGER
assign	CAMERA_RESET_n	    =	DLY_RST_1;
//assign	LEDG		=	Y_Cont;

///////////////////// D5M//////////////////////////////
//auto start when power on
assign auto_start = ((BUTTON[0])&&(DLY_RST_3)&&(!DLY_RST_4))? 1'b1:1'b0;

always@(posedge CAMERA_PIXCLK)
begin
	rCCD_DATA	<= CAMERA_D;
	rCCD_LVAL	<=	CAMERA_LVAL;
	rCCD_FVAL	<=	CAMERA_FVAL;
end
//reset signals
Reset_Delay			u2	(	.iCLK(OSC_50_BANK1),
							.iRST(BUTTON[0]),
							.oRST_0(DLY_RST_0),
							.oRST_1(DLY_RST_1),
							.oRST_2(DLY_RST_2),
							.oRST_3(DLY_RST_3), //auto-start start point
							.oRST_4(DLY_RST_4)  //auto-start end point
						);
//cmos sensor capture
CCD_Capture			u3	(	.oDATA(mCCD_DATA),
							.oDVAL(mCCD_DVAL),
							.oX_Cont(X_Cont),
							.oY_Cont(Y_Cont),
							.oFrame_Cont(Frame_Cont),
							.iDATA(rCCD_DATA),
							.iFVAL(rCCD_FVAL),
							.iLVAL(rCCD_LVAL),
							.iSTART((!BUTTON[3])| auto_start),
							.iEND(!BUTTON[2]),
							.iCLK(~CAMERA_PIXCLK),
							.iRST(DLY_RST_2)
						);
//raw data to RGB conversion
RAW2RGB				u4	(	.iCLK(CAMERA_PIXCLK),
							.iRST_n(DLY_RST_1),
							.iData(mCCD_DATA),
							.iDval(mCCD_DVAL),
							.oRed(sCCD_R),
							.oGreen(sCCD_G),
							.oBlue(sCCD_B),
							.oDval(sCCD_DVAL),
							.iMIRROR(SW[3]),
							.iX_Cont(X_Cont),
							.iY_Cont(Y_Cont)
						);
////frame data display
//SEG7_LUT_8 			u5	(	.oSEG0(HEX0),.oSEG1(HEX1),
//							.oSEG2(HEX2),.oSEG3(HEX3),
//							.oSEG4(HEX4),.oSEG5(HEX5),
//							.oSEG6(HEX6),.oSEG7(HEX7),
//							.iDIG(Frame_Cont[31:0])
//						);
						
//cmos sensor configuration
I2C_CCD_Config 		u8	(	//	Host Side
							.iCLK(OSC_50_BANK1),
							.iRST_N(DLY_RST_2),
							.iEXPOSURE_ADJ(BUTTON[1]),
							.iEXPOSURE_DEC_p(SW[0]),
							.iMIRROR_SW(SW[3]),
							//	I2C Side
							.I2C_SCLK(CAMERA_SCLK),
							.I2C_SDAT(CAMERA_SDATA)
						);


endmodule
