module tx_pattern (

iclk,
rst_n,
tx_data,
tx_ctrl_en,
error_insert,

);

input			iclk;
input			rst_n;
output	[7:0]	tx_data;
output			tx_ctrl_en;
input			error_insert;

//=======================================================
//  PARAMETER declarations
//=======================================================
parameter tx_idle_state			=	5'd0;
parameter tx_preamable_d1_state	=	5'd1;
parameter tx_pattern_d1_state	= 	5'd4;
parameter tx_pattern_d2_state	= 	5'd5;
parameter tx_pattern_d3_state	= 	5'd6;
parameter tx_pattern_d4_state	= 	5'd7;
parameter tx_pattern_d5_state	= 	5'd8;
parameter tx_pattern_d6_state	= 	5'd9;
parameter tx_pattern_d7_state	= 	5'd10;
parameter tx_pattern_d8_state	= 	5'd11;
parameter tx_pattern_d9_state	= 	5'd12;
parameter tx_pattern_d10_state	= 	5'd13;
parameter tx_pattern_d11_state	= 	5'd14;
parameter tx_pattern_d12_state	= 	5'd15;
parameter tx_pattern_d13_state	= 	5'd16;
parameter tx_pattern_d14_state	= 	5'd17;
parameter tx_pattern_d15_state	= 	5'd18;
parameter tx_pattern_d16_state	= 	5'd19;


parameter peamable_d1			=	8'hbc;
//parameter tx_pattern_d1			= 	8'hf1;
parameter tx_pattern_d2			= 	8'he2;
parameter tx_pattern_d3			= 	8'hd3;
parameter tx_pattern_d4			= 	8'hc4;
parameter tx_pattern_d5			= 	8'hb5;
parameter tx_pattern_d6			= 	8'ha6;
parameter tx_pattern_d7			= 	8'h97;
parameter tx_pattern_d8			= 	8'h8a;
parameter tx_pattern_d9			= 	8'h7b;
parameter tx_pattern_d10		= 	8'h6c;
parameter tx_pattern_d11		= 	8'h5d;
parameter tx_pattern_d12		= 	8'h4e;
parameter tx_pattern_d13		= 	8'h3f;
parameter tx_pattern_d14		= 	8'h29;
parameter tx_pattern_d15		= 	8'h18;
parameter tx_pattern_d16		= 	8'h0d;
//=======================================================
//  REG/WIRE declarations
//=======================================================
reg	[4:0]	tx_state;
reg	[9:0]	tx_data;
wire		rst_n;
reg			tx_ctrl_en;

wire [9:0]	tx_pattern_d1;


//=======================================================
//  Structural coding
//=======================================================

assign tx_pattern_d1 = error_insert ? 8'hf1 : 8'h0;

always@(posedge iclk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				tx_state <= 5'h0;
				tx_data <= 8'h0;
				tx_ctrl_en <= 1'b0;
			end	
		else
			begin
				case(tx_state)
				
				tx_idle_state : 
						begin
							tx_state <= tx_preamable_d1_state;
							tx_data <= peamable_d1;
							tx_ctrl_en <= 1'b1;
						end
				tx_preamable_d1_state : 
						begin
							tx_state <= tx_pattern_d1_state;
							tx_data <= tx_pattern_d1;
							tx_ctrl_en <= 1'b0;
						end						
				tx_pattern_d1_state : 
						begin
							tx_state <= tx_pattern_d2_state;
							tx_data <= tx_pattern_d2;
						end		
				tx_pattern_d2_state : 
						begin
							tx_state <= tx_pattern_d3_state;
							tx_data <= tx_pattern_d3;
						end		
				tx_pattern_d3_state : 
						begin
							tx_state <= tx_pattern_d4_state;
							tx_data <= tx_pattern_d4;
						end		
				tx_pattern_d4_state : 
						begin
							tx_state <= tx_pattern_d5_state;
							tx_data <= tx_pattern_d5;
						end		
				tx_pattern_d5_state : 
						begin
							tx_state <= tx_pattern_d6_state;
							tx_data <= tx_pattern_d6;
						end		
				tx_pattern_d6_state : 
						begin
							tx_state <= tx_pattern_d7_state;
							tx_data <= tx_pattern_d7;
						end		
				tx_pattern_d7_state : 
						begin
							tx_state <= tx_pattern_d8_state;
							tx_data <= tx_pattern_d8;
						end		
				tx_pattern_d8_state : 
						begin
							tx_state <= tx_pattern_d9_state;
							tx_data <= tx_pattern_d9;
						end		
				tx_pattern_d9_state : 
						begin
							tx_state <= tx_pattern_d10_state;
							tx_data <= tx_pattern_d10;
						end		
				tx_pattern_d10_state : 
						begin
							tx_state <= tx_pattern_d11_state;
							tx_data <= tx_pattern_d11;
						end	
				tx_pattern_d11_state : 
						begin
							tx_state <= tx_pattern_d12_state;
							tx_data <= tx_pattern_d12;
						end		
				tx_pattern_d12_state : 
						begin
							tx_state <= tx_pattern_d13_state;
							tx_data <= tx_pattern_d13;
						end		
				tx_pattern_d13_state : 
						begin
							tx_state <= tx_pattern_d14_state;
							tx_data <= tx_pattern_d14;
						end		
				tx_pattern_d14_state : 
						begin
							tx_state <= tx_pattern_d15_state;
							tx_data <= tx_pattern_d15;
						end		
				tx_pattern_d15_state : 
						begin
							tx_state <= tx_pattern_d16_state;
							tx_data <= tx_pattern_d16;
						end		
				tx_pattern_d16_state : 
						begin
							tx_state <= tx_preamable_d1_state;
							tx_data <= peamable_d1;
							tx_ctrl_en <= 1'b1;
						end		
				endcase
					
			end
	end


endmodule
