TR4_QSYS | TR4_QSYS 1.0

2012.08.01.19:43:46 | Generation Report

Output Directory | E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/
Files | E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/TR4_QSYS.v (894575 bytes VERILOG) E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.ocp (848 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.sdc (3743 bytes SDC)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.v (424864 bytes VERILOG_ENCRYPT)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_bht_ram.mif (2392 bytes MIF)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_dc_tag_ram.mif (984 bytes MIF)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_ic_tag_ram.mif (2009 bytes MIF)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_sysclk.v (7033 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_tck.v (8319 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_wrapper.v (10163 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_ociram_default_contents.mif (5714 bytes MIF)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_oci_test_bench.v (1468 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_rf_ram_a.mif (600 bytes MIF)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_rf_ram_b.mif (600 bytes MIF)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_test_bench.v (31415 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_sysid.v (1447 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart.v (23819 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_input_mutex.dat (3 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_input_stream.dat (10 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_output_stream.dat (0 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_onchip_mem.hex (688141 bytes HEX)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_onchip_mem.v (3981 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v (10049 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_dc_fifo.v (23570 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v (1458 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_timer.v (6907 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_ddr3_i2c_scl.v (2293 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_ddr3_i2c_sda.v (2811 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3.v (37691 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_pll0.sv (17307 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_clock_pair_generator.v (3520 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_valid_selector.v (2379 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_datapath.v (6482 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset.v (4153 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_pads.v (13511 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_ldc_pads.v (12360 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_ldc_pad.v (4485 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/addr_cmd_non_ldc_pad.v (3149 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_memphy.v (33324 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset_sync.v (1978 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_new_io_pads.v (13342 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_fr_cycle_shifter.v (3943 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_datapath.v (28424 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_write_datapath.v (9197 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_hr_to_fr.v (1348 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_simple_ddio_out.v (9122 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_mux_bridge.sv (18324 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_phy_csr.sv (6103 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_iss_probe.v (1784 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_flop_mem.v (2755 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sv (17257 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_altdqdqs.v (6089 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altdq_dqs2_ddio_3reg_stratixiv.sv (58068 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.ppf (96488 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sdc (29970 bytes SDC)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_timing.tcl (5746 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing.tcl (17669 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing_core.tcl (80849 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_map.tcl (81320 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_assignments.tcl (18670 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_parameters.tcl (3112 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_cpu.sdc (796 bytes SDC)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/afi_mux_ddr3_ddrx.v (10652 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_software/sequencer.c (206778 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_software/sequencer.h (13073 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_make_qsys_seq.tcl (4964 bytes OTHER)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0.v (266782 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v (32228 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v (85632 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v (33763 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv (2805 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv (9460 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10370 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv (8683 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv (16799 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv (19129 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv (16040 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v (3561 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_no_ifdef_params.v (3053 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_reg.v (1456 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_bitcheck.v (3398 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_core.sv (16601 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_datamux.v (1733 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_data_broadcast.v (2357 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_data_decoder.v (2899 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_ddr3.v (7735 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer.v (2855 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer_wrap.v (2076 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_dm_decoder.v (1770 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_generic.sv (7314 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_no_ifdef_params.v (3065 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_reg.v (1480 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_jumplogic.v (3333 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_lfsr12.v (1448 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_lfsr36.v (2107 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_lfsr72.v (1391 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_pattern_fifo.v (2851 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_ram.v (1322 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_ram_csr.v (2522 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_read_datapath.v (3618 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/rw_manager_write_decoder.v (2858 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/sequencer_data_mgr.sv (3828 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/sequencer_phy_mgr.sv (14127 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/sequencer_reg_file.sv (5845 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/sequencer_scc_acv_phase_decode.v (1890 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/sequencer_scc_acv_wrapper.sv (5253 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/sequencer_scc_mgr.sv (24043 bytes SYSTEM_VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_tse_mac_constraints.sdc (31316 bytes SDC)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_altgx_civgx_gige.v (60400 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_altgx_civgx_gige_wo_rmfifo.v (60466 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_altshifttaps.v (1696 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_bin_cnt.v (2448 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_clk_cntl.v (4104 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_fifoless_mac_tx.v (95408 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_fifoless_retransmit_cntl.v (27544 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_geth_pcs_wo_ratematch.v (20424 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_gige_reset_ctrl.v (21928 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_gxb_gige_phyip_inst.v (8683 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_lb_read_cntl.v (2816 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_lb_wrt_cntl.v (3312 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_lfsr_10.v (3224 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_lvds_reset_sequencer.v (4447 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mac_pcs_gige_woff.v (24408 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mac_pcs_pma.v (18042 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mac_pcs_pma_ena.v (20328 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mac_pcs_pma_gige.v (20742 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mac_pcs_pma_gige_phyip.v (19542 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mac_pcs_pma_strx_gx_ena.v (20848 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mdio_clk_gen.v (2576 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mdio_cntl.v (8424 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mii_rx_if_pcs.v (6776 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_mii_tx_if.v (5312 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_multi_channel_arbiter.v (8960 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_multi_mac_pcs.v (141670 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_multi_mac_pcs_pma.v (251314 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_multi_mac_pcs_pma_gige.v (324239 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_multi_mac_pcs_pma_gige_phyip.v (274075 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_pcs_pma.v (12261 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_pcs_pma_gige.v (15243 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_pcs_pma_gige_phyip.v (13468 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_pma_lvds_rx.v (12598 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_pma_lvds_tx.v (8490 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_quad_16x32.v (8032 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_quad_8x32.v (8024 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_register_map.v (82256 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_register_map_small.v (75064 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_reset_ctrl_lego.sv (10161 bytes SYSTEM_VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_reset_synchronizer.v (3349 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_retransmit_cntl.v (25304 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rgmii_in1.v (4277 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rgmii_in4.v (4192 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rgmii_module.v (7700 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rgmii_out1.v (4468 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rgmii_out4.v (4352 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_converter.v (6856 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_counter_cntl.v (20736 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_encapsulation.v (20944 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_encapsulation_strx_gx.v (26144 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_ff.v (21968 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_ff_cntrl.v (19976 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_ff_cntrl_32.v (21560 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_ff_cntrl_32_shift16.v (29992 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_ff_length.v (3112 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_fifo_rd.v (3976 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_min_ff.v (27856 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_stat_extract.v (14984 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_rx_sync.v (11224 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_sdpm_altsyncram.v (2984 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_sdpm_gen.v (1712 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_sgmii_clk_cntl.v (3864 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_sgmii_clk_div.v (2152 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_sgmii_clk_enable.v (2904 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_sgmii_clk_scheduler.v (3688 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_shared_mac_control.v (29840 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_shared_register_map.v (77432 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_timing_adapter32.v (4704 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_timing_adapter8.v (4512 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_timing_adapter_fifo32.v (11360 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_timing_adapter_fifo8.v (11352 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_1000_base_x.ocp (1688 bytes unknown type)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_1000_base_x_strx_gx.ocp (1664 bytes unknown type)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_1geth.v (29688 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_autoneg.v (23888 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_fifoless_1geth.v (30000 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_gen_host.ocp (1672 bytes unknown type)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_multi_mac_pcs.v (235456 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_multi_mac_pcs_gige.v (244528 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_pcs_strx_gx.v (6624 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_sgmii_strx_gx.v (8440 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_tx_converter.v (9880 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_wo_fifo_10_100_1000.v (39592 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_top_w_fifo_10_100_1000.v (45800 bytes VERILOG)
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E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_tx_ff_cntrl.v (9664 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_tx_ff_cntrl_32.v (11448 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_tx_ff_cntrl_32_shift16.v (15872 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_tx_ff_length.v (2320 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_tx_ff_read_cntl.v (9144 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_tx_min_ff.v (27160 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_tx_stat_extract.v (13512 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_tse_xcvr_resync.v (2673 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_sgdma_tx.v (94174 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_sgdma_rx.v (91983 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_descriptor_memory.hex (21517 bytes HEX)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_descriptor_memory.v (4082 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_altpll_0.v (11061 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_led_pio.v (2240 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router.sv (8476 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_001.sv (6046 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_005.sv (6772 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_006.sv (6046 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router.sv (6033 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_002.sv (5964 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_006.sv (6213 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_008.sv (6300 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_008.sv (7689 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_009.sv (5964 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_009.sv (6032 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_016.sv (5977 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv (12799 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux.sv (8554 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_001.sv (3482 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_002.sv (3479 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_005.sv (4752 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_mux.sv (10419 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_mux_006.sv (12007 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_mux_008.sv (12797 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux.sv (4103 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux_006.sv (5375 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux_008.sv (6007 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux.sv (16874 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux_005.sv (12046 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_008.sv (7292 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux_009.sv (3479 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux_008.sv (15270 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_009.sv (3479 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_width_adapter.sv (35858 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v (7493 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_st_clock_crosser.v (4900 bytes VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/TR4_QSYS_irq_mapper.sv (1992 bytes SYSTEM_VERILOG)
E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_irq_clock_crosser.sv (1648 bytes SYSTEM_VERILOG)
Instantiations |

TR4_QSYS TR4_QSYS v1.0 | TR4_QSYS_cpu as cpu TR4_QSYS_sysid as sysid TR4_QSYS_jtag_uart as jtag_uart TR4_QSYS_onchip_mem as onchip_mem altera_avalon_mm_clock_crossing_bridge as clock_crossing_bridge, mm_clock_crossing_bridge_0
TR4_QSYS_timer as timer
TR4_QSYS_ddr3_i2c_scl as ddr3_i2c_scl
TR4_QSYS_ddr3_i2c_sda as ddr3_i2c_sda
TR4_QSYS_uniphy_ddr3 as uniphy_ddr3
TR4_QSYS_button as button
TR4_QSYS_tse_mac as tse_mac
TR4_QSYS_sgdma_tx as sgdma_tx
TR4_QSYS_sgdma_rx as sgdma_rx
TR4_QSYS_descriptor_memory as descriptor_memory
TR4_QSYS_altpll_0 as altpll_0
TR4_QSYS_led_pio as led_pio
altera_merlin_master_translator as cpu_data_master_translator, sgdma_tx_descriptor_read_translator, sgdma_tx_descriptor_write_translator, sgdma_rx_descriptor_read_translator, sgdma_rx_descriptor_write_translator, cpu_instruction_master_translator, sgdma_tx_m_read_translator, sgdma_rx_m_write_translator, clock_crossing_bridge_m0_translator, mm_clock_crossing_bridge_0_m0_translator
altera_merlin_slave_translator as cpu_jtag_debug_module_translator, onchip_mem_s1_translator, clock_crossing_bridge_s0_translator, tse_mac_control_port_translator, sgdma_tx_csr_translator, sgdma_rx_csr_translator, mm_clock_crossing_bridge_0_s0_translator, altpll_0_pll_slave_translator, descriptor_memory_s1_translator, timer_s1_translator, ddr3_i2c_scl_s1_translator, ddr3_i2c_sda_s1_translator, sysid_control_slave_translator, button_s1_translator, jtag_uart_avalon_jtag_slave_translator, led_pio_s1_translator, uniphy_ddr3_avl_translator
altera_merlin_master_agent as sgdma_rx_m_write_translator_avalon_universal_master_0_agent, cpu_instruction_master_translator_avalon_universal_master_0_agent, sgdma_rx_descriptor_write_translator_avalon_universal_master_0_agent, sgdma_tx_m_read_translator_avalon_universal_master_0_agent, sgdma_rx_descriptor_read_translator_avalon_universal_master_0_agent, cpu_data_master_translator_avalon_universal_master_0_agent, sgdma_tx_descriptor_read_translator_avalon_universal_master_0_agent, sgdma_tx_descriptor_write_translator_avalon_universal_master_0_agent, clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent, mm_clock_crossing_bridge_0_m0_translator_avalon_universal_master_0_agent
altera_merlin_slave_agent as clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent, tse_mac_control_port_translator_avalon_universal_slave_0_agent, sgdma_rx_csr_translator_avalon_universal_slave_0_agent, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent, mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent, onchip_mem_s1_translator_avalon_universal_slave_0_agent, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent, descriptor_memory_s1_translator_avalon_universal_slave_0_agent, sgdma_tx_csr_translator_avalon_universal_slave_0_agent, ddr3_i2c_sda_s1_translator_avalon_universal_slave_0_agent, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent, ddr3_i2c_scl_s1_translator_avalon_universal_slave_0_agent, timer_s1_translator_avalon_universal_slave_0_agent, led_pio_s1_translator_avalon_universal_slave_0_agent, sysid_control_slave_translator_avalon_universal_slave_0_agent, button_s1_translator_avalon_universal_slave_0_agent, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent
altera_avalon_sc_fifo as clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo, tse_mac_control_port_translator_avalon_universal_slave_0_agent_rsp_fifo, sgdma_rx_csr_translator_avalon_universal_slave_0_agent_rsp_fifo, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo, mm_clock_crossing_bridge_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo, onchip_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo, descriptor_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, sgdma_tx_csr_translator_avalon_universal_slave_0_agent_rsp_fifo, ddr3_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, ddr3_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, led_pio_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo
TR4_QSYS_addr_router as addr_router
TR4_QSYS_addr_router_001 as addr_router_001, addr_router_002, addr_router_003, addr_router_004
TR4_QSYS_addr_router_005 as addr_router_005
TR4_QSYS_addr_router_006 as addr_router_006, addr_router_007
TR4_QSYS_id_router as id_router, id_router_001
TR4_QSYS_id_router_002 as id_router_002, id_router_003, id_router_004, id_router_005, id_router_007
TR4_QSYS_id_router_006 as id_router_006
TR4_QSYS_id_router_008 as id_router_008
TR4_QSYS_addr_router_008 as addr_router_008
TR4_QSYS_id_router_009 as id_router_009, id_router_010, id_router_011, id_router_012, id_router_013, id_router_014, id_router_015
TR4_QSYS_addr_router_009 as addr_router_009
TR4_QSYS_id_router_016 as id_router_016
altera_merlin_traffic_limiter as limiter, limiter_001, limiter_002, limiter_003, limiter_004, limiter_005
altera_reset_controller as rst_controller, rst_controller_001, rst_controller_002, rst_controller_003, rst_controller_004
TR4_QSYS_cmd_xbar_demux as cmd_xbar_demux
TR4_QSYS_cmd_xbar_demux_001 as cmd_xbar_demux_001, cmd_xbar_demux_003, cmd_xbar_demux_006
TR4_QSYS_cmd_xbar_demux_002 as cmd_xbar_demux_002, cmd_xbar_demux_004, cmd_xbar_demux_007, rsp_xbar_demux_002, rsp_xbar_demux_003, rsp_xbar_demux_004, rsp_xbar_demux_005, rsp_xbar_demux_007
TR4_QSYS_cmd_xbar_demux_005 as cmd_xbar_demux_005
TR4_QSYS_cmd_xbar_mux as cmd_xbar_mux, cmd_xbar_mux_001
TR4_QSYS_cmd_xbar_mux_006 as cmd_xbar_mux_006
TR4_QSYS_cmd_xbar_mux_008 as cmd_xbar_mux_008
TR4_QSYS_rsp_xbar_demux as rsp_xbar_demux, rsp_xbar_demux_001
TR4_QSYS_rsp_xbar_demux_006 as rsp_xbar_demux_006
TR4_QSYS_rsp_xbar_demux_008 as rsp_xbar_demux_008
TR4_QSYS_rsp_xbar_mux as rsp_xbar_mux
TR4_QSYS_rsp_xbar_mux_005 as rsp_xbar_mux_005
TR4_QSYS_cmd_xbar_demux_008 as cmd_xbar_demux_008
TR4_QSYS_rsp_xbar_demux_009 as rsp_xbar_demux_009, rsp_xbar_demux_010, rsp_xbar_demux_011, rsp_xbar_demux_012, rsp_xbar_demux_013, rsp_xbar_demux_014, rsp_xbar_demux_015
TR4_QSYS_rsp_xbar_mux_008 as rsp_xbar_mux_008
TR4_QSYS_cmd_xbar_demux_009 as cmd_xbar_demux_009, rsp_xbar_demux_016
altera_merlin_width_adapter as width_adapter, width_adapter_001
altera_avalon_st_handshake_clock_crosser as crosser, crosser_001, crosser_002, crosser_003
TR4_QSYS_irq_mapper as irq_mapper
altera_irq_clock_crosser as irq_synchronizer, irq_synchronizer_001
TR4_QSYS_cpu altera_nios2_qsys v11.1 |
TR4_QSYS_sysid altera_avalon_sysid_qsys v11.1 |
TR4_QSYS_jtag_uart altera_avalon_jtag_uart v11.1 |
TR4_QSYS_onchip_mem altera_avalon_onchip_memory2 v11.1 |
altera_avalon_mm_clock_crossing_bridge altera_avalon_mm_clock_crossing_bridge v11.1 |
TR4_QSYS_timer altera_avalon_timer v11.1 |
TR4_QSYS_ddr3_i2c_scl altera_avalon_pio v11.1 |
TR4_QSYS_ddr3_i2c_sda altera_avalon_pio v11.1 |
TR4_QSYS_uniphy_ddr3 altera_mem_if_ddr3_emif v11.1 | TR4_QSYS_uniphy_ddr3_pll0 as pll0 TR4_QSYS_uniphy_ddr3_p0 as p0 afi_mux_ddr3_ddrx as m0 TR4_QSYS_uniphy_ddr3_s0 as s0 TR4_QSYS_uniphy_ddr3_c0 as c0
altera_mem_if_oct_stratixiv as oct0
altera_mem_if_dll_stratixiv as dll0
TR4_QSYS_button altera_avalon_pio v11.1 |
TR4_QSYS_tse_mac triple_speed_ethernet v11.1 |
TR4_QSYS_sgdma_tx altera_avalon_sgdma v11.1 |
TR4_QSYS_sgdma_rx altera_avalon_sgdma v11.1 |
TR4_QSYS_descriptor_memory altera_avalon_onchip_memory2 v11.1 |
TR4_QSYS_altpll_0 altpll v11.1 |
TR4_QSYS_led_pio altera_avalon_pio v11.1 |
altera_merlin_master_translator altera_merlin_master_translator v11.1 |
altera_merlin_slave_translator altera_merlin_slave_translator v11.1 |
altera_merlin_master_agent altera_merlin_master_agent v11.1 |
altera_merlin_slave_agent altera_merlin_slave_agent v11.1 |
altera_avalon_sc_fifo altera_avalon_sc_fifo v11.1 |
TR4_QSYS_addr_router altera_merlin_router v11.1 |
TR4_QSYS_addr_router_001 altera_merlin_router v11.1 |
TR4_QSYS_addr_router_005 altera_merlin_router v11.1 |
TR4_QSYS_addr_router_006 altera_merlin_router v11.1 |
TR4_QSYS_id_router altera_merlin_router v11.1 |
TR4_QSYS_id_router_002 altera_merlin_router v11.1 |
TR4_QSYS_id_router_006 altera_merlin_router v11.1 |
TR4_QSYS_id_router_008 altera_merlin_router v11.1 |
TR4_QSYS_addr_router_008 altera_merlin_router v11.1 |
TR4_QSYS_id_router_009 altera_merlin_router v11.1 |
TR4_QSYS_addr_router_009 altera_merlin_router v11.1 |
TR4_QSYS_id_router_016 altera_merlin_router v11.1 |
altera_merlin_traffic_limiter altera_merlin_traffic_limiter v11.1 |
altera_reset_controller altera_reset_controller v11.1 |
TR4_QSYS_cmd_xbar_demux altera_merlin_demultiplexer v11.1 |
TR4_QSYS_cmd_xbar_demux_001 altera_merlin_demultiplexer v11.1 |
TR4_QSYS_cmd_xbar_demux_002 altera_merlin_demultiplexer v11.1 |
TR4_QSYS_cmd_xbar_demux_005 altera_merlin_demultiplexer v11.1 |
TR4_QSYS_cmd_xbar_mux altera_merlin_multiplexer v11.1 |
TR4_QSYS_cmd_xbar_mux_006 altera_merlin_multiplexer v11.1 |
TR4_QSYS_cmd_xbar_mux_008 altera_merlin_multiplexer v11.1 |
TR4_QSYS_rsp_xbar_demux altera_merlin_demultiplexer v11.1 |
TR4_QSYS_rsp_xbar_demux_006 altera_merlin_demultiplexer v11.1 |
TR4_QSYS_rsp_xbar_demux_008 altera_merlin_demultiplexer v11.1 |
TR4_QSYS_rsp_xbar_mux altera_merlin_multiplexer v11.1 |
TR4_QSYS_rsp_xbar_mux_005 altera_merlin_multiplexer v11.1 |
TR4_QSYS_cmd_xbar_demux_008 altera_merlin_demultiplexer v11.1 |
TR4_QSYS_rsp_xbar_demux_009 altera_merlin_demultiplexer v11.1 |
TR4_QSYS_rsp_xbar_mux_008 altera_merlin_multiplexer v11.1 |
TR4_QSYS_cmd_xbar_demux_009 altera_merlin_demultiplexer v11.1 |
altera_merlin_width_adapter altera_merlin_width_adapter v11.1 |
altera_avalon_st_handshake_clock_crosser altera_avalon_st_handshake_clock_crosser v11.1 |
TR4_QSYS_irq_mapper altera_irq_mapper v11.1 |
altera_irq_clock_crosser altera_irq_clock_crosser v11.1 |
TR4_QSYS_uniphy_ddr3_pll0 altera_mem_if_ddr3_pll_dll_oct v11.1 |
TR4_QSYS_uniphy_ddr3_p0 altera_mem_if_ddr3_phy_core v11.1 |
afi_mux_ddr3_ddrx altera_mem_if_ddr3_afi_mux v11.1 |
TR4_QSYS_uniphy_ddr3_s0 altera_mem_if_ddr3_qsys_sequencer v11.1 |
TR4_QSYS_uniphy_ddr3_c0 altera_mem_if_nextgen_ddr3_controller v11.1 | alt_mem_if_nextgen_ddr3_controller_core as ng0 alt_mem_ddrx_mm_st_converter as a0
altera_mem_if_oct_stratixiv altera_mem_if_oct v11.1 |
altera_mem_if_dll_stratixiv altera_mem_if_dll v11.1 |
alt_mem_if_nextgen_ddr3_controller_core altera_mem_if_nextgen_ddr3_controller_core v11.1 |
alt_mem_ddrx_mm_st_converter alt_mem_ddrx_mm_st_converter v11.1 |

Generation Messages
2012.08.01.19:21:28 [Debug] TR4_QSYS.altera_nios2_qsys: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:01 [Warning] TR4_QSYS.cpu: The address range of the slaves connected to the Nios II instruction masters exceeds 28 bits. Attempts to call functions across 28-bit boundaries is not supported by GCC and will result in linker errors. 2012.08.01.19:39:01 [Info] TR4_QSYS.cpu: CPUID control register value is 0. Please manually assign CPUID if creating multiple Nios II system 2012.08.01.19:39:10 [Debug] TR4_QSYS.cpu: Timing: VAL:1/0.046s ELA:1/0.016s 2012.08.01.19:39:06 [Info] TR4_QSYS.sysid: System ID will no longer be automatically assigned. 2012.08.01.19:39:06 [Info] TR4_QSYS.sysid: Time stamp will be automatically updated when this component is generated. 2012.08.01.19:39:10 [Debug] TR4_QSYS.sysid: Timing: VAL:2/0.000s/0.000s 2012.08.01.19:39:10 [Info] TR4_QSYS.onchip_mem: Memory will be initialized from onchip_mem.hex 2012.08.01.19:39:10 [Debug] TR4_QSYS.clock_crossing_bridge: Timing: ELA:1/0.000s 2012.08.01.19:39:10 [Info] TR4_QSYS.ddr3_i2c_sda: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2012.08.01.19:39:08 [Info] TR4_QSYS.uniphy_ddr3: Auto interface leveling mode set to 'Leveling' 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.pll_ref_clk: Timing: ELA:1/0.000s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.global_reset: Timing: ELA:4/0.003s/0.015s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.soft_reset: Timing: ELA:4/0.000s/0.000s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.afi_clk: Timing: ELA:8/0.000s/0.000s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.afi_half_clk: Timing: ELA:8/0.000s/0.000s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.afi_reset: Timing: ELA:4/0.000s/0.000s 2012.08.01.19:21:33 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_pll_dll_oct: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.pll0: Timing: VAL:4/0.234s/0.250s ELA:4/0.000s/0.000s 2012.08.01.19:21:34 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_phy_core: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.p0: Timing: VAL:4/0.226s/0.235s ELA:4/0.011s/0.016s 2012.08.01.19:21:34 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_afi_mux: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.m0: Timing: VAL:4/0.015s/0.016s ELA:4/0.020s/0.032s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.as0: Timing: VAL:4/0.023s/0.031s ELA:4/0.011s/0.016s 2012.08.01.19:21:35 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_qsys_sequencer: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.s0: Timing: VAL:4/0.230s/0.250s ELA:4/0.004s/0.016s 2012.08.01.19:21:38 [Debug] TR4_QSYS.uniphy_ddr3.c0.altera_mem_if_nextgen_ddr3_controller_core: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.c0.ng0: Timing: VAL:4/0.074s/0.078s ELA:4/0.015s/0.032s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_reset: Timing: ELA:4/0.000s/0.000s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_clk: Timing: ELA:1/0.000s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_half_clk: Timing: ELA:1/0.000s 2012.08.01.19:21:38 [Debug] TR4_QSYS.uniphy_ddr3.c0.alt_mem_ddrx_mm_st_converter: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.c0.a0: Timing: VAL:4/0.000s/0.000s ELA:4/0.004s/0.016s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.c0: Timing: VAL:4/0.078s/0.078s COM:4/0.183s/0.188s 2012.08.01.19:21:38 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_oct: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.oct0: Timing: VAL:4/0.000s/0.000s ELA:4/0.003s/0.015s 2012.08.01.19:21:38 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_dll: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3.dll0: Timing: VAL:4/0.000s/0.000s ELA:4/0.008s/0.016s 2012.08.01.19:39:10 [Debug] TR4_QSYS.uniphy_ddr3: Timing: VAL:4/0.355s/0.375s COM:4/1.730s/1.750s 2012.08.01.19:39:10 [Info] TR4_QSYS.button: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2012.08.01.19:39:10 [Info] TR4_QSYS.descriptor_memory: Memory will be initialized from descriptor_memory.hex 2012.08.01.19:39:10 [Debug] TR4_QSYS.mm_clock_crossing_bridge_0: Timing: ELA:1/0.016s 2012.08.01.19:39:10 [Debug] TR4_QSYS.altpll_0: Timing: VAL:1/0.047s ELA:1/0.000s 2012.08.01.19:39:10 [Info] TR4_QSYS: Generating TR4_QSYS "TR4_QSYS" for QUARTUS_SYNTH 2012.08.01.19:39:11 [Debug] TR4_QSYS: queue size: 0 starting:TR4_QSYS "TR4_QSYS" 2012.08.01.19:39:14 [Debug] Transform: PipelineBridgeSwap 2012.08.01.19:39:14 [Info] pipeline_bridge_swap_transform: After transform: 19 modules, 73 connections 2012.08.01.19:39:14 [Debug] Transform: ClockCrossingBridgeSwap 2012.08.01.19:39:14 [Debug] Transform: QsysBetaIPSwap 2012.08.01.19:39:14 [Debug] Transform: CustomInstructionTransform 2012.08.01.19:39:14 [Info] No custom instruction connections, skipping transform 2012.08.01.19:39:14 [Debug] Transform: TristateConduitUpgradeTransform 2012.08.01.19:39:16 [Debug] Transform: TranslatorTransform 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 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2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:16 [Info] merlin_translator_transform: After transform: 46 modules, 154 connections 2012.08.01.19:39:16 [Debug] Transform: DomainTransform 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_tx.descriptor_read and sgdma_tx_descriptor_read_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_tx.descriptor_write and sgdma_tx_descriptor_write_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_rx.descriptor_read and sgdma_rx_descriptor_read_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_rx.descriptor_write and sgdma_rx_descriptor_write_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_tx.m_read and sgdma_tx_m_read_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_rx.m_write and sgdma_rx_m_write_translator.avalon_anti_master_0 2012.08.01.19:39:16 [Progress] min: 0 2012.08.01.19:39:16 [Progress] max: 1 2012.08.01.19:39:16 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 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2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_jtag_debug_module_translator.avalon_anti_slave_0 and cpu.jtag_debug_module 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces onchip_mem_s1_translator.avalon_anti_slave_0 and onchip_mem.s1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_bridge_s0_translator.avalon_anti_slave_0 and clock_crossing_bridge.s0 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces tse_mac_control_port_translator.avalon_anti_slave_0 and tse_mac.control_port 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_tx_csr_translator.avalon_anti_slave_0 and sgdma_tx.csr 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces sgdma_rx_csr_translator.avalon_anti_slave_0 and sgdma_rx.csr 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces mm_clock_crossing_bridge_0_s0_translator.avalon_anti_slave_0 and mm_clock_crossing_bridge_0.s0 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces altpll_0_pll_slave_translator.avalon_anti_slave_0 and altpll_0.pll_slave 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces descriptor_memory_s1_translator.avalon_anti_slave_0 and descriptor_memory.s1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_bridge.m0 and clock_crossing_bridge_m0_translator.avalon_anti_master_0 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces timer_s1_translator.avalon_anti_slave_0 and timer.s1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces ddr3_i2c_scl_s1_translator.avalon_anti_slave_0 and ddr3_i2c_scl.s1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces ddr3_i2c_sda_s1_translator.avalon_anti_slave_0 and ddr3_i2c_sda.s1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces button_s1_translator.avalon_anti_slave_0 and button.s1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces led_pio_s1_translator.avalon_anti_slave_0 and led_pio.s1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces mm_clock_crossing_bridge_0.m0 and mm_clock_crossing_bridge_0_m0_translator.avalon_anti_master_0 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Debug] Transform merlin_domain_transform not run on matched interfaces uniphy_ddr3_avl_translator.avalon_anti_slave_0 and uniphy_ddr3.avl 2012.08.01.19:39:17 [Info] merlin_domain_transform: After transform: 95 modules, 408 connections 2012.08.01.19:39:17 [Debug] Transform: RouterTransform 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:17 [Progress] min: 0 2012.08.01.19:39:17 [Progress] max: 1 2012.08.01.19:39:17 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] merlin_router_transform: After transform: 122 modules, 489 connections 2012.08.01.19:39:18 [Debug] Transform: TrafficLimiterTransform 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] merlin_traffic_limiter_transform: After transform: 128 modules, 513 connections 2012.08.01.19:39:18 [Debug] Transform: BurstTransform 2012.08.01.19:39:18 [Debug] Transform: ResetAdaptation 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] reset_adaptation_transform: After transform: 133 modules, 523 connections 2012.08.01.19:39:18 [Debug] Transform: NetworkToSwitchTransform 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] merlin_network_to_switch_transform: After transform: 184 modules, 629 connections 2012.08.01.19:39:18 [Debug] Transform: WidthTransform 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] merlin_width_transform: After transform: 186 modules, 635 connections 2012.08.01.19:39:18 [Debug] Transform: RouterTableTransform 2012.08.01.19:39:18 [Debug] Transform: ClockCrossingTransform 2012.08.01.19:39:18 [Info] Inserting clock-crossing logic between cmd_xbar_demux.src7 and cmd_xbar_mux_007.sink0 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] Inserting clock-crossing logic between rsp_xbar_demux_007.src0 and rsp_xbar_mux.sink7 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] Inserting clock-crossing logic between cmd_xbar_demux_009.src0 and cmd_xbar_mux_016.sink0 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:18 [Info] Inserting clock-crossing logic between rsp_xbar_demux_016.src0 and rsp_xbar_mux_009.sink0 2012.08.01.19:39:18 [Progress] min: 0 2012.08.01.19:39:18 [Progress] max: 1 2012.08.01.19:39:18 [Progress] current: 1 2012.08.01.19:39:19 [Info] com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform: After transform: 190 modules, 655 connections 2012.08.01.19:39:19 [Debug] Transform: PipelineTransform 2012.08.01.19:39:19 [Debug] Transform: TrafficLimiterUpdateTransform 2012.08.01.19:39:19 [Info] limiter_update_transform: After transform: 190 modules, 661 connections 2012.08.01.19:39:19 [Debug] Transform: InterruptMapperTransform 2012.08.01.19:39:19 [Progress] min: 0 2012.08.01.19:39:19 [Progress] max: 1 2012.08.01.19:39:19 [Progress] current: 1 2012.08.01.19:39:19 [Info] merlin_interrupt_mapper_transform: After transform: 191 modules, 664 connections 2012.08.01.19:39:19 [Debug] Transform: InterruptSyncTransform 2012.08.01.19:39:19 [Progress] min: 0 2012.08.01.19:39:19 [Progress] max: 1 2012.08.01.19:39:19 [Progress] current: 1 2012.08.01.19:39:19 [Progress] min: 0 2012.08.01.19:39:19 [Progress] max: 1 2012.08.01.19:39:19 [Progress] current: 1 2012.08.01.19:39:19 [Info] merlin_interrupt_sync_transform: After transform: 193 modules, 674 connections 2012.08.01.19:39:19 [Debug] Transform: InterruptFanoutTransform 2012.08.01.19:39:22 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:dataavailable (dataavailable)" 2012.08.01.19:39:22 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:readyfordata (readyfordata)" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_nios2_qsys "submodules/TR4_QSYS_cpu" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sysid_qsys "submodules/TR4_QSYS_sysid" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_jtag_uart "submodules/TR4_QSYS_jtag_uart" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_onchip_memory2 "submodules/TR4_QSYS_onchip_mem" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_timer "submodules/TR4_QSYS_timer" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_scl" 2012.08.01.19:39:22 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_sda" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_button" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses triple_speed_ethernet "submodules/TR4_QSYS_tse_mac" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sgdma "submodules/TR4_QSYS_sgdma_tx" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sgdma "submodules/TR4_QSYS_sgdma_rx" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_onchip_memory2 "submodules/TR4_QSYS_descriptor_memory" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altpll "submodules/TR4_QSYS_altpll_0" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_led_pio" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_001" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_001" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_001" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_001" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_005" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_006" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_006" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_006" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_008" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_008" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_016" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_001" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_001" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_005" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_001" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux_006" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux_008" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_006" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_008" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_005" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_008" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_008" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_009" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_irq_mapper "submodules/TR4_QSYS_irq_mapper" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2012.08.01.19:39:23 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2012.08.01.19:39:24 [Debug] TR4_QSYS: queue size: 170 starting:altera_nios2_qsys "submodules/TR4_QSYS_cpu" 2012.08.01.19:39:24 [Info] cpu: Starting RTL generation for module 'TR4_QSYS_cpu' 2012.08.01.19:39:24 [Info] cpu: Generation command is [exec C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/11.1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/11.1/quartus/sopc_builder/bin/europa -I C:/altera/11.1/quartus/sopc_builder/bin/perl_lib -I C:/altera/11.1/quartus/sopc_builder/bin -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=TR4_QSYS_cpu --dir=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0001_cpu_gen/ --quartus_dir=C:/altera/11.1/quartus --verilog --config=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0001_cpu_gen//TR4_QSYS_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:25 (*) Starting Nios II generation 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:25 (*) Checking for encrypted license (non-evaluation). 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:38 (*) Encrypted license found. SOF will not be time-limited. 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:38 (*) Elaborating CPU configuration settings 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:38 (*) Creating all objects for CPU 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:38 (*) Testbench 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:39 (*) Instruction decoding 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:39 (*) Instruction fields 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:39 (*) Instruction decodes 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:40 (*) Signals for RTL simulation waveforms 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:40 (*) Instruction controls 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:40 (*) Pipeline frontend 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:40 (*) Pipeline backend 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:44 (*) Generating RTL from CPU objects 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:47 (*) Creating encrypted RTL 2012.08.01.19:39:49 [Info] cpu: # 2012.08.01 19:39:49 (*) Done Nios II generation 2012.08.01.19:39:49 [Info] cpu: Done RTL generation for module 'TR4_QSYS_cpu' 2012.08.01.19:39:49 [Info] cpu: "TR4_QSYS" instantiated altera_nios2_qsys "cpu" 2012.08.01.19:39:49 [Debug] TR4_QSYS: queue size: 169 starting:altera_avalon_sysid_qsys "submodules/TR4_QSYS_sysid" 2012.08.01.19:39:49 [Info] sysid: "TR4_QSYS" instantiated altera_avalon_sysid_qsys "sysid" 2012.08.01.19:39:49 [Debug] TR4_QSYS: queue size: 168 starting:altera_avalon_jtag_uart "submodules/TR4_QSYS_jtag_uart" 2012.08.01.19:39:49 [Info] Starting classic module elaboration. 2012.08.01.19:39:52 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0003_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:39:55 [Info] Finished elaborating classic module. 2012.08.01.19:39:55 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0003_sopclgen/yysystem.ptf 2012.08.01.19:39:55 [Info] Running sopc_builder... 2012.08.01.19:39:57 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0003_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:39:59 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:39:59 [Progress] . 2012.08.01.19:40:01 [Progress] # 2012.08.01 19:40:01 (*) Success: sopc_builder finished. 2012.08.01.19:40:01 [Info] jtag_uart: "TR4_QSYS" instantiated altera_avalon_jtag_uart "jtag_uart" 2012.08.01.19:40:01 [Debug] TR4_QSYS: queue size: 167 starting:altera_avalon_onchip_memory2 "submodules/TR4_QSYS_onchip_mem" 2012.08.01.19:40:01 [Info] Starting classic module elaboration. 2012.08.01.19:40:03 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0004_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:05 [Info] Finished elaborating classic module. 2012.08.01.19:40:05 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0004_sopclgen/yysystem.ptf 2012.08.01.19:40:05 [Info] Running sopc_builder... 2012.08.01.19:40:07 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0004_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:09 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:40:09 [Progress] . 2012.08.01.19:40:12 [Progress] # 2012.08.01 19:40:12 (*) Success: sopc_builder finished. 2012.08.01.19:40:12 [Info] onchip_mem: "TR4_QSYS" instantiated altera_avalon_onchip_memory2 "onchip_mem" 2012.08.01.19:40:12 [Debug] TR4_QSYS: queue size: 166 starting:altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" 2012.08.01.19:40:12 [Info] clock_crossing_bridge: "TR4_QSYS" instantiated altera_avalon_mm_clock_crossing_bridge "clock_crossing_bridge" 2012.08.01.19:40:12 [Debug] TR4_QSYS: queue size: 165 starting:altera_avalon_timer "submodules/TR4_QSYS_timer" 2012.08.01.19:40:12 [Info] Starting classic module elaboration. 2012.08.01.19:40:14 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0005_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:16 [Info] Finished elaborating classic module. 2012.08.01.19:40:16 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0005_sopclgen/yysystem.ptf 2012.08.01.19:40:16 [Info] Running sopc_builder... 2012.08.01.19:40:18 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0005_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:19 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:40:19 [Progress] . 2012.08.01.19:40:21 [Progress] # 2012.08.01 19:40:21 (*) Success: sopc_builder finished. 2012.08.01.19:40:21 [Info] timer: "TR4_QSYS" instantiated altera_avalon_timer "timer" 2012.08.01.19:40:21 [Debug] TR4_QSYS: queue size: 164 starting:altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_scl" 2012.08.01.19:40:21 [Info] Starting classic module elaboration. 2012.08.01.19:40:23 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0006_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:25 [Info] Finished elaborating classic module. 2012.08.01.19:40:25 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0006_sopclgen/yysystem.ptf 2012.08.01.19:40:25 [Info] Running sopc_builder... 2012.08.01.19:40:27 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0006_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:29 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:40:29 [Progress] . 2012.08.01.19:40:30 [Progress] # 2012.08.01 19:40:30 (*) Success: sopc_builder finished. 2012.08.01.19:40:30 [Info] ddr3_i2c_scl: "TR4_QSYS" instantiated altera_avalon_pio "ddr3_i2c_scl" 2012.08.01.19:40:30 [Debug] TR4_QSYS: queue size: 163 starting:altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_sda" 2012.08.01.19:40:30 [Info] Starting classic module elaboration. 2012.08.01.19:40:32 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0007_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:34 [Info] Finished elaborating classic module. 2012.08.01.19:40:34 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0007_sopclgen/yysystem.ptf 2012.08.01.19:40:34 [Info] Running sopc_builder... 2012.08.01.19:40:36 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0007_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:38 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:40:38 [Progress] . 2012.08.01.19:40:39 [Progress] # 2012.08.01 19:40:39 (*) Success: sopc_builder finished. 2012.08.01.19:40:40 [Info] ddr3_i2c_sda: "TR4_QSYS" instantiated altera_avalon_pio "ddr3_i2c_sda" 2012.08.01.19:40:40 [Debug] TR4_QSYS: queue size: 162 starting:altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2012.08.01.19:40:40 [Info] uniphy_ddr3: Running transform AvalonTransform 2012.08.01.19:40:41 [Debug] Transform: PipelineBridgeSwap 2012.08.01.19:40:41 [Info] pipeline_bridge_swap_transform: After transform: 14 modules, 33 connections 2012.08.01.19:40:41 [Debug] Transform: ClockCrossingBridgeSwap 2012.08.01.19:40:41 [Debug] Transform: QsysBetaIPSwap 2012.08.01.19:40:41 [Debug] Transform: CustomInstructionTransform 2012.08.01.19:40:41 [Info] No custom instruction connections, skipping transform 2012.08.01.19:40:41 [Debug] Transform: TristateConduitUpgradeTransform 2012.08.01.19:40:42 [Debug] Transform: TranslatorTransform 2012.08.01.19:40:42 [Info] No Avalon connections, skipping transform 2012.08.01.19:40:42 [Debug] Transform: DomainTransform 2012.08.01.19:40:42 [Debug] Transform: RouterTransform 2012.08.01.19:40:42 [Debug] Transform: TrafficLimiterTransform 2012.08.01.19:40:42 [Debug] Transform: BurstTransform 2012.08.01.19:40:42 [Debug] Transform: ResetAdaptation 2012.08.01.19:40:42 [Debug] Transform: NetworkToSwitchTransform 2012.08.01.19:40:42 [Debug] Transform: WidthTransform 2012.08.01.19:40:42 [Debug] Transform: RouterTableTransform 2012.08.01.19:40:42 [Debug] Transform: ClockCrossingTransform 2012.08.01.19:40:42 [Debug] Transform: TrafficLimiterUpdateTransform 2012.08.01.19:40:42 [Debug] Transform: InterruptMapperTransform 2012.08.01.19:40:42 [Debug] Transform: InterruptSyncTransform 2012.08.01.19:40:42 [Debug] Transform: InterruptFanoutTransform 2012.08.01.19:40:42 [Info] uniphy_ddr3: Running transform AvalonTransform took 2.250s 2012.08.01.19:40:42 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_pll_dll_oct "submodules/TR4_QSYS_uniphy_ddr3_pll0" 2012.08.01.19:40:42 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_phy_core "submodules/TR4_QSYS_uniphy_ddr3_p0" 2012.08.01.19:40:42 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx" 2012.08.01.19:40:42 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_qsys_sequencer "submodules/TR4_QSYS_uniphy_ddr3_s0" 2012.08.01.19:40:42 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2012.08.01.19:40:42 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_oct "submodules/altera_mem_if_oct_stratixiv" 2012.08.01.19:40:42 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_dll "submodules/altera_mem_if_dll_stratixiv" 2012.08.01.19:40:42 [Info] uniphy_ddr3: "TR4_QSYS" instantiated altera_mem_if_ddr3_emif "uniphy_ddr3" 2012.08.01.19:40:42 [Debug] TR4_QSYS: queue size: 168 starting:altera_avalon_pio "submodules/TR4_QSYS_button" 2012.08.01.19:40:42 [Info] Starting classic module elaboration. 2012.08.01.19:40:44 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0008_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:46 [Info] Finished elaborating classic module. 2012.08.01.19:40:46 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0008_sopclgen/yysystem.ptf 2012.08.01.19:40:46 [Info] Running sopc_builder... 2012.08.01.19:40:48 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0008_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:40:50 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:40:50 [Progress] . 2012.08.01.19:40:51 [Progress] # 2012.08.01 19:40:51 (*) Success: sopc_builder finished. 2012.08.01.19:40:52 [Info] button: "TR4_QSYS" instantiated altera_avalon_pio "button" 2012.08.01.19:40:52 [Debug] TR4_QSYS: queue size: 167 starting:triple_speed_ethernet "submodules/TR4_QSYS_tse_mac" 2012.08.01.19:40:52 [Info] tse_mac: HDL generated 2012.08.01.19:40:53 [Info] tse_mac: Variation name : TR4_QSYS_tse_mac 2012.08.01.19:40:53 [Info] tse_mac: Variation language : Verilog HDL 2012.08.01.19:40:53 [Info] tse_mac: Output directory : C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\alt5553_3407040960643954065.dir\0009_iptb_gen 2012.08.01.19:40:53 [Info] tse_mac: Generating HDL... 2012.08.01.19:40:53 [Info] tse_mac: Generating MegaCore function top-level... 2012.08.01.19:40:54 [Info] tse_mac: Generating QIP file ... 2012.08.01.19:40:56 [Info] tse_mac: Updating user's project directory... 2012.08.01.19:40:52 [Info] tse_mac: HDL generated 2012.08.01.19:40:56 [Info] tse_mac: Generation successful. 2012.08.01.19:40:57 [Info] tse_mac: "TR4_QSYS" instantiated triple_speed_ethernet "tse_mac" 2012.08.01.19:40:57 [Debug] TR4_QSYS: queue size: 166 starting:altera_avalon_sgdma "submodules/TR4_QSYS_sgdma_tx" 2012.08.01.19:40:57 [Info] Starting classic module elaboration. 2012.08.01.19:40:59 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0010_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:01 [Info] Finished elaborating classic module. 2012.08.01.19:41:01 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0010_sopclgen/yysystem.ptf 2012.08.01.19:41:01 [Info] Running sopc_builder... 2012.08.01.19:41:03 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0010_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:05 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:41:05 [Progress] . 2012.08.01.19:41:09 [Progress] # 2012.08.01 19:41:09 (*) Success: sopc_builder finished. 2012.08.01.19:41:10 [Info] sgdma_tx: "TR4_QSYS" instantiated altera_avalon_sgdma "sgdma_tx" 2012.08.01.19:41:10 [Debug] TR4_QSYS: queue size: 165 starting:altera_avalon_sgdma "submodules/TR4_QSYS_sgdma_rx" 2012.08.01.19:41:10 [Info] Starting classic module elaboration. 2012.08.01.19:41:12 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0011_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:14 [Info] Finished elaborating classic module. 2012.08.01.19:41:14 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0011_sopclgen/yysystem.ptf 2012.08.01.19:41:14 [Info] Running sopc_builder... 2012.08.01.19:41:15 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0011_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:18 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:41:18 [Progress] . 2012.08.01.19:41:21 [Progress] # 2012.08.01 19:41:21 (*) Success: sopc_builder finished. 2012.08.01.19:41:22 [Info] sgdma_rx: "TR4_QSYS" instantiated altera_avalon_sgdma "sgdma_rx" 2012.08.01.19:41:22 [Debug] TR4_QSYS: queue size: 164 starting:altera_avalon_onchip_memory2 "submodules/TR4_QSYS_descriptor_memory" 2012.08.01.19:41:22 [Info] Starting classic module elaboration. 2012.08.01.19:41:24 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0012_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0012_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:26 [Info] Finished elaborating classic module. 2012.08.01.19:41:26 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0012_sopclgen/yysystem.ptf 2012.08.01.19:41:26 [Info] Running sopc_builder... 2012.08.01.19:41:27 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0012_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0012_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:29 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:41:29 [Progress] . 2012.08.01.19:41:31 [Progress] # 2012.08.01 19:41:31 (*) Success: sopc_builder finished. 2012.08.01.19:41:31 [Info] descriptor_memory: "TR4_QSYS" instantiated altera_avalon_onchip_memory2 "descriptor_memory" 2012.08.01.19:41:31 [Debug] TR4_QSYS: queue size: 162 starting:altpll "submodules/TR4_QSYS_altpll_0" 2012.08.01.19:41:32 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2012.08.01.19:41:32 [Debug] Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0013_sopcgen/TR4_QSYS_altpll_0.v --source=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0013_sopcgen/TR4_QSYS_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0014_sopcqmap/ 2012.08.01.19:41:45 [Debug] Command took 13.125s 2012.08.01.19:41:45 [Info] altpll_0: "TR4_QSYS" instantiated altpll "altpll_0" 2012.08.01.19:41:45 [Debug] TR4_QSYS: queue size: 161 starting:altera_avalon_pio "submodules/TR4_QSYS_led_pio" 2012.08.01.19:41:45 [Info] Starting classic module elaboration. 2012.08.01.19:41:47 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0015_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0015_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:49 [Info] Finished elaborating classic module. 2012.08.01.19:41:49 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0015_sopclgen/yysystem.ptf 2012.08.01.19:41:49 [Info] Running sopc_builder... 2012.08.01.19:41:51 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0015_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5553_3407040960643954065.dir/0015_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.08.01.19:41:53 [Progress] No .sopc_builder configuration file(!) 2012.08.01.19:41:53 [Progress] . 2012.08.01.19:41:54 [Progress] # 2012.08.01 19:41:54 (*) Success: sopc_builder finished. 2012.08.01.19:41:55 [Info] led_pio: "TR4_QSYS" instantiated altera_avalon_pio "led_pio" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 160 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.08.01.19:41:55 [Info] cpu_data_master_translator: "TR4_QSYS" instantiated altera_merlin_master_translator "cpu_data_master_translator" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 152 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.08.01.19:41:55 [Info] cpu_jtag_debug_module_translator: "TR4_QSYS" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 133 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.08.01.19:41:55 [Info] sgdma_rx_m_write_translator_avalon_universal_master_0_agent: "TR4_QSYS" instantiated altera_merlin_master_agent "sgdma_rx_m_write_translator_avalon_universal_master_0_agent" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 132 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.08.01.19:41:55 [Info] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent: "TR4_QSYS" instantiated altera_merlin_slave_agent "clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 131 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.08.01.19:41:55 [Info] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo: "TR4_QSYS" instantiated altera_avalon_sc_fifo "clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 87 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router" 2012.08.01.19:41:55 [Info] addr_router: "TR4_QSYS" instantiated altera_merlin_router "addr_router" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 86 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_001" 2012.08.01.19:41:55 [Info] addr_router_001: "TR4_QSYS" instantiated altera_merlin_router "addr_router_001" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 82 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_005" 2012.08.01.19:41:55 [Info] addr_router_005: "TR4_QSYS" instantiated altera_merlin_router "addr_router_005" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 81 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_006" 2012.08.01.19:41:55 [Info] addr_router_006: "TR4_QSYS" instantiated altera_merlin_router "addr_router_006" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 79 starting:altera_merlin_router "submodules/TR4_QSYS_id_router" 2012.08.01.19:41:55 [Info] id_router: "TR4_QSYS" instantiated altera_merlin_router "id_router" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 77 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.08.01.19:41:55 [Info] id_router_002: "TR4_QSYS" instantiated altera_merlin_router "id_router_002" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 73 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_006" 2012.08.01.19:41:55 [Info] id_router_006: "TR4_QSYS" instantiated altera_merlin_router "id_router_006" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 71 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_008" 2012.08.01.19:41:55 [Info] id_router_008: "TR4_QSYS" instantiated altera_merlin_router "id_router_008" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 70 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_008" 2012.08.01.19:41:55 [Info] addr_router_008: "TR4_QSYS" instantiated altera_merlin_router "addr_router_008" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 69 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_009" 2012.08.01.19:41:55 [Info] id_router_009: "TR4_QSYS" instantiated altera_merlin_router "id_router_009" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 62 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_009" 2012.08.01.19:41:55 [Info] addr_router_009: "TR4_QSYS" instantiated altera_merlin_router "addr_router_009" 2012.08.01.19:41:55 [Debug] TR4_QSYS: queue size: 61 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_016" 2012.08.01.19:41:56 [Info] id_router_016: "TR4_QSYS" instantiated altera_merlin_router "id_router_016" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 60 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.08.01.19:41:56 [Info] limiter: "TR4_QSYS" instantiated altera_merlin_traffic_limiter "limiter" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 54 starting:altera_reset_controller "submodules/altera_reset_controller" 2012.08.01.19:41:56 [Info] rst_controller: "TR4_QSYS" instantiated altera_reset_controller "rst_controller" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 49 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2012.08.01.19:41:56 [Info] cmd_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 48 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_001" 2012.08.01.19:41:56 [Info] cmd_xbar_demux_001: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 47 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.08.01.19:41:56 [Info] cmd_xbar_demux_002: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_002" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 44 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_005" 2012.08.01.19:41:56 [Info] cmd_xbar_demux_005: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_005" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 41 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2012.08.01.19:41:56 [Info] cmd_xbar_mux: "TR4_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 39 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux_006" 2012.08.01.19:41:56 [Info] cmd_xbar_mux_006: "TR4_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux_006" 2012.08.01.19:41:56 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 38 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux_008" 2012.08.01.19:41:56 [Info] cmd_xbar_mux_008: "TR4_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux_008" 2012.08.01.19:41:56 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 37 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2012.08.01.19:41:56 [Info] rsp_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 31 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_006" 2012.08.01.19:41:56 [Info] rsp_xbar_demux_006: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_006" 2012.08.01.19:41:56 [Debug] TR4_QSYS: queue size: 29 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_008" 2012.08.01.19:41:57 [Info] rsp_xbar_demux_008: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_008" 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 28 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux" 2012.08.01.19:41:57 [Info] rsp_xbar_mux: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux" 2012.08.01.19:41:57 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 27 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_005" 2012.08.01.19:41:57 [Info] rsp_xbar_mux_005: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_005" 2012.08.01.19:41:57 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 26 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_008" 2012.08.01.19:41:57 [Info] cmd_xbar_demux_008: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_008" 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 25 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_009" 2012.08.01.19:41:57 [Info] rsp_xbar_demux_009: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_009" 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 18 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_008" 2012.08.01.19:41:57 [Info] rsp_xbar_mux_008: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_008" 2012.08.01.19:41:57 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 17 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_009" 2012.08.01.19:41:57 [Info] cmd_xbar_demux_009: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_009" 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 15 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.08.01.19:41:57 [Info] width_adapter: "TR4_QSYS" instantiated altera_merlin_width_adapter "width_adapter" 2012.08.01.19:41:57 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 13 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.08.01.19:41:57 [Info] crosser: "TR4_QSYS" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2012.08.01.19:41:57 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 9 starting:altera_irq_mapper "submodules/TR4_QSYS_irq_mapper" 2012.08.01.19:41:57 [Info] irq_mapper: "TR4_QSYS" instantiated altera_irq_mapper "irq_mapper" 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 8 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2012.08.01.19:41:57 [Info] irq_synchronizer: "TR4_QSYS" instantiated altera_irq_clock_crosser "irq_synchronizer" 2012.08.01.19:41:57 [Debug] TR4_QSYS: queue size: 6 starting:altera_mem_if_ddr3_pll_dll_oct "submodules/TR4_QSYS_uniphy_ddr3_pll0" 2012.08.01.19:41:58 [Info] pll0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_pll_dll_oct "pll0" 2012.08.01.19:41:58 [Debug] TR4_QSYS: queue size: 5 starting:altera_mem_if_ddr3_phy_core "submodules/TR4_QSYS_uniphy_ddr3_p0" 2012.08.01.19:41:58 [Info] p0: Generating clock pair generator 2012.08.01.19:42:05 [Info] p0: Generating TR4_QSYS_uniphy_ddr3_p0_altdqdqs 2012.08.01.19:42:24 [Info] p0: 2012.08.01.19:42:24 [Info] p0: ***************************** 2012.08.01.19:42:24 [Info] p0: 2012.08.01.19:42:24 [Info] p0: Remember to run the TR4_QSYS_uniphy_ddr3_p0_pin_assignments.tcl 2012.08.01.19:42:24 [Info] p0: script after running Synthesis and before Fitting. 2012.08.01.19:42:24 [Info] p0: 2012.08.01.19:42:24 [Info] p0: ***************************** 2012.08.01.19:42:24 [Info] p0: 2012.08.01.19:42:24 [Info] p0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_phy_core "p0" 2012.08.01.19:42:24 [Debug] TR4_QSYS: queue size: 4 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx" 2012.08.01.19:42:24 [Info] m0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_afi_mux "m0" 2012.08.01.19:42:24 [Debug] TR4_QSYS: queue size: 3 starting:altera_mem_if_ddr3_qsys_sequencer "submodules/TR4_QSYS_uniphy_ddr3_s0" 2012.08.01.19:42:25 [Info] s0: Determining sequencer memory size 2012.08.01.19:42:58 [Info] s0: Generating Qsys sequencer system 2012.08.01.19:43:16 [Info] s0: QSYS sequencer system generated successfully 2012.08.01.19:43:17 [Info] s0: Building sequencer software 2012.08.01.19:43:43 [Info] s0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_qsys_sequencer "s0" 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_reset_controller.v 2012.08.01.19:43:43 [Info] Reusing file E:/Product/TR4_V.1.0.0_SystemCD/TR4_Install/Demonstrations/NET/NET/TR4_NET/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v 2012.08.01.19:43:43 [Debug] TR4_QSYS: queue size: 2 starting:altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2012.08.01.19:43:43 [Info] c0: Running transform AvalonTransform 2012.08.01.19:43:43 [Debug] Transform: PipelineBridgeSwap 2012.08.01.19:43:43 [Info] pipeline_bridge_swap_transform: After transform: 5 modules, 8 connections 2012.08.01.19:43:43 [Debug] Transform: ClockCrossingBridgeSwap 2012.08.01.19:43:43 [Debug] Transform: QsysBetaIPSwap 2012.08.01.19:43:43 [Debug] Transform: CustomInstructionTransform 2012.08.01.19:43:43 [Info] No custom instruction connections, skipping transform 2012.08.01.19:43:43 [Debug] Transform: TristateConduitUpgradeTransform 2012.08.01.19:43:43 [Debug] Transform: TranslatorTransform 2012.08.01.19:43:43 [Info] No Avalon connections, skipping transform 2012.08.01.19:43:43 [Debug] Transform: DomainTransform 2012.08.01.19:43:43 [Debug] Transform: RouterTransform 2012.08.01.19:43:43 [Debug] Transform: TrafficLimiterTransform 2012.08.01.19:43:43 [Debug] Transform: BurstTransform 2012.08.01.19:43:43 [Debug] Transform: ResetAdaptation 2012.08.01.19:43:43 [Debug] Transform: NetworkToSwitchTransform 2012.08.01.19:43:43 [Debug] Transform: WidthTransform 2012.08.01.19:43:43 [Debug] Transform: RouterTableTransform 2012.08.01.19:43:43 [Debug] Transform: ClockCrossingTransform 2012.08.01.19:43:43 [Debug] Transform: TrafficLimiterUpdateTransform 2012.08.01.19:43:43 [Debug] Transform: InterruptMapperTransform 2012.08.01.19:43:43 [Debug] Transform: InterruptSyncTransform 2012.08.01.19:43:43 [Debug] Transform: InterruptFanoutTransform 2012.08.01.19:43:43 [Info] c0: Running transform AvalonTransform took 0.250s 2012.08.01.19:43:43 [Debug] c0: "c0" reuses altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2012.08.01.19:43:43 [Debug] c0: "c0" reuses alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2012.08.01.19:43:43 [Info] c0: "uniphy_ddr3" instantiated altera_mem_if_nextgen_ddr3_controller "c0" 2012.08.01.19:43:43 [Debug] TR4_QSYS: queue size: 3 starting:altera_mem_if_oct "submodules/altera_mem_if_oct_stratixiv" 2012.08.01.19:43:43 [Info] oct0: "uniphy_ddr3" instantiated altera_mem_if_oct "oct0" 2012.08.01.19:43:43 [Debug] TR4_QSYS: queue size: 2 starting:altera_mem_if_dll "submodules/altera_mem_if_dll_stratixiv" 2012.08.01.19:43:43 [Info] dll0: "uniphy_ddr3" instantiated altera_mem_if_dll "dll0" 2012.08.01.19:43:43 [Debug] TR4_QSYS: queue size: 1 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2012.08.01.19:43:44 [Info] ng0: "c0" instantiated altera_mem_if_nextgen_ddr3_controller_core "ng0" 2012.08.01.19:43:44 [Debug] TR4_QSYS: queue size: 0 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2012.08.01.19:43:44 [Info] a0: "c0" instantiated alt_mem_ddrx_mm_st_converter "a0" 2012.08.01.19:43:44 [Info] TR4_QSYS: Done TR4_QSYS" with 65 modules, 530 files, 12909664 bytes