// TR4_QSYS_uniphy_ddr3_s0.v

// This file was auto-generated from qsys_sequencer_110_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 11.1 173 at 2012.08.01.19:43:14

`timescale 1 ps / 1 ps
module TR4_QSYS_uniphy_ddr3_s0 (
		input  wire         avl_clk,                     //          avl_clk.clk
		input  wire         avl_reset_n,                 //        avl_reset.reset_n
		input  wire         phy_clk,                     //              phy.phy_clk
		input  wire         phy_reset_n,                 //                 .phy_reset_n
		output wire [4:0]   phy_read_latency_counter,    //                 .phy_read_latency_counter
		output wire [5:0]   phy_afi_wlat,                //                 .phy_afi_wlat
		output wire [5:0]   phy_afi_rlat,                //                 .phy_afi_rlat
		output wire [7:0]   phy_read_increment_vfifo_fr, //                 .phy_read_increment_vfifo_fr
		output wire [7:0]   phy_read_increment_vfifo_hr, //                 .phy_read_increment_vfifo_hr
		output wire [7:0]   phy_read_increment_vfifo_qr, //                 .phy_read_increment_vfifo_qr
		output wire         phy_reset_mem_stable,        //                 .phy_reset_mem_stable
		output wire         phy_cal_success,             //                 .phy_cal_success
		output wire         phy_cal_fail,                //                 .phy_cal_fail
		output wire [31:0]  phy_cal_debug_info,          //                 .phy_cal_debug_info
		output wire [7:0]   phy_read_fifo_reset,         //                 .phy_read_fifo_reset
		output wire [7:0]   phy_vfifo_rd_en_override,    //                 .phy_vfifo_rd_en_override
		input  wire [255:0] phy_read_fifo_q,             //                 .phy_read_fifo_q
		output wire         phy_mux_sel,                 //          mux_sel.mux_sel
		input  wire [7:0]   calib_skip_steps,            //            calib.calib_skip_steps
		input  wire         afi_clk,                     //          afi_clk.clk
		input  wire         afi_reset_n,                 //        afi_reset.reset_n
		output wire [25:0]  afi_addr,                    //              afi.afi_addr
		output wire [5:0]   afi_ba,                      //                 .afi_ba
		output wire [1:0]   afi_cs_n,                    //                 .afi_cs_n
		output wire [1:0]   afi_cke,                     //                 .afi_cke
		output wire [1:0]   afi_odt,                     //                 .afi_odt
		output wire [1:0]   afi_ras_n,                   //                 .afi_ras_n
		output wire [1:0]   afi_cas_n,                   //                 .afi_cas_n
		output wire [1:0]   afi_we_n,                    //                 .afi_we_n
		output wire [15:0]  afi_dqs_burst,               //                 .afi_dqs_burst
		output wire [1:0]   afi_rst_n,                   //                 .afi_rst_n
		output wire [255:0] afi_wdata,                   //                 .afi_wdata
		output wire [15:0]  afi_wdata_valid,             //                 .afi_wdata_valid
		output wire [31:0]  afi_dm,                      //                 .afi_dm
		output wire [1:0]   afi_rdata_en,                //                 .afi_rdata_en
		output wire [1:0]   afi_rdata_en_full,           //                 .afi_rdata_en_full
		input  wire [255:0] afi_rdata,                   //                 .afi_rdata
		input  wire [1:0]   afi_rdata_valid,             //                 .afi_rdata_valid
		output wire         scc_data,                    //              scc.scc_data
		output wire [7:0]   scc_dqs_ena,                 //                 .scc_dqs_ena
		output wire [7:0]   scc_dqs_io_ena,              //                 .scc_dqs_io_ena
		output wire [63:0]  scc_dq_ena,                  //                 .scc_dq_ena
		output wire [7:0]   scc_dm_ena,                  //                 .scc_dm_ena
		output wire         scc_upd,                     //                 .scc_upd
		input  wire [7:0]   capture_strobe_tracking,     //                 .capture_strobe_tracking
		input  wire         afi_init_req,                // afi_init_cal_req.afi_init_req
		input  wire         afi_cal_req,                 //                 .afi_cal_req
		input  wire         scc_clk,                     //          scc_clk.clk
		input  wire         reset_n_scc_clk              //        scc_reset.reset_n
	);

	wire         cpu_inst_data_master_waitrequest;                                                                 // cpu_inst_data_master_translator:av_waitrequest -> cpu_inst:d_waitrequest
	wire  [31:0] cpu_inst_data_master_writedata;                                                                   // cpu_inst:d_writedata -> cpu_inst_data_master_translator:av_writedata
	wire  [19:0] cpu_inst_data_master_address;                                                                     // cpu_inst:d_address -> cpu_inst_data_master_translator:av_address
	wire         cpu_inst_data_master_write;                                                                       // cpu_inst:d_write -> cpu_inst_data_master_translator:av_write
	wire         cpu_inst_data_master_read;                                                                        // cpu_inst:d_read -> cpu_inst_data_master_translator:av_read
	wire  [31:0] cpu_inst_data_master_readdata;                                                                    // cpu_inst_data_master_translator:av_readdata -> cpu_inst:d_readdata
	wire   [3:0] cpu_inst_data_master_byteenable;                                                                  // cpu_inst:d_byteenable -> cpu_inst_data_master_translator:av_byteenable
	wire         cpu_inst_instruction_master_waitrequest;                                                          // cpu_inst_instruction_master_translator:av_waitrequest -> cpu_inst:i_waitrequest
	wire  [16:0] cpu_inst_instruction_master_address;                                                              // cpu_inst:i_address -> cpu_inst_instruction_master_translator:av_address
	wire         cpu_inst_instruction_master_read;                                                                 // cpu_inst:i_read -> cpu_inst_instruction_master_translator:av_read
	wire  [31:0] cpu_inst_instruction_master_readdata;                                                             // cpu_inst_instruction_master_translator:av_readdata -> cpu_inst:i_readdata
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest;                            // sequencer_phy_mgr_inst:avl_waitrequest -> sequencer_phy_mgr_inst_avl_translator:av_waitrequest
	wire  [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata;                              // sequencer_phy_mgr_inst_avl_translator:av_writedata -> sequencer_phy_mgr_inst:avl_writedata
	wire  [12:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address;                                // sequencer_phy_mgr_inst_avl_translator:av_address -> sequencer_phy_mgr_inst:avl_address
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write;                                  // sequencer_phy_mgr_inst_avl_translator:av_write -> sequencer_phy_mgr_inst:avl_write
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read;                                   // sequencer_phy_mgr_inst_avl_translator:av_read -> sequencer_phy_mgr_inst:avl_read
	wire  [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata;                               // sequencer_phy_mgr_inst:avl_readdata -> sequencer_phy_mgr_inst_avl_translator:av_readdata
	wire         sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest;                           // sequencer_data_mgr_inst:avl_waitrequest -> sequencer_data_mgr_inst_avl_translator:av_waitrequest
	wire  [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata;                             // sequencer_data_mgr_inst_avl_translator:av_writedata -> sequencer_data_mgr_inst:avl_writedata
	wire  [12:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address;                               // sequencer_data_mgr_inst_avl_translator:av_address -> sequencer_data_mgr_inst:avl_address
	wire         sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write;                                 // sequencer_data_mgr_inst_avl_translator:av_write -> sequencer_data_mgr_inst:avl_write
	wire         sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read;                                  // sequencer_data_mgr_inst_avl_translator:av_read -> sequencer_data_mgr_inst:avl_read
	wire  [31:0] sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata;                              // sequencer_data_mgr_inst:avl_readdata -> sequencer_data_mgr_inst_avl_translator:av_readdata
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest;                             // sequencer_rw_mgr_inst:avl_waitrequest -> sequencer_rw_mgr_inst_avl_translator:av_waitrequest
	wire  [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata;                               // sequencer_rw_mgr_inst_avl_translator:av_writedata -> sequencer_rw_mgr_inst:avl_writedata
	wire  [12:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address;                                 // sequencer_rw_mgr_inst_avl_translator:av_address -> sequencer_rw_mgr_inst:avl_address
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write;                                   // sequencer_rw_mgr_inst_avl_translator:av_write -> sequencer_rw_mgr_inst:avl_write
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read;                                    // sequencer_rw_mgr_inst_avl_translator:av_read -> sequencer_rw_mgr_inst:avl_read
	wire  [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata;                                // sequencer_rw_mgr_inst:avl_readdata -> sequencer_rw_mgr_inst_avl_translator:av_readdata
	wire  [31:0] sequencer_mem_s1_translator_avalon_anti_slave_0_writedata;                                        // sequencer_mem_s1_translator:av_writedata -> sequencer_mem:s1_writedata
	wire  [11:0] sequencer_mem_s1_translator_avalon_anti_slave_0_address;                                          // sequencer_mem_s1_translator:av_address -> sequencer_mem:s1_address
	wire         sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect;                                       // sequencer_mem_s1_translator:av_chipselect -> sequencer_mem:s1_chipselect
	wire         sequencer_mem_s1_translator_avalon_anti_slave_0_clken;                                            // sequencer_mem_s1_translator:av_clken -> sequencer_mem:s1_clken
	wire         sequencer_mem_s1_translator_avalon_anti_slave_0_write;                                            // sequencer_mem_s1_translator:av_write -> sequencer_mem:s1_write
	wire  [31:0] sequencer_mem_s1_translator_avalon_anti_slave_0_readdata;                                         // sequencer_mem:s1_readdata -> sequencer_mem_s1_translator:av_readdata
	wire   [3:0] sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable;                                       // sequencer_mem_s1_translator:av_byteenable -> sequencer_mem:s1_be
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest;                            // sequencer_scc_mgr_inst:avl_waitrequest -> sequencer_scc_mgr_inst_avl_translator:av_waitrequest
	wire  [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata;                              // sequencer_scc_mgr_inst_avl_translator:av_writedata -> sequencer_scc_mgr_inst:avl_writedata
	wire  [12:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address;                                // sequencer_scc_mgr_inst_avl_translator:av_address -> sequencer_scc_mgr_inst:avl_address
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write;                                  // sequencer_scc_mgr_inst_avl_translator:av_write -> sequencer_scc_mgr_inst:avl_write
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read;                                   // sequencer_scc_mgr_inst_avl_translator:av_read -> sequencer_scc_mgr_inst:avl_read
	wire  [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata;                               // sequencer_scc_mgr_inst:avl_readdata -> sequencer_scc_mgr_inst_avl_translator:av_readdata
	wire         sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest;                           // sequencer_reg_file_inst:avl_waitrequest -> sequencer_reg_file_inst_avl_translator:av_waitrequest
	wire  [31:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata;                             // sequencer_reg_file_inst_avl_translator:av_writedata -> sequencer_reg_file_inst:avl_writedata
	wire  [12:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address;                               // sequencer_reg_file_inst_avl_translator:av_address -> sequencer_reg_file_inst:avl_address
	wire         sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write;                                 // sequencer_reg_file_inst_avl_translator:av_write -> sequencer_reg_file_inst:avl_write
	wire         sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read;                                  // sequencer_reg_file_inst_avl_translator:av_read -> sequencer_reg_file_inst:avl_read
	wire  [31:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata;                              // sequencer_reg_file_inst:avl_readdata -> sequencer_reg_file_inst_avl_translator:av_readdata
	wire   [3:0] sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable;                            // sequencer_reg_file_inst_avl_translator:av_byteenable -> sequencer_reg_file_inst:avl_be
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // sequencer_reg_file_inst_avl_translator:uav_waitrequest -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;              // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_reg_file_inst_avl_translator:uav_burstcount
	wire  [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;               // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_reg_file_inst_avl_translator:uav_writedata
	wire  [19:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                 // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_reg_file_inst_avl_translator:uav_address
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                   // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_reg_file_inst_avl_translator:uav_write
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_reg_file_inst_avl_translator:uav_lock
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_reg_file_inst_avl_translator:uav_read
	wire  [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                // sequencer_reg_file_inst_avl_translator:uav_readdata -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // sequencer_reg_file_inst_avl_translator:uav_readdatavalid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_reg_file_inst_avl_translator:uav_debugaccess
	wire   [3:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;              // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_reg_file_inst_avl_translator:uav_byteenable
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;            // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [75:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;             // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;            // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [75:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;              // sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;               // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
	wire  [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
	wire  [19:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                  // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                    // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
	wire  [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                 // sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;            // sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;              // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
	wire   [3:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;               // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;       // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;             // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [75:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;              // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;             // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;    // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;          // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;  // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [75:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;           // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;          // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;        // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;         // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;        // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;             // sequencer_data_mgr_inst_avl_translator:uav_waitrequest -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;              // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_data_mgr_inst_avl_translator:uav_burstcount
	wire  [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;               // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_data_mgr_inst_avl_translator:uav_writedata
	wire  [19:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                 // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_data_mgr_inst_avl_translator:uav_address
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                   // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_data_mgr_inst_avl_translator:uav_write
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_data_mgr_inst_avl_translator:uav_lock
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_data_mgr_inst_avl_translator:uav_read
	wire  [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                // sequencer_data_mgr_inst_avl_translator:uav_readdata -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;           // sequencer_data_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;             // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_data_mgr_inst_avl_translator:uav_debugaccess
	wire   [3:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;              // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_data_mgr_inst_avl_translator:uav_byteenable
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;      // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;            // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [75:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;             // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;            // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;   // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;         // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [75:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;          // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;         // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;       // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;        // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;       // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest;                        // sequencer_mem_s1_translator:uav_waitrequest -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount;                         // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_mem_s1_translator:uav_burstcount
	wire  [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata;                          // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_mem_s1_translator:uav_writedata
	wire  [19:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address;                            // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_mem_s1_translator:uav_address
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write;                              // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_mem_s1_translator:uav_write
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock;                               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_mem_s1_translator:uav_lock
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read;                               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_mem_s1_translator:uav_read
	wire  [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata;                           // sequencer_mem_s1_translator:uav_readdata -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid;                      // sequencer_mem_s1_translator:uav_readdatavalid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess;                        // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_mem_s1_translator:uav_debugaccess
	wire   [3:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable;                         // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_mem_s1_translator:uav_byteenable
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;                 // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid;                       // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [75:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data;                        // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready;                       // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;              // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;                    // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;            // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [75:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;                     // sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;                    // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;                  // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;                   // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;                  // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;              // sequencer_scc_mgr_inst_avl_translator:uav_waitrequest -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;               // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_scc_mgr_inst_avl_translator:uav_burstcount
	wire  [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_scc_mgr_inst_avl_translator:uav_writedata
	wire  [19:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                  // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_scc_mgr_inst_avl_translator:uav_address
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                    // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_scc_mgr_inst_avl_translator:uav_write
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_scc_mgr_inst_avl_translator:uav_lock
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_scc_mgr_inst_avl_translator:uav_read
	wire  [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                 // sequencer_scc_mgr_inst_avl_translator:uav_readdata -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;            // sequencer_scc_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;              // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_scc_mgr_inst_avl_translator:uav_debugaccess
	wire   [3:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;               // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_scc_mgr_inst_avl_translator:uav_byteenable
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;       // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;             // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [75:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;              // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;             // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;    // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;          // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;  // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [75:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;           // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;          // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;        // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;         // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;        // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest;                            // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
	wire   [2:0] cpu_inst_data_master_translator_avalon_universal_master_0_burstcount;                             // cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_writedata;                              // cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_writedata
	wire  [19:0] cpu_inst_data_master_translator_avalon_universal_master_0_address;                                // cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_address
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_lock;                                   // cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_lock
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_write;                                  // cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_write
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_read;                                   // cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_read
	wire  [31:0] cpu_inst_data_master_translator_avalon_universal_master_0_readdata;                               // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess;                            // cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire   [3:0] cpu_inst_data_master_translator_avalon_universal_master_0_byteenable;                             // cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid;                          // cpu_inst_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest;                     // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_inst_instruction_master_translator:uav_waitrequest
	wire   [2:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount;                      // cpu_inst_instruction_master_translator:uav_burstcount -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
	wire  [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata;                       // cpu_inst_instruction_master_translator:uav_writedata -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
	wire  [19:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_address;                         // cpu_inst_instruction_master_translator:uav_address -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_address
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_lock;                            // cpu_inst_instruction_master_translator:uav_lock -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_lock
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_write;                           // cpu_inst_instruction_master_translator:uav_write -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_write
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_read;                            // cpu_inst_instruction_master_translator:uav_read -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_read
	wire  [31:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata;                        // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_inst_instruction_master_translator:uav_readdata
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess;                     // cpu_inst_instruction_master_translator:uav_debugaccess -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
	wire   [3:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable;                      // cpu_inst_instruction_master_translator:uav_byteenable -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid;                   // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_inst_instruction_master_translator:uav_readdatavalid
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest;               // sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_waitrequest
	wire   [2:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount;                // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
	wire  [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata;                 // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
	wire  [19:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address;                   // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write;                     // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock;                      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read;                      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
	wire  [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata;                  // sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdata
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid;             // sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_readdatavalid
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess;               // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
	wire   [3:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable;                // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket;        // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid;              // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket;      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
	wire  [75:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data;               // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready;              // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_source_ready
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket;     // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid;           // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_valid
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket;   // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
	wire  [75:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data;            // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_data
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready;           // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid;         // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
	wire  [31:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data;          // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready;         // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket;                   // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid;                         // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket;                 // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
	wire  [74:0] cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data;                          // cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
	wire         cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready;                         // addr_router:sink_ready -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:cp_ready
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket;            // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid;                  // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket;          // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
	wire  [74:0] cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data;                   // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
	wire         cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready;                  // addr_router_001:sink_ready -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;              // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                    // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;            // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
	wire  [74:0] sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                     // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
	wire         sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                    // id_router:sink_ready -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                   // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
	wire  [74:0] sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                    // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
	wire         sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router_001:sink_ready -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;               // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                     // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;             // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
	wire  [74:0] sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                      // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
	wire         sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                     // id_router_002:sink_ready -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket;                        // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid;                              // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket;                      // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
	wire  [74:0] sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data;                               // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
	wire         sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready;                              // id_router_003:sink_ready -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:rp_ready
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;              // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                    // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;            // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
	wire  [74:0] sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                     // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
	wire         sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                    // id_router_004:sink_ready -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket;             // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid;                   // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket;           // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
	wire  [74:0] sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data;                    // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
	wire         sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready;                   // id_router_005:sink_ready -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:rp_ready
	wire         rst_controller_reset_out_reset;                                                                   // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux_003:reset, cpu_inst:reset_n, cpu_inst_data_master_translator:reset, cpu_inst_data_master_translator_avalon_universal_master_0_agent:reset, cpu_inst_instruction_master_translator:reset, cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, irq_mapper:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_mux:reset, sequencer_data_mgr_inst:avl_reset_n, sequencer_data_mgr_inst_avl_translator:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_mem:reset1, sequencer_mem_s1_translator:reset, sequencer_mem_s1_translator_avalon_universal_slave_0_agent:reset, sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_phy_mgr_inst:avl_reset_n, sequencer_phy_mgr_inst_avl_translator:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_reg_file_inst:avl_reset_n, sequencer_reg_file_inst_avl_translator:reset, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_rw_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst_avl_translator:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sequencer_scc_mgr_inst:avl_reset_n, sequencer_scc_mgr_inst_avl_translator:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:reset, sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo:reset]
	wire         cmd_xbar_demux_src0_endofpacket;                                                                  // cmd_xbar_demux:src0_endofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_src0_valid;                                                                        // cmd_xbar_demux:src0_valid -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_src0_startofpacket;                                                                // cmd_xbar_demux:src0_startofpacket -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [74:0] cmd_xbar_demux_src0_data;                                                                         // cmd_xbar_demux:src0_data -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_src0_channel;                                                                      // cmd_xbar_demux:src0_channel -> sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_src1_endofpacket;                                                                  // cmd_xbar_demux:src1_endofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_src1_valid;                                                                        // cmd_xbar_demux:src1_valid -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_src1_startofpacket;                                                                // cmd_xbar_demux:src1_startofpacket -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [74:0] cmd_xbar_demux_src1_data;                                                                         // cmd_xbar_demux:src1_data -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_src1_channel;                                                                      // cmd_xbar_demux:src1_channel -> sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_src2_endofpacket;                                                                  // cmd_xbar_demux:src2_endofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_src2_valid;                                                                        // cmd_xbar_demux:src2_valid -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_src2_startofpacket;                                                                // cmd_xbar_demux:src2_startofpacket -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [74:0] cmd_xbar_demux_src2_data;                                                                         // cmd_xbar_demux:src2_data -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_src2_channel;                                                                      // cmd_xbar_demux:src2_channel -> sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_src3_endofpacket;                                                                  // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
	wire         cmd_xbar_demux_src3_valid;                                                                        // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
	wire         cmd_xbar_demux_src3_startofpacket;                                                                // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
	wire  [74:0] cmd_xbar_demux_src3_data;                                                                         // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
	wire   [5:0] cmd_xbar_demux_src3_channel;                                                                      // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
	wire         cmd_xbar_demux_src3_ready;                                                                        // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
	wire         cmd_xbar_demux_src4_endofpacket;                                                                  // cmd_xbar_demux:src4_endofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_src4_valid;                                                                        // cmd_xbar_demux:src4_valid -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_src4_startofpacket;                                                                // cmd_xbar_demux:src4_startofpacket -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [74:0] cmd_xbar_demux_src4_data;                                                                         // cmd_xbar_demux:src4_data -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_src4_channel;                                                                      // cmd_xbar_demux:src4_channel -> sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_src5_endofpacket;                                                                  // cmd_xbar_demux:src5_endofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_demux_src5_valid;                                                                        // cmd_xbar_demux:src5_valid -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_demux_src5_startofpacket;                                                                // cmd_xbar_demux:src5_startofpacket -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [74:0] cmd_xbar_demux_src5_data;                                                                         // cmd_xbar_demux:src5_data -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_demux_src5_channel;                                                                      // cmd_xbar_demux:src5_channel -> sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_demux_001_src0_endofpacket;                                                              // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
	wire         cmd_xbar_demux_001_src0_valid;                                                                    // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux_003:sink1_valid
	wire         cmd_xbar_demux_001_src0_startofpacket;                                                            // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
	wire  [74:0] cmd_xbar_demux_001_src0_data;                                                                     // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux_003:sink1_data
	wire   [5:0] cmd_xbar_demux_001_src0_channel;                                                                  // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux_003:sink1_channel
	wire         cmd_xbar_demux_001_src0_ready;                                                                    // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src0_ready
	wire         rsp_xbar_demux_src0_endofpacket;                                                                  // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
	wire         rsp_xbar_demux_src0_valid;                                                                        // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
	wire         rsp_xbar_demux_src0_startofpacket;                                                                // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
	wire  [74:0] rsp_xbar_demux_src0_data;                                                                         // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
	wire   [5:0] rsp_xbar_demux_src0_channel;                                                                      // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
	wire         rsp_xbar_demux_src0_ready;                                                                        // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
	wire         rsp_xbar_demux_001_src0_endofpacket;                                                              // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
	wire         rsp_xbar_demux_001_src0_valid;                                                                    // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
	wire         rsp_xbar_demux_001_src0_startofpacket;                                                            // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
	wire  [74:0] rsp_xbar_demux_001_src0_data;                                                                     // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
	wire   [5:0] rsp_xbar_demux_001_src0_channel;                                                                  // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
	wire         rsp_xbar_demux_001_src0_ready;                                                                    // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
	wire         rsp_xbar_demux_002_src0_endofpacket;                                                              // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
	wire         rsp_xbar_demux_002_src0_valid;                                                                    // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
	wire         rsp_xbar_demux_002_src0_startofpacket;                                                            // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
	wire  [74:0] rsp_xbar_demux_002_src0_data;                                                                     // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
	wire   [5:0] rsp_xbar_demux_002_src0_channel;                                                                  // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
	wire         rsp_xbar_demux_002_src0_ready;                                                                    // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
	wire         rsp_xbar_demux_003_src0_endofpacket;                                                              // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
	wire         rsp_xbar_demux_003_src0_valid;                                                                    // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
	wire         rsp_xbar_demux_003_src0_startofpacket;                                                            // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
	wire  [74:0] rsp_xbar_demux_003_src0_data;                                                                     // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
	wire   [5:0] rsp_xbar_demux_003_src0_channel;                                                                  // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
	wire         rsp_xbar_demux_003_src0_ready;                                                                    // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
	wire         rsp_xbar_demux_003_src1_endofpacket;                                                              // rsp_xbar_demux_003:src1_endofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire         rsp_xbar_demux_003_src1_valid;                                                                    // rsp_xbar_demux_003:src1_valid -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
	wire         rsp_xbar_demux_003_src1_startofpacket;                                                            // rsp_xbar_demux_003:src1_startofpacket -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [74:0] rsp_xbar_demux_003_src1_data;                                                                     // rsp_xbar_demux_003:src1_data -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_data
	wire   [5:0] rsp_xbar_demux_003_src1_channel;                                                                  // rsp_xbar_demux_003:src1_channel -> cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
	wire         rsp_xbar_demux_004_src0_endofpacket;                                                              // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket
	wire         rsp_xbar_demux_004_src0_valid;                                                                    // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid
	wire         rsp_xbar_demux_004_src0_startofpacket;                                                            // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket
	wire  [74:0] rsp_xbar_demux_004_src0_data;                                                                     // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data
	wire   [5:0] rsp_xbar_demux_004_src0_channel;                                                                  // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel
	wire         rsp_xbar_demux_004_src0_ready;                                                                    // rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready
	wire         rsp_xbar_demux_005_src0_endofpacket;                                                              // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux:sink5_endofpacket
	wire         rsp_xbar_demux_005_src0_valid;                                                                    // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux:sink5_valid
	wire         rsp_xbar_demux_005_src0_startofpacket;                                                            // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux:sink5_startofpacket
	wire  [74:0] rsp_xbar_demux_005_src0_data;                                                                     // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux:sink5_data
	wire   [5:0] rsp_xbar_demux_005_src0_channel;                                                                  // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux:sink5_channel
	wire         rsp_xbar_demux_005_src0_ready;                                                                    // rsp_xbar_mux:sink5_ready -> rsp_xbar_demux_005:src0_ready
	wire         addr_router_src_endofpacket;                                                                      // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
	wire         addr_router_src_valid;                                                                            // addr_router:src_valid -> cmd_xbar_demux:sink_valid
	wire         addr_router_src_startofpacket;                                                                    // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
	wire  [74:0] addr_router_src_data;                                                                             // addr_router:src_data -> cmd_xbar_demux:sink_data
	wire   [5:0] addr_router_src_channel;                                                                          // addr_router:src_channel -> cmd_xbar_demux:sink_channel
	wire         addr_router_src_ready;                                                                            // cmd_xbar_demux:sink_ready -> addr_router:src_ready
	wire         rsp_xbar_mux_src_endofpacket;                                                                     // rsp_xbar_mux:src_endofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
	wire         rsp_xbar_mux_src_valid;                                                                           // rsp_xbar_mux:src_valid -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_valid
	wire         rsp_xbar_mux_src_startofpacket;                                                                   // rsp_xbar_mux:src_startofpacket -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
	wire  [74:0] rsp_xbar_mux_src_data;                                                                            // rsp_xbar_mux:src_data -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_data
	wire   [5:0] rsp_xbar_mux_src_channel;                                                                         // rsp_xbar_mux:src_channel -> cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_channel
	wire         rsp_xbar_mux_src_ready;                                                                           // cpu_inst_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
	wire         addr_router_001_src_endofpacket;                                                                  // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
	wire         addr_router_001_src_valid;                                                                        // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
	wire         addr_router_001_src_startofpacket;                                                                // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
	wire  [74:0] addr_router_001_src_data;                                                                         // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
	wire   [5:0] addr_router_001_src_channel;                                                                      // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
	wire         addr_router_001_src_ready;                                                                        // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
	wire         rsp_xbar_demux_003_src1_ready;                                                                    // cpu_inst_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_003:src1_ready
	wire         cmd_xbar_demux_src0_ready;                                                                        // sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src0_ready
	wire         id_router_src_endofpacket;                                                                        // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
	wire         id_router_src_valid;                                                                              // id_router:src_valid -> rsp_xbar_demux:sink_valid
	wire         id_router_src_startofpacket;                                                                      // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
	wire  [74:0] id_router_src_data;                                                                               // id_router:src_data -> rsp_xbar_demux:sink_data
	wire   [5:0] id_router_src_channel;                                                                            // id_router:src_channel -> rsp_xbar_demux:sink_channel
	wire         id_router_src_ready;                                                                              // rsp_xbar_demux:sink_ready -> id_router:src_ready
	wire         cmd_xbar_demux_src1_ready;                                                                        // sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src1_ready
	wire         id_router_001_src_endofpacket;                                                                    // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
	wire         id_router_001_src_valid;                                                                          // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
	wire         id_router_001_src_startofpacket;                                                                  // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
	wire  [74:0] id_router_001_src_data;                                                                           // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
	wire   [5:0] id_router_001_src_channel;                                                                        // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
	wire         id_router_001_src_ready;                                                                          // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
	wire         cmd_xbar_demux_src2_ready;                                                                        // sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src2_ready
	wire         id_router_002_src_endofpacket;                                                                    // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
	wire         id_router_002_src_valid;                                                                          // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
	wire         id_router_002_src_startofpacket;                                                                  // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
	wire  [74:0] id_router_002_src_data;                                                                           // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
	wire   [5:0] id_router_002_src_channel;                                                                        // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
	wire         id_router_002_src_ready;                                                                          // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
	wire         cmd_xbar_mux_003_src_endofpacket;                                                                 // cmd_xbar_mux_003:src_endofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
	wire         cmd_xbar_mux_003_src_valid;                                                                       // cmd_xbar_mux_003:src_valid -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_valid
	wire         cmd_xbar_mux_003_src_startofpacket;                                                               // cmd_xbar_mux_003:src_startofpacket -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
	wire  [74:0] cmd_xbar_mux_003_src_data;                                                                        // cmd_xbar_mux_003:src_data -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_data
	wire   [5:0] cmd_xbar_mux_003_src_channel;                                                                     // cmd_xbar_mux_003:src_channel -> sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_channel
	wire         cmd_xbar_mux_003_src_ready;                                                                       // sequencer_mem_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_003:src_ready
	wire         id_router_003_src_endofpacket;                                                                    // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
	wire         id_router_003_src_valid;                                                                          // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
	wire         id_router_003_src_startofpacket;                                                                  // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
	wire  [74:0] id_router_003_src_data;                                                                           // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
	wire   [5:0] id_router_003_src_channel;                                                                        // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
	wire         id_router_003_src_ready;                                                                          // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
	wire         cmd_xbar_demux_src4_ready;                                                                        // sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src4_ready
	wire         id_router_004_src_endofpacket;                                                                    // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
	wire         id_router_004_src_valid;                                                                          // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
	wire         id_router_004_src_startofpacket;                                                                  // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
	wire  [74:0] id_router_004_src_data;                                                                           // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
	wire   [5:0] id_router_004_src_channel;                                                                        // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
	wire         id_router_004_src_ready;                                                                          // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
	wire         cmd_xbar_demux_src5_ready;                                                                        // sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux:src5_ready
	wire         id_router_005_src_endofpacket;                                                                    // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
	wire         id_router_005_src_valid;                                                                          // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
	wire         id_router_005_src_startofpacket;                                                                  // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
	wire  [74:0] id_router_005_src_data;                                                                           // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
	wire   [5:0] id_router_005_src_channel;                                                                        // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
	wire         id_router_005_src_ready;                                                                          // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
	wire  [31:0] cpu_inst_d_irq_irq;                                                                               // irq_mapper:sender_irq -> cpu_inst:d_irq

	altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst cpu_inst (
		.clk           (avl_clk),                                 //                       clk.clk
		.reset_n       (~rst_controller_reset_out_reset),         //                   reset_n.reset_n
		.d_address     (cpu_inst_data_master_address),            //               data_master.address
		.d_byteenable  (cpu_inst_data_master_byteenable),         //                          .byteenable
		.d_read        (cpu_inst_data_master_read),               //                          .read
		.d_readdata    (cpu_inst_data_master_readdata),           //                          .readdata
		.d_waitrequest (cpu_inst_data_master_waitrequest),        //                          .waitrequest
		.d_write       (cpu_inst_data_master_write),              //                          .write
		.d_writedata   (cpu_inst_data_master_writedata),          //                          .writedata
		.i_address     (cpu_inst_instruction_master_address),     //        instruction_master.address
		.i_read        (cpu_inst_instruction_master_read),        //                          .read
		.i_readdata    (cpu_inst_instruction_master_readdata),    //                          .readdata
		.i_waitrequest (cpu_inst_instruction_master_waitrequest), //                          .waitrequest
		.d_irq         (cpu_inst_d_irq_irq),                      //                     d_irq.irq
		.no_ci_readra  ()                                         // custom_instruction_master.readra
	);

	sequencer_scc_mgr #(
		.AVL_DATA_WIDTH         (32),
		.AVL_ADDR_WIDTH         (13),
		.MEM_IF_READ_DQS_WIDTH  (8),
		.MEM_IF_WRITE_DQS_WIDTH (8),
		.MEM_IF_DQ_WIDTH        (64),
		.MEM_IF_DM_WIDTH        (8),
		.DLL_DELAY_CHAIN_LENGTH (12),
		.FAMILY                 ("STRATIXIV"),
		.DQS_TRK_ENABLED        (0),
		.DUAL_WRITE_CLOCK       (0)
	) sequencer_scc_mgr_inst (
		.avl_clk                 (avl_clk),                                                               //          avl_clk.clk
		.avl_reset_n             (~rst_controller_reset_out_reset),                                       //        avl_reset.reset_n
		.avl_address             (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address),     //              avl.address
		.avl_write               (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write),       //                 .write
		.avl_writedata           (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),   //                 .writedata
		.avl_read                (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read),        //                 .read
		.avl_readdata            (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),    //                 .readdata
		.avl_waitrequest         (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), //                 .waitrequest
		.scc_clk                 (scc_clk),                                                               //          scc_clk.clk
		.scc_reset_n             (reset_n_scc_clk),                                                       //        scc_reset.reset_n
		.scc_data                (scc_data),                                                              //              scc.scc_data
		.scc_dqs_ena             (scc_dqs_ena),                                                           //                 .scc_dqs_ena
		.scc_dqs_io_ena          (scc_dqs_io_ena),                                                        //                 .scc_dqs_io_ena
		.scc_dq_ena              (scc_dq_ena),                                                            //                 .scc_dq_ena
		.scc_dm_ena              (scc_dm_ena),                                                            //                 .scc_dm_ena
		.scc_upd                 (scc_upd),                                                               //                 .scc_upd
		.capture_strobe_tracking (capture_strobe_tracking),                                               //                 .capture_strobe_tracking
		.afi_init_req            (afi_init_req),                                                          // afi_init_cal_req.afi_init_req
		.afi_cal_req             (afi_cal_req)                                                            //                 .afi_cal_req
	);

	sequencer_reg_file #(
		.AVL_DATA_WIDTH    (32),
		.AVL_ADDR_WIDTH    (13),
		.AVL_NUM_SYMBOLS   (4),
		.AVL_SYMBOL_WIDTH  (8),
		.REGISTER_RDATA    (0),
		.NUM_REGFILE_WORDS (16)
	) sequencer_reg_file_inst (
		.avl_clk         (avl_clk),                                                                //   avl_clk.clk
		.avl_reset_n     (~rst_controller_reset_out_reset),                                        // avl_reset.reset_n
		.avl_address     (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address),     //       avl.address
		.avl_write       (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write),       //          .write
		.avl_writedata   (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata),   //          .writedata
		.avl_read        (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read),        //          .read
		.avl_readdata    (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata),    //          .readdata
		.avl_waitrequest (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest), //          .waitrequest
		.avl_be          (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable)   //          .byteenable
	);

	sequencer_phy_mgr #(
		.AVL_DATA_WIDTH                    (32),
		.AVL_ADDR_WIDTH                    (13),
		.MAX_LATENCY_COUNT_WIDTH           (5),
		.MEM_IF_READ_DQS_WIDTH             (8),
		.AFI_DQ_WIDTH                      (256),
		.AFI_DEBUG_INFO_WIDTH              (32),
		.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
		.AFI_MAX_READ_LATENCY_COUNT_WIDTH  (6),
		.CALIB_VFIFO_OFFSET                (20),
		.CALIB_LFIFO_OFFSET                (8),
		.CALIB_REG_WIDTH                   (8),
		.READ_VALID_FIFO_SIZE              (16),
		.MEM_T_WL                          (11),
		.MEM_T_RL                          (13),
		.CTL_REGDIMM_ENABLED               (0)
	) sequencer_phy_mgr_inst (
		.avl_clk                     (avl_clk),                                                               //   avl_clk.clk
		.avl_reset_n                 (~rst_controller_reset_out_reset),                                       // avl_reset.reset_n
		.avl_address                 (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address),     //       avl.address
		.avl_write                   (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write),       //          .write
		.avl_writedata               (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),   //          .writedata
		.avl_read                    (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read),        //          .read
		.avl_readdata                (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),    //          .readdata
		.avl_waitrequest             (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), //          .waitrequest
		.phy_clk                     (phy_clk),                                                               //       phy.phy_clk
		.phy_reset_n                 (phy_reset_n),                                                           //          .phy_reset_n
		.phy_read_latency_counter    (phy_read_latency_counter),                                              //          .phy_read_latency_counter
		.phy_afi_wlat                (phy_afi_wlat),                                                          //          .phy_afi_wlat
		.phy_afi_rlat                (phy_afi_rlat),                                                          //          .phy_afi_rlat
		.phy_read_increment_vfifo_fr (phy_read_increment_vfifo_fr),                                           //          .phy_read_increment_vfifo_fr
		.phy_read_increment_vfifo_hr (phy_read_increment_vfifo_hr),                                           //          .phy_read_increment_vfifo_hr
		.phy_read_increment_vfifo_qr (phy_read_increment_vfifo_qr),                                           //          .phy_read_increment_vfifo_qr
		.phy_reset_mem_stable        (phy_reset_mem_stable),                                                  //          .phy_reset_mem_stable
		.phy_cal_success             (phy_cal_success),                                                       //          .phy_cal_success
		.phy_cal_fail                (phy_cal_fail),                                                          //          .phy_cal_fail
		.phy_cal_debug_info          (phy_cal_debug_info),                                                    //          .phy_cal_debug_info
		.phy_read_fifo_reset         (phy_read_fifo_reset),                                                   //          .phy_read_fifo_reset
		.phy_vfifo_rd_en_override    (phy_vfifo_rd_en_override),                                              //          .phy_vfifo_rd_en_override
		.phy_read_fifo_q             (phy_read_fifo_q),                                                       //          .phy_read_fifo_q
		.calib_skip_steps            (calib_skip_steps),                                                      //     calib.calib_skip_steps
		.phy_mux_sel                 (phy_mux_sel)                                                            //   mux_sel.mux_sel
	);

	sequencer_data_mgr #(
		.AVL_DATA_WIDTH                    (32),
		.AVL_ADDR_WIDTH                    (13),
		.MAX_LATENCY_COUNT_WIDTH           (5),
		.MEM_READ_DQS_WIDTH                (8),
		.AFI_DEBUG_INFO_WIDTH              (32),
		.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH (6),
		.AFI_MAX_READ_LATENCY_COUNT_WIDTH  (6),
		.CALIB_VFIFO_OFFSET                (20),
		.CALIB_LFIFO_OFFSET                (8),
		.CALIB_SKIP_STEPS_WIDTH            (8),
		.READ_VALID_FIFO_SIZE              (16),
		.MEM_T_WL                          (11),
		.MEM_T_RL                          (13),
		.CTL_REGDIMM_ENABLED               (0),
		.SEQUENCER_VERSION                 (11)
	) sequencer_data_mgr_inst (
		.avl_clk         (avl_clk),                                                                //   avl_clk.clk
		.avl_reset_n     (~rst_controller_reset_out_reset),                                        // avl_reset.reset_n
		.avl_address     (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address),     //       avl.address
		.avl_write       (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write),       //          .write
		.avl_writedata   (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),   //          .writedata
		.avl_read        (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read),        //          .read
		.avl_readdata    (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),    //          .readdata
		.avl_waitrequest (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest)  //          .waitrequest
	);

	rw_manager_ddr3 #(
		.RATE                    ("Half"),
		.AVL_DATA_WIDTH          (32),
		.AVL_ADDR_WIDTH          (13),
		.MEM_ADDRESS_WIDTH       (13),
		.MEM_CONTROL_WIDTH       (1),
		.MEM_DQ_WIDTH            (64),
		.MEM_DM_WIDTH            (8),
		.MEM_NUMBER_OF_RANKS     (1),
		.MEM_CLK_EN_WIDTH        (1),
		.MEM_BANK_WIDTH          (3),
		.MEM_ODT_WIDTH           (1),
		.MEM_CHIP_SELECT_WIDTH   (1),
		.MEM_READ_DQS_WIDTH      (8),
		.MEM_WRITE_DQS_WIDTH     (8),
		.AFI_RATIO               (2),
		.AC_BUS_WIDTH            (27),
		.HCX_COMPAT_MODE         (0),
		.DEVICE_FAMILY           ("STRATIXIV"),
		.AC_ROM_INIT_FILE_NAME   ("TR4_QSYS_uniphy_ddr3_s0_AC_ROM.hex"),
		.INST_ROM_INIT_FILE_NAME ("TR4_QSYS_uniphy_ddr3_s0_inst_ROM.hex")
	) sequencer_rw_mgr_inst (
		.avl_clk           (avl_clk),                                                              //   avl_clk.clk
		.avl_reset_n       (~rst_controller_reset_out_reset),                                      // avl_reset.reset_n
		.avl_address       (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address),     //       avl.address
		.avl_write         (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write),       //          .write
		.avl_writedata     (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),   //          .writedata
		.avl_read          (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read),        //          .read
		.avl_readdata      (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),    //          .readdata
		.avl_waitrequest   (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest), //          .waitrequest
		.afi_clk           (afi_clk),                                                              //   afi_clk.clk
		.afi_reset_n       (afi_reset_n),                                                          // afi_reset.reset_n
		.afi_addr          (afi_addr),                                                             //       afi.afi_addr
		.afi_ba            (afi_ba),                                                               //          .afi_ba
		.afi_cs_n          (afi_cs_n),                                                             //          .afi_cs_n
		.afi_cke           (afi_cke),                                                              //          .afi_cke
		.afi_odt           (afi_odt),                                                              //          .afi_odt
		.afi_ras_n         (afi_ras_n),                                                            //          .afi_ras_n
		.afi_cas_n         (afi_cas_n),                                                            //          .afi_cas_n
		.afi_we_n          (afi_we_n),                                                             //          .afi_we_n
		.afi_dqs_burst     (afi_dqs_burst),                                                        //          .afi_dqs_burst
		.afi_rst_n         (afi_rst_n),                                                            //          .afi_rst_n
		.afi_wdata         (afi_wdata),                                                            //          .afi_wdata
		.afi_wdata_valid   (afi_wdata_valid),                                                      //          .afi_wdata_valid
		.afi_dm            (afi_dm),                                                               //          .afi_dm
		.afi_rdata_en      (afi_rdata_en),                                                         //          .afi_rdata_en
		.afi_rdata_en_full (afi_rdata_en_full),                                                    //          .afi_rdata_en_full
		.afi_rdata         (afi_rdata),                                                            //          .afi_rdata
		.afi_rdata_valid   (afi_rdata_valid),                                                      //          .afi_rdata_valid
		.csr_clk           (),                                                                     //       csr.csr_clk
		.csr_ena           (),                                                                     //          .csr_ena
		.csr_dout_phy      (),                                                                     //          .csr_dout_phy
		.csr_dout          ()                                                                      //          .csr_dout
	);

	altera_mem_if_sequencer_mem_no_ifdef_params #(
		.AVL_DATA_WIDTH   (32),
		.AVL_ADDR_WIDTH   (12),
		.AVL_NUM_SYMBOLS  (4),
		.AVL_SYMBOL_WIDTH (8),
		.MEM_SIZE         (11264),
		.INIT_FILE        ("TR4_QSYS_uniphy_ddr3_s0_sequencer_mem.hex")
	) sequencer_mem (
		.clk1          (avl_clk),                                                    //   clk1.clk
		.reset1        (rst_controller_reset_out_reset),                             // reset1.reset
		.s1_address    (sequencer_mem_s1_translator_avalon_anti_slave_0_address),    //     s1.address
		.s1_write      (sequencer_mem_s1_translator_avalon_anti_slave_0_write),      //       .write
		.s1_writedata  (sequencer_mem_s1_translator_avalon_anti_slave_0_writedata),  //       .writedata
		.s1_readdata   (sequencer_mem_s1_translator_avalon_anti_slave_0_readdata),   //       .readdata
		.s1_be         (sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable), //       .byteenable
		.s1_chipselect (sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect), //       .chipselect
		.s1_clken      (sequencer_mem_s1_translator_avalon_anti_slave_0_clken)       //       .clken
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (20),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (20),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (1)
	) cpu_inst_data_master_translator (
		.clk                   (avl_clk),                                                                 //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                          //                     reset.reset
		.uav_address           (cpu_inst_data_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (cpu_inst_data_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (cpu_inst_data_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (cpu_inst_data_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (cpu_inst_data_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (cpu_inst_data_master_waitrequest),                                        //                          .waitrequest
		.av_byteenable         (cpu_inst_data_master_byteenable),                                         //                          .byteenable
		.av_read               (cpu_inst_data_master_read),                                               //                          .read
		.av_readdata           (cpu_inst_data_master_readdata),                                           //                          .readdata
		.av_write              (cpu_inst_data_master_write),                                              //                          .write
		.av_writedata          (cpu_inst_data_master_writedata),                                          //                          .writedata
		.av_burstcount         (1'b1),                                                                    //               (terminated)
		.av_beginbursttransfer (1'b0),                                                                    //               (terminated)
		.av_begintransfer      (1'b0),                                                                    //               (terminated)
		.av_chipselect         (1'b0),                                                                    //               (terminated)
		.av_readdatavalid      (),                                                                        //               (terminated)
		.av_lock               (1'b0),                                                                    //               (terminated)
		.av_debugaccess        (1'b0),                                                                    //               (terminated)
		.uav_clken             (),                                                                        //               (terminated)
		.av_clken              (1'b1)                                                                     //               (terminated)
	);

	altera_merlin_master_translator #(
		.AV_ADDRESS_W                (17),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (20),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (0),
		.USE_WAITREQUEST             (1),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (1),
		.AV_REGISTERINCOMINGSIGNALS  (0)
	) cpu_inst_instruction_master_translator (
		.clk                   (avl_clk),                                                                        //                       clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                 //                     reset.reset
		.uav_address           (cpu_inst_instruction_master_translator_avalon_universal_master_0_address),       // avalon_universal_master_0.address
		.uav_burstcount        (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount),    //                          .burstcount
		.uav_read              (cpu_inst_instruction_master_translator_avalon_universal_master_0_read),          //                          .read
		.uav_write             (cpu_inst_instruction_master_translator_avalon_universal_master_0_write),         //                          .write
		.uav_waitrequest       (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest),   //                          .waitrequest
		.uav_readdatavalid     (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid), //                          .readdatavalid
		.uav_byteenable        (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable),    //                          .byteenable
		.uav_readdata          (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata),      //                          .readdata
		.uav_writedata         (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata),     //                          .writedata
		.uav_lock              (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock),          //                          .lock
		.uav_debugaccess       (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess),   //                          .debugaccess
		.av_address            (cpu_inst_instruction_master_address),                                            //      avalon_anti_master_0.address
		.av_waitrequest        (cpu_inst_instruction_master_waitrequest),                                        //                          .waitrequest
		.av_read               (cpu_inst_instruction_master_read),                                               //                          .read
		.av_readdata           (cpu_inst_instruction_master_readdata),                                           //                          .readdata
		.av_burstcount         (1'b1),                                                                           //               (terminated)
		.av_byteenable         (4'b1111),                                                                        //               (terminated)
		.av_beginbursttransfer (1'b0),                                                                           //               (terminated)
		.av_begintransfer      (1'b0),                                                                           //               (terminated)
		.av_chipselect         (1'b0),                                                                           //               (terminated)
		.av_readdatavalid      (),                                                                               //               (terminated)
		.av_write              (1'b0),                                                                           //               (terminated)
		.av_writedata          (32'b00000000000000000000000000000000),                                           //               (terminated)
		.av_lock               (1'b0),                                                                           //               (terminated)
		.av_debugaccess        (1'b0),                                                                           //               (terminated)
		.uav_clken             (),                                                                               //               (terminated)
		.av_clken              (1'b1)                                                                            //               (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_phy_mgr_inst_avl_translator (
		.clk                   (avl_clk),                                                                               //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                        //                    reset.reset
		.uav_address           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_waitrequest        (sequencer_phy_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_begintransfer      (),                                                                                      //              (terminated)
		.av_beginbursttransfer (),                                                                                      //              (terminated)
		.av_burstcount         (),                                                                                      //              (terminated)
		.av_byteenable         (),                                                                                      //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                  //              (terminated)
		.av_writebyteenable    (),                                                                                      //              (terminated)
		.av_lock               (),                                                                                      //              (terminated)
		.av_chipselect         (),                                                                                      //              (terminated)
		.av_clken              (),                                                                                      //              (terminated)
		.uav_clken             (1'b0),                                                                                  //              (terminated)
		.av_debugaccess        (),                                                                                      //              (terminated)
		.av_outputenable       ()                                                                                       //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_data_mgr_inst_avl_translator (
		.clk                   (avl_clk),                                                                                //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                         //                    reset.reset
		.uav_address           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_waitrequest        (sequencer_data_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_begintransfer      (),                                                                                       //              (terminated)
		.av_beginbursttransfer (),                                                                                       //              (terminated)
		.av_burstcount         (),                                                                                       //              (terminated)
		.av_byteenable         (),                                                                                       //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                   //              (terminated)
		.av_writebyteenable    (),                                                                                       //              (terminated)
		.av_lock               (),                                                                                       //              (terminated)
		.av_chipselect         (),                                                                                       //              (terminated)
		.av_clken              (),                                                                                       //              (terminated)
		.uav_clken             (1'b0),                                                                                   //              (terminated)
		.av_debugaccess        (),                                                                                       //              (terminated)
		.av_outputenable       ()                                                                                        //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_rw_mgr_inst_avl_translator (
		.clk                   (avl_clk),                                                                              //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                       //                    reset.reset
		.uav_address           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_waitrequest        (sequencer_rw_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_begintransfer      (),                                                                                     //              (terminated)
		.av_beginbursttransfer (),                                                                                     //              (terminated)
		.av_burstcount         (),                                                                                     //              (terminated)
		.av_byteenable         (),                                                                                     //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                 //              (terminated)
		.av_writebyteenable    (),                                                                                     //              (terminated)
		.av_lock               (),                                                                                     //              (terminated)
		.av_chipselect         (),                                                                                     //              (terminated)
		.av_clken              (),                                                                                     //              (terminated)
		.uav_clken             (1'b0),                                                                                 //              (terminated)
		.av_debugaccess        (),                                                                                     //              (terminated)
		.av_outputenable       ()                                                                                      //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (12),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_mem_s1_translator (
		.clk                   (avl_clk),                                                                     //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                              //                    reset.reset
		.uav_address           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (sequencer_mem_s1_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (sequencer_mem_s1_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_readdata           (sequencer_mem_s1_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (sequencer_mem_s1_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_byteenable         (sequencer_mem_s1_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_chipselect         (sequencer_mem_s1_translator_avalon_anti_slave_0_chipselect),                  //                         .chipselect
		.av_clken              (sequencer_mem_s1_translator_avalon_anti_slave_0_clken),                       //                         .clken
		.av_read               (),                                                                            //              (terminated)
		.av_begintransfer      (),                                                                            //              (terminated)
		.av_beginbursttransfer (),                                                                            //              (terminated)
		.av_burstcount         (),                                                                            //              (terminated)
		.av_readdatavalid      (1'b0),                                                                        //              (terminated)
		.av_waitrequest        (1'b0),                                                                        //              (terminated)
		.av_writebyteenable    (),                                                                            //              (terminated)
		.av_lock               (),                                                                            //              (terminated)
		.uav_clken             (1'b0),                                                                        //              (terminated)
		.av_debugaccess        (),                                                                            //              (terminated)
		.av_outputenable       ()                                                                             //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_scc_mgr_inst_avl_translator (
		.clk                   (avl_clk),                                                                               //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                        //                    reset.reset
		.uav_address           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_waitrequest        (sequencer_scc_mgr_inst_avl_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_begintransfer      (),                                                                                      //              (terminated)
		.av_beginbursttransfer (),                                                                                      //              (terminated)
		.av_burstcount         (),                                                                                      //              (terminated)
		.av_byteenable         (),                                                                                      //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                  //              (terminated)
		.av_writebyteenable    (),                                                                                      //              (terminated)
		.av_lock               (),                                                                                      //              (terminated)
		.av_chipselect         (),                                                                                      //              (terminated)
		.av_clken              (),                                                                                      //              (terminated)
		.uav_clken             (1'b0),                                                                                  //              (terminated)
		.av_debugaccess        (),                                                                                      //              (terminated)
		.av_outputenable       ()                                                                                       //              (terminated)
	);

	altera_merlin_slave_translator #(
		.AV_ADDRESS_W                   (13),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (20),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0)
	) sequencer_reg_file_inst_avl_translator (
		.clk                   (avl_clk),                                                                                //                      clk.clk
		.reset                 (rst_controller_reset_out_reset),                                                         //                    reset.reset
		.uav_address           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),       // avalon_universal_slave_0.address
		.uav_burstcount        (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),    //                         .burstcount
		.uav_read              (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),          //                         .read
		.uav_write             (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),         //                         .write
		.uav_waitrequest       (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),   //                         .waitrequest
		.uav_readdatavalid     (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid), //                         .readdatavalid
		.uav_byteenable        (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),    //                         .byteenable
		.uav_readdata          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),      //                         .readdata
		.uav_writedata         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),     //                         .writedata
		.uav_lock              (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),          //                         .lock
		.uav_debugaccess       (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),   //                         .debugaccess
		.av_address            (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_address),                     //      avalon_anti_slave_0.address
		.av_write              (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_write),                       //                         .write
		.av_read               (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_read),                        //                         .read
		.av_readdata           (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_readdata),                    //                         .readdata
		.av_writedata          (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_writedata),                   //                         .writedata
		.av_byteenable         (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_byteenable),                  //                         .byteenable
		.av_waitrequest        (sequencer_reg_file_inst_avl_translator_avalon_anti_slave_0_waitrequest),                 //                         .waitrequest
		.av_begintransfer      (),                                                                                       //              (terminated)
		.av_beginbursttransfer (),                                                                                       //              (terminated)
		.av_burstcount         (),                                                                                       //              (terminated)
		.av_readdatavalid      (1'b0),                                                                                   //              (terminated)
		.av_writebyteenable    (),                                                                                       //              (terminated)
		.av_lock               (),                                                                                       //              (terminated)
		.av_chipselect         (),                                                                                       //              (terminated)
		.av_clken              (),                                                                                       //              (terminated)
		.uav_clken             (1'b0),                                                                                   //              (terminated)
		.av_debugaccess        (),                                                                                       //              (terminated)
		.av_outputenable       ()                                                                                        //              (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (67),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (75),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk),                                                                                          //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                   //       clk_reset.reset
		.m0_address              (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_src5_ready),                                                                        //              cp.ready
		.cp_valid                (cmd_xbar_demux_src5_valid),                                                                        //                .valid
		.cp_data                 (cmd_xbar_demux_src5_data),                                                                         //                .data
		.cp_startofpacket        (cmd_xbar_demux_src5_startofpacket),                                                                //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_src5_endofpacket),                                                                  //                .endofpacket
		.cp_channel              (cmd_xbar_demux_src5_channel),                                                                      //                .channel
		.rf_sink_ready           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (76),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk),                                                                                          //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                   // clk_reset.reset
		.in_data           (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                            // (terminated)
		.csr_read          (1'b0),                                                                                             // (terminated)
		.csr_write         (1'b0),                                                                                             // (terminated)
		.csr_readdata      (),                                                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                             // (terminated)
		.almost_full_data  (),                                                                                                 // (terminated)
		.almost_empty_data (),                                                                                                 // (terminated)
		.in_empty          (1'b0),                                                                                             // (terminated)
		.out_empty         (),                                                                                                 // (terminated)
		.in_error          (1'b0),                                                                                             // (terminated)
		.out_error         (),                                                                                                 // (terminated)
		.in_channel        (1'b0),                                                                                             // (terminated)
		.out_channel       ()                                                                                                  // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (67),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (75),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk),                                                                                         //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                  //       clk_reset.reset
		.m0_address              (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_src0_ready),                                                                       //              cp.ready
		.cp_valid                (cmd_xbar_demux_src0_valid),                                                                       //                .valid
		.cp_data                 (cmd_xbar_demux_src0_data),                                                                        //                .data
		.cp_startofpacket        (cmd_xbar_demux_src0_startofpacket),                                                               //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_src0_endofpacket),                                                                 //                .endofpacket
		.cp_channel              (cmd_xbar_demux_src0_channel),                                                                     //                .channel
		.rf_sink_ready           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (76),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk),                                                                                         //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                  // clk_reset.reset
		.in_data           (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                           // (terminated)
		.csr_read          (1'b0),                                                                                            // (terminated)
		.csr_write         (1'b0),                                                                                            // (terminated)
		.csr_readdata      (),                                                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                            // (terminated)
		.almost_full_data  (),                                                                                                // (terminated)
		.almost_empty_data (),                                                                                                // (terminated)
		.in_empty          (1'b0),                                                                                            // (terminated)
		.out_empty         (),                                                                                                // (terminated)
		.in_error          (1'b0),                                                                                            // (terminated)
		.out_error         (),                                                                                                // (terminated)
		.in_channel        (1'b0),                                                                                            // (terminated)
		.out_channel       ()                                                                                                 // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (67),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (75),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk),                                                                                          //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                   //       clk_reset.reset
		.m0_address              (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_src1_ready),                                                                        //              cp.ready
		.cp_valid                (cmd_xbar_demux_src1_valid),                                                                        //                .valid
		.cp_data                 (cmd_xbar_demux_src1_data),                                                                         //                .data
		.cp_startofpacket        (cmd_xbar_demux_src1_startofpacket),                                                                //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_src1_endofpacket),                                                                  //                .endofpacket
		.cp_channel              (cmd_xbar_demux_src1_channel),                                                                      //                .channel
		.rf_sink_ready           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (76),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk),                                                                                          //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                   // clk_reset.reset
		.in_data           (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                            // (terminated)
		.csr_read          (1'b0),                                                                                             // (terminated)
		.csr_write         (1'b0),                                                                                             // (terminated)
		.csr_readdata      (),                                                                                                 // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                             // (terminated)
		.almost_full_data  (),                                                                                                 // (terminated)
		.almost_empty_data (),                                                                                                 // (terminated)
		.in_empty          (1'b0),                                                                                             // (terminated)
		.out_empty         (),                                                                                                 // (terminated)
		.in_error          (1'b0),                                                                                             // (terminated)
		.out_error         (),                                                                                                 // (terminated)
		.in_channel        (1'b0),                                                                                             // (terminated)
		.out_channel       ()                                                                                                  // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (67),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (75),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) sequencer_mem_s1_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk),                                                                               //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                        //       clk_reset.reset
		.m0_address              (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_mux_003_src_ready),                                                            //              cp.ready
		.cp_valid                (cmd_xbar_mux_003_src_valid),                                                            //                .valid
		.cp_data                 (cmd_xbar_mux_003_src_data),                                                             //                .data
		.cp_startofpacket        (cmd_xbar_mux_003_src_startofpacket),                                                    //                .startofpacket
		.cp_endofpacket          (cmd_xbar_mux_003_src_endofpacket),                                                      //                .endofpacket
		.cp_channel              (cmd_xbar_mux_003_src_channel),                                                          //                .channel
		.rf_sink_ready           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (76),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk),                                                                               //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                        // clk_reset.reset
		.in_data           (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                 // (terminated)
		.csr_read          (1'b0),                                                                                  // (terminated)
		.csr_write         (1'b0),                                                                                  // (terminated)
		.csr_readdata      (),                                                                                      // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                  // (terminated)
		.almost_full_data  (),                                                                                      // (terminated)
		.almost_empty_data (),                                                                                      // (terminated)
		.in_empty          (1'b0),                                                                                  // (terminated)
		.out_empty         (),                                                                                      // (terminated)
		.in_error          (1'b0),                                                                                  // (terminated)
		.out_error         (),                                                                                      // (terminated)
		.in_channel        (1'b0),                                                                                  // (terminated)
		.out_channel       ()                                                                                       // (terminated)
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (67),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (75),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk),                                                                                         //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                  //       clk_reset.reset
		.m0_address              (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_src4_ready),                                                                       //              cp.ready
		.cp_valid                (cmd_xbar_demux_src4_valid),                                                                       //                .valid
		.cp_data                 (cmd_xbar_demux_src4_data),                                                                        //                .data
		.cp_startofpacket        (cmd_xbar_demux_src4_startofpacket),                                                               //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_src4_endofpacket),                                                                 //                .endofpacket
		.cp_channel              (cmd_xbar_demux_src4_channel),                                                                     //                .channel
		.rf_sink_ready           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (76),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk),                                                                                         //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                  // clk_reset.reset
		.in_data           (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                           // (terminated)
		.csr_read          (1'b0),                                                                                            // (terminated)
		.csr_write         (1'b0),                                                                                            // (terminated)
		.csr_readdata      (),                                                                                                // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                            // (terminated)
		.almost_full_data  (),                                                                                                // (terminated)
		.almost_empty_data (),                                                                                                // (terminated)
		.in_empty          (1'b0),                                                                                            // (terminated)
		.out_empty         (),                                                                                                // (terminated)
		.in_error          (1'b0),                                                                                            // (terminated)
		.out_error         (),                                                                                                // (terminated)
		.in_channel        (1'b0),                                                                                            // (terminated)
		.out_channel       ()                                                                                                 // (terminated)
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.PKT_BEGIN_BURST           (67),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.ST_DATA_W                 (75),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (7)
	) cpu_inst_data_master_translator_avalon_universal_master_0_agent (
		.clk              (avl_clk),                                                                          //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                   // clk_reset.reset
		.av_address       (cpu_inst_data_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (cpu_inst_data_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (cpu_inst_data_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (cpu_inst_data_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (cpu_inst_data_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (cpu_inst_data_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (cpu_inst_data_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (cpu_inst_data_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (rsp_xbar_mux_src_valid),                                                           //        rp.valid
		.rp_data          (rsp_xbar_mux_src_data),                                                            //          .data
		.rp_channel       (rsp_xbar_mux_src_channel),                                                         //          .channel
		.rp_startofpacket (rsp_xbar_mux_src_startofpacket),                                                   //          .startofpacket
		.rp_endofpacket   (rsp_xbar_mux_src_endofpacket),                                                     //          .endofpacket
		.rp_ready         (rsp_xbar_mux_src_ready)                                                            //          .ready
	);

	altera_merlin_master_agent #(
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.PKT_BEGIN_BURST           (67),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.ST_DATA_W                 (75),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (1),
		.BURSTWRAP_VALUE           (3)
	) cpu_inst_instruction_master_translator_avalon_universal_master_0_agent (
		.clk              (avl_clk),                                                                                 //       clk.clk
		.reset            (rst_controller_reset_out_reset),                                                          // clk_reset.reset
		.av_address       (cpu_inst_instruction_master_translator_avalon_universal_master_0_address),                //        av.address
		.av_write         (cpu_inst_instruction_master_translator_avalon_universal_master_0_write),                  //          .write
		.av_read          (cpu_inst_instruction_master_translator_avalon_universal_master_0_read),                   //          .read
		.av_writedata     (cpu_inst_instruction_master_translator_avalon_universal_master_0_writedata),              //          .writedata
		.av_readdata      (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdata),               //          .readdata
		.av_waitrequest   (cpu_inst_instruction_master_translator_avalon_universal_master_0_waitrequest),            //          .waitrequest
		.av_readdatavalid (cpu_inst_instruction_master_translator_avalon_universal_master_0_readdatavalid),          //          .readdatavalid
		.av_byteenable    (cpu_inst_instruction_master_translator_avalon_universal_master_0_byteenable),             //          .byteenable
		.av_burstcount    (cpu_inst_instruction_master_translator_avalon_universal_master_0_burstcount),             //          .burstcount
		.av_debugaccess   (cpu_inst_instruction_master_translator_avalon_universal_master_0_debugaccess),            //          .debugaccess
		.av_lock          (cpu_inst_instruction_master_translator_avalon_universal_master_0_lock),                   //          .lock
		.cp_valid         (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //        cp.valid
		.cp_data          (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.cp_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.cp_endofpacket   (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.cp_ready         (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //          .ready
		.rp_valid         (rsp_xbar_demux_003_src1_valid),                                                           //        rp.valid
		.rp_data          (rsp_xbar_demux_003_src1_data),                                                            //          .data
		.rp_channel       (rsp_xbar_demux_003_src1_channel),                                                         //          .channel
		.rp_startofpacket (rsp_xbar_demux_003_src1_startofpacket),                                                   //          .startofpacket
		.rp_endofpacket   (rsp_xbar_demux_003_src1_endofpacket),                                                     //          .endofpacket
		.rp_ready         (rsp_xbar_demux_003_src1_ready)                                                            //          .ready
	);

	altera_merlin_slave_agent #(
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BEGIN_BURST           (67),
		.PKT_SYMBOL_W              (8),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_ADDR_H                (55),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (56),
		.PKT_TRANS_POSTED          (57),
		.PKT_TRANS_WRITE           (58),
		.PKT_TRANS_READ            (59),
		.PKT_TRANS_LOCK            (60),
		.PKT_SRC_ID_H              (70),
		.PKT_SRC_ID_L              (68),
		.PKT_DEST_ID_H             (73),
		.PKT_DEST_ID_L             (71),
		.PKT_BURSTWRAP_H           (66),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_PROTECTION_H          (74),
		.PKT_PROTECTION_L          (74),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (75),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.PREVENT_FIFO_OVERFLOW     (1)
	) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent (
		.clk                     (avl_clk),                                                                                        //             clk.clk
		.reset                   (rst_controller_reset_out_reset),                                                                 //       clk_reset.reset
		.m0_address              (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_address),                 //              m0.address
		.m0_burstcount           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_burstcount),              //                .burstcount
		.m0_byteenable           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_byteenable),              //                .byteenable
		.m0_debugaccess          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_debugaccess),             //                .debugaccess
		.m0_lock                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_lock),                    //                .lock
		.m0_readdata             (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdata),                //                .readdata
		.m0_readdatavalid        (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_readdatavalid),           //                .readdatavalid
		.m0_read                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_read),                    //                .read
		.m0_waitrequest          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_waitrequest),             //                .waitrequest
		.m0_writedata            (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_writedata),               //                .writedata
		.m0_write                (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_m0_write),                   //                .write
		.rp_endofpacket          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),             //              rp.endofpacket
		.rp_ready                (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),                   //                .ready
		.rp_valid                (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),                   //                .valid
		.rp_data                 (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),                    //                .data
		.rp_startofpacket        (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket),           //                .startofpacket
		.cp_ready                (cmd_xbar_demux_src2_ready),                                                                      //              cp.ready
		.cp_valid                (cmd_xbar_demux_src2_valid),                                                                      //                .valid
		.cp_data                 (cmd_xbar_demux_src2_data),                                                                       //                .data
		.cp_startofpacket        (cmd_xbar_demux_src2_startofpacket),                                                              //                .startofpacket
		.cp_endofpacket          (cmd_xbar_demux_src2_endofpacket),                                                                //                .endofpacket
		.cp_channel              (cmd_xbar_demux_src2_channel),                                                                    //                .channel
		.rf_sink_ready           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //         rf_sink.ready
		.rf_sink_valid           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //                .valid
		.rf_sink_startofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //                .startofpacket
		.rf_sink_endofpacket     (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //                .endofpacket
		.rf_sink_data            (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //                .data
		.rf_source_ready         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //       rf_source.ready
		.rf_source_valid         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //                .valid
		.rf_source_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //                .startofpacket
		.rf_source_endofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //                .endofpacket
		.rf_source_data          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //                .data
		.rdata_fifo_sink_ready   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       // rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_sink_data    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data),        //                .data
		.rdata_fifo_src_ready    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready),       //  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid),       //                .valid
		.rdata_fifo_src_data     (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data)         //                .data
	);

	altera_avalon_sc_fifo #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (76),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0)
	) sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo (
		.clk               (avl_clk),                                                                                        //       clk.clk
		.reset             (rst_controller_reset_out_reset),                                                                 // clk_reset.reset
		.in_data           (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_data),             //        in.data
		.in_valid          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_valid),            //          .valid
		.in_ready          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_ready),            //          .ready
		.in_startofpacket  (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_startofpacket),    //          .startofpacket
		.in_endofpacket    (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rf_source_endofpacket),      //          .endofpacket
		.out_data          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data),          //       out.data
		.out_valid         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid),         //          .valid
		.out_ready         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready),         //          .ready
		.out_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), //          .startofpacket
		.out_endofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket),   //          .endofpacket
		.csr_address       (2'b00),                                                                                          // (terminated)
		.csr_read          (1'b0),                                                                                           // (terminated)
		.csr_write         (1'b0),                                                                                           // (terminated)
		.csr_readdata      (),                                                                                               // (terminated)
		.csr_writedata     (32'b00000000000000000000000000000000),                                                           // (terminated)
		.almost_full_data  (),                                                                                               // (terminated)
		.almost_empty_data (),                                                                                               // (terminated)
		.in_empty          (1'b0),                                                                                           // (terminated)
		.out_empty         (),                                                                                               // (terminated)
		.in_error          (1'b0),                                                                                           // (terminated)
		.out_error         (),                                                                                               // (terminated)
		.in_channel        (1'b0),                                                                                           // (terminated)
		.out_channel       ()                                                                                                // (terminated)
	);

	TR4_QSYS_uniphy_ddr3_s0_addr_router addr_router (
		.sink_ready         (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_inst_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                          //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                   // clk_reset.reset
		.src_ready          (addr_router_src_ready),                                                            //       src.ready
		.src_valid          (addr_router_src_valid),                                                            //          .valid
		.src_data           (addr_router_src_data),                                                             //          .data
		.src_channel        (addr_router_src_channel),                                                          //          .channel
		.src_startofpacket  (addr_router_src_startofpacket),                                                    //          .startofpacket
		.src_endofpacket    (addr_router_src_endofpacket)                                                       //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_addr_router_001 addr_router_001 (
		.sink_ready         (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_ready),         //      sink.ready
		.sink_valid         (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_valid),         //          .valid
		.sink_data          (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_data),          //          .data
		.sink_startofpacket (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), //          .startofpacket
		.sink_endofpacket   (cpu_inst_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                                 //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                          // clk_reset.reset
		.src_ready          (addr_router_001_src_ready),                                                               //       src.ready
		.src_valid          (addr_router_001_src_valid),                                                               //          .valid
		.src_data           (addr_router_001_src_data),                                                                //          .data
		.src_channel        (addr_router_001_src_channel),                                                             //          .channel
		.src_startofpacket  (addr_router_001_src_startofpacket),                                                       //          .startofpacket
		.src_endofpacket    (addr_router_001_src_endofpacket)                                                          //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_id_router id_router (
		.sink_ready         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_phy_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                        // clk_reset.reset
		.src_ready          (id_router_src_ready),                                                                   //       src.ready
		.src_valid          (id_router_src_valid),                                                                   //          .valid
		.src_data           (id_router_src_data),                                                                    //          .data
		.src_channel        (id_router_src_channel),                                                                 //          .channel
		.src_startofpacket  (id_router_src_startofpacket),                                                           //          .startofpacket
		.src_endofpacket    (id_router_src_endofpacket)                                                              //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_id_router id_router_001 (
		.sink_ready         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_data_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                                //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                         // clk_reset.reset
		.src_ready          (id_router_001_src_ready),                                                                //       src.ready
		.src_valid          (id_router_001_src_valid),                                                                //          .valid
		.src_data           (id_router_001_src_data),                                                                 //          .data
		.src_channel        (id_router_001_src_channel),                                                              //          .channel
		.src_startofpacket  (id_router_001_src_startofpacket),                                                        //          .startofpacket
		.src_endofpacket    (id_router_001_src_endofpacket)                                                           //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_id_router id_router_002 (
		.sink_ready         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_rw_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                              //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                       // clk_reset.reset
		.src_ready          (id_router_002_src_ready),                                                              //       src.ready
		.src_valid          (id_router_002_src_valid),                                                              //          .valid
		.src_data           (id_router_002_src_data),                                                               //          .data
		.src_channel        (id_router_002_src_channel),                                                            //          .channel
		.src_startofpacket  (id_router_002_src_startofpacket),                                                      //          .startofpacket
		.src_endofpacket    (id_router_002_src_endofpacket)                                                         //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_id_router_003 id_router_003 (
		.sink_ready         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_mem_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                     //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                              // clk_reset.reset
		.src_ready          (id_router_003_src_ready),                                                     //       src.ready
		.src_valid          (id_router_003_src_valid),                                                     //          .valid
		.src_data           (id_router_003_src_data),                                                      //          .data
		.src_channel        (id_router_003_src_channel),                                                   //          .channel
		.src_startofpacket  (id_router_003_src_startofpacket),                                             //          .startofpacket
		.src_endofpacket    (id_router_003_src_endofpacket)                                                //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_id_router id_router_004 (
		.sink_ready         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_scc_mgr_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                        // clk_reset.reset
		.src_ready          (id_router_004_src_ready),                                                               //       src.ready
		.src_valid          (id_router_004_src_valid),                                                               //          .valid
		.src_data           (id_router_004_src_data),                                                                //          .data
		.src_channel        (id_router_004_src_channel),                                                             //          .channel
		.src_startofpacket  (id_router_004_src_startofpacket),                                                       //          .startofpacket
		.src_endofpacket    (id_router_004_src_endofpacket)                                                          //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_id_router id_router_005 (
		.sink_ready         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_ready),         //      sink.ready
		.sink_valid         (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_valid),         //          .valid
		.sink_data          (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_data),          //          .data
		.sink_startofpacket (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_startofpacket), //          .startofpacket
		.sink_endofpacket   (sequencer_reg_file_inst_avl_translator_avalon_universal_slave_0_agent_rp_endofpacket),   //          .endofpacket
		.clk                (avl_clk),                                                                                //       clk.clk
		.reset              (rst_controller_reset_out_reset),                                                         // clk_reset.reset
		.src_ready          (id_router_005_src_ready),                                                                //       src.ready
		.src_valid          (id_router_005_src_valid),                                                                //          .valid
		.src_data           (id_router_005_src_data),                                                                 //          .data
		.src_channel        (id_router_005_src_channel),                                                              //          .channel
		.src_startofpacket  (id_router_005_src_startofpacket),                                                        //          .startofpacket
		.src_endofpacket    (id_router_005_src_endofpacket)                                                           //          .endofpacket
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~avl_reset_n),                   // reset_in0.reset
		.clk        (avl_clk),                        //       clk.clk
		.reset_out  (rst_controller_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                           // (terminated)
		.reset_in2  (1'b0),                           // (terminated)
		.reset_in3  (1'b0),                           // (terminated)
		.reset_in4  (1'b0),                           // (terminated)
		.reset_in5  (1'b0),                           // (terminated)
		.reset_in6  (1'b0),                           // (terminated)
		.reset_in7  (1'b0),                           // (terminated)
		.reset_in8  (1'b0),                           // (terminated)
		.reset_in9  (1'b0),                           // (terminated)
		.reset_in10 (1'b0),                           // (terminated)
		.reset_in11 (1'b0),                           // (terminated)
		.reset_in12 (1'b0),                           // (terminated)
		.reset_in13 (1'b0),                           // (terminated)
		.reset_in14 (1'b0),                           // (terminated)
		.reset_in15 (1'b0)                            // (terminated)
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux cmd_xbar_demux (
		.clk                (avl_clk),                           //       clk.clk
		.reset              (rst_controller_reset_out_reset),    // clk_reset.reset
		.sink_ready         (addr_router_src_ready),             //      sink.ready
		.sink_channel       (addr_router_src_channel),           //          .channel
		.sink_data          (addr_router_src_data),              //          .data
		.sink_startofpacket (addr_router_src_startofpacket),     //          .startofpacket
		.sink_endofpacket   (addr_router_src_endofpacket),       //          .endofpacket
		.sink_valid         (addr_router_src_valid),             //          .valid
		.src0_ready         (cmd_xbar_demux_src0_ready),         //      src0.ready
		.src0_valid         (cmd_xbar_demux_src0_valid),         //          .valid
		.src0_data          (cmd_xbar_demux_src0_data),          //          .data
		.src0_channel       (cmd_xbar_demux_src0_channel),       //          .channel
		.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_src0_endofpacket),   //          .endofpacket
		.src1_ready         (cmd_xbar_demux_src1_ready),         //      src1.ready
		.src1_valid         (cmd_xbar_demux_src1_valid),         //          .valid
		.src1_data          (cmd_xbar_demux_src1_data),          //          .data
		.src1_channel       (cmd_xbar_demux_src1_channel),       //          .channel
		.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), //          .startofpacket
		.src1_endofpacket   (cmd_xbar_demux_src1_endofpacket),   //          .endofpacket
		.src2_ready         (cmd_xbar_demux_src2_ready),         //      src2.ready
		.src2_valid         (cmd_xbar_demux_src2_valid),         //          .valid
		.src2_data          (cmd_xbar_demux_src2_data),          //          .data
		.src2_channel       (cmd_xbar_demux_src2_channel),       //          .channel
		.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), //          .startofpacket
		.src2_endofpacket   (cmd_xbar_demux_src2_endofpacket),   //          .endofpacket
		.src3_ready         (cmd_xbar_demux_src3_ready),         //      src3.ready
		.src3_valid         (cmd_xbar_demux_src3_valid),         //          .valid
		.src3_data          (cmd_xbar_demux_src3_data),          //          .data
		.src3_channel       (cmd_xbar_demux_src3_channel),       //          .channel
		.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), //          .startofpacket
		.src3_endofpacket   (cmd_xbar_demux_src3_endofpacket),   //          .endofpacket
		.src4_ready         (cmd_xbar_demux_src4_ready),         //      src4.ready
		.src4_valid         (cmd_xbar_demux_src4_valid),         //          .valid
		.src4_data          (cmd_xbar_demux_src4_data),          //          .data
		.src4_channel       (cmd_xbar_demux_src4_channel),       //          .channel
		.src4_startofpacket (cmd_xbar_demux_src4_startofpacket), //          .startofpacket
		.src4_endofpacket   (cmd_xbar_demux_src4_endofpacket),   //          .endofpacket
		.src5_ready         (cmd_xbar_demux_src5_ready),         //      src5.ready
		.src5_valid         (cmd_xbar_demux_src5_valid),         //          .valid
		.src5_data          (cmd_xbar_demux_src5_data),          //          .data
		.src5_channel       (cmd_xbar_demux_src5_channel),       //          .channel
		.src5_startofpacket (cmd_xbar_demux_src5_startofpacket), //          .startofpacket
		.src5_endofpacket   (cmd_xbar_demux_src5_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux_001 cmd_xbar_demux_001 (
		.clk                (avl_clk),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (addr_router_001_src_ready),             //      sink.ready
		.sink_channel       (addr_router_001_src_channel),           //          .channel
		.sink_data          (addr_router_001_src_data),              //          .data
		.sink_startofpacket (addr_router_001_src_startofpacket),     //          .startofpacket
		.sink_endofpacket   (addr_router_001_src_endofpacket),       //          .endofpacket
		.sink_valid         (addr_router_001_src_valid),             //          .valid
		.src0_ready         (cmd_xbar_demux_001_src0_ready),         //      src0.ready
		.src0_valid         (cmd_xbar_demux_001_src0_valid),         //          .valid
		.src0_data          (cmd_xbar_demux_001_src0_data),          //          .data
		.src0_channel       (cmd_xbar_demux_001_src0_channel),       //          .channel
		.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_mux_003 cmd_xbar_mux_003 (
		.clk                 (avl_clk),                               //       clk.clk
		.reset               (rst_controller_reset_out_reset),        // clk_reset.reset
		.src_ready           (cmd_xbar_mux_003_src_ready),            //       src.ready
		.src_valid           (cmd_xbar_mux_003_src_valid),            //          .valid
		.src_data            (cmd_xbar_mux_003_src_data),             //          .data
		.src_channel         (cmd_xbar_mux_003_src_channel),          //          .channel
		.src_startofpacket   (cmd_xbar_mux_003_src_startofpacket),    //          .startofpacket
		.src_endofpacket     (cmd_xbar_mux_003_src_endofpacket),      //          .endofpacket
		.sink0_ready         (cmd_xbar_demux_src3_ready),             //     sink0.ready
		.sink0_valid         (cmd_xbar_demux_src3_valid),             //          .valid
		.sink0_channel       (cmd_xbar_demux_src3_channel),           //          .channel
		.sink0_data          (cmd_xbar_demux_src3_data),              //          .data
		.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (cmd_xbar_demux_src3_endofpacket),       //          .endofpacket
		.sink1_ready         (cmd_xbar_demux_001_src0_ready),         //     sink1.ready
		.sink1_valid         (cmd_xbar_demux_001_src0_valid),         //          .valid
		.sink1_channel       (cmd_xbar_demux_001_src0_channel),       //          .channel
		.sink1_data          (cmd_xbar_demux_001_src0_data),          //          .data
		.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (cmd_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux_001 rsp_xbar_demux (
		.clk                (avl_clk),                           //       clk.clk
		.reset              (rst_controller_reset_out_reset),    // clk_reset.reset
		.sink_ready         (id_router_src_ready),               //      sink.ready
		.sink_channel       (id_router_src_channel),             //          .channel
		.sink_data          (id_router_src_data),                //          .data
		.sink_startofpacket (id_router_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux_001 rsp_xbar_demux_001 (
		.clk                (avl_clk),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_001_src_ready),               //      sink.ready
		.sink_channel       (id_router_001_src_channel),             //          .channel
		.sink_data          (id_router_001_src_data),                //          .data
		.sink_startofpacket (id_router_001_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_001_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_001_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_001_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_001_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_001_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_001_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_001_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux_001 rsp_xbar_demux_002 (
		.clk                (avl_clk),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_002_src_ready),               //      sink.ready
		.sink_channel       (id_router_002_src_channel),             //          .channel
		.sink_data          (id_router_002_src_data),                //          .data
		.sink_startofpacket (id_router_002_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_002_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_002_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_002_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_002_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_002_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_002_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_002_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_rsp_xbar_demux_003 rsp_xbar_demux_003 (
		.clk                (avl_clk),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_003_src_ready),               //      sink.ready
		.sink_channel       (id_router_003_src_channel),             //          .channel
		.sink_data          (id_router_003_src_data),                //          .data
		.sink_startofpacket (id_router_003_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_003_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_003_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_003_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_003_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_003_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_003_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_003_src0_endofpacket),   //          .endofpacket
		.src1_ready         (rsp_xbar_demux_003_src1_ready),         //      src1.ready
		.src1_valid         (rsp_xbar_demux_003_src1_valid),         //          .valid
		.src1_data          (rsp_xbar_demux_003_src1_data),          //          .data
		.src1_channel       (rsp_xbar_demux_003_src1_channel),       //          .channel
		.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), //          .startofpacket
		.src1_endofpacket   (rsp_xbar_demux_003_src1_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux_001 rsp_xbar_demux_004 (
		.clk                (avl_clk),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_004_src_ready),               //      sink.ready
		.sink_channel       (id_router_004_src_channel),             //          .channel
		.sink_data          (id_router_004_src_data),                //          .data
		.sink_startofpacket (id_router_004_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_004_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_004_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_004_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_004_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_004_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_004_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_004_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux_001 rsp_xbar_demux_005 (
		.clk                (avl_clk),                               //       clk.clk
		.reset              (rst_controller_reset_out_reset),        // clk_reset.reset
		.sink_ready         (id_router_005_src_ready),               //      sink.ready
		.sink_channel       (id_router_005_src_channel),             //          .channel
		.sink_data          (id_router_005_src_data),                //          .data
		.sink_startofpacket (id_router_005_src_startofpacket),       //          .startofpacket
		.sink_endofpacket   (id_router_005_src_endofpacket),         //          .endofpacket
		.sink_valid         (id_router_005_src_valid),               //          .valid
		.src0_ready         (rsp_xbar_demux_005_src0_ready),         //      src0.ready
		.src0_valid         (rsp_xbar_demux_005_src0_valid),         //          .valid
		.src0_data          (rsp_xbar_demux_005_src0_data),          //          .data
		.src0_channel       (rsp_xbar_demux_005_src0_channel),       //          .channel
		.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), //          .startofpacket
		.src0_endofpacket   (rsp_xbar_demux_005_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_rsp_xbar_mux rsp_xbar_mux (
		.clk                 (avl_clk),                               //       clk.clk
		.reset               (rst_controller_reset_out_reset),        // clk_reset.reset
		.src_ready           (rsp_xbar_mux_src_ready),                //       src.ready
		.src_valid           (rsp_xbar_mux_src_valid),                //          .valid
		.src_data            (rsp_xbar_mux_src_data),                 //          .data
		.src_channel         (rsp_xbar_mux_src_channel),              //          .channel
		.src_startofpacket   (rsp_xbar_mux_src_startofpacket),        //          .startofpacket
		.src_endofpacket     (rsp_xbar_mux_src_endofpacket),          //          .endofpacket
		.sink0_ready         (rsp_xbar_demux_src0_ready),             //     sink0.ready
		.sink0_valid         (rsp_xbar_demux_src0_valid),             //          .valid
		.sink0_channel       (rsp_xbar_demux_src0_channel),           //          .channel
		.sink0_data          (rsp_xbar_demux_src0_data),              //          .data
		.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket),     //          .startofpacket
		.sink0_endofpacket   (rsp_xbar_demux_src0_endofpacket),       //          .endofpacket
		.sink1_ready         (rsp_xbar_demux_001_src0_ready),         //     sink1.ready
		.sink1_valid         (rsp_xbar_demux_001_src0_valid),         //          .valid
		.sink1_channel       (rsp_xbar_demux_001_src0_channel),       //          .channel
		.sink1_data          (rsp_xbar_demux_001_src0_data),          //          .data
		.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), //          .startofpacket
		.sink1_endofpacket   (rsp_xbar_demux_001_src0_endofpacket),   //          .endofpacket
		.sink2_ready         (rsp_xbar_demux_002_src0_ready),         //     sink2.ready
		.sink2_valid         (rsp_xbar_demux_002_src0_valid),         //          .valid
		.sink2_channel       (rsp_xbar_demux_002_src0_channel),       //          .channel
		.sink2_data          (rsp_xbar_demux_002_src0_data),          //          .data
		.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), //          .startofpacket
		.sink2_endofpacket   (rsp_xbar_demux_002_src0_endofpacket),   //          .endofpacket
		.sink3_ready         (rsp_xbar_demux_003_src0_ready),         //     sink3.ready
		.sink3_valid         (rsp_xbar_demux_003_src0_valid),         //          .valid
		.sink3_channel       (rsp_xbar_demux_003_src0_channel),       //          .channel
		.sink3_data          (rsp_xbar_demux_003_src0_data),          //          .data
		.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), //          .startofpacket
		.sink3_endofpacket   (rsp_xbar_demux_003_src0_endofpacket),   //          .endofpacket
		.sink4_ready         (rsp_xbar_demux_004_src0_ready),         //     sink4.ready
		.sink4_valid         (rsp_xbar_demux_004_src0_valid),         //          .valid
		.sink4_channel       (rsp_xbar_demux_004_src0_channel),       //          .channel
		.sink4_data          (rsp_xbar_demux_004_src0_data),          //          .data
		.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), //          .startofpacket
		.sink4_endofpacket   (rsp_xbar_demux_004_src0_endofpacket),   //          .endofpacket
		.sink5_ready         (rsp_xbar_demux_005_src0_ready),         //     sink5.ready
		.sink5_valid         (rsp_xbar_demux_005_src0_valid),         //          .valid
		.sink5_channel       (rsp_xbar_demux_005_src0_channel),       //          .channel
		.sink5_data          (rsp_xbar_demux_005_src0_data),          //          .data
		.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), //          .startofpacket
		.sink5_endofpacket   (rsp_xbar_demux_005_src0_endofpacket)    //          .endofpacket
	);

	TR4_QSYS_uniphy_ddr3_s0_irq_mapper irq_mapper (
		.clk        (avl_clk),                        //       clk.clk
		.reset      (rst_controller_reset_out_reset), // clk_reset.reset
		.sender_irq (cpu_inst_d_irq_irq)              //    sender.irq
	);

endmodule
