<?xml version="1.0" encoding="UTF-8"?>
<preferences>
 <debug showDebugMenu="0" />
 <systemtable filter="Default">
  <columns>
   <connections preferredWidth="30" />
   <irq preferredWidth="34" />
   <name preferredWidth="315" />
   <inputclock preferredWidth="240" />
  </columns>
 </systemtable>
 <clocktable>
  <columns>
   <clockname preferredWidth="547" />
   <clocksource preferredWidth="546" />
   <frequency preferredWidth="527" />
  </columns>
 </clocktable>
 <window width="1928" height="1054" x="-4" y="-4" />
 <library expandedCategories="Project,Library" />
 <hdlexample language="VERILOG" />
</preferences>
