// --------------------------------------------------------------------
// Copyright (c) 2011 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
//
// Major Functions:	TR4 DDR3 1G
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V1.0 :| BEN               :| 12/15/11  :| Initial Revision
// --------------------------------------------------------------------


module Tr4_ETHERNET_HSMC_Card(

							///////////BUTTON/////////////
							BUTTON,

							/////////FAN/////////
							FAN_CTRL,

							/////////FLASH/////////
							FLASH_ADV_n,
							FLASH_CE_n,
							FLASH_CLK,
							FLASH_RDY_BSY_n,
							FLASH_RESET_n,
							FLASH_WP_n,

							/////////FSM/////////
							FSM_A,
							FSM_D,
							FSM_OE_n,
							FSM_WE_n,

							/////////HSMA/////////
							HSMA_CLKIN0,
							HSMA_CLKIN_n1,
							HSMA_CLKIN_n2,
							HSMA_CLKIN_p1,
							HSMA_CLKIN_p2,
							HSMA_D,
							HSMA_OUT0,
							HSMA_OUT_n1,
							HSMA_OUT_n2,
							HSMA_OUT_p1,
							HSMA_OUT_p2,
							HSMA_RX_n,
							HSMA_RX_p,
							HSMA_TX_n,
							HSMA_TX_p,

							/////////HSMB/////////
							HSMB_CLKIN0,
							HSMB_CLKIN_n1,
							HSMB_CLKIN_n2,
							HSMB_CLKIN_p1,
							HSMB_CLKIN_p2,
							HSMB_D,
							HSMB_OUT0,
							HSMB_OUT_n1,
							HSMB_OUT_n2,
							HSMB_OUT_p1,
							HSMB_OUT_p2,
							HSMB_RX_n,
							HSMB_RX_p,
							HSMB_SCL,
							HSMB_SDA,
							HSMB_TX_n,
							HSMB_TX_p,

							/////////HSMC/////////
							HSMC_CLKIN0,
							HSMC_CLKIN_n1,
							HSMC_CLKIN_n2,
							HSMC_CLKIN_p1,
							HSMC_CLKIN_p2,
							HSMC_CLKOUT_n1,
							HSMC_CLKOUT_p1,
							HSMC_D,
							HSMC_OUT0,
							HSMC_OUT_n2,
							HSMC_OUT_p2,
							HSMC_RX_n,
							HSMC_RX_p,
							HSMC_TX_n,
							HSMC_TX_p,

							/////////HSMD/////////
							HSMD_CLKIN0,
							HSMD_CLKIN_n1,
							HSMD_CLKIN_n2,
							HSMD_CLKIN_p1,
							HSMD_CLKIN_p2,
							HSMD_CLKOUT_n1,
							HSMD_CLKOUT_p1,
							HSMD_D,
							HSMD_OUT0,
							HSMD_OUT_n2,
							HSMD_OUT_p2,
							HSMD_RX_n,
							HSMD_RX_p,
							HSMD_SCL,
							HSMD_SDA,
							HSMD_TX_n,
							HSMD_TX_p,
							/////////HSME/////////
							HSME_CLKIN0,
							HSME_CLKIN_n1,
							HSME_CLKIN_n2,
							HSME_CLKIN_p1,
							HSME_CLKIN_p2,
							HSME_CLKOUT_n1,
							HSME_CLKOUT_p1,
							HSME_D,
							HSME_OUT0,
							HSME_OUT_n2,
							HSME_OUT_p2,
							HSME_RX_n,
							HSME_RX_p,
							HSME_TX_n,
							HSME_TX_p,

							/////////HSMF/////////
//							HSMF_CLKIN0,
//							HSMF_CLKIN_n1,
//							HSMF_CLKIN_n2,
//							HSMF_CLKIN_p1,
//							HSMF_CLKIN_p2,
//							HSMF_CLKOUT_n1,
//							HSMF_CLKOUT_n2,
//							HSMF_CLKOUT_p1,
//							HSMF_CLKOUT_p2,
//							HSMF_D,
//							HSMF_OUT0,
//							HSMF_RX_n,
//							HSMF_RX_p,
//							HSMF_TX_n,
//							HSMF_TX_p,
	//////////// HSMC-F, HSMC-F connect to NET - 10/100/1000 Ethernet //////////
							NET0_GTX_CLK,
							NET0_INTN,
							NET0_LINK1000,
							NET0_MDC,
							NET0_MDIO,
							NET0_RESETN,
							NET0_RX_CLK,
							NET0_RX_COL,
							NET0_RX_CRS,
							NET0_RX_D,
							NET0_RX_DV,
							NET0_RX_ER,
							NET0_S_CLKN,
							NET0_S_CLKP,
							NET0_S_RX_N,
							NET0_S_RX_P,
							NET0_S_TX_N,
							NET0_S_TX_P,
							NET0_TX_CLK,
							NET0_TX_D,
							NET0_TX_EN,
							NET0_TX_ER,
							NET1_GTX_CLK,
							NET1_INTN,
							NET1_LINK1000,
							NET1_MDC,
							NET1_MDIO,
							NET1_RESETN,
							NET1_RX_CLK,
							NET1_RX_COL,
							NET1_RX_CRS,
							NET1_RX_D,
							NET1_RX_DV,
							NET1_RX_ER,
							NET1_S_CLKN,
							NET1_S_CLKP,
							NET1_S_RX_N,
							NET1_S_RX_P,
							NET1_S_TX_N,
							NET1_S_TX_P,
							NET1_TX_CLK,
							NET1_TX_D,
							NET1_TX_EN,
							NET1_TX_ER,
							
							/////////LED/////////
							LED,

							/////////LOOP/////////
							LOOP_CLKIN0,
							LOOP_CLKOUT0,
							LOOP_CLKIN1,
							LOOP_CLKOUT1,

							/////////MAX2/////////
							MAX2_CS_n,
							MAX2_I2C_SCL,
							MAX2_I2C_SDA,

							/////////mem/////////
							mem_a,
							mem_ba,
							mem_cas_n,
							mem_cke,
							mem_ck,
							mem_ck_n,
							mem_cs_n,
							mem_dm,
							mem_dq,
							mem_dqs,
							mem_dqs_n,
							mem_event_n,
							mem_odt,
							mem_ras_n,
							mem_reset_n,
							mem_scl,
							mem_sda,
							mem_we_n,

							/////////OSC/////////
							OSC_50_BANK1,
							OSC_50_BANK3,
							OSC_50_BANK4,
							OSC_50_BANK7,
							OSC_50_BANK8,

							/////////mem_oct_rdn/////////
							mem_oct_rdn,

							/////////mem_oct_rup/////////
							mem_oct_rup,

							/////////SMA/////////
							SMA_CLKIN,
							SMA_CLKOUT,
							SMA_CLKOUT_n,
							SMA_CLKOUT_p,

							/////////SSRAM/////////
							SSRAM_ADSC_n,
							SSRAM_ADSP_n,
							SSRAM_ADV_n,
							SSRAM_BE_n,
							SSRAM_CE1_n,
							SSRAM_CLK,

							/////////SW/////////
							SW,

							/////////TEMP/////////
							TEMP_CLK,
							TEMP_DATA,
							TEMP_INT_n,
							TEMP_OVERT_n,
);

//=======================================================
//  PORT declarations
//=======================================================
///////////BUTTON/////////////
input							[3:0]							BUTTON;

///////// FAN /////////
output														FAN_CTRL;

///////// FLASH /////////
output														FLASH_ADV_n;
output														FLASH_CE_n;
output														FLASH_CLK;
input															FLASH_RDY_BSY_n;
output														FLASH_RESET_n;
output														FLASH_WP_n;

///////// FSM /////////
output							[25:1]					FSM_A;
inout							[31:0]						FSM_D;
output														FSM_OE_n;
output														FSM_WE_n;

///////// HSMA /////////
input															HSMA_CLKIN0;
input															HSMA_CLKIN_n1;
input															HSMA_CLKIN_n2;
input															HSMA_CLKIN_p1;
input															HSMA_CLKIN_p2;
inout							[3:0]							HSMA_D;
inout															HSMA_OUT0;
inout															HSMA_OUT_n1;
inout															HSMA_OUT_n2;
inout															HSMA_OUT_p1;
inout															HSMA_OUT_p2;
inout							[16:0]						HSMA_RX_n;
inout							[16:0]						HSMA_RX_p;
inout							[16:0]						HSMA_TX_n;
inout							[16:0]						HSMA_TX_p;

///////// HSMB /////////
input															HSMB_CLKIN0;
input															HSMB_CLKIN_n1;
input															HSMB_CLKIN_n2;
input															HSMB_CLKIN_p1;
input															HSMB_CLKIN_p2;
inout							[3:0]							HSMB_D;
inout															HSMB_OUT0;
inout															HSMB_OUT_n1;
inout															HSMB_OUT_n2;
inout															HSMB_OUT_p1;
inout															HSMB_OUT_p2;
inout							[16:0]						HSMB_RX_n;
inout							[16:0]						HSMB_RX_p;
output														HSMB_SCL;
inout															HSMB_SDA;
inout							[16:0]						HSMB_TX_n;
inout							[16:0]						HSMB_TX_p;

///////// HSMC /////////
input															HSMC_CLKIN0;
input															HSMC_CLKIN_n1;
input															HSMC_CLKIN_n2;
input															HSMC_CLKIN_p1;
input															HSMC_CLKIN_p2;
inout															HSMC_CLKOUT_n1;
inout															HSMC_CLKOUT_p1;
inout							[3:0]							HSMC_D;
inout															HSMC_OUT0;
inout															HSMC_OUT_n2;
inout															HSMC_OUT_p2;
inout							[16:0]						HSMC_RX_n;
inout							[16:0]						HSMC_RX_p;
inout							[16:0]						HSMC_TX_n;
inout							[16:0]						HSMC_TX_p;

///////// HSMD /////////
input															HSMD_CLKIN0;
input															HSMD_CLKIN_n1;
input															HSMD_CLKIN_n2;
input															HSMD_CLKIN_p1;
input															HSMD_CLKIN_p2;
inout															HSMD_CLKOUT_n1;
inout															HSMD_CLKOUT_p1;
inout							[3:0]							HSMD_D;
inout															HSMD_OUT0;
inout															HSMD_OUT_n2;
inout															HSMD_OUT_p2;
inout							[16:0]						HSMD_RX_n;
inout							[16:0]						HSMD_RX_p;
output														HSMD_SCL;
inout															HSMD_SDA;
inout							[16:0]						HSMD_TX_n;
inout							[16:0]						HSMD_TX_p;
///////// HSME /////////
input															HSME_CLKIN0;
input															HSME_CLKIN_n1;
input															HSME_CLKIN_n2;
input															HSME_CLKIN_p1;
input															HSME_CLKIN_p2;
inout															HSME_CLKOUT_n1;
inout															HSME_CLKOUT_p1;
inout							[3:0]							HSME_D;
inout															HSME_OUT0;
inout															HSME_OUT_n2;
inout															HSME_OUT_p2;
inout							[16:0]						HSME_RX_n;
inout							[16:0]						HSME_RX_p;
inout							[16:0]						HSME_TX_n;
inout							[16:0]						HSME_TX_p;

//////////// HSMC-F, HSMC-F connect to NET - 10/100/1000 Ethernet //////////
output						          					NET0_GTX_CLK;
input 						          					NET0_INTN;
input 						          					NET0_LINK1000;
output						          					NET0_MDC;
inout 						          					NET0_MDIO;
output						          					NET0_RESETN;
input 						          					NET0_RX_CLK;
input 						          					NET0_RX_COL;
input 						          					NET0_RX_CRS;
input 						     [7:0]					NET0_RX_D;
input 						          					NET0_RX_DV;
input 						          					NET0_RX_ER;
input 						          					NET0_S_CLKN;
input 						          					NET0_S_CLKP;
input 						          					NET0_S_RX_N;
input 						          					NET0_S_RX_P;
output						          					NET0_S_TX_N;
output						          					NET0_S_TX_P;
input 						          					NET0_TX_CLK;
output						     [7:0]					NET0_TX_D;
output						          					NET0_TX_EN;
output						          					NET0_TX_ER;
output						          					NET1_GTX_CLK;
input 						          					NET1_INTN;
input 						          					NET1_LINK1000;
output						          					NET1_MDC;
inout 						          					NET1_MDIO;
output						          					NET1_RESETN;
input 						          					NET1_RX_CLK;
input 						          					NET1_RX_COL;
input 						          					NET1_RX_CRS;
input 						     [7:0]					NET1_RX_D;
input 						          					NET1_RX_DV;
input 						          					NET1_RX_ER;
input 						          					NET1_S_CLKN;
input 						          					NET1_S_CLKP;
input 						          					NET1_S_RX_N;
input 						          					NET1_S_RX_P;
output						          					NET1_S_TX_N;
output						          					NET1_S_TX_P;
input 						          					NET1_TX_CLK;
output						     [7:0]					NET1_TX_D;
output						          					NET1_TX_EN;
output						          					NET1_TX_ER;

///////// LED /////////
output							[3:0]						LED;

///////// LOOP /////////
input															LOOP_CLKIN0;
output														LOOP_CLKOUT0;
input															LOOP_CLKIN1;
output														LOOP_CLKOUT1;

///////// MAX2 /////////
output														MAX2_CS_n;
output														MAX2_I2C_SCL;
inout															MAX2_I2C_SDA;

///////// mem /////////
output							[15:0]					mem_a;
output							[2:0]						mem_ba;
output														mem_cas_n;
output							[1:0]						mem_cke;
output							[1:0]						mem_ck;
output							[1:0]						mem_ck_n;
output							[1:0]						mem_cs_n;
output							[7:0]						mem_dm;
inout								[63:0]					mem_dq;
inout								[7:0]						mem_dqs;
inout								[7:0]						mem_dqs_n;
input															mem_event_n;
output							[1:0]						mem_odt;
output														mem_ras_n;
output														mem_reset_n;
output														mem_scl;
inout															mem_sda;
output														mem_we_n;

///////// OSC /////////
input															OSC_50_BANK1;
input															OSC_50_BANK3;
input															OSC_50_BANK4;
input															OSC_50_BANK7;
input															OSC_50_BANK8;

///////// mem_oct_rdn /////////
input															mem_oct_rdn;

///////// mem_oct_rup /////////
input															mem_oct_rup;

///////// SMA /////////
input															SMA_CLKIN;
output														SMA_CLKOUT;
output														SMA_CLKOUT_n;
output														SMA_CLKOUT_p;

///////// SSRAM /////////
output														SSRAM_ADSC_n;
output														SSRAM_ADSP_n;
output														SSRAM_ADV_n;
output							[3:0]						SSRAM_BE_n;
output														SSRAM_CE1_n;
output														SSRAM_CLK;

///////// SW /////////
input							[3:0]							SW;

///////// TEMP /////////
output														TEMP_CLK;
inout															TEMP_DATA;
input															TEMP_INT_n;
input															TEMP_OVERT_n;

//=======================================================
//  Structural coding
//=======================================================
//=======================================================
//  REG/WIRE declarations
//=======================================================
wire			global_reset_n;
wire			CLK_125MHz;
reg				LEDR_dummy;
//===== ethernet =====
wire			enet_resetn;
// clock
wire			tx_clk_ref125;
wire			tx_clk_phy125;
wire			tx_clk_mac;
wire			enet_gtx_clk;
wire			enet_tx_clk;
wire			enet_rx_clk;

// Management Interface and Interrupt
wire			enet_mdc;
wire			enet_mdio_in;
wire			enet_mdio_oen;
wire			enet_mdio_out;

// SOPC control signal
wire			ena_10_from_the_tse_mac;
wire			eth_mode_from_the_tse_mac;
wire			set_1000_to_the_tse_mac;
wire			set_10_to_the_tse_mac;

// local MUX signal
wire			m_rx_col;
wire			m_rx_crs;
wire	[3:0]	m_rx_d;
wire			m_rx_dv;
wire			m_rx_err;
wire	[3:0]	m_tx_d;
wire			m_tx_en;
wire			m_tx_err;
wire	[7:0]	gm_rx_d;
wire			gm_rx_dv;
wire			gm_rx_err;
wire	[7:0]	gm_tx_d;
wire			gm_tx_en;
wire			gm_tx_err;
// ===== ethernet clock =====
// ===== ethernet signal =====
assign NET0_RESETN		   = enet_resetn;
assign NET1_RESETN		   = enet_resetn;

`ifdef NET0
assign enet_rx_clk			= NET0_RX_CLK;
assign enet_tx_clk			= NET0_TX_CLK;
assign NET0_GTX_CLK	      = enet_gtx_clk;
assign NET0_MDC		      = enet_mdc;

`else
assign enet_rx_clk			= NET1_RX_CLK;
assign enet_tx_clk			= NET1_TX_CLK;
assign NET1_GTX_CLK	      = enet_gtx_clk;
assign NET1_MDC		      = enet_mdc;

`endif

// ===== SOPC control signal defing
assign set_1000_to_the_tse_mac	= 1'b0;
assign set_10_to_the_tse_mac	   = 1'b0;
//assign ena_10_from_the_tse_mac   = 1'b0;
enet_tx_clk_pll enet_tx_clk_pll
(
		.inclk0(OSC_50_BANK3),
		.c0(tx_clk_ref125),
		.c1(tx_clk_phy125)
);


gen_reset_n	system_gen_reset_n (
		.tx_clk(OSC_50_BANK1),
		.reset_n_in(BUTTON[0]),
		.reset_n_out(global_reset_n)
		);

gen_reset_n	net_gen_reset_n(
		.tx_clk(OSC_50_BANK1),
		.reset_n_in(BUTTON[0]),
		.reset_n_out(enet_resetn)
);


//=======================================================
//  Structural coding
//=======================================================
assign FAN_CTRL = 1'b1;

    TR4_QSYS u0 (
	     .clk_clk                                            (OSC_50_BANK4),
        .external_clk50_clk                                 (OSC_50_BANK8),                               
        .external_reset_reset_n                             (global_reset_n),  
		
		  .button_export                                      (),
		  .led_export                                         (LED),
		    
        .ddr2_i2c_sda_export                                (mem_sda),    
        .ddr2_i2c_scl_export                                (mem_scl), 
		  
        .memory_mem_cs_n                                    (mem_cs_n),      
        .memory_mem_odt                                     (mem_odt), 
        .memory_mem_cas_n                                   (mem_cas_n), 
        .memory_mem_dm                                      (mem_dm),  
        .memory_mem_dqs                                     (mem_dqs), 
        .memory_mem_we_n                                    (mem_we_n),
        .memory_mem_ck                                      (mem_ck),   
        .memory_mem_ras_n                                   (mem_ras_n), 
        .memory_mem_dq                                      (mem_dq), 
        .memory_mem_ck_n                                    (mem_ck_n), 
        .memory_mem_cke                                     (mem_cke), 
        .memory_mem_dqs_n                                   (mem_dqs_n),  
        .memory_mem_reset_n                                 (mem_reset_n), 
        .memory_mem_a                                       (mem_a),    
        .memory_mem_ba                                      (mem_ba),   
        .oct_rup                                            (mem_oct_rup),      
        .oct_rdn                                            (mem_oct_rdn),      
		  
        .uniphy_ddr3_oct_sharing_parallelterminationcontrol (), 
        .uniphy_ddr3_oct_sharing_seriesterminationcontrol   (),   
        .uniphy_ddr3_pll_sharing_pll_addr_cmd_clk           (),  
        .uniphy_ddr3_pll_sharing_pll_config_clk             (),  
        .uniphy_ddr3_pll_sharing_pll_write_clk              (),   
        .uniphy_ddr3_pll_sharing_pll_avl_clk                (),    
        .uniphy_ddr3_pll_sharing_pll_mem_clk                (),     
        .uniphy_ddr3_pll_sharing_pll_locked                 (),     
        .uniphy_ddr3_dll_sharing_dll_delayctrl              (),    
        .uniphy_ddr3_local_powerdown_local_powerdn_ack      (),    
        .uniphy_ddr3_local_powerdown_local_powerdn_req      (),    
        .uniphy_ddr3_status_local_cal_success               (uniphy_ddr3_status_local_cal_success),       
        .uniphy_ddr3_status_local_cal_fail                  (uniphy_ddr3_status_local_cal_fail),     
        .uniphy_ddr3_status_local_init_done                 (uniphy_ddr3_status_local_init_done),
        .ethernet_mac_eth_mode                              (eth_mode_from_the_tse_mac),//                            .ethernet_mac.eth_mode
		  .ethernet_mac_mdio_oen                              (enet_mdio_oen),//                            .mdio_oen
		  .ethernet_mac_gm_rx_d                               (gm_rx_d),//                            .gm_rx_d
		  .ethernet_mac_m_rx_d                                (m_rx_d),//                            .m_rx_d
		  .ethernet_mac_m_tx_err                              (m_tx_err),//                            .m_tx_err
		  .ethernet_mac_m_tx_d                                (m_tx_d),//                            .m_tx_d
		  .ethernet_mac_m_tx_en                               (m_tx_en),//                            .m_tx_en
		  .ethernet_mac_m_rx_col                              (m_rx_col),//                            .m_rx_col
		  .ethernet_mac_m_rx_en                               (m_rx_dv),//                            .m_rx_en
		  .ethernet_mac_set_1000                              (set_1000_to_the_tse_mac),//                            .set_1000
		  .ethernet_mac_gm_tx_d                               (gm_tx_d),//                            .gm_tx_d
		  .ethernet_mac_set_10                                (set_10_to_the_tse_mac),//                            .set_10
		  .ethernet_mac_m_rx_crs                              (m_rx_crs),//                            .m_rx_crs
		  .ethernet_mac_mdc                                   (enet_mdc),//                            .mdc
		  .ethernet_mac_ena_10                                (ena_10_from_the_tse_mac),//                            .ena_10wire        
		  .ethernet_mac_gm_rx_dv 		                        (gm_rx_dv),//                            .gm_rx_dv
		  .ethernet_mac_gm_rx_err                             (gm_rx_err),//                            .gm_rx_err
		  .ethernet_mac_gm_tx_en                              (gm_tx_en),//                            .gm_tx_en
		  .ethernet_mac_rx_clk                                (enet_rx_clk),//                            .rx_clk
		  .ethernet_mac_m_rx_err                              (m_rx_err),//                            .m_rx_err
		  .ethernet_mac_tx_clk                                (tx_clk_mac),//                            .tx_clk
		  .ethernet_mac_mdio_in                               (enet_mdio_in),//                            .mdio_in
		  .ethernet_mac_mdio_out                              (enet_mdio_out),//                            .mdio_out
		  .ethernet_mac_gm_tx_err                             (gm_tx_err)//                            .gm_tx_err		  
    );
`ifdef	NET0
GMII_MII_MUX INST_MUX(
					//--- PHY Interface
					.reset_rx_clk_n(enet_resetn),
					.phy_rx_clk(enet_rx_clk),
					.phy_rx_col(NET0_RX_COL),
					.phy_rx_crs(NET0_RX_CRS),
					.phy_rx_d(NET0_RX_D),
					.phy_rx_dv(NET0_RX_DV),
					.phy_rx_err(NET0_RX_ER),
					.reset_tx_clk_n(enet_resetn),
					.tx_clk_ref125(tx_clk_ref125),
					.tx_clk_phy125(tx_clk_phy125),
					.tx_clk_mac(tx_clk_mac),
					.tx_clk(enet_tx_clk),
					.phy_gtx_clk(enet_gtx_clk),
					.phy_tx_d(NET0_TX_D),
					.phy_tx_en(NET0_TX_EN),
					.phy_tx_err(NET0_TX_ER),
					.phy_mdio(NET0_MDIO),
					//--- Local MII Interface
					.m_rx_col(m_rx_col),
					.m_rx_crs(m_rx_crs),
					.m_rx_d(m_rx_d),
					.m_rx_dv(m_rx_dv),
					.m_rx_err(m_rx_err),
					.m_tx_d(m_tx_d),
					.m_tx_en(m_tx_en),
					.m_tx_err(m_tx_err),
					//--- Local GMII Interface
					.gm_rx_d(gm_rx_d),
					.gm_rx_dv(gm_rx_dv),
					.gm_rx_err(gm_rx_err),
					.gm_tx_d(gm_tx_d),
					.gm_tx_en(gm_tx_en),
					.gm_tx_err(gm_tx_err),
					//--- 
					.eth_mode(eth_mode_from_the_tse_mac),
					.mdio_in(enet_mdio_in),
					.mdio_oen(enet_mdio_oen),
					.mdio_out(enet_mdio_out)
					);
`else
GMII_MII_MUX INST_MUX(
					//--- PHY Interface
					.reset_rx_clk_n(enet_resetn),
					.phy_rx_clk(enet_rx_clk),
					.phy_rx_col(NET1_RX_COL),
					.phy_rx_crs(NET1_RX_CRS),
					.phy_rx_d(NET1_RX_D),
					.phy_rx_dv(NET1_RX_DV),
					.phy_rx_err(NET1_RX_ER),
					.reset_tx_clk_n(enet_resetn),
					.tx_clk_ref125(tx_clk_ref125),
					.tx_clk_phy125(tx_clk_phy125),
					.tx_clk_mac(tx_clk_mac),
					.tx_clk(enet_tx_clk),
					.phy_gtx_clk(enet_gtx_clk),
					.phy_tx_d(NET1_TX_D),
					.phy_tx_en(NET1_TX_EN),
					.phy_tx_err(NET1_TX_ER),
					.phy_mdio(NET1_MDIO),
					//--- Local MII Interface
					.m_rx_col(m_rx_col),
					.m_rx_crs(m_rx_crs),
					.m_rx_d(m_rx_d),
					.m_rx_dv(m_rx_dv),
					.m_rx_err(m_rx_err),
					.m_tx_d(m_tx_d),
					.m_tx_en(m_tx_en),
					.m_tx_err(m_tx_err),
					//--- Local GMII Interface
					.gm_rx_d(gm_rx_d),
					.gm_rx_dv(gm_rx_dv),
					.gm_rx_err(gm_rx_err),
					.gm_tx_d(gm_tx_d),
					.gm_tx_en(gm_tx_en),
					.gm_tx_err(gm_tx_err),
					//--- 
					.eth_mode(eth_mode_from_the_tse_mac),
					.mdio_in(enet_mdio_in),
					.mdio_oen(enet_mdio_oen),
					.mdio_out(enet_mdio_out)
					);
`endif	 
//wire uniphy_ddr3_status_local_cal_success,uniphy_ddr3_status_local_cal_fail,uniphy_ddr3_status_local_init_done;
//
//assign LED = {1'b1,~uniphy_ddr3_status_local_cal_success,~uniphy_ddr3_status_local_cal_fail,~uniphy_ddr3_status_local_init_done};
//assign LED[2:1]	= ~{count[25:23]};
//assign LED[3]	 	= ~eth_mode_from_the_tse_mac;
//
//reg	[31:0]	count;
//always @(posedge tx_clk_mac)
//begin
//	count = count + 1;
//end

endmodule
