
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module TR4_SATA(

	//////////// CLOCK //////////
	OSC_50_BANK1,
	OSC_50_BANK3,
	OSC_50_BANK4,
	OSC_50_BANK7,
	OSC_50_BANK8,

	//////////// Loop //////////
	LOOP_CLKIN0,
	LOOP_CLKIN1,
	LOOP_CLKOUT0,
	LOOP_CLKOUT1,

	//////////// SMA //////////
	SMA_CLKIN,
	SMA_CLKOUT,
	SMA_CLKOUT_p,
//	SMA_GXBCLK_p,

	//////////// LED x 4 //////////
	LED,

	//////////// BUTTON x 4 //////////
	BUTTON,

	//////////// SWITCH x 4 //////////
	SW,

	//////////// Fan //////////
	FAN_CTRL,

	//////////// HSMC-E, HSMC-E connect to SATA/SAS //////////
	TR4_SAS_SIDEBAND,
	TR4_SATA_CLK_FS,
//	TR4_SATA_CLK_N,
	TR4_SATA_CLK_OE,
	TR4_SATA_CLK_P,
//	TR4_SATA_HSM_RX_N,
	TR4_SATA_HSM_RX_P,
//	TR4_SATA_HSM_TX_N,
	TR4_SATA_HSM_TX_P,
	TR4_SATA_RX_LED_G,
	TR4_SATA_RX_LED_R,
	TR4_SATA_TX_LED_G,
	TR4_SATA_TX_LED_R,
	TR4_SATA_USER_DIPSW 
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input 		          		OSC_50_BANK1;
input 		          		OSC_50_BANK3;
input 		          		OSC_50_BANK4;
input 		          		OSC_50_BANK7;
input 		          		OSC_50_BANK8;

//////////// Loop //////////
input 		          		LOOP_CLKIN0;
input 		          		LOOP_CLKIN1;
output		          		LOOP_CLKOUT0;
output		          		LOOP_CLKOUT1;

//////////// SMA //////////
input 		          		SMA_CLKIN;
output		          		SMA_CLKOUT;
output		          		SMA_CLKOUT_p;
//input 		          		SMA_GXBCLK_p;

//////////// LED x 4 //////////
output		     [3:0]		LED;

//////////// BUTTON x 4 //////////
input 		     [3:0]		BUTTON;

//////////// SWITCH x 4 //////////
input 		     [3:0]		SW;

//////////// Fan //////////
output		          		FAN_CTRL;

//////////// HSMC-E, HSMC-E connect to SATA/SAS //////////
input 		     [5:0]		TR4_SAS_SIDEBAND;
output		          		TR4_SATA_CLK_FS;
//input 		          		TR4_SATA_CLK_N;
output		          		TR4_SATA_CLK_OE;
input 		          		TR4_SATA_CLK_P;
//input 		     [7:0]		TR4_SATA_HSM_RX_N;
input 		     [7:0]		TR4_SATA_HSM_RX_P;
//output		     [7:0]		TR4_SATA_HSM_TX_N;
output		     [7:0]		TR4_SATA_HSM_TX_P;
output		     [7:0]		TR4_SATA_RX_LED_G;
output		     [7:0]		TR4_SATA_RX_LED_R;
output		     [7:0]		TR4_SATA_TX_LED_G;
output		     [7:0]		TR4_SATA_TX_LED_R;
input 		     [7:0]		TR4_SATA_USER_DIPSW;


//=======================================================
//  REG/WIRE declarations
//=======================================================				
wire			cal_blk_clk;				
wire	[7:0]		test_error;
wire			sys_rst_n;
wire			CLK125;

//=======================================================
//  Structural coding
//=======================================================

assign FAN_CTRL = 1'b1;

cal_pll0 p0(
	.inclk0(OSC_50_BANK3),
	.c0(CLK125)
	);




//========== sata channel 0 verify ==========

xcvr_test g0(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[0]),
.xcvr_rx(TR4_SATA_HSM_RX_P[0]),
.error_insert(BUTTON[1]),
.test_error(test_error[0]),
.tx_clock(),

);

//========== sata channel 1 verify ==========

xcvr_test g1(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[1]),
.xcvr_rx(TR4_SATA_HSM_RX_P[1]),
.error_insert(BUTTON[1]),
.test_error(test_error[1]),
.tx_clock(),
);

//========== sata channel 2 verify ==========

xcvr_test g2(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[2]),
.xcvr_rx(TR4_SATA_HSM_RX_P[2]),
.error_insert(BUTTON[1]),
.test_error(test_error[2]),
.tx_clock(),
);

//========== sata channel 3 verify ==========
xcvr_test g3(

.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[3]),
.xcvr_rx(TR4_SATA_HSM_RX_P[3]),
.error_insert(BUTTON[1]),
.test_error(test_error[3]),
.tx_clock(),
);

//========== sata channel 4 verify ==========
xcvr_test g4(
.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[4]),
.xcvr_rx(TR4_SATA_HSM_RX_P[4]),
.error_insert(BUTTON[1]),
.test_error(test_error[4]),
.tx_clock(),
);

//========== sata channel 5 verify ==========
xcvr_test g5(
.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[5]),
.xcvr_rx(TR4_SATA_HSM_RX_P[5]),
.error_insert(BUTTON[1]),
.test_error(test_error[5]),
.tx_clock(),
);

//========== sata channel 6 verify ==========
xcvr_test g6(
.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[6]),
.xcvr_rx(TR4_SATA_HSM_RX_P[6]),
.error_insert(BUTTON[1]),
.test_error(test_error[6]),
.tx_clock(),
);

//========== sata channel 7 verify ==========
xcvr_test g7(
.cal_blk_clk(OSC_50_BANK3),
.xcvr_refclk(CLK125),
.irst_n(BUTTON[0]),
.xcvr_tx(TR4_SATA_HSM_TX_P[7]),
.xcvr_rx(TR4_SATA_HSM_RX_P[7]),
.error_insert(BUTTON[1]),
.test_error(test_error[7]),
.tx_clock(),
);
//========== test result  ==========

assign TR4_SATA_RX_LED_G=test_error;
assign TR4_SATA_TX_LED_G=test_error;

assign TR4_SATA_TX_LED_R=8'hff;
assign TR4_SATA_RX_LED_R=8'hff;
endmodule

