
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module Tr4_SDI(

	//////////// CLOCK //////////
	OSC_50_BANK1,
	OSC_50_BANK3,
	OSC_50_BANK4,
	OSC_50_BANK7,
	OSC_50_BANK8,

	//////////// Loop //////////
	LOOP_CLKIN0,
	LOOP_CLKIN1,
	LOOP_CLKOUT0,
	LOOP_CLKOUT1,

	//////////// LED x 4 //////////
	LED,

	//////////// BUTTON x 4 //////////
	BUTTON,

	//////////// SWITCH x 4 //////////
	SW,

	//////////// HSMC-A, HSMC-A connect to SDI - SD/HD/3G //////////
	AES_CLK,
	AES_CLK_PDTSn,
	AES_CLK_S,
	AES_IN,
	AES_OUT,
	AES_VCXO_DN,
	AES_VCXO_UP,
	HSYNC,
	ODDEVEN,
	SDI_BYPASS,
	SDI_CLK_BP,
	SDI_CLK_MLTF,
	SDI_CLK_N,
	SDI_CLK_OE,
	SDI_CLK_RST,
	SDI_CLK_SEL,
	SDI_CLK_V,
	SDI_EQOUT_P,
	SDI_HSMC_CLK,
	SDI_HSMC_CLK_P,
	SDI_LED_RX_G,
	SDI_LED_RX_R,
	SDI_LED_TX_G,
	SDI_LED_TX_R,
	SDI_RATE_SEL,
	SDI_TX_P,
	SDI_XTAL_SEL,
	VFORMAT,
	VSYNC,

	//////////// HSMC A/B/C I2C //////////
	HSMC_ABC_SCL,
	HSMC_ABC_SDA 
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input 		          		OSC_50_BANK1;
input 		          		OSC_50_BANK3;
input 		          		OSC_50_BANK4;
input 		          		OSC_50_BANK7;
input 		          		OSC_50_BANK8;

//////////// Loop //////////
input 		          		LOOP_CLKIN0;
input 		          		LOOP_CLKIN1;
output		          		LOOP_CLKOUT0;
output		          		LOOP_CLKOUT1;

//////////// LED x 4 //////////
output		     [3:0]		LED;

//////////// BUTTON x 4 //////////
input 		     [3:0]		BUTTON;

//////////// SWITCH x 4 //////////
input 		     [3:0]		SW;

//////////// HSMC-A, HSMC-A connect to SDI - SD/HD/3G //////////
input 		          		AES_CLK;
output		          		AES_CLK_PDTSn;
output		     [2:0]		AES_CLK_S;
input 		     [1:0]		AES_IN;
output		     [1:0]		AES_OUT;
output		          		AES_VCXO_DN;
output		          		AES_VCXO_UP;
input 		          		HSYNC;
input 		          		ODDEVEN;
output		     [1:0]		SDI_BYPASS;
output		     [1:0]		SDI_CLK_BP;
output		          		SDI_CLK_MLTF;
output		     [1:0]		SDI_CLK_N;
output		          		SDI_CLK_OE;
output		          		SDI_CLK_RST;
output		          		SDI_CLK_SEL;
output		     [3:0]		SDI_CLK_V;
input 		     [1:0]		SDI_EQOUT_P;
output		          		SDI_HSMC_CLK;
input 		          		SDI_HSMC_CLK_P;
output		     [1:0]		SDI_LED_RX_G;
output		     [1:0]		SDI_LED_RX_R;
output		     [1:0]		SDI_LED_TX_G;
output		     [1:0]		SDI_LED_TX_R;
output		     [1:0]		SDI_RATE_SEL;
output		     [1:0]		SDI_TX_P;
output		          		SDI_XTAL_SEL;
input 		          		VFORMAT;
input 		          		VSYNC;

//////////// HSMC A/B/C I2C //////////
output		          		HSMC_ABC_SCL;
inout 		          		HSMC_ABC_SDA;

//=======================================================
//  Structural coding
//=======================================================
TR4_SDI_TOP TR4_SDI_TOP_inst
(
   .gp_clk(OSC_50_BANK1),
	.BUTTON(BUTTON),
	.SW(SW),
	.LED(LED),
	.AES_CLK(AES_CLK),
	.AES_CLK_PDTSn(AES_CLK_PDTSn),
	.AES_CLK_S(AES_CLK_S),
	.AES_IN(AES_IN),
	.AES_OUT(AES_OUT),
	.AES_VCXO_DN(AES_VCXO_DN),
	.AES_VCXO_UP(AES_VCXO_UP),
	.HSYNC(),
	.ODDEVEN(),
	.SDI_BYPASS(SDI_BYPASS),
	.SDI_CLK_BP(SDI_CLK_BP),
	.SDI_CLK_MLTF(SDI_CLK_MLTF),
	.SDI_CLK_N(SDI_CLK_N),
	.SDI_CLK_OE(SDI_CLK_OE),
	.SDI_CLK_RST(SDI_CLK_RST),
	.SDI_CLK_SEL(SDI_CLK_SEL),
	.SDI_CLK_V(SDI_CLK_V),
	.SDI_EQOUT_P(SDI_EQOUT_P),
	.SDI_HSMC_CLK(SDI_HSMC_CLK),
	.SDI_HSMC_CLK_P(sdi_hsmc_clk_p),
	.SDI_LED_RX_G(SDI_LED_RX_G),
	.SDI_LED_RX_R(SDI_LED_RX_R),
	.SDI_LED_TX_G(SDI_LED_TX_G),
	.SDI_LED_TX_R(SDI_LED_TX_R),
	.SDI_RATE_SEL(SDI_RATE_SEL),
	.SDI_TX_P(SDI_TX_P),
	.SDI_XTAL_SEL(SDI_XTAL_SEL),
	.VFORMAT(),
	.VSYNC()
			);

wire sdi_hsmc_clk_p;			

pll pll (
	.areset(1'b0),
	.inclk0(OSC_50_BANK1),
	.c0(sdi_hsmc_clk_p),
	.locked());
			
			
			
endmodule
