----------------------------------------------------------------------------------------------------------
--
-- STRATIXII_PLL.INC
--
-- Wysiwyg include file for Stratix II family PLL
--
-- (c) Altera Corporation, 2003
--
----------------------------------------------------------------------------------------------------------
FUNCTION stratixii_pll(
						inclk[1..0],
						clkswitch,
						ena,
						areset,
						pfdena,
						fbin,
						scanclk,
						scanread,
						scanwrite,
						scandata,
						testin[3..0]
					)
					WITH
					(
						OPERATION_MODE,
						QUALIFY_CONF_DONE,
						COMPENSATE_CLOCK,
						PLL_TYPE,
						-- Internal clock specifications
						CLK5_MULTIPLY_BY,
						CLK4_MULTIPLY_BY,
						CLK3_MULTIPLY_BY,
						CLK2_MULTIPLY_BY,
						CLK1_MULTIPLY_BY,
						CLK0_MULTIPLY_BY,
						CLK5_DIVIDE_BY,
						CLK4_DIVIDE_BY,
						CLK3_DIVIDE_BY,
						CLK2_DIVIDE_BY,
						CLK1_DIVIDE_BY,
						CLK0_DIVIDE_BY,
						CLK5_PHASE_SHIFT,
						CLK4_PHASE_SHIFT,
						CLK3_PHASE_SHIFT,
						CLK2_PHASE_SHIFT,
						CLK1_PHASE_SHIFT,
						CLK0_PHASE_SHIFT,
						CLK5_DUTY_CYCLE,
						CLK4_DUTY_CYCLE,
						CLK3_DUTY_CYCLE,
						CLK2_DUTY_CYCLE,
						CLK1_DUTY_CYCLE,
						CLK0_DUTY_CYCLE,
						SCLKOUT1_PHASE_SHIFT,
						SCLKOUT0_PHASE_SHIFT,
						INCLK0_INPUT_FREQUENCY,
						INCLK1_INPUT_FREQUENCY,
						VCO_MULTIPLY_BY,
						VCO_DIVIDE_BY,
						GATE_LOCK_SIGNAL,
						GATE_LOCK_COUNTER,
						LOCK_HIGH,
						LOCK_LOW,
						VALID_LOCK_MULTIPLIER,
						INVALID_LOCK_MULTIPLIER,
						SWITCH_OVER_ON_LOSSCLK,
						SWITCH_OVER_ON_GATED_LOCK,
						ENABLE_SWITCH_OVER_COUNTER,
						SWITCH_OVER_COUNTER,
						SWITCH_OVER_TYPE,
						FEEDBACK_SOURCE,
						BANDWIDTH,
						BANDWIDTH_TYPE,
						SPREAD_FREQUENCY,
						DOWN_SPREAD,
						TEST_INPUT_COMP_DELAY_CHAIN_BITS,
						TEST_FEEDBACK_COMP_DELAY_CHAIN_BITS,
						VCO_MULTIPLY_BY,
						VCO_DIVIDE_BY,
						-- Advanced use parameters
						VCO_MIN,
						VCO_MAX,
						VCO_CENTER,
						PFD_MIN,
						PFD_MAX,
						M_INITIAL,
						M,
						N,
						VCO_POST_SCALE,
						M2,
						N2,
						SS,
						C0_HIGH,
						C1_HIGH,
						C2_HIGH,
						C3_HIGH,
						C4_HIGH,
						C5_HIGH,
						C0_LOW,
						C1_LOW,
						C2_LOW,
						C3_LOW,
						C4_LOW,
						C5_LOW,
						C0_INITIAL,
						C1_INITIAL,
						C2_INITIAL,
						C3_INITIAL,
						C4_INITIAL,
						C5_INITIAL,
						C0_MODE,
						C1_MODE,
						C2_MODE,
						C3_MODE,
						C4_MODE,
						C5_MODE,
						C0_PH,
						C1_PH,
						C2_PH,
						C3_PH,
						C4_PH,
						C5_PH,
						M_PH,
						C1_USE_CASC_IN,
						C2_USE_CASC_IN,
						C3_USE_CASC_IN,
						C4_USE_CASC_IN,
						C5_USE_CASC_IN,
						C0_TEST_SOURCE,
						C1_TEST_SOURCE,
						C2_TEST_SOURCE,
						C3_TEST_SOURCE,
						C4_TEST_SOURCE,
						C5_TEST_SOURCE,
						CLK5_COUNTER,
						CLK4_COUNTER,
						CLK3_COUNTER,
						CLK2_COUNTER,
						CLK1_COUNTER,
						CLK0_COUNTER,
						ENABLE0_COUNTER,
						ENABLE1_COUNTER,
						CHARGE_PUMP_CURRENT,
						LOOP_FILTER_R,
						LOOP_FILTER_C,
						M_TEST_SOURCE,
						C0_TEST_SOURCE,
						C1_TEST_SOURCE,
						C2_TEST_SOURCE,
						C3_TEST_SOURCE,
						C4_TEST_SOURCE,
						C5_TEST_SOURCE
					)
					RETURNS
					(
						clk[5..0],
						clkbad[1..0],
						activeclock,
						locked,
						clkloss,
						sclkout[1..0],
						enable1,
						enable0,
						scandataout,
						scandone,
						testupout,
						testdownout
					);
