

module serial_prbs7 (

	clk,
	reset,
	prbs_seed ,
	load ,

	dataout
	);
	


input		clk ;
input		reset ;
input	[7:1]	prbs_seed ;
input		load ;

output		dataout ;

/////////////////////////////////////////////////////////////////////////////

wire	[7:1]	prbs_seed ;

reg	[7:1]	prbs7 ; 



always @ (posedge clk or posedge reset)
begin
  if (reset ) begin
  	prbs7	<= #1 prbs_seed ;
  end
  else if ( load ) 
  	prbs7	<= #1 prbs_seed ;
  else
	prbs7	<= #1 {prbs7[6:1], prbs7[7] ^ prbs7[6]} ;
end

assign	dataout = prbs7[7] ;


endmodule 



