module prbs7_lb_test (

	input		clk_tx ,	//sync clock with data
	input		clk_rx ,
	input		reset ,		//module reset
	input	[7:1]	prbs_seed ,	//seed for data gen
	input		load ,		//prbs seed load sig
	input		force_err ,	//inject an error into the stream
	input		datain ,	//data input from pin
	
	output reg	dataout ,	//data output from data gen
	output		bit_error	// bit error (valid on error only)
	) ;
///////////////////////////////////////////////////////////////////////////////
// registers
reg	[15:0]	holdreg ;
reg		comparereg ; 	
reg		bit_err ;



///////////////////////////////////////////////////////////////////////////////
// data generators (prbs7)
serial_prbs7 datagen_tx (

	.clk		( clk_tx ),
	.reset		( reset ),
	.prbs_seed 	( prbs_seed ),
	.load 		( reset ),
	//lsfr_out,
	.dataout	( prbs7 )
	);
//

////////////////////////////////////////////////////////////////////
// insert data error 
reg		txerror_r, txerror_r2 ;

always @ (posedge clk_tx ) begin
  	
  	//sync to the xcvr referenc clock
  	txerror_r	<= #1 force_err ;
  	txerror_r2	<= #1 txerror_r ;

  	dataout		<= #1 prbs7 ^ txerror_r2 ;
end


///////////////////////////////////////////////////////////////////////////////
// data generators (prbs7)
serial_prbs7 datagen_rx (

	.clk		( clk_rx ),
	.reset		( reset ),
	.prbs_seed 	( holdreg[6:0] ),
	.load 		( load ),
	//lsfr_out,
	.dataout	( prbsrx_data )
	);
//



always @ (posedge clk_rx or posedge reset)
begin
  if ( reset ) begin
  	holdreg		<= #1 7'h01 ;
  	comparereg	<= #1 1'b0 ;
  end
  else  begin 
  	holdreg[15:0]	<= #1 { holdreg[14:0], datain }  ;
	comparereg	<= #1 ( holdreg[7] == prbsrx_data ) ;
	end
end


// sticky bit_err, hold until load signal
always @ ( posedge clk_rx or posedge reset ) 
begin
	if ( reset ) begin
		bit_err		<= #1 1'b0 ;
		end
	else
		if ( ~comparereg )
			bit_err		<= #1 1'b1 ;
		else if ( load )	// clear the error
			bit_err		<= #1 1'b0 ;
		else
			bit_err		<= #1 bit_error ;
end

//assign bit_error = ~comparereg ;
assign bit_error = bit_err ;

///////////////////////////////////////////////////////////////////////////////

endmodule 










