----------------------------------------------------------------------------------------------------------
--
-- STRATIX_PLL.INC
--
-- Wysiwyg include file for Stratix family PLL
--
-- (c) Altera Corporation, 2001
--
----------------------------------------------------------------------------------------------------------
FUNCTION stratix_pll(
						inclk[1..0],
						fbin,
						ena,
						clkswitch,
						areset,
						pfdena,
						clkena[5..0],
						extclkena[3..0],
						scanclk,
						scanaclr,
						scandata,
						comparator
					)
					WITH
					(
						OPERATION_MODE,
						QUALIFY_CONF_DONE,
						COMPENSATE_CLOCK,
						PLL_TYPE,
						SCAN_CHAIN,
						-- Internal clock specifications
						CLK5_MULTIPLY_BY,
						CLK4_MULTIPLY_BY,
						CLK3_MULTIPLY_BY,
						CLK2_MULTIPLY_BY,
						CLK1_MULTIPLY_BY,
						CLK0_MULTIPLY_BY,
						CLK5_DIVIDE_BY,
						CLK4_DIVIDE_BY,
						CLK3_DIVIDE_BY,
						CLK2_DIVIDE_BY,
						CLK1_DIVIDE_BY,
						CLK0_DIVIDE_BY,
						CLK5_PHASE_SHIFT,
						CLK4_PHASE_SHIFT,
						CLK3_PHASE_SHIFT,
						CLK2_PHASE_SHIFT,
						CLK1_PHASE_SHIFT,
						CLK0_PHASE_SHIFT,
						CLK5_TIME_DELAY,
						CLK4_TIME_DELAY,
						CLK3_TIME_DELAY,
						CLK2_TIME_DELAY,
						CLK1_TIME_DELAY,
						CLK0_TIME_DELAY,
						CLK5_DUTY_CYCLE,
						CLK4_DUTY_CYCLE,
						CLK3_DUTY_CYCLE,
						CLK2_DUTY_CYCLE,
						CLK1_DUTY_CYCLE,
						CLK0_DUTY_CYCLE,
						-- External clock specifications
						EXTCLK3_MULTIPLY_BY,
						EXTCLK2_MULTIPLY_BY,
						EXTCLK1_MULTIPLY_BY,
						EXTCLK0_MULTIPLY_BY,
						EXTCLK3_DIVIDE_BY,
						EXTCLK2_DIVIDE_BY,
						EXTCLK1_DIVIDE_BY,
						EXTCLK0_DIVIDE_BY,
						EXTCLK3_PHASE_SHIFT,
						EXTCLK2_PHASE_SHIFT,
						EXTCLK1_PHASE_SHIFT,
						EXTCLK0_PHASE_SHIFT,
						EXTCLK3_TIME_DELAY,
						EXTCLK2_TIME_DELAY,
						EXTCLK1_TIME_DELAY,
						EXTCLK0_TIME_DELAY,
						EXTCLK3_DUTY_CYCLE,
						EXTCLK2_DUTY_CYCLE,
						EXTCLK1_DUTY_CYCLE,
						EXTCLK0_DUTY_CYCLE,
						PRIMARY_CLOCK,
						INCLK0_INPUT_FREQUENCY,
						INCLK1_INPUT_FREQUENCY,
						GATE_LOCK_SIGNAL,
						GATE_LOCK_COUNTER,
						LOCK_HIGH,
						LOCK_LOW,
						VALID_LOCK_MULTIPLIER,
						INVALID_LOCK_MULTIPLIER,
						SWITCH_OVER_ON_LOSSCLK,
						SWITCH_OVER_ON_GATED_LOCK,
						ENABLE_SWITCH_OVER_COUNTER,
						SWITCH_OVER_COUNTER,
						FEEDBACK_SOURCE,
						BANDWIDTH,
						BANDWIDTH_TYPE,
						SPREAD_FREQUENCY,
						DOWN_SPREAD,
						-- Advanced use parameters
						VCO_MIN,
						VCO_MAX,
						VCO_CENTER,
						PFD_MIN,
						PFD_MAX,
						M_INITIAL,
						M,
						N,
						M2,
						N2,
						SS,
						L0_HIGH,
						L1_HIGH,
						G0_HIGH,
						G1_HIGH,
						G2_HIGH,
						G3_HIGH,
						E0_HIGH,
						E1_HIGH,
						E2_HIGH,
						E3_HIGH,
						L0_LOW,
						L1_LOW,
						G0_LOW,
						G1_LOW,
						G2_LOW,
						G3_LOW,
						E0_LOW,
						E1_LOW,
						E2_LOW,
						E3_LOW,
						L0_INITIAL,
						L1_INITIAL,
						G0_INITIAL,
						G1_INITIAL,
						G2_INITIAL,
						G3_INITIAL,
						E0_INITIAL,
						E1_INITIAL,
						E2_INITIAL,
						E3_INITIAL,
						L0_MODE,
						L1_MODE,
						G0_MODE,
						G1_MODE,
						G2_MODE,
						G3_MODE,
						E0_MODE,
						E1_MODE,
						E2_MODE,
						E3_MODE,
						L0_PH,
						L1_PH,
						G0_PH,
						G1_PH,
						G2_PH,
						G3_PH,
						E0_PH,
						E1_PH,
						E2_PH,
						E3_PH,
						M_PH,
						L0_TIME_DELAY,
						L1_TIME_DELAY,
						G0_TIME_DELAY,
						G1_TIME_DELAY,
						G2_TIME_DELAY,
						G3_TIME_DELAY,
						E0_TIME_DELAY,
						E1_TIME_DELAY,
						E2_TIME_DELAY,
						E3_TIME_DELAY,
						M_TIME_DELAY,
						N_TIME_DELAY,
						EXTCLK3_COUNTER,
						EXTCLK2_COUNTER,
						EXTCLK1_COUNTER,
						EXTCLK0_COUNTER,
						CLK5_COUNTER,
						CLK4_COUNTER,
						CLK3_COUNTER,
						CLK2_COUNTER,
						CLK1_COUNTER,
						CLK0_COUNTER,
						ENABLE0_COUNTER,
						ENABLE1_COUNTER,
						CHARGE_PUMP_CURRENT,
						LOOP_FILTER_R,
						LOOP_FILTER_C,
						RX_OUTCLOCK_RESOURCE,
						SKIP_VCO
					)
					RETURNS
					(
						clk[5..0],
						extclk[3..0],
						clkbad[1..0],
						activeclock,
						locked,
						clkloss,
						enable1,
						enable0,
						scandataout
					);
