


module aes_lpbk (
	input		reset ,
	input		aes_clk ,	//aes clock
	input	[3:0]	aes_data_i ,	// ddr inputs for checking on both edges
	input	[2:1]	load_i ,
	input	[2:1]	force_err_i ,

	//outputs
	output	[2:1]	aes_data_o ,
	output	[2:1]	aes_err_o 

	) ;


///////////////////////////////////////////////////////////////////////////////
//  AES IO testing

//generate AES output clock. 
//reg [3:0]	aes_clk_div4 ;

// start to read from fifo when half full  
//always @ (posedge aes_clk or posedge reset) begin
//     if (reset)
//		aes_clk_div4 <= #1 4'b1100 ; 
//     else 
//     		aes_clk_div4 <= #1 { aes_clk_div4[2:0], aes_clk_div4[3] };
//end

// register aes input signals
//reg 	[2:1]	aes_in_R ;
//always @ ( posedge aes_clk_div4[0] ) begin
//     		aes_in_R <= #1 aes_data_i ;
//end

wire	[2:1]	force_err ;


wire	[2:1]	aes_load ;
wire	[3:0]	aes_err ;

reg	[3:0]	aes_err_r ;

assign force_err = force_err_i ;

prbs7_lb_test u1p_prbs_test (

	.clk_tx		( aes_clk ) ,	//sync clock with data
	.clk_rx		( aes_clk ) ,
	.reset		( reset ) ,	//module reset
	.prbs_seed	( 7'h03 ) ,	//seed for data gen
	.load		( load_i[1] ) ,	//prbs seed load sig
	.force_err	( force_err[1] ),
	.datain		( aes_data_i[0] ) ,	//data input from pin
	
	.dataout	( aes_data_o[1] ) ,//data output from data gen
	.bit_error	( aes_err[0] )	// bit error (valid on error only)
	) ;

prbs7_lb_test u1n_prbs_test (

	.clk_tx		( aes_clk ) ,	//sync clock with data
	.clk_rx		( aes_clk ) ,
	.reset		( reset ) ,	//module reset
	.prbs_seed	( 7'h03 ) ,	//seed for data gen
	.load		( load_i[1] ) ,	//prbs seed load sig
	.force_err	( force_err[1] ),
	.datain		( aes_data_i[1] ) ,	//data input from pin
	
	.dataout	(  ) ,//data output from data gen
	.bit_error	( aes_err[1] )	// bit error (valid on error only)
	) ;


prbs7_lb_test u2p_prbs_test (

	.clk_tx		( aes_clk ) ,	//sync clock with data
	.clk_rx		( aes_clk ) ,
	.reset		( reset ) ,	//module reset
	.prbs_seed	( 7'h70 ) ,	//seed for data gen
	.load		( load_i[2] ) ,	//prbs seed load sig
	.force_err	( force_err[2] ),
	.datain		( aes_data_i[2] ) ,	//data input from pin
	
	.dataout	( aes_data_o[2] ) ,//data output from data gen
	.bit_error	( aes_err[2] )	// bit error (valid on error only)
	) ;

prbs7_lb_test u2n_prbs_test (

	.clk_tx		( aes_clk ) ,	//sync clock with data
	.clk_rx		( aes_clk ) ,
	.reset		( reset ) ,	//module reset
	.prbs_seed	( 7'h70 ) ,	//seed for data gen
	.load		( load_i[2] ) ,	//prbs seed load sig
	.force_err	( force_err[2] ),
	.datain		( aes_data_i[3] ) ,	//data input from pin
	
	.dataout	(  ) ,//data output from data gen
	.bit_error	( aes_err[3] )	// bit error (valid on error only)
	) ;

////////////////////////////////////////////////////////////////////////
// sticky error signals cleared with a load signal
always @(posedge aes_clk or posedge reset ) begin
	if ( reset ) begin
		aes_err_r	<= #1 4'b0000 ; 	
	end
		
	else begin
		if ( load_i[1] )
			aes_err_r[0]	<=#1 1'b0 ;
		
		else if ( aes_err[0] )
			aes_err_r[0]	<= #1 1'b1 ;
		
		else
			aes_err_r[0]	<= #1 aes_err_r[0] ;

		if ( load_i[1] )
			aes_err_r[1]	<=#1 1'b0 ;
		
		else if ( aes_err[1] )
			aes_err_r[1]	<= #1 1'b1 ;
		
		else
			aes_err_r[1]	<= #1 aes_err_r[1] ;
		
		//////////////////////////////////////////////
		if ( load_i[2] )
			aes_err_r[2]	<=#1 1'b0 ;
		
		else if ( aes_err[2] )
			aes_err_r[2]	<= #1 1'b1 ;
		
		else
			aes_err_r[2]	<= #1 aes_err_r[2] ;

		if ( load_i[2] )
			aes_err_r[3]	<=#1 1'b0 ;
		
		else if ( aes_err[3] )
			aes_err_r[3]	<= #1 1'b1 ;
	
		else
			aes_err_r[3]	<= #1 aes_err_r[3] ;

	end
end

assign aes_err_o[1]	= aes_err_r[0] & aes_err_r[1] ;
assign aes_err_o[2]	= aes_err_r[2] & aes_err_r[3] ;


endmodule




