TSOM top Board Configuration

TSOM top Board Configuration

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Copyright © 2003-2018 Terasic Inc. All Rights Reserved.

Pin Assignments:

Buttons
Name Location Direction IO Standard
KEY[0] D11 input 2.5 V
KEY[1] AB25 input 2.5 V

Swtiches
Name Location Direction IO Standard
SW[0] AC24 input 1.5 V
SW[1] AB23 input 1.5 V

LED
Name Location Direction IO Standard
LED[0] AA26 output 2.5 V
LED[1] W12 output 2.5 V

HDMI
Name Location Direction IO Standard
HDMI_LRCLK Y8 inout 2.5 V
HDMI_MCLK AA4 inout 2.5 V
HDMI_SCLK W8 inout 2.5 V
HDMI_TX_CLK AB26 output 2.5 V
HDMI_TX_HS Y5 output 2.5 V
HDMI_TX_VS Y4 output 2.5 V
HDMI_TX_D[0] AC4 output 2.5 V
HDMI_TX_D[1] AD4 output 2.5 V
HDMI_TX_D[2] AD5 output 2.5 V
HDMI_TX_D[3] AE6 output 2.5 V
HDMI_TX_D[4] AF5 output 2.5 V
HDMI_TX_D[5] AF6 output 2.5 V
HDMI_TX_D[6] AH3 output 2.5 V
HDMI_TX_D[7] AH2 output 2.5 V
HDMI_TX_D[8] AE4 output 2.5 V
HDMI_TX_D[9] AF4 output 2.5 V
HDMI_TX_D[10] AE7 output 2.5 V
HDMI_TX_D[11] AF8 output 2.5 V
HDMI_TX_D[12] U10 output 2.5 V
HDMI_TX_D[13] V10 output 2.5 V
HDMI_TX_D[14] Y11 output 2.5 V
HDMI_TX_D[15] AA11 output 2.5 V
HDMI_TX_D[16] AD11 output 2.5 V
HDMI_TX_D[17] AE11 output 2.5 V
HDMI_TX_D[18] D12 output 2.5 V
HDMI_TX_D[19] C12 output 2.5 V
HDMI_TX_D[20] T13 output 2.5 V
HDMI_TX_D[21] T12 output 2.5 V
HDMI_TX_D[22] T11 output 2.5 V
HDMI_TX_D[23] U11 output 2.5 V
HDMI_TX_DE V12 output 2.5 V
HDMI_I2C_SCL T8 inout 2.5 V
HDMI_I2C_SDA U9 inout 2.5 V
HDMI_TX_INT D8 input 2.5 V
HDMI_I2S0 AB4 inout 2.5 V

ADC
Name Location Direction IO Standard
ADC_SCK AA20 output 1.5 V
ADC_SDO Y13 input 1.5 V
ADC_SDI AA13 output 1.5 V
ADC_CONVST Y19 output 1.5 V

TMD0
Name Location Direction IO Standard
TMD0_D[0] AH6 inout 2.5 V
TMD0_D[1] AH5 inout 2.5 V
TMD0_D[2] AF7 inout 2.5 V
TMD0_D[3] AG6 inout 2.5 V
TMD0_D[4] AE8 inout 2.5 V
TMD0_D[5] AF9 inout 2.5 V
TMD0_D[6] AG5 inout 2.5 V
TMD0_D[7] AH4 inout 2.5 V

TMD1
Name Location Direction IO Standard
TMD1_D[0] AF11 inout 2.5 V
TMD1_D[1] AF10 inout 2.5 V
TMD1_D[2] AE12 inout 2.5 V
TMD1_D[3] AD12 inout 2.5 V
TMD1_D[4] AD10 inout 2.5 V
TMD1_D[5] AE9 inout 2.5 V
TMD1_D[6] V11 inout 2.5 V
TMD1_D[7] W11 inout 2.5 V

Name Location Direction IO Standard

FPGA
Name Location Direction IO Standard
FPGA_DDR3_CK_p AC22 output Differential 1.5-V SSTL Class I
FPGA_DDR3_CK_n AC23 output Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_p[0] U14 inout Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_p[1] W14 inout Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_p[2] AA19 inout Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_p[3] AD23 inout Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_n[0] U13 inout Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_n[1] V13 inout Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_n[2] AA18 inout Differential 1.5-V SSTL Class I
FPGA_DDR3_DQS_n[3] AE22 inout Differential 1.5-V SSTL Class I
FPGA_CLK1_50 E11 input 2.5 V
FPGA_CLK2_50 Y15 input 1.5 V
FPGA_DDR3_CS_n[0] V15 output SSTL-15 Class I
FPGA_DDR3_CS_n[1] AH11 output SSTL-15 Class I
FPGA_DDR3_ADDR[0] AH24 output SSTL-15 Class I
FPGA_DDR3_ADDR[1] AD26 output SSTL-15 Class I
FPGA_DDR3_ADDR[2] AG25 output SSTL-15 Class I
FPGA_DDR3_ADDR[3] AE23 output SSTL-15 Class I
FPGA_DDR3_ADDR[4] AE26 output SSTL-15 Class I
FPGA_DDR3_ADDR[5] AE24 output SSTL-15 Class I
FPGA_DDR3_ADDR[6] AF28 output SSTL-15 Class I
FPGA_DDR3_ADDR[7] AH26 output SSTL-15 Class I
FPGA_DDR3_ADDR[8] AG28 output SSTL-15 Class I
FPGA_DDR3_ADDR[9] AG26 output SSTL-15 Class I
FPGA_DDR3_ADDR[10] AG18 output SSTL-15 Class I
FPGA_DDR3_ADDR[11] AF27 output SSTL-15 Class I
FPGA_DDR3_ADDR[12] AA23 output SSTL-15 Class I
FPGA_DDR3_ADDR[13] AF25 output SSTL-15 Class I
FPGA_DDR3_ADDR[14] AE25 output SSTL-15 Class I
FPGA_DDR3_ADDR[15] AA15 output SSTL-15 Class I
FPGA_DDR3_BA[0] AG9 output SSTL-15 Class I
FPGA_DDR3_BA[1] AA24 output SSTL-15 Class I
FPGA_DDR3_BA[2] Y17 output SSTL-15 Class I
FPGA_DDR3_CAS_n V16 output SSTL-15 Class I
FPGA_DDR3_CKE[0] AF18 output SSTL-15 Class I
FPGA_DDR3_CKE[1] Y18 output SSTL-15 Class I
FPGA_DDR3_DM[0] AG8 output SSTL-15 Class I
FPGA_DDR3_DM[1] AH12 output SSTL-15 Class I
FPGA_DDR3_DM[2] AF20 output SSTL-15 Class I
FPGA_DDR3_DM[3] AG24 output SSTL-15 Class I
FPGA_DDR3_DQ[0] AG13 inout SSTL-15 Class I
FPGA_DDR3_DQ[1] AF13 inout SSTL-15 Class I
FPGA_DDR3_DQ[2] AH9 inout SSTL-15 Class I
FPGA_DDR3_DQ[3] AE15 inout SSTL-15 Class I
FPGA_DDR3_DQ[4] AG11 inout SSTL-15 Class I
FPGA_DDR3_DQ[5] AF15 inout SSTL-15 Class I
FPGA_DDR3_DQ[6] AH8 inout SSTL-15 Class I
FPGA_DDR3_DQ[7] AG10 inout SSTL-15 Class I
FPGA_DDR3_DQ[8] AH17 inout SSTL-15 Class I
FPGA_DDR3_DQ[9] AD17 inout SSTL-15 Class I
FPGA_DDR3_DQ[10] AF17 inout SSTL-15 Class I
FPGA_DDR3_DQ[11] AE17 inout SSTL-15 Class I
FPGA_DDR3_DQ[12] AG15 inout SSTL-15 Class I
FPGA_DDR3_DQ[13] AH13 inout SSTL-15 Class I
FPGA_DDR3_DQ[14] AG16 inout SSTL-15 Class I
FPGA_DDR3_DQ[15] AH14 inout SSTL-15 Class I
FPGA_DDR3_DQ[16] AG20 inout SSTL-15 Class I
FPGA_DDR3_DQ[17] AE20 inout SSTL-15 Class I
FPGA_DDR3_DQ[18] AH18 inout SSTL-15 Class I
FPGA_DDR3_DQ[19] AD20 inout SSTL-15 Class I
FPGA_DDR3_DQ[20] AH19 inout SSTL-15 Class I
FPGA_DDR3_DQ[21] AD19 inout SSTL-15 Class I
FPGA_DDR3_DQ[22] AG19 inout SSTL-15 Class I
FPGA_DDR3_DQ[23] AE19 inout SSTL-15 Class I
FPGA_DDR3_DQ[24] AH21 inout SSTL-15 Class I
FPGA_DDR3_DQ[25] AH22 inout SSTL-15 Class I
FPGA_DDR3_DQ[26] AG23 inout SSTL-15 Class I
FPGA_DDR3_DQ[27] AF21 inout SSTL-15 Class I
FPGA_DDR3_DQ[28] AG21 inout SSTL-15 Class I
FPGA_DDR3_DQ[29] AF22 inout SSTL-15 Class I
FPGA_DDR3_DQ[30] AF23 inout SSTL-15 Class I
FPGA_DDR3_DQ[31] AH23 inout SSTL-15 Class I
FPGA_DDR3_ODT[0] W15 output SSTL-15 Class I
FPGA_DDR3_ODT[1] Y16 output SSTL-15 Class I
FPGA_DDR3_RAS_n AH16 output SSTL-15 Class I
FPGA_DDR3_RESET_n AH27 output SSTL-15 Class I
FPGA_DDR3_RZQ[0] AH7 input SSTL-15 Class I
FPGA_DDR3_RZQ[1] AF26 input SSTL-15 Class I
FPGA_DDR3_WE_n AG14 output SSTL-15 Class I
FPGA_GPIO[0] Y24 inout 2.5 V
FPGA_GPIO[1] W24 inout 2.5 V
FPGA_GPIO[2] W20 inout 2.5 V
FPGA_GPIO[3] W21 inout 2.5 V
FPGA_GPIO[4] E8 inout 2.5 V

HPS
Name Location Direction IO Standard
HPS_DDR3_ADDR[0] C28 output SSTL-15 Class I
HPS_DDR3_ADDR[1] B28 output SSTL-15 Class I
HPS_DDR3_ADDR[2] E26 output SSTL-15 Class I
HPS_DDR3_ADDR[3] D26 output SSTL-15 Class I
HPS_DDR3_ADDR[4] J21 output SSTL-15 Class I
HPS_DDR3_ADDR[5] J20 output SSTL-15 Class I
HPS_DDR3_ADDR[6] C26 output SSTL-15 Class I
HPS_DDR3_ADDR[7] B26 output SSTL-15 Class I
HPS_DDR3_ADDR[8] F26 output SSTL-15 Class I
HPS_DDR3_ADDR[9] F25 output SSTL-15 Class I
HPS_DDR3_ADDR[10] A24 output SSTL-15 Class I
HPS_DDR3_ADDR[11] B24 output SSTL-15 Class I
HPS_DDR3_ADDR[12] D24 output SSTL-15 Class I
HPS_DDR3_ADDR[13] C24 output SSTL-15 Class I
HPS_DDR3_ADDR[14] G23 output SSTL-15 Class I
HPS_DDR3_ADDR[15] F24 output SSTL-15 Class I
HPS_DDR3_BA[0] A27 output SSTL-15 Class I
HPS_DDR3_BA[1] H25 output SSTL-15 Class I
HPS_DDR3_BA[2] G25 output SSTL-15 Class I
HPS_DDR3_CAS_n A26 output SSTL-15 Class I
HPS_DDR3_CKE[0] L28 output SSTL-15 Class I
HPS_DDR3_CKE[1] K28 output SSTL-15 Class I
HPS_DDR3_CK_n N20 output Differential 1.5-V SSTL Class I
HPS_DDR3_CK_p N21 output Differential 1.5-V SSTL Class I
HPS_DDR3_CS_n[0] L21 output SSTL-15 Class I
HPS_DDR3_CS_n[1] L20 output SSTL-15 Class I
HPS_DDR3_DM[0] G28 output SSTL-15 Class I
HPS_DDR3_DM[1] P28 output SSTL-15 Class I
HPS_DDR3_DM[2] W28 output SSTL-15 Class I
HPS_DDR3_DM[3] AB28 output SSTL-15 Class I
HPS_DDR3_DQ[0] J25 inout SSTL-15 Class I
HPS_DDR3_DQ[1] J24 inout SSTL-15 Class I
HPS_DDR3_DQ[2] E28 inout SSTL-15 Class I
HPS_DDR3_DQ[3] D27 inout SSTL-15 Class I
HPS_DDR3_DQ[4] J26 inout SSTL-15 Class I
HPS_DDR3_DQ[5] K26 inout SSTL-15 Class I
HPS_DDR3_DQ[6] G27 inout SSTL-15 Class I
HPS_DDR3_DQ[7] F28 inout SSTL-15 Class I
HPS_DDR3_DQ[8] K25 inout SSTL-15 Class I
HPS_DDR3_DQ[9] L25 inout SSTL-15 Class I
HPS_DDR3_DQ[10] J27 inout SSTL-15 Class I
HPS_DDR3_DQ[11] J28 inout SSTL-15 Class I
HPS_DDR3_DQ[12] M27 inout SSTL-15 Class I
HPS_DDR3_DQ[13] M26 inout SSTL-15 Class I
HPS_DDR3_DQ[14] M28 inout SSTL-15 Class I
HPS_DDR3_DQ[15] N28 inout SSTL-15 Class I
HPS_DDR3_DQ[16] N24 inout SSTL-15 Class I
HPS_DDR3_DQ[17] N25 inout SSTL-15 Class I
HPS_DDR3_DQ[18] T28 inout SSTL-15 Class I
HPS_DDR3_DQ[19] U28 inout SSTL-15 Class I
HPS_DDR3_DQ[20] N26 inout SSTL-15 Class I
HPS_DDR3_DQ[21] N27 inout SSTL-15 Class I
HPS_DDR3_DQ[22] R27 inout SSTL-15 Class I
HPS_DDR3_DQ[23] V27 inout SSTL-15 Class I
HPS_DDR3_DQ[24] R26 inout SSTL-15 Class I
HPS_DDR3_DQ[25] R25 inout SSTL-15 Class I
HPS_DDR3_DQ[26] AA28 inout SSTL-15 Class I
HPS_DDR3_DQ[27] W26 inout SSTL-15 Class I
HPS_DDR3_DQ[28] R24 inout SSTL-15 Class I
HPS_DDR3_DQ[29] T24 inout SSTL-15 Class I
HPS_DDR3_DQ[30] Y27 inout SSTL-15 Class I
HPS_DDR3_DQ[31] AA27 inout SSTL-15 Class I
HPS_DDR3_DQS_n[0] R16 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[1] R18 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[2] T18 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_n[3] T20 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[0] R17 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[1] R19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[2] T19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_DQS_p[3] U19 inout Differential 1.5-V SSTL Class I
HPS_DDR3_ODT[0] D28 output SSTL-15 Class I
HPS_DDR3_ODT[1] G26 output SSTL-15 Class I
HPS_DDR3_RAS_n A25 output SSTL-15 Class I
HPS_DDR3_RESET_n V28 output SSTL-15 Class I
HPS_DDR3_RZQ D25 input SSTL-15 Class I
HPS_DDR3_WE_n E25 output SSTL-15 Class I
HPS_EMMC_RST_n A5 output 3.3-V LVTTL
HPS_EMMC_SEL B12 inout 3.3-V LVTTL
HPS_ENET_GTX_CLK J15 output 3.3-V LVTTL
HPS_ENET_INT_n B14 inout 3.3-V LVTTL
HPS_ENET_MDC A13 output 3.3-V LVTTL
HPS_ENET_MDIO E16 inout 3.3-V LVTTL
HPS_ENET_RX_CLK J12 input 3.3-V LVTTL
HPS_ENET_RX_DATA[0] A14 input 3.3-V LVTTL
HPS_ENET_RX_DATA[1] A11 input 3.3-V LVTTL
HPS_ENET_RX_DATA[2] C15 input 3.3-V LVTTL
HPS_ENET_RX_DATA[3] A9 input 3.3-V LVTTL
HPS_ENET_RX_DV J13 input 3.3-V LVTTL
HPS_ENET_TX_DATA[0] A16 output 3.3-V LVTTL
HPS_ENET_TX_DATA[1] J14 output 3.3-V LVTTL
HPS_ENET_TX_DATA[2] A15 output 3.3-V LVTTL
HPS_ENET_TX_DATA[3] D17 output 3.3-V LVTTL
HPS_ENET_TX_EN A12 output 3.3-V LVTTL
HPS_FLASH_DATA[0] A8 inout 3.3-V LVTTL
HPS_FLASH_DATA[1] H16 inout 3.3-V LVTTL
HPS_FLASH_DATA[2] A7 inout 3.3-V LVTTL
HPS_FLASH_DATA[3] J16 inout 3.3-V LVTTL
HPS_FLASH_DCLK C14 output 3.3-V LVTTL
HPS_FLASH_NCSO A6 output 3.3-V LVTTL
HPS_RPI_GPIO02 A19 inout 3.3-V LVTTL
HPS_RPI_GPIO03 C18 inout 3.3-V LVTTL
HPS_RPI_GPIO04 A21 inout 3.3-V LVTTL
HPS_RPI_GPIO07 A17 inout 3.3-V LVTTL
HPS_RPI_GPIO08 J17 inout 3.3-V LVTTL
HPS_RPI_GPIO09 B18 inout 3.3-V LVTTL
HPS_RPI_GPIO10 C17 inout 3.3-V LVTTL
HPS_RPI_GPIO11 A18 inout 3.3-V LVTTL
HPS_RPI_GPIO14 C19 inout 3.3-V LVTTL
HPS_RPI_GPIO15 B16 inout 3.3-V LVTTL
HPS_RPI_GPIO17 C21 inout 3.3-V LVTTL
HPS_RPI_GPIO18 K18 inout 3.3-V LVTTL
HPS_RPI_GPIO22 J18 inout 3.3-V LVTTL
HPS_RPI_GPIO23 B19 inout 3.3-V LVTTL
HPS_RPI_GPIO24 C16 inout 3.3-V LVTTL
HPS_RPI_GPIO25 H17 inout 3.3-V LVTTL
HPS_RPI_GPIO27 A20 inout 3.3-V LVTTL
HPS_SDMMC_CLK B8 output 3.3-V LVTTL
HPS_SDMMC_CMD D14 inout 3.3-V LVTTL
HPS_SDMMC_DATA[0] C13 inout 3.3-V LVTTL
HPS_SDMMC_DATA[1] B6 inout 3.3-V LVTTL
HPS_SDMMC_DATA[2] B11 inout 3.3-V LVTTL
HPS_SDMMC_DATA[3] B9 inout 3.3-V LVTTL
HPS_SDMMC_DATA[4] H13 inout 3.3-V LVTTL
HPS_SDMMC_DATA[5] A4 inout 3.3-V LVTTL
HPS_SDMMC_DATA[6] H12 inout 3.3-V LVTTL
HPS_SDMMC_DATA[7] B4 inout 3.3-V LVTTL
HPS_UART_RX A22 input 3.3-V LVTTL
HPS_UART_TX B21 output 3.3-V LVTTL
HPS_USB_CLKOUT G4 input 3.3-V LVTTL
HPS_USB_DATA[0] C10 inout 3.3-V LVTTL
HPS_USB_DATA[1] F5 inout 3.3-V LVTTL
HPS_USB_DATA[2] C9 inout 3.3-V LVTTL
HPS_USB_DATA[3] C4 inout 3.3-V LVTTL
HPS_USB_DATA[4] C8 inout 3.3-V LVTTL
HPS_USB_DATA[5] D4 inout 3.3-V LVTTL
HPS_USB_DATA[6] C7 inout 3.3-V LVTTL
HPS_USB_DATA[7] F4 inout 3.3-V LVTTL
HPS_USB_DIR E5 input 3.3-V LVTTL
HPS_USB_NXT D5 input 3.3-V LVTTL
HPS_USB_STP C5 output 3.3-V LVTTL