DE2_115_SOPC

2014.05.15.09:12:42 Datasheet
Overview
  clk_50  DE2_115_SOPC
Processor
   cpu Nios II 13.1
All Components
   sys_clk_timer altera_avalon_timer 13.1
   jtag_uart altera_avalon_jtag_uart 13.1
   button_pio altera_avalon_pio 13.1
   led_pio altera_avalon_pio 13.1
   touch_panel_pen_irq_n altera_avalon_pio 13.1
   touch_panel_spi altera_avalon_spi 13.1
   av_i2c_data_pio altera_avalon_pio 13.1
   av_i2c_clk_pio altera_avalon_pio 13.1
   alt_vip_mix_0 alt_vip_mix 13.1
   alt_vip_custom_tpg_0 alt_vip_custom_tpg 2.0
   audio_avalon_controller audio_avalon_controller 1.0
   td_reset_pio altera_avalon_pio 13.1
   alt_vip_vfr_0 alt_vip_vfr 13.1
   alt_vip_cts_0 alt_vip_cts 13.1
   sdram altera_avalon_new_sdram_controller 13.1
   sram TERASIC_SRAM 1.0
   altpll_0 altpll 13.1
   multi_touch TERASIC_MULTI_TOUCH 1.0
   cpu altera_nios2_qsys 13.1
   sysid altera_avalon_sysid_qsys 13.1
   cfi_flash altera_generic_tristate_controller 13.1
   alt_vip_scl_0 alt_vip_cl_scl 13.1
   alt_vip_clip_0 alt_vip_cl_clp 13.1
Memory Map
alt_vip_vfb_0 alt_vip_vfr_0 alt_vip_cts_0 alt_vip_vfb_2 cpu
 read_master  write_master  avalon_master  master  read_master  write_master  data_master  instruction_master
  sys_clk_timer
s1  0x09001500
  jtag_uart
avalon_jtag_slave  0x090016d0
  button_pio
s1  0x090015c0
  led_pio
s1  0x090015e0
  touch_panel_pen_irq_n
s1  0x09001600
  touch_panel_spi
spi_control_port  0x09001540
  av_i2c_data_pio
s1  0x09001640
  av_i2c_clk_pio
s1  0x09001620
  alt_vip_mix_0
control  0x09001000 0x09001000
  alt_vip_custom_tpg_0
avalon_slave  0x090016f0 0x090016f0
  audio_avalon_controller
s1  0x09001660
  td_reset_pio
s1  0x090016a0
  alt_vip_vfr_0
avalon_slave  0x09001200 0x09001200
  alt_vip_cts_0
slave  0x09001300
  sdram
s1  0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
  sram
avalon_slave  0x0a200000 0x0a200000
  altpll_0
pll_slave  0x090016e0
  multi_touch
avalon_slave  0x09001400
  cpu
jtag_debug_module  0x09000800 0x09000800
  sysid
control_slave  0x090016c0
  cfi_flash
uas  0x08800000 0x08800000
  alt_vip_scl_0
control  0x08000000 0x08000000
  alt_vip_clip_0
control  0x08000200 0x08000200

clk_50

clock_source v13.1


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sys_clk_timer

altera_avalon_timer v13.1
cpu d_irq   sys_clk_timer
  irq
data_master  
  s1
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 10.0
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 120000000
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0
loadValue 1199999
mult 0
ticksPerSec 100
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 120000000
LOAD_VALUE 1199999
MULT 0.001
PERIOD 10.0
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 100.0
TIMEOUT_PULSE_OUTPUT 0

jtag_uart

altera_avalon_jtag_uart v13.1
cpu d_irq   jtag_uart
  irq
data_master  
  avalon_jtag_slave
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 256
readIRQThreshold 4
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 256
writeIRQThreshold 4
avalonSpec 2.0
legacySignalAllow false
enableInteractiveInput false
enableInteractiveOutput true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

READ_DEPTH 256
READ_THRESHOLD 4
WRITE_DEPTH 256
WRITE_THRESHOLD 4

button_pio

altera_avalon_pio v13.1
cpu d_irq   button_pio
  irq
data_master  
  s1
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
direction Input
edgeType RISING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 15
width 4
clockRate 120000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring true
derived_capture true
derived_edge_type RISING
derived_irq_type EDGE
derived_has_irq true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 15
EDGE_TYPE RISING
FREQ 120000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

led_pio

altera_avalon_pio v13.1
cpu data_master   led_pio
  s1
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
clockRate 120000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 120000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

touch_panel_pen_irq_n

altera_avalon_pio v13.1
cpu d_irq   touch_panel_pen_irq_n
  irq
data_master  
  s1
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 0
width 1
clockRate 120000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring true
derived_capture true
derived_edge_type FALLING
derived_irq_type EDGE
derived_has_irq true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 120000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

touch_panel_spi

altera_avalon_spi v13.1
cpu d_irq   touch_panel_spi
  irq
data_master  
  spi_control_port
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

clockPhase 0
clockPolarity 0
dataWidth 8
disableAvalonFlowControl false
insertDelayBetweenSlaveSelectAndSClk false
insertSync false
lsbOrderedFirst false
masterSPI true
numberOfSlaves 1
syncRegDepth 2
targetClockRate 32000
targetSlaveSelectToSClkDelay 0.0
avalonSpec 2.0
inputClockRate 120000000
actualClockRate 32000.0
actualSlaveSelectToSClkDelay 0.0
legacySignalsAllow false
slaveDataBusWidth 16
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CLOCKMULT 1
CLOCKPHASE 0
CLOCKPOLARITY 0
CLOCKUNITS "Hz"
DATABITS 8
DATAWIDTH 16
DELAYMULT "1.0E-9"
DELAYUNITS "ns"
EXTRADELAY 0
INSERT_SYNC 0
ISMASTER 1
LSBFIRST 0
NUMSLAVES 1
PREFIX "spi_"
SYNC_REG_DEPTH 2
TARGETCLOCK 32000u
TARGETSSDELAY "0.0"

alt_vip_itc_0

alt_vip_itc v13.1
alt_vip_cpr_0 dout1   alt_vip_itc_0
  din
altpll_0 c1  
  is_clk_rst
clk_50 clk_reset  
  is_clk_rst_reset
cpu jtag_debug_module_reset  
  is_clk_rst_reset


Parameters

FAMILY CYCLONEIVE
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
BPS 8
INTERLACED 0
H_ACTIVE_PIXELS 800
V_ACTIVE_LINES 600
ACCEPT_COLOURS_IN_SEQ 0
FIFO_DEPTH 512
CLOCKS_ARE_SAME 0
USE_CONTROL 0
NO_OF_MODES 1
THRESHOLD 0
STD_WIDTH 1
GENERATE_SYNC 0
USE_EMBEDDED_SYNCS 0
AP_LINE 0
V_BLANK 0
H_BLANK 0
H_SYNC_LENGTH 128
H_FRONT_PORCH 40
H_BACK_PORCH 88
V_SYNC_LENGTH 4
V_FRONT_PORCH 1
V_BACK_PORCH 23
F_RISING_EDGE 0
F_FALLING_EDGE 0
FIELD0_V_RISING_EDGE 0
FIELD0_V_BLANK 0
FIELD0_V_SYNC_LENGTH 0
FIELD0_V_FRONT_PORCH 0
FIELD0_V_BACK_PORCH 0
ANC_LINE 0
FIELD0_ANC_LINE 0
AUTO_IS_CLK_RST_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_vfb_0

alt_vip_vfb v13.1
alt_vip_cts_0 dout   alt_vip_vfb_0
  din
altpll_0 c1  
  clock
clk_50 clk_reset  
  reset
cpu jtag_debug_module_reset  
  reset
dout   alt_vip_cpr_0
  din0
read_master   sdram
  s1
write_master  
  s1


Parameters

AUTO_DEVICE_FAMILY CYCLONEIVE
AUTO_READ_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_CLOCKS_SAME 2
AUTO_READ_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_NEED_ADDR_WIDTH 29
AUTO_READ_MASTER_NEED_ADDR_WIDTH 29
AUTO_WRITER_CONTROL_CLOCKS_SAME 0
AUTO_READ_MASTER_CLOCKS_SAME 2
AUTO_READER_CONTROL_CLOCKS_SAME 0
PARAMETERISATION <frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>800</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>480</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>0</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>true</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>true</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>64</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>256</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>64</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>256</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>64</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>0</VFB_DROP_INVALID_FIELDS></frameBufferParams>
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

av_i2c_data_pio

altera_avalon_pio v13.1
cpu data_master   av_i2c_data_pio
  s1
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Bidir
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring true
simDrivenValue 0
width 1
clockRate 120000000
derived_has_tri true
derived_has_out false
derived_has_in false
derived_do_test_bench_wiring true
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 120000000
HAS_IN 0
HAS_OUT 0
HAS_TRI 1
IRQ_TYPE NONE
RESET_VALUE 0

av_i2c_clk_pio

altera_avalon_pio v13.1
cpu data_master   av_i2c_clk_pio
  s1
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 120000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 120000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

alt_vip_mix_0

alt_vip_mix v13.1
cpu data_master   alt_vip_mix_0
  control
jtag_debug_module_reset  
  reset
alt_vip_vfr_0 avalon_streaming_source  
  din_2
alt_vip_cts_0 master  
  control
altpll_0 c1  
  clock
post_fifo_vip_empty_adapter_4 avalon_streaming_source  
  din_0
clk_50 clk_reset  
  reset
alt_vip_scl_0 dout  
  din_1
dout   alt_vip_cts_0
  din


Parameters

AUTO_CONTROL_CLOCKS_SAME 2
AUTO_DEVICE_FAMILY CYCLONEIVE
PARAMETERISATION <mixerParams><MIX_NAME>mixer</MIX_NAME><MIX_ALPHA_ENABLED>false</MIX_ALPHA_ENABLED><MIX_ALPHA_BPS>8</MIX_ALPHA_BPS><MIX_CHANNELS_IN_SEQ>1</MIX_CHANNELS_IN_SEQ><MIX_CHANNELS_IN_PAR>3</MIX_CHANNELS_IN_PAR><MIX_BPS>8</MIX_BPS><MIX_NUM_LAYERS>3</MIX_NUM_LAYERS><MIX_RUNTIME_MAX_WIDTH>800</MIX_RUNTIME_MAX_WIDTH><MIX_RUNTIME_MAX_HEIGHT>480</MIX_RUNTIME_MAX_HEIGHT></mixerParams>
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

alt_vip_custom_tpg_0

alt_vip_custom_tpg v2.0
cpu data_master   alt_vip_custom_tpg_0
  avalon_slave
jtag_debug_module_reset  
  clock_sink_reset
alt_vip_cts_0 master  
  avalon_slave
altpll_0 c1  
  clock_sink
clk_50 clk_reset  
  clock_sink_reset
avalon_streaming_source   fifo_1
  in


Parameters

WIDTH 800
HEIGHT 480
CTRL_PKT_NUM 3
CTRL_PKT_HEADER 15
DATA_PKT_HEADER 0
STATE_CTRL_PKT_SOP 0
STATE_CTRL_PKT_DAT 1
STATE_DATA_PKT_SOP 2
STATE_DATA_PKT_DAT 3
AUTO_CLOCK_SINK_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

fifo_1

altera_avalon_fifo v13.1
altpll_0 c1   fifo_1
  clk_in
alt_vip_custom_tpg_0 avalon_streaming_source  
  in
clk_50 clk_reset  
  reset_in
cpu jtag_debug_module_reset  
  reset_in
out   post_fifo_vip_empty_adapter_4
  avalon_streaming_sink


Parameters

avalonMMAvalonMMDataWidth 32
avalonMMAvalonSTDataWidth 32
bitsPerSymbol 8
channelWidth 0
errorWidth 0
fifoDepth 256
fifoInputInterfaceOptions AVALONST_SINK
fifoOutputInterfaceOptions AVALONST_SOURCE
showHiddenFeatures false
singleClockMode true
singleResetMode false
symbolsPerBeat 3
useBackpressure true
useIRQ true
usePacket true
useReadControl false
useRegister false
useWriteControl false
deviceFamilyString CYCLONEIVE
derived_use_avalonMM_wr_slave false
derived_use_avalonST_sink true
derived_use_avalonMM_rd_slave false
derived_use_avalonST_source true
derived_sink_source_avalonST_width 24
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

AVALONMM_AVALONMM_DATA_WIDTH 32
AVALONMM_AVALONST_DATA_WIDTH 32
BITS_PER_SYMBOL 8
CHANNEL_WIDTH 0
ERROR_WIDTH 0
FIFO_DEPTH 256
SINGLE_CLOCK_MODE 1
SYMBOLS_PER_BEAT 3
USE_AVALONMM_READ_SLAVE 0
USE_AVALONMM_WRITE_SLAVE 0
USE_AVALONST_SINK 1
USE_AVALONST_SOURCE 1
USE_BACKPRESSURE 1
USE_IRQ 1
USE_PACKET 1
USE_READ_CONTROL 0
USE_REGISTER 0
USE_WRITE_CONTROL 0

alt_vip_itc_1

alt_vip_itc v13.1
altpll_0 c1   alt_vip_itc_1
  is_clk_rst
clk_50 clk_reset  
  is_clk_rst_reset
cpu jtag_debug_module_reset  
  is_clk_rst_reset
alt_vip__clp_1 dout  
  din


Parameters

FAMILY CYCLONEIVE
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
BPS 8
INTERLACED 0
H_ACTIVE_PIXELS 800
V_ACTIVE_LINES 480
ACCEPT_COLOURS_IN_SEQ 0
FIFO_DEPTH 512
CLOCKS_ARE_SAME 0
USE_CONTROL 0
NO_OF_MODES 1
THRESHOLD 0
STD_WIDTH 1
GENERATE_SYNC 0
USE_EMBEDDED_SYNCS 0
AP_LINE 0
V_BLANK 0
H_BLANK 0
H_SYNC_LENGTH 30
H_FRONT_PORCH 210
H_BACK_PORCH 16
V_SYNC_LENGTH 13
V_FRONT_PORCH 22
V_BACK_PORCH 10
F_RISING_EDGE 0
F_FALLING_EDGE 0
FIELD0_V_RISING_EDGE 0
FIELD0_V_BLANK 0
FIELD0_V_SYNC_LENGTH 0
FIELD0_V_FRONT_PORCH 0
FIELD0_V_BACK_PORCH 0
ANC_LINE 0
FIELD0_ANC_LINE 0
AUTO_IS_CLK_RST_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

post_fifo_vip_empty_adapter_4

post_fifo_vip_empty_adapter v1.0
altpll_0 c1   post_fifo_vip_empty_adapter_4
  clock_reset
fifo_1 out  
  avalon_streaming_sink
clk_50 clk_reset  
  clock_reset_reset
cpu jtag_debug_module_reset  
  clock_reset_reset
avalon_streaming_source   alt_vip_mix_0
  din_0


Parameters

AUTO_CLOCK_RESET_CLOCK_RATE 120000000
AUTO_DEVICE_FAMILY CYCLONEIVE
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

audio_avalon_controller

audio_avalon_controller v1.0
cpu d_irq   audio_avalon_controller
  irq_s1
data_master  
  s1
jtag_debug_module_reset  
  clock_reset_reset
clk_50 clk  
  clock_reset
clk_reset  
  clock_reset_reset


Parameters

AUTO_CLOCK_RESET_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

td_reset_pio

altera_avalon_pio v13.1
cpu data_master   td_reset_pio
  s1
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 120000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 120000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

alt_vip_vfr_0

alt_vip_vfr v13.1
cpu data_master   alt_vip_vfr_0
  avalon_slave
d_irq  
  interrupt_sender
jtag_debug_module_reset  
  clock_reset_reset
jtag_debug_module_reset  
  clock_master_reset
alt_vip_cts_0 master  
  avalon_slave
altpll_0 c1  
  clock_reset
c1  
  clock_master
clk_50 clk_reset  
  clock_reset_reset
clk_reset  
  clock_master_reset
avalon_streaming_source   alt_vip_mix_0
  din_2
avalon_master   sdram
  s1


Parameters

FAMILY CYCLONEIVE
BITS_PER_PIXEL_PER_COLOR_PLANE 8
NUMBER_OF_CHANNELS_IN_PARALLEL 3
NUMBER_OF_CHANNELS_IN_SEQUENCE 1
MAX_IMAGE_WIDTH 800
MAX_IMAGE_HEIGHT 480
MEM_PORT_WIDTH 32
RMASTER_FIFO_DEPTH 64
RMASTER_BURST_TARGET 32
CLOCKS_ARE_SEPARATE 0
AUTO_CLOCK_RESET_CLOCK_RATE 120000000
AUTO_CLOCK_MASTER_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cts_0

alt_vip_cts v13.1
cpu data_master   alt_vip_cts_0
  slave
d_irq  
  interrupt_sender
jtag_debug_module_reset  
  main_clock_reset
alt_vip_mix_0 dout  
  din
altpll_0 c1  
  main_clock
clk_50 clk_reset  
  main_clock_reset
dout   alt_vip_vfb_0
  din
master   alt_vip_mix_0
  control
master   alt_vip_vfr_0
  avalon_slave
master   alt_vip_custom_tpg_0
  avalon_slave
master   alt_vip_scl_0
  control
master   alt_vip_clip_0
  control


Parameters

FAMILY CYCLONEIVE
BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
TRIGGER_ON_WIDTH_CHANGE 0
TRIGGER_ON_HEIGHT_CHANGE 0
TRIGGER_ON_IMAGE_SOP 1
DISARM_ON_TRIGGER 1
MAX_INSTRUCTION_COUNT 10
AUTO_MAIN_CLOCK_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cpr_0

alt_vip_cpr v13.1
alt_vip_vfb_0 dout   alt_vip_cpr_0
  din0
altpll_0 c1  
  clock
clk_50 clk_reset  
  reset
cpu jtag_debug_module_reset  
  reset
dout1   alt_vip_itc_0
  din
dout0   alt_vip__clp_1
  din


Parameters

AUTO_DEVICE_FAMILY CYCLONEIVE
DIN1_ENABLED 0
DOUT1_SYMBOLS_PER_BEAT 3
DOUT0_SYMBOLS_PER_BEAT 3
DOUT1_ENABLED 1
PARAMETERISATION <colourPatternRearrangerParams><CPR_NAME>Color Plane Sequencer</CPR_NAME><CPR_BPS>8</CPR_BPS><CPR_PORTS><INPUT_PORT><NAME>din0</NAME><STREAMING_DESCRIPTOR>[R:G:B]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED></INPUT_PORT><INPUT_PORT><NAME>din1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED></INPUT_PORT><OUTPUT_PORT><NAME>dout0</NAME><STREAMING_DESCRIPTOR>[R:G:B]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT><OUTPUT_PORT><NAME>dout1</NAME><STREAMING_DESCRIPTOR>[R:G:B]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT></CPR_PORTS><CPR_INPUT_2_PIXELS>false</CPR_INPUT_2_PIXELS></colourPatternRearrangerParams>
DIN0_SYMBOLS_PER_BEAT 3
DIN1_SYMBOLS_PER_BEAT 0
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

sdram

altera_avalon_new_sdram_controller v13.1
cpu instruction_master   sdram
  s1
data_master  
  s1
jtag_debug_module_reset  
  reset
alt_vip_vfr_0 avalon_master  
  s1
alt_vip_vfb_0 read_master  
  s1
write_master  
  s1
altpll_0 c1  
  clk
alt_vip_vfb_2 read_master  
  s1
write_master  
  s1
clk_50 clk_reset  
  reset


Parameters

TAC 5.5
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
columnWidth 10
dataWidth 32
generateSimulationModel true
initRefreshCommands 2
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
rowWidth 13
masteredTristateBridgeSlave 0
TMRD 3
initNOPDelay 0.0
registerDataIn true
clockRate 120000000
componentName DE2_115_SOPC_sdram
size 134217728
addressWidth 25
bankWidth 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CAS_LATENCY 3
CONTENTS_INFO
INIT_NOP_DELAY 0.0
INIT_REFRESH_COMMANDS 2
IS_INITIALIZED 1
POWERUP_DELAY 100.0
REFRESH_PERIOD 15.625
REGISTER_DATA_IN 1
SDRAM_ADDR_WIDTH 25
SDRAM_BANK_WIDTH 2
SDRAM_COL_WIDTH 10
SDRAM_DATA_WIDTH 32
SDRAM_NUM_BANKS 4
SDRAM_NUM_CHIPSELECTS 1
SDRAM_ROW_WIDTH 13
SHARED_DATA 0
SIM_MODEL_BASE 1
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
T_AC 5.5
T_MRD 3
T_RCD 20.0
T_RFC 70.0
T_RP 20.0
T_WR 14.0

sram

TERASIC_SRAM v1.0
cpu instruction_master   sram
  avalon_slave
data_master  
  avalon_slave
jtag_debug_module_reset  
  clock_reset_reset
altpll_0 c1  
  clock_reset
clk_50 clk_reset  
  clock_reset_reset


Parameters

DATA_BITS 16
ADDR_BITS 20
AUTO_CLOCK_RESET_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

altpll_0

altpll v13.1
clk_50 clk   altpll_0
  inclk_interface
clk_reset  
  inclk_interface_reset
cpu data_master  
  pll_slave
jtag_debug_module_reset  
  inclk_interface_reset
c1   cpu
  clk
c1   sram
  clock_reset
c1   sys_clk_timer
  clk
c1   sysid
  clk
c1   jtag_uart
  clk
c1   button_pio
  clk
c1   led_pio
  clk
c1   touch_panel_pen_irq_n
  clk
c1   touch_panel_spi
  clk
c1   av_i2c_clk_pio
  clk
c1   av_i2c_data_pio
  clk
c1   td_reset_pio
  clk
c1   sdram
  clk
c1   alt_vip_vfr_0
  clock_reset
c1  
  clock_master
c1   alt_vip_custom_tpg_0
  clock_sink
c1   fifo_1
  clk_in
c1   post_fifo_vip_empty_adapter_4
  clock_reset
c1   alt_vip_mix_0
  clock
c1   alt_vip_vfb_0
  clock
c1   alt_vip_cpr_0
  clock
c1   alt_vip_itc_0
  is_clk_rst
c1   alt_vip_itc_1
  is_clk_rst
c1   alt_vip_cts_0
  main_clock
c1   alt_vip_cpr_2
  clock
c1   alt_vip_vfb_2
  clock
c1   alt_vip_cti_0
  is_clk_rst
c1   tri_state_bridge_flash_bridge_0
  clk
c1   tri_state_bridge_flash_pinSharer_0
  clk
c1   cfi_flash
  clk
c1   c1
  in_clk
c1   alt_vip_scl_0
  main_clock
c1   alt_vip_clip_0
  main_clock
c1   alt_vip__clp_1
  main_clock


Parameters

HIDDEN_CUSTOM_ELABORATION altpll_avalon_elaboration
HIDDEN_CUSTOM_POST_EDIT altpll_avalon_post_edit
INTENDED_DEVICE_FAMILY Cyclone IV E
WIDTH_CLOCK 5
WIDTH_PHASECOUNTERSELECT
PRIMARY_CLOCK
INCLK0_INPUT_FREQUENCY 20000
INCLK1_INPUT_FREQUENCY
OPERATION_MODE NORMAL
PLL_TYPE AUTO
QUALIFY_CONF_DONE
COMPENSATE_CLOCK CLK0
SCAN_CHAIN
GATE_LOCK_SIGNAL
GATE_LOCK_COUNTER
LOCK_HIGH
LOCK_LOW
VALID_LOCK_MULTIPLIER
INVALID_LOCK_MULTIPLIER
SWITCH_OVER_ON_LOSSCLK
SWITCH_OVER_ON_GATED_LOCK
ENABLE_SWITCH_OVER_COUNTER
SKIP_VCO
SWITCH_OVER_COUNTER
SWITCH_OVER_TYPE
FEEDBACK_SOURCE
BANDWIDTH
BANDWIDTH_TYPE AUTO
SPREAD_FREQUENCY
DOWN_SPREAD
SELF_RESET_ON_GATED_LOSS_LOCK
SELF_RESET_ON_LOSS_LOCK
CLK0_MULTIPLY_BY 12
CLK1_MULTIPLY_BY 12
CLK2_MULTIPLY_BY 3333
CLK3_MULTIPLY_BY 1
CLK4_MULTIPLY_BY 1
CLK5_MULTIPLY_BY
CLK6_MULTIPLY_BY
CLK7_MULTIPLY_BY
CLK8_MULTIPLY_BY
CLK9_MULTIPLY_BY
EXTCLK0_MULTIPLY_BY
EXTCLK1_MULTIPLY_BY
EXTCLK2_MULTIPLY_BY
EXTCLK3_MULTIPLY_BY
CLK0_DIVIDE_BY 5
CLK1_DIVIDE_BY 5
CLK2_DIVIDE_BY 5000
CLK3_DIVIDE_BY 2
CLK4_DIVIDE_BY 2
CLK5_DIVIDE_BY
CLK6_DIVIDE_BY
CLK7_DIVIDE_BY
CLK8_DIVIDE_BY
CLK9_DIVIDE_BY
EXTCLK0_DIVIDE_BY
EXTCLK1_DIVIDE_BY
EXTCLK2_DIVIDE_BY
EXTCLK3_DIVIDE_BY
CLK0_PHASE_SHIFT -1505
CLK1_PHASE_SHIFT 0
CLK2_PHASE_SHIFT 0
CLK3_PHASE_SHIFT 0
CLK4_PHASE_SHIFT 0
CLK5_PHASE_SHIFT
CLK6_PHASE_SHIFT
CLK7_PHASE_SHIFT
CLK8_PHASE_SHIFT
CLK9_PHASE_SHIFT
EXTCLK0_PHASE_SHIFT
EXTCLK1_PHASE_SHIFT
EXTCLK2_PHASE_SHIFT
EXTCLK3_PHASE_SHIFT
CLK0_DUTY_CYCLE 50
CLK1_DUTY_CYCLE 50
CLK2_DUTY_CYCLE 50
CLK3_DUTY_CYCLE 50
CLK4_DUTY_CYCLE 50
CLK5_DUTY_CYCLE
CLK6_DUTY_CYCLE
CLK7_DUTY_CYCLE
CLK8_DUTY_CYCLE
CLK9_DUTY_CYCLE
EXTCLK0_DUTY_CYCLE
EXTCLK1_DUTY_CYCLE
EXTCLK2_DUTY_CYCLE
EXTCLK3_DUTY_CYCLE
PORT_clkena0 PORT_UNUSED
PORT_clkena1 PORT_UNUSED
PORT_clkena2 PORT_UNUSED
PORT_clkena3 PORT_UNUSED
PORT_clkena4 PORT_UNUSED
PORT_clkena5 PORT_UNUSED
PORT_extclkena0
PORT_extclkena1
PORT_extclkena2
PORT_extclkena3
PORT_extclk0 PORT_UNUSED
PORT_extclk1 PORT_UNUSED
PORT_extclk2 PORT_UNUSED
PORT_extclk3 PORT_UNUSED
PORT_CLKBAD0 PORT_UNUSED
PORT_CLKBAD1 PORT_UNUSED
PORT_clk0 PORT_USED
PORT_clk1 PORT_USED
PORT_clk2 PORT_USED
PORT_clk3 PORT_USED
PORT_clk4 PORT_USED
PORT_clk5 PORT_UNUSED
PORT_clk6
PORT_clk7
PORT_clk8
PORT_clk9
PORT_SCANDATA PORT_UNUSED
PORT_SCANDATAOUT PORT_UNUSED
PORT_SCANDONE PORT_UNUSED
PORT_SCLKOUT1
PORT_SCLKOUT0
PORT_ACTIVECLOCK PORT_UNUSED
PORT_CLKLOSS PORT_UNUSED
PORT_INCLK1 PORT_UNUSED
PORT_INCLK0 PORT_USED
PORT_FBIN PORT_UNUSED
PORT_PLLENA PORT_UNUSED
PORT_CLKSWITCH PORT_UNUSED
PORT_ARESET PORT_USED
PORT_PFDENA PORT_UNUSED
PORT_SCANCLK PORT_UNUSED
PORT_SCANACLR PORT_UNUSED
PORT_SCANREAD PORT_UNUSED
PORT_SCANWRITE PORT_UNUSED
PORT_ENABLE0
PORT_ENABLE1
PORT_LOCKED PORT_USED
PORT_CONFIGUPDATE PORT_UNUSED
PORT_FBOUT
PORT_PHASEDONE PORT_UNUSED
PORT_PHASESTEP PORT_UNUSED
PORT_PHASEUPDOWN PORT_UNUSED
PORT_SCANCLKENA PORT_UNUSED
PORT_PHASECOUNTERSELECT PORT_UNUSED
PORT_VCOOVERRANGE
PORT_VCOUNDERRANGE
DPA_MULTIPLY_BY
DPA_DIVIDE_BY
DPA_DIVIDER
VCO_MULTIPLY_BY
VCO_DIVIDE_BY
SCLKOUT0_PHASE_SHIFT
SCLKOUT1_PHASE_SHIFT
VCO_FREQUENCY_CONTROL
VCO_PHASE_SHIFT_STEP
USING_FBMIMICBIDIR_PORT
SCAN_CHAIN_MIF_FILE
AVALON_USE_SEPARATE_SYSCLK NO
HIDDEN_CONSTANTS CT#CLK2_DIVIDE_BY 5000 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 12 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 2 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 1 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT -1505 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 12 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 3333 CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 5 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_USED
HIDDEN_PRIVATES PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 25.00000000 PT#OUTPUT_FREQ3 25.00000000 PT#OUTPUT_FREQ2 33.33000000 PT#OUTPUT_FREQ1 120.00000000 PT#OUTPUT_FREQ0 120.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK e0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR1 1 PT#PHASE_SHIFT0 -65.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 25.000000 PT#EFF_OUTPUT_FREQ_VALUE3 25.000000 PT#EFF_OUTPUT_FREQ_VALUE2 33.330002 PT#EFF_OUTPUT_FREQ_VALUE1 120.000000 PT#EFF_OUTPUT_FREQ_VALUE0 120.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1280373182412473.mif PT#ACTIVECLK_CHECK 0
HIDDEN_USED_PORTS UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
HIDDEN_IS_NUMERIC IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK4_DIVIDE_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
HIDDEN_MF_PORTS MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
HIDDEN_IF_PORTS IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}
HIDDEN_IS_FIRST_EDIT 0
AUTO_INCLK_INTERFACE_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY CYCLONEIVE
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

alt_vip_vfb_2

alt_vip_vfb v13.1
alt_vip_cpr_2 dout0   alt_vip_vfb_2
  din
altpll_0 c1  
  clock
clk_50 clk_reset  
  reset
cpu jtag_debug_module_reset  
  reset
read_master   sdram
  s1
write_master  
  s1
dout   alt_vip_clip_0
  din


Parameters

AUTO_DEVICE_FAMILY CYCLONEIVE
AUTO_READ_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_CLOCKS_SAME 2
AUTO_READ_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_NEED_ADDR_WIDTH 29
AUTO_READ_MASTER_NEED_ADDR_WIDTH 29
AUTO_WRITER_CONTROL_CLOCKS_SAME 0
AUTO_READ_MASTER_CLOCKS_SAME 2
AUTO_READER_CONTROL_CLOCKS_SAME 0
PARAMETERISATION <frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>800</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>600</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>false</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>true</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>true</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>01000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>0</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>512</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>32</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>512</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>32</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>0</VFB_DROP_INVALID_FIELDS></frameBufferParams>
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cti_0

alt_vip_cti v13.1
altpll_0 c1   alt_vip_cti_0
  is_clk_rst
clk_50 clk_reset  
  is_clk_rst_reset
cpu jtag_debug_module_reset  
  is_clk_rst_reset
dout   alt_vip_cpr_2
  din0


Parameters

FAMILY CYCLONEIVE
BPS 8
NUMBER_OF_COLOUR_PLANES 3
COLOUR_PLANES_ARE_IN_PARALLEL 1
SYNC_TO 2
USE_EMBEDDED_SYNCS 0
ADD_DATA_ENABLE_SIGNAL 0
ACCEPT_COLOURS_IN_SEQ 0
USE_STD 0
STD_WIDTH 1
GENERATE_ANC 0
INTERLACED 0
H_ACTIVE_PIXELS_F0 800
V_ACTIVE_LINES_F0 600
V_ACTIVE_LINES_F1 32
FIFO_DEPTH 4800
CLOCKS_ARE_SAME 0
USE_CONTROL 0
GENERATE_SYNC 0
AUTO_IS_CLK_RST_CLOCK_RATE 120000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_cpr_2

alt_vip_cpr v13.1
alt_vip_cti_0 dout   alt_vip_cpr_2
  din0
altpll_0 c1  
  clock
clk_50 clk_reset  
  reset
cpu jtag_debug_module_reset  
  reset
dout0   alt_vip_vfb_2
  din


Parameters

AUTO_DEVICE_FAMILY CYCLONEIVE
DIN1_ENABLED 0
DOUT1_SYMBOLS_PER_BEAT 0
DOUT0_SYMBOLS_PER_BEAT 3
DOUT1_ENABLED 0
PARAMETERISATION <colourPatternRearrangerParams><CPR_NAME>Color Plane Sequencer</CPR_NAME><CPR_BPS>8</CPR_BPS><CPR_PORTS><INPUT_PORT><NAME>din0</NAME><STREAMING_DESCRIPTOR>[B:G:R]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED></INPUT_PORT><INPUT_PORT><NAME>din1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED></INPUT_PORT><OUTPUT_PORT><NAME>dout0</NAME><STREAMING_DESCRIPTOR>[B:G:R]</STREAMING_DESCRIPTOR><ENABLED>true</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT><OUTPUT_PORT><NAME>dout1</NAME><STREAMING_DESCRIPTOR>[Channel]</STREAMING_DESCRIPTOR><ENABLED>false</ENABLED><NON_IMAGE_PACKET_SOURCE>din0</NON_IMAGE_PACKET_SOURCE><HALVE_WIDTH>false</HALVE_WIDTH></OUTPUT_PORT></CPR_PORTS><CPR_INPUT_2_PIXELS>false</CPR_INPUT_2_PIXELS></colourPatternRearrangerParams>
DIN0_SYMBOLS_PER_BEAT 3
DIN1_SYMBOLS_PER_BEAT 0
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

multi_touch

TERASIC_MULTI_TOUCH v1.0
cpu data_master   multi_touch
  avalon_slave
d_irq  
  interrupt_sender
jtag_debug_module_reset  
  reset
clk_50 clk  
  clock
clk_reset  
  reset


Parameters

AUTO_CLOCK_CLOCK_RATE 50000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2_qsys v13.1
altpll_0 c1   cpu
  clk
clk_50 clk_reset  
  reset_n
d_irq   button_pio
  irq
data_master  
  s1
jtag_debug_module_reset  
  reset
d_irq   jtag_uart
  irq
data_master  
  avalon_jtag_slave
jtag_debug_module_reset  
  reset
d_irq   sys_clk_timer
  irq
data_master  
  s1
jtag_debug_module_reset  
  reset
d_irq   touch_panel_pen_irq_n
  irq
data_master  
  s1
jtag_debug_module_reset  
  reset
d_irq   touch_panel_spi
  irq
data_master  
  spi_control_port
jtag_debug_module_reset  
  reset
d_irq   audio_avalon_controller
  irq_s1
data_master  
  s1
jtag_debug_module_reset  
  clock_reset_reset
data_master   sysid
  control_slave
jtag_debug_module_reset  
  reset
data_master   led_pio
  s1
jtag_debug_module_reset  
  reset
data_master   av_i2c_clk_pio
  s1
jtag_debug_module_reset  
  reset
data_master   av_i2c_data_pio
  s1
jtag_debug_module_reset  
  reset
data_master   alt_vip_custom_tpg_0
  avalon_slave
jtag_debug_module_reset  
  clock_sink_reset
data_master   alt_vip_mix_0
  control
jtag_debug_module_reset  
  reset
data_master   td_reset_pio
  s1
jtag_debug_module_reset  
  reset
data_master   alt_vip_vfr_0
  avalon_slave
d_irq  
  interrupt_sender
jtag_debug_module_reset  
  clock_reset_reset
jtag_debug_module_reset  
  clock_master_reset
data_master   alt_vip_cts_0
  slave
d_irq  
  interrupt_sender
jtag_debug_module_reset  
  main_clock_reset
instruction_master   sdram
  s1
data_master  
  s1
jtag_debug_module_reset  
  reset
instruction_master   sram
  avalon_slave
data_master  
  avalon_slave
jtag_debug_module_reset  
  clock_reset_reset
data_master   altpll_0
  pll_slave
jtag_debug_module_reset  
  inclk_interface_reset
data_master   multi_touch
  avalon_slave
d_irq  
  interrupt_sender
jtag_debug_module_reset  
  reset
instruction_master   cfi_flash
  uas
data_master  
  uas
jtag_debug_module_reset  
  reset
jtag_debug_module_reset   alt_vip_itc_0
  is_clk_rst_reset
jtag_debug_module_reset   alt_vip_vfb_0
  reset
jtag_debug_module_reset   fifo_1
  reset_in
jtag_debug_module_reset   alt_vip_itc_1
  is_clk_rst_reset
jtag_debug_module_reset   post_fifo_vip_empty_adapter_4
  clock_reset_reset
jtag_debug_module_reset   alt_vip_cpr_0
  reset
jtag_debug_module_reset   alt_vip_vfb_2
  reset
jtag_debug_module_reset   alt_vip_cti_0
  is_clk_rst_reset
jtag_debug_module_reset   alt_vip_cpr_2
  reset
jtag_debug_module_reset   tri_state_bridge_flash_bridge_0
  reset
jtag_debug_module_reset   tri_state_bridge_flash_pinSharer_0
  reset
jtag_debug_module_reset   alt_vip_scl_0
  main_reset
data_master  
  control
jtag_debug_module_reset   alt_vip_clip_0
  main_reset
data_master  
  control
jtag_debug_module_reset   alt_vip__clp_1
  main_reset


Parameters

setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_bit31BypassDCache true
setting_bigEndian false
setting_export_large_RAMs false
setting_asic_enabled false
setting_asic_synopsys_translate_on_off false
setting_oci_export_jtag_signals false
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTrace_user false
setting_activateTestEndChecker false
setting_ecc_sim_test_ports false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
setting_breakslaveoveride false
muldiv_divider false
mpu_useLimit false
mpu_enabled false
mmu_enabled false
mmu_autoAssignTlbPtrSz true
manuallyAssignCpuID false
debug_triggerArming true
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
dcache_omitDataMaster false
cpuReset false
is_hardcopy_compatible false
setting_shadowRegisterSets 0
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mmu_TLBMissExcOffset 0
debug_jtagInstanceID 0
resetOffset 0
exceptionOffset 32
cpuID 0
cpuID_stored 0
breakOffset 32
userDefinedSettings
resetSlave cfi_flash.uas
mmu_TLBMissExcSlave
exceptionSlave sram.avalon_slave
breakSlave cpu.jtag_debug_module
setting_perfCounterWidth 32
setting_interruptControllerType Internal
setting_branchPredictionType Automatic
setting_bhtPtrSz 8
muldiv_multiplierType EmbeddedMulFast
mpu_minInstRegionSize 12
mpu_minDataRegionSize 12
mmu_uitlbNumEntries 4
mmu_udtlbNumEntries 6
mmu_tlbPtrSz 7
mmu_tlbNumWays 16
mmu_processIDNumBits 8
impl Fast
icache_size 4096
icache_tagramBlockType Automatic
icache_ramBlockType Automatic
icache_numTCIM 0
icache_burstType None
dcache_bursts false
dcache_victim_buf_impl ram
debug_level Level1
debug_OCIOnchipTrace _128
dcache_size 1024
dcache_tagramBlockType Automatic
dcache_ramBlockType Automatic
dcache_numTCDM 0
dcache_lineSize 32
setting_exportvectors false
setting_ecc_present false
setting_ic_ecc_present true
setting_rf_ecc_present true
setting_mmu_ecc_present true
setting_dc_ecc_present false
setting_itcm_ecc_present false
setting_dtcm_ecc_present false
regfile_ramBlockType Automatic
ocimem_ramBlockType Automatic
mmu_ramBlockType Automatic
bht_ramBlockType Automatic
resetAbsoluteAddr 142606336
exceptionAbsoluteAddr 169869344
breakAbsoluteAddr 150997024
mmu_TLBMissExcAbsAddr 0
dcache_bursts_derived false
dcache_size_derived 1024
dcache_lineSize_derived 32
translate_on "synthesis translate_on"
translate_off "synthesis translate_off"
instAddrWidth 28
dataAddrWidth 28
tightlyCoupledDataMaster0AddrWidth 1
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster3AddrWidth 1
instSlaveMapParam <address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='cfi_flash.uas' start='0x8800000' end='0x9000000' /><slave name='cpu.jtag_debug_module' start='0x9000800' end='0x9001000' /><slave name='sram.avalon_slave' start='0xA200000' end='0xA300000' /></address-map>
dataSlaveMapParam <address-map><slave name='sdram.s1' start='0x0' end='0x8000000' /><slave name='alt_vip_scl_0.control' start='0x8000000' end='0x8000200' /><slave name='alt_vip_clip_0.control' start='0x8000200' end='0x8000220' /><slave name='cfi_flash.uas' start='0x8800000' end='0x9000000' /><slave name='cpu.jtag_debug_module' start='0x9000800' end='0x9001000' /><slave name='alt_vip_mix_0.control' start='0x9001000' end='0x9001100' /><slave name='alt_vip_vfr_0.avalon_slave' start='0x9001200' end='0x9001280' /><slave name='alt_vip_cts_0.slave' start='0x9001300' end='0x9001380' /><slave name='multi_touch.avalon_slave' start='0x9001400' end='0x9001480' /><slave name='sys_clk_timer.s1' start='0x9001500' end='0x9001520' /><slave name='touch_panel_spi.spi_control_port' start='0x9001540' end='0x9001560' /><slave name='button_pio.s1' start='0x90015C0' end='0x90015D0' /><slave name='led_pio.s1' start='0x90015E0' end='0x90015F0' /><slave name='touch_panel_pen_irq_n.s1' start='0x9001600' end='0x9001610' /><slave name='av_i2c_clk_pio.s1' start='0x9001620' end='0x9001630' /><slave name='av_i2c_data_pio.s1' start='0x9001640' end='0x9001650' /><slave name='audio_avalon_controller.s1' start='0x9001660' end='0x9001680' /><slave name='td_reset_pio.s1' start='0x90016A0' end='0x90016B0' /><slave name='sysid.control_slave' start='0x90016C0' end='0x90016C8' /><slave name='jtag_uart.avalon_jtag_slave' start='0x90016D0' end='0x90016D8' /><slave name='altpll_0.pll_slave' start='0x90016E0' end='0x90016F0' /><slave name='alt_vip_custom_tpg_0.avalon_slave' start='0x90016F0' end='0x90016F8' /><slave name='sram.avalon_slave' start='0xA200000' end='0xA300000' /></address-map>
clockFrequency 120000000
deviceFamilyName CYCLONEIVE
internalIrqMaskSystemInfo 511
customInstSlavesSystemInfo <info/>
deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 0 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 0 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x09000820
CPU_FREQ 120000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 28
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 1024
EXCEPTION_ADDR 0x0a200020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INITDA_SUPPORTED
INST_ADDR_WIDTH 28
NUM_OF_SHADOW_REG_SETS 0
RESET_ADDR 0x08800000

sysid

altera_avalon_sysid_qsys v13.1
cpu data_master   sysid
  control_slave
jtag_debug_module_reset  
  reset
altpll_0 c1  
  clk
clk_50 clk_reset  
  reset


Parameters

id 0
timestamp 1400116360
AUTO_CLK_CLOCK_RATE 120000000
AUTO_DEVICE_FAMILY CYCLONEIVE
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 1400116360

tri_state_bridge_flash_bridge_0

altera_tristate_conduit_bridge v13.1
altpll_0 c1   tri_state_bridge_flash_bridge_0
  clk
tri_state_bridge_flash_pinSharer_0 tcm  
  tcs
clk_50 clk_reset  
  reset
cpu jtag_debug_module_reset  
  reset


Parameters

INTERFACE_INFO <info><slave name="tcs"><master name="tri_state_bridge_flash_pinSharer_0.tcm"><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="write_n_to_the_cfi_flash" width="1" type="Output" output_name="write_n_to_the_cfi_flash" output_enable_name="" input_name="" /><pin role="read_n_to_the_cfi_flash" width="1" type="Output" output_name="read_n_to_the_cfi_flash" output_enable_name="" input_name="" /><pin role="tri_state_bridge_flash_data" width="8" type="Bidirectional" output_name="tri_state_bridge_flash_data" output_enable_name="tri_state_bridge_flash_data_outen" input_name="tri_state_bridge_flash_data_in" /><pin role="address_to_the_cfi_flash" width="23" type="Output" output_name="address_to_the_cfi_flash" output_enable_name="" input_name="" /><pin role="select_n_to_the_cfi_flash" width="1" type="Output" output_name="select_n_to_the_cfi_flash" output_enable_name="" input_name="" /></master></slave></info>
AUTO_CLK_CLOCK_RATE 120000000
AUTO_DEVICE_FAMILY CYCLONEIVE
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

tri_state_bridge_flash_pinSharer_0

altera_tristate_conduit_pin_sharer v13.1
altpll_0 c1   tri_state_bridge_flash_pinSharer_0
  clk
cfi_flash tcm  
  tcs0
clk_50 clk_reset  
  reset
cpu jtag_debug_module_reset  
  reset
tcm   tri_state_bridge_flash_bridge_0
  tcs


Parameters

INTERFACE_INFO <info><slave name="tcs0"><master name="cfi_flash.tcm"><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="address" width="23" type="Output" output_name="tcm_address_out" output_enable_name="" input_name="" /><pin role="write_n" width="1" type="Output" output_name="tcm_write_n_out" output_enable_name="" input_name="" /><pin role="data" width="8" type="Bidirectional" output_name="tcm_data_out" output_enable_name="tcm_data_outen" input_name="tcm_data_in" /><pin role="read_n" width="1" type="Output" output_name="tcm_read_n_out" output_enable_name="" input_name="" /><pin role="chipselect_n" width="1" type="Output" output_name="tcm_chipselect_n_out" output_enable_name="" input_name="" /></master></slave></info>
NUM_INTERFACES 1
MODULE_ORIGIN_LIST cfi_flash.tcm,cfi_flash.tcm,cfi_flash.tcm,cfi_flash.tcm,cfi_flash.tcm
SIGNAL_ORIGIN_LIST address,read_n,write_n,data,chipselect_n
SIGNAL_ORIGIN_TYPE Output,Output,Output,Bidirectional,Output
SIGNAL_ORIGIN_WIDTH 23,1,1,8,1
SHARED_SIGNAL_LIST address_to_the_cfi_flash,read_n_to_the_cfi_flash,write_n_to_the_cfi_flash,tri_state_bridge_flash_data,select_n_to_the_cfi_flash
SIGNAL_OUTPUT_NAMES tcm_address_out,tcm_read_n_out,tcm_write_n_out,tcm_data_out,tcm_chipselect_n_out
SIGNAL_INPUT_NAMES ,,,tcm_data_in
SIGNAL_OUTPUT_ENABLE_NAMES ,,,tcm_data_outen
REALTIME_MODULE_ORIGIN_LIST cfi_flash.tcm,cfi_flash.tcm,cfi_flash.tcm,cfi_flash.tcm,cfi_flash.tcm
REALTIME_SIGNAL_ORIGIN_LIST address,read_n,write_n,data,chipselect_n
REALTIME_SHARED_SIGNAL_LIST address_to_the_cfi_flash,read_n_to_the_cfi_flash,write_n_to_the_cfi_flash,tri_state_bridge_flash_data,select_n_to_the_cfi_flash
AUTO_CLK_CLOCK_RATE 120000000
AUTO_CLK_CLOCK_DOMAIN 8
AUTO_CLK_RESET_DOMAIN 8
AUTO_TRISTATECONDUIT_MASTERS <info><slave name="tcs0"><master name="cfi_flash.tcm"><port role="write_n_out" direction="output" width="1" /><port role="read_n_out" direction="output" width="1" /><port role="chipselect_n_out" direction="output" width="1" /><port role="request" direction="output" width="1" /><port role="grant" direction="input" width="1" /><port role="address_out" direction="output" width="23" /><port role="data_out" direction="output" width="8" /><port role="data_outen" direction="output" width="1" /><port role="data_in" direction="input" width="8" /></master></slave></info>
AUTO_DEVICE_FAMILY CYCLONEIVE
AUTO_DEVICE EP4CE115F29C7
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)

cfi_flash

altera_generic_tristate_controller v13.1
altpll_0 c1   cfi_flash
  clk
cpu instruction_master  
  uas
data_master  
  uas
jtag_debug_module_reset  
  reset
clk_50 clk_reset  
  reset
tcm   tri_state_bridge_flash_pinSharer_0
  tcs0


Parameters

TCM_ADDRESS_W 23
TCM_DATA_W 8
TCM_BYTEENABLE_W 1
TCM_READ_WAIT 160
TCM_WRITE_WAIT 160
TCM_SETUP_WAIT 60
TCM_DATA_HOLD 60
TCM_MAX_PENDING_READ_TRANSACTIONS 3
TCM_TURNAROUND_TIME 2
TCM_TIMING_UNITS 0
TCM_READLATENCY 2
TCM_SYMBOLS_PER_WORD 1
USE_READDATA 1
USE_WRITEDATA 1
USE_READ 1
USE_WRITE 1
USE_BEGINTRANSFER 0
USE_BYTEENABLE 0
USE_CHIPSELECT 1
USE_LOCK 0
USE_ADDRESS 1
USE_WAITREQUEST 0
USE_WRITEBYTEENABLE 0
USE_OUTPUTENABLE 0
USE_RESETREQUEST 0
USE_IRQ 0
USE_RESET_OUTPUT 0
ACTIVE_LOW_READ 1
ACTIVE_LOW_LOCK 0
ACTIVE_LOW_WRITE 1
ACTIVE_LOW_CHIPSELECT 1
ACTIVE_LOW_BYTEENABLE 0
ACTIVE_LOW_OUTPUTENABLE 0
ACTIVE_LOW_WRITEBYTEENABLE 0
ACTIVE_LOW_WAITREQUEST 0
ACTIVE_LOW_BEGINTRANSFER 0
ACTIVE_LOW_RESETREQUEST 0
ACTIVE_LOW_IRQ 0
ACTIVE_LOW_RESET_OUTPUT 0
CHIPSELECT_THROUGH_READLATENCY 0
IS_MEMORY_DEVICE 1
MODULE_ASSIGNMENT_KEYS embeddedsw.configuration.hwClassnameDriverSupportList,embeddedsw.configuration.hwClassnameDriverSupportDefault,embeddedsw.CMacro.SETUP_VALUE,embeddedsw.CMacro.WAIT_VALUE,embeddedsw.CMacro.HOLD_VALUE,embeddedsw.CMacro.TIMING_UNITS,embeddedsw.CMacro.SIZE,embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH,embeddedsw.memoryInfo.HAS_BYTE_LANE,embeddedsw.memoryInfo.IS_FLASH,embeddedsw.memoryInfo.GENERATE_DAT_SYM,embeddedsw.memoryInfo.GENERATE_FLASH,embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR,embeddedsw.memoryInfo.FLASH_INSTALL_DIR
MODULE_ASSIGNMENT_VALUES altera_avalon_lan91c111:altera_avalon_cfi_flash,altera_avalon_cfi_flash,60,160,60,"ns",8388608u,8,0,1,1,1,SIM_DIR,APP_DIR
INTERFACE_ASSIGNMENT_KEYS embeddedsw.configuration.isFlash,embeddedsw.configuration.isMemoryDevice,embeddedsw.configuration.isNonVolatileStorage
INTERFACE_ASSIGNMENT_VALUES 1,1,1
CLOCK_RATE 120000000
AUTO_CLK_CLOCK_DOMAIN 8
AUTO_CLK_RESET_DOMAIN 8
AUTO_TRISTATECONDUIT_MASTERS
AUTO_DEVICE_FAMILY CYCLONEIVE
AUTO_DEVICE EP4CE115F29C7
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

HOLD_VALUE 60
SETUP_VALUE 60
SIZE 8388608u
TIMING_UNITS "ns"
WAIT_VALUE 160

c1

altera_clock_bridge v13.1
altpll_0 c1   c1
  in_clk


Parameters

DERIVED_CLOCK_RATE 120000000
EXPLICIT_CLOCK_RATE 0
NUM_CLOCK_OUTPUTS 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_scl_0

alt_vip_cl_scl v13.1
altpll_0 c1   alt_vip_scl_0
  main_clock
cpu jtag_debug_module_reset  
  main_reset
data_master  
  control
clk_50 clk_reset  
  main_reset
alt_vip_cts_0 master  
  control
alt_vip_clip_0 dout  
  din
dout   alt_vip_mix_0
  din_1


Parameters

FAMILY CYCLONEIVE
SYMBOLS_IN_SEQ 1
SYMBOLS_IN_PAR 3
BITS_PER_SYMBOL 8
EXTRA_PIPELINING 0
IS_422 0
NO_BLANKING 1
MAX_IN_WIDTH 800
MAX_IN_HEIGHT 480
MAX_OUT_WIDTH 800
MAX_OUT_HEIGHT 480
RUNTIME_CONTROL 1
ALWAYS_DOWNSCALE 0
ALGORITHM_NAME BILINEAR
DEFAULT_EDGE_THRESH 7
DEFAULT_UPPER_BLUR 15
DEFAULT_LOWER_BLUR 0
ENABLE_FIR 0
ARE_IDENTICAL 1
V_TAPS 8
V_PHASES 16
H_TAPS 8
H_PHASES 16
V_SIGNED 1
V_INTEGER_BITS 1
V_FRACTION_BITS 7
H_SIGNED 1
H_INTEGER_BITS 1
H_FRACTION_BITS 7
PRESERVE_BITS 0
LOAD_AT_RUNTIME 0
V_BANKS 1
V_SYMMETRIC 0
V_FUNCTION LANCZOS_2
V_COEFF_FILE <enter file name (including full path)>
H_BANKS 1
H_SYMMETRIC 0
H_FUNCTION LANCZOS_2
H_COEFF_FILE <enter file name (including full path)>
IS_420 0
AUTO_MAIN_CLOCK_CLOCK_RATE 120000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 8
AUTO_MAIN_CLOCK_RESET_DOMAIN 8
AUTO_DEVICE EP4CE115F29C7
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_clip_0

alt_vip_cl_clp v13.1
altpll_0 c1   alt_vip_clip_0
  main_clock
cpu jtag_debug_module_reset  
  main_reset
data_master  
  control
clk_50 clk_reset  
  main_reset
alt_vip_vfb_2 dout  
  din
alt_vip_cts_0 master  
  control
dout   alt_vip_scl_0
  din


Parameters

FAMILY CYCLONEIVE
MAX_IN_WIDTH 800
MAX_IN_HEIGHT 600
BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 3
COLOR_PLANES_ARE_IN_PARALLEL 1
CLIPPING_METHOD RECTANGLE
LEFT_OFFSET 0
RIGHT_OFFSET 10
TOP_OFFSET 60
BOTTOM_OFFSET 10
RECTANGLE_WIDTH 800
RECTANGLE_HEIGHT 480
RUNTIME_CONTROL 1
AUTO_MAIN_CLOCK_CLOCK_RATE 120000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 8
AUTO_MAIN_CLOCK_RESET_DOMAIN 8
AUTO_DEVICE EP4CE115F29C7
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip__clp_1

alt_vip_cl_clp v13.1
altpll_0 c1   alt_vip__clp_1
  main_clock
cpu jtag_debug_module_reset  
  main_reset
clk_50 clk_reset  
  main_reset
alt_vip_cpr_0 dout0  
  din
dout   alt_vip_itc_1
  din


Parameters

FAMILY CYCLONEIVE
MAX_IN_WIDTH 800
MAX_IN_HEIGHT 480
BITS_PER_SYMBOL 8
NUMBER_OF_COLOR_PLANES 3
COLOR_PLANES_ARE_IN_PARALLEL 1
CLIPPING_METHOD RECTANGLE
LEFT_OFFSET 0
RIGHT_OFFSET 10
TOP_OFFSET 0
BOTTOM_OFFSET 10
RECTANGLE_WIDTH 800
RECTANGLE_HEIGHT 480
RUNTIME_CONTROL 0
AUTO_MAIN_CLOCK_CLOCK_RATE 120000000
AUTO_MAIN_CLOCK_CLOCK_DOMAIN 8
AUTO_MAIN_CLOCK_RESET_DOMAIN 8
AUTO_DEVICE EP4CE115F29C7
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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