pcie_ed |
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2023.03.23.17:15:20 | Datasheet |
BAM_INTERPRETER | pcie_ftile_mcdma | |||
AVMM_BAM_Master | p0_d2hdm_master | p0_h2ddm_master | p0_bam_master | |
BAM_INTERPRETER | ||||
AVMM_BAM_Slave | 0x00000000 | |||
emif_fm_ddr4a | ||||
ctrl_amm_0 | 0x0000001000000000 | 0x0000001000000000 | ||
emif_fm_ddr4b | ||||
ctrl_amm_0 | 0x0000001200000000 | 0x0000001200000000 | ||
mem | ||||
s1 | 0x00100000 | |||
s2 | 0x04100000 | 0x00100000 | ||
pio_button | ||||
s1 | 0x04800040 | |||
pio_led | ||||
s1 | 0x04800000 |
pcie_ftile_mcdma | p0_bam_master | BAM_INTERPRETER | |
AVMM_BAM_Slave | |||
app_clk | |||
clock | |||
app_nreset_status | |||
reset | |||
AVMM_BAM_Master | mm_bridge_bar4 | ||
s0 |
Parameters
|
Software Assignments(none) |
emif_fm_ddr4a | emif_calbus | emif_cal_a | |
emif_calbus_0 | |||
emif_calbus_clk | emif_fm_ddr4a | ||
emif_calbus_clk |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
mm_bridge_ddr4a_0 | m0 | emif_fm_ddr4a | |
ctrl_amm_0 | |||
emif_cal_a | emif_calbus_clk | ||
emif_calbus_clk | |||
emif_usr_clk | mm_bridge_ddr4a_0 | ||
clk | |||
emif_usr_reset_n | |||
reset | |||
emif_usr_clk | mm_ccb_ddr4a | ||
m0_clk | |||
emif_usr_reset_n | |||
m0_reset | |||
emif_calbus | emif_cal_a | ||
emif_calbus_0 |
Parameters
|
Software Assignments(none) |
mm_bridge_ddr4b_0 | m0 | emif_fm_ddr4b | |
ctrl_amm_0 | |||
emif_cal_b | emif_calbus_clk | ||
emif_calbus_clk | |||
emif_calbus_0 | |||
emif_calbus | |||
emif_usr_clk | mm_bridge_ddr4b_0 | ||
clk | |||
emif_usr_reset_n | |||
reset | |||
emif_usr_clk | mm_ccb_ddr4b | ||
m0_clk | |||
emif_usr_reset_n | |||
m0_reset |
Parameters
|
Software Assignments(none) |
mm_bridge_bar4 | m0 | mem |
s2 | ||
mm_bridge_onchip_mem | m0 | |
s2 | ||
pcie_ftile_mcdma | p0_d2hdm_master | |
s1 | ||
app_clk | ||
clk1 | ||
app_nreset_status | ||
reset1 |
Parameters
|
Software Assignments
|
BAM_INTERPRETER | AVMM_BAM_Master | mm_bridge_bar4 | |
s0 | |||
pcie_ftile_mcdma | app_clk | ||
clk | |||
app_nreset_status | |||
reset | |||
m0 | pio_button | ||
s1 | |||
m0 | pio_led | ||
s1 | |||
m0 | mem | ||
s2 |
Parameters
|
Software Assignments(none) |
mm_ccb_ddr4a | m0 | mm_bridge_ddr4a_0 | |
s0 | |||
emif_fm_ddr4a | emif_usr_clk | ||
clk | |||
emif_usr_reset_n | |||
reset | |||
m0 | emif_fm_ddr4a | ||
ctrl_amm_0 |
Parameters
|
Software Assignments(none) |
mm_ccb_ddr4b | m0 | mm_bridge_ddr4b_0 | |
s0 | |||
emif_fm_ddr4b | emif_usr_clk | ||
clk | |||
emif_usr_reset_n | |||
reset | |||
m0 | emif_fm_ddr4b | ||
ctrl_amm_0 |
Parameters
|
Software Assignments(none) |
pcie_ftile_mcdma | p0_h2ddm_master | mm_bridge_onchip_mem | |
s0 | |||
app_clk | |||
clk | |||
app_nreset_status | |||
reset | |||
m0 | mem | ||
s2 |
Parameters
|
Software Assignments(none) |
pcie_ftile_mcdma | p0_d2hdm_master | mm_bridge_pcie_rd | |
s0 | |||
app_clk | |||
clk | |||
app_nreset_status | |||
reset | |||
m0 | mm_bridge_pcie_rd_512 | ||
s0 |
Parameters
|
Software Assignments(none) |
mm_bridge_pcie_rd | m0 | mm_bridge_pcie_rd_512 | |
s0 | |||
pcie_ftile_mcdma | app_clk | ||
clk | |||
app_nreset_status | |||
reset | |||
m0 | mm_ccb_ddr4a | ||
s0 | |||
m0 | mm_ccb_ddr4b | ||
s0 |
Parameters
|
Software Assignments(none) |
pcie_ftile_mcdma | p0_h2ddm_master | mm_bridge_pcie_wr | |
s0 | |||
app_clk | |||
clk | |||
app_nreset_status | |||
reset | |||
m0 | mm_bridge_pcie_wr_512 | ||
s0 |
Parameters
|
Software Assignments(none) |
mm_bridge_pcie_wr | m0 | mm_bridge_pcie_wr_512 | |
s0 | |||
pcie_ftile_mcdma | app_clk | ||
clk | |||
app_nreset_status | |||
reset | |||
m0 | mm_ccb_ddr4a | ||
s0 | |||
m0 | mm_ccb_ddr4b | ||
s0 |
Parameters
|
Software Assignments(none) |
mm_bridge_pcie_wr_512 | m0 | mm_ccb_ddr4a | |
s0 | |||
mm_bridge_pcie_rd_512 | m0 | ||
s0 | |||
pcie_ftile_mcdma | app_clk | ||
s0_clk | |||
app_nreset_status | |||
s0_reset | |||
emif_fm_ddr4a | emif_usr_clk | ||
m0_clk | |||
emif_usr_reset_n | |||
m0_reset | |||
m0 | mm_bridge_ddr4a_0 | ||
s0 |
Parameters
|
Software Assignments(none) |
mm_bridge_pcie_wr_512 | m0 | mm_ccb_ddr4b | |
s0 | |||
mm_bridge_pcie_rd_512 | m0 | ||
s0 | |||
pcie_ftile_mcdma | app_clk | ||
s0_clk | |||
app_nreset_status | |||
s0_reset | |||
emif_fm_ddr4b | emif_usr_clk | ||
m0_clk | |||
emif_usr_reset_n | |||
m0_reset | |||
m0 | mm_bridge_ddr4b_0 | ||
s0 |
Parameters
|
Software Assignments(none) |
systemclk_f | out_refclk_fgt_0 | pcie_ftile_mcdma | |
refclk0 | |||
out_refclk_fgt_0 | |||
refclk1 | |||
out_systempll_clk_0 | |||
pcie_systempll_clk | |||
resetIP | ninit_done | ||
ninit_done | |||
p0_bam_master | BAM_INTERPRETER | ||
AVMM_BAM_Slave | |||
app_clk | |||
clock | |||
app_nreset_status | |||
reset | |||
p0_d2hdm_master | mm_bridge_pcie_rd | ||
s0 | |||
app_clk | |||
clk | |||
app_nreset_status | |||
reset | |||
p0_d2hdm_master | mem | ||
s1 | |||
app_clk | |||
clk1 | |||
app_nreset_status | |||
reset1 | |||
p0_h2ddm_master | mm_bridge_onchip_mem | ||
s0 | |||
app_clk | |||
clk | |||
app_nreset_status | |||
reset | |||
p0_h2ddm_master | mm_bridge_pcie_wr | ||
s0 | |||
app_clk | |||
clk | |||
app_nreset_status | |||
reset | |||
app_clk | mm_bridge_bar4 | ||
clk | |||
app_nreset_status | |||
reset | |||
app_clk | pio_led | ||
clk | |||
app_nreset_status | |||
reset | |||
app_clk | pio_button | ||
clk | |||
app_nreset_status | |||
reset | |||
app_clk | mm_bridge_pcie_rd_512 | ||
clk | |||
app_nreset_status | |||
reset | |||
app_clk | mm_bridge_pcie_wr_512 | ||
clk | |||
app_nreset_status | |||
reset | |||
app_clk | mm_ccb_ddr4a | ||
s0_clk | |||
app_nreset_status | |||
s0_reset | |||
app_clk | mm_ccb_ddr4b | ||
s0_clk | |||
app_nreset_status | |||
s0_reset |
Parameters
|
Software Assignments(none) |
mm_bridge_bar4 | m0 | pio_button |
s1 | ||
pcie_ftile_mcdma | app_clk | |
clk | ||
app_nreset_status | ||
reset |
Parameters
|
Software Assignments
|
mm_bridge_bar4 | m0 | pio_led |
s1 | ||
pcie_ftile_mcdma | app_clk | |
clk | ||
app_nreset_status | ||
reset |
Parameters
|
Software Assignments
|
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
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