pcie_ftile_mcdma

2023.03.23.17:15:39 Datasheet
Overview

Memory Map
pcie_ftile_mcdma
 p0_d2hdm_master  p0_h2ddm_master  p0_bam_master

pcie_ftile_mcdma

intel_pcie_ftile_mcdma v4.0.0


Parameters

enable_example_design_sim_hwtcl 1
enable_example_design_synth_hwtcl 1
select_design_example_rtl_lang_hwtcl Verilog
example_design_mode_hwtcl PIO/SRIOV
chosen_devkit_hwtcl NONE
top_topology_hwtcl Gen4 1x8, Interface - 256 bit
total_core_num_hwtcl 1
virtual_rp_ep_mode_hwtcl Native Endpoint
xcvr_reconfig_user_hwtcl 0
ftile_debug_toolkit_hwtcl 0
g4_pld_clkfreq_user_hwtcl 350MHz
virtual_sris_enable_en_hwtcl 0
core16_enable_power_mgnt_intf_hwtcl 0
core16_enable_legacy_int_hwtcl 0
core16_enable_cii_hwtcl 0
core16_enable_prs_event_hwtcl 0
core16_enable_10bit_tag_support_intf_hwtcl 0
core16_pf0_gen3_eq_pset_req_vec_b0_user_hwtcl 1023
core16_pf0_gen3_eq_pset_req_vec_atg4_b0_user_hwtcl 1023
core16_virtual_num_of_lanes_8_hwtcl 8
core16_enable_rx_buffer_limit_ports_hwtcl 1
core16_virtual_maxpayload_size_hwtcl 512
core16_pcie_cvp_attr_hwtcl 0
core16_user_vsec_cap_enable_hwtcl 0
core16_pf0_pcie_cap_port_num_hwtcl 1
core16_cap_slot_clk_config_hwtcl 1
core16_virtual_pf0_msi_enable_user_hwtcl 0
core16_virtual_pf0_msix_enable_user_hwtcl 1
core16_pf0_pci_msix_table_size_hwtcl 15
core16_pf0_pci_msix_table_offset_hwtcl 131072
core16_pf0_pci_msix_bir_hwtcl 0
core16_pf0_pci_msix_pba_offset_hwtcl 196608
core16_pf0_pci_msix_pba_hwtcl 0
core16_exvf_msix_tablesize_pf0 0
core16_exvf_msixtable_offset_pf0 0
core16_exvf_msixtable_bir_pf0 0
core16_exvf_msixpba_offset_pf0 0
core16_exvf_msixpba_bir_pf0 0
core16_exvf_msix_tablesize_pf1 0
core16_exvf_msixtable_offset_pf1 0
core16_exvf_msixtable_bir_pf1 0
core16_exvf_msixpba_offset_pf1 0
core16_exvf_msixpba_bir_pf1 0
core16_exvf_msix_tablesize_pf2 0
core16_exvf_msixtable_offset_pf2 0
core16_exvf_msixtable_bir_pf2 0
core16_exvf_msixpba_offset_pf2 0
core16_exvf_msixpba_bir_pf2 0
core16_exvf_msix_tablesize_pf3 0
core16_exvf_msixtable_offset_pf3 0
core16_exvf_msixtable_bir_pf3 0
core16_exvf_msixpba_offset_pf3 0
core16_exvf_msixpba_bir_pf3 0
core16_exvf_msix_tablesize_pf4 0
core16_exvf_msixtable_offset_pf4 0
core16_exvf_msixtable_bir_pf4 0
core16_exvf_msixpba_offset_pf4 0
core16_exvf_msixpba_bir_pf4 0
core16_exvf_msix_tablesize_pf5 0
core16_exvf_msixtable_offset_pf5 0
core16_exvf_msixtable_bir_pf5 0
core16_exvf_msixpba_offset_pf5 0
core16_exvf_msixpba_bir_pf5 0
core16_exvf_msix_tablesize_pf6 0
core16_exvf_msixtable_offset_pf6 0
core16_exvf_msixtable_bir_pf6 0
core16_exvf_msixpba_offset_pf6 0
core16_exvf_msixpba_bir_pf6 0
core16_exvf_msix_tablesize_pf7 0
core16_exvf_msixtable_offset_pf7 0
core16_exvf_msixtable_bir_pf7 0
core16_exvf_msixpba_offset_pf7 0
core16_exvf_msixpba_bir_pf7 0
core16_pf0_pcie_slot_imp_hwtcl 0
core16_pf0_pcie_cap_slot_power_limit_scale_hwtcl 0
core16_pf0_pcie_cap_slot_power_limit_value_hwtcl 0
core16_pf0_pcie_cap_phy_slot_num_hwtcl 0
core16_user_pcie_cap_ep_l0s_accpt_latency_hwtcl 0
core16_user_pcie_cap_ep_l1_accpt_latency_hwtcl 0
core16_virtual_pf0_prs_ext_cap_enable_hwtcl 0
core16_virtual_sn_cap_enable_hwtcl 0
core16_sn_ser_num_reg_1_dw_hwtcl 0
core16_sn_ser_num_reg_2_dw_hwtcl 0
core16_virtual_pf0_pasid_cap_enable_hwtcl 0
core16_virtual_pf0_ltr_cap_enable_hwtcl 0
core16_virtual_ptm_hwtcl 0
core16_cfg_ptm_auto_update_period_hwtcl Disable
core16_pf0_pci_type0_vendor_id_hwtcl 4466
core16_pf0_pci_type0_device_id_hwtcl 2500
core16_pf0_revision_id_hwtcl 1
core16_pf0_class_code_hwtcl 16711680
core16_pf0_subsys_vendor_id_hwtcl 0
core16_pf0_subsys_dev_id_hwtcl 0
core16_exvf_subsysid_pf0 0
core16_exvf_subsysid_pf1 0
core16_exvf_subsysid_pf2 0
core16_exvf_subsysid_pf3 0
core16_exvf_subsysid_pf4 0
core16_exvf_subsysid_pf5 0
core16_exvf_subsysid_pf6 0
core16_exvf_subsysid_pf7 0
core16_cvp_user_id_hwtcl 0
core16_virtual_drop_vendor0_msg_hwtcl 0
core16_virtual_drop_vendor1_msg_hwtcl 0
core16_pf0_int_pin_hwtcl NO INT
core16_pf0_bar0_type_user_hwtcl 64-bit prefetchable memory
core16_pf0_bar0_address_width_user_hwtcl 22
core16_enable_multi_func_hwtcl 0
core16_enable_sriov_hwtcl 0
core16_virtual_pf0_ats_cap_enable_hwtcl 0
core16_virtual_pf0_tph_cap_enable_hwtcl 0
core16_virtual_pf0_acs_cap_enable_hwtcl 0
core16_pf0_virtio_capability_present_hwtcl 0
core16_pf0_virtio_device_specific_cap_present_hwtcl 0
core16_pf0_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf0_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf0_virtio_cmn_config_structure_length_hwtcl 0
core16_pf0_virtio_notification_bar_indicator_hwtcl 0
core16_pf0_virtio_notification_bar_offset_hwtcl 0
core16_pf0_virtio_notification_structure_length_hwtcl 0
core16_pf0_virtio_notify_off_multiplier_hwtcl 0
core16_pf0_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf0_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf0_virtio_isrstatus_structure_length_hwtcl 0
core16_pf0_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf0_virtio_devspecific_bar_offset_hwtcl 0
core16_pf0_virtio_devspecific_structure_length_hwtcl 0
core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf0_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf0vf_virtio_capability_present_hwtcl 0
core16_pf0vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf0vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf0vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf0vf_virtio_notification_bar_offset_hwtcl 0
core16_pf0vf_virtio_notification_structure_length_hwtcl 0
core16_pf0vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf0vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf0vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf0vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf1vf_virtio_capability_present_hwtcl 0
core16_pf1vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf1vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf1vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf1vf_virtio_notification_bar_offset_hwtcl 0
core16_pf1vf_virtio_notification_structure_length_hwtcl 0
core16_pf1vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf1vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf1vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf1vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf2vf_virtio_capability_present_hwtcl 0
core16_pf2vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf2vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf2vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf2vf_virtio_notification_bar_offset_hwtcl 0
core16_pf2vf_virtio_notification_structure_length_hwtcl 0
core16_pf2vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf2vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf2vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf2vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf3vf_virtio_capability_present_hwtcl 0
core16_pf3vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf3vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf3vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf3vf_virtio_notification_bar_offset_hwtcl 0
core16_pf3vf_virtio_notification_structure_length_hwtcl 0
core16_pf3vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf3vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf3vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf3vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf4vf_virtio_capability_present_hwtcl 0
core16_pf4vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf4vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf4vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf4vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf4vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf4vf_virtio_notification_bar_offset_hwtcl 0
core16_pf4vf_virtio_notification_structure_length_hwtcl 0
core16_pf4vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf4vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf4vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf4vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf4vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf4vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf4vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf4vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf4vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf4vf_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf5vf_virtio_capability_present_hwtcl 0
core16_pf5vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf5vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf5vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf5vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf5vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf5vf_virtio_notification_bar_offset_hwtcl 0
core16_pf5vf_virtio_notification_structure_length_hwtcl 0
core16_pf5vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf5vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf5vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf5vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf5vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf5vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf5vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf5vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf5vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf5vf_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf6vf_virtio_capability_present_hwtcl 0
core16_pf6vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf6vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf6vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf6vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf6vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf6vf_virtio_notification_bar_offset_hwtcl 0
core16_pf6vf_virtio_notification_structure_length_hwtcl 0
core16_pf6vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf6vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf6vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf6vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf6vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf6vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf6vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf6vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf6vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf6vf_virtio_pciconfig_access_structure_length_hwtcl 0
core16_pf7vf_virtio_capability_present_hwtcl 0
core16_pf7vf_virtio_device_specific_cap_present_hwtcl 0
core16_pf7vf_virtio_cmn_config_bar_indicator_hwtcl 0
core16_pf7vf_virtio_cmn_config_bar_offset_hwtcl 0
core16_pf7vf_virtio_cmn_config_structure_length_hwtcl 0
core16_pf7vf_virtio_notification_bar_indicator_hwtcl 0
core16_pf7vf_virtio_notification_bar_offset_hwtcl 0
core16_pf7vf_virtio_notification_structure_length_hwtcl 0
core16_pf7vf_virtio_notify_off_multiplier_hwtcl 0
core16_pf7vf_virtio_isrstatus_bar_indicator_hwtcl 0
core16_pf7vf_virtio_isrstatus_bar_offset_hwtcl 0
core16_pf7vf_virtio_isrstatus_structure_length_hwtcl 0
core16_pf7vf_virtio_devspecific_bar_indicator_hwtcl 0
core16_pf7vf_virtio_devspecific_bar_offset_hwtcl 0
core16_pf7vf_virtio_devspecific_structure_length_hwtcl 0
core16_pf7vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
core16_pf7vf_virtio_pciconfig_access_bar_offset_hwtcl 0
core16_pf7vf_virtio_pciconfig_access_structure_length_hwtcl 0
duplex_mode DISABLE
virtual_sup_mode USER_MODE
topology PCIE_X16
ctop_ctrltop_r_hrc_rst_ctrl_k_hrc_pin_perst_is_full_rst_attr CTOP_CTRLTOP_R_HRC_RST_CTRL_K_HRC_PIN_PERST_IS_FULL_RST_ATTR_1
ctop_core16_clrhip_not_rst_sticky FALSE
pcie_cvp_attr PCIE_CVP_ATTR_DISABLE
ctop_core16_cvp_user_id 0
ctop_core16_exvf_msix_tablesize_pf0 0
ctop_core16_exvf_msix_tablesize_pf1 0
ctop_core16_exvf_msix_tablesize_pf2 0
ctop_core16_exvf_msix_tablesize_pf3 0
ctop_core16_exvf_msix_tablesize_pf4 0
ctop_core16_exvf_msix_tablesize_pf5 0
ctop_core16_exvf_msix_tablesize_pf6 0
ctop_core16_exvf_msix_tablesize_pf7 0
ctop_core16_exvf_msixpba_bir_pf0 0
ctop_core16_exvf_msixpba_bir_pf1 0
ctop_core16_exvf_msixpba_bir_pf2 0
ctop_core16_exvf_msixpba_bir_pf3 0
ctop_core16_exvf_msixpba_bir_pf4 0
ctop_core16_exvf_msixpba_bir_pf5 0
ctop_core16_exvf_msixpba_bir_pf6 0
ctop_core16_exvf_msixpba_bir_pf7 0
ctop_core16_exvf_msixpba_offset_pf0 0
ctop_core16_exvf_msixpba_offset_pf1 0
ctop_core16_exvf_msixpba_offset_pf2 0
ctop_core16_exvf_msixpba_offset_pf3 0
ctop_core16_exvf_msixpba_offset_pf4 0
ctop_core16_exvf_msixpba_offset_pf5 0
ctop_core16_exvf_msixpba_offset_pf6 0
ctop_core16_exvf_msixpba_offset_pf7 0
ctop_core16_exvf_msixtable_bir_pf0 0
ctop_core16_exvf_msixtable_bir_pf1 0
ctop_core16_exvf_msixtable_bir_pf2 0
ctop_core16_exvf_msixtable_bir_pf3 0
ctop_core16_exvf_msixtable_bir_pf4 0
ctop_core16_exvf_msixtable_bir_pf5 0
ctop_core16_exvf_msixtable_bir_pf6 0
ctop_core16_exvf_msixtable_bir_pf7 0
ctop_core16_exvf_msixtable_offset_pf0 0
ctop_core16_exvf_msixtable_offset_pf1 0
ctop_core16_exvf_msixtable_offset_pf2 0
ctop_core16_exvf_msixtable_offset_pf3 0
ctop_core16_exvf_msixtable_offset_pf4 0
ctop_core16_exvf_msixtable_offset_pf5 0
ctop_core16_exvf_msixtable_offset_pf6 0
ctop_core16_exvf_msixtable_offset_pf7 0
ctop_core16_exvf_subsysid_pf0 0
ctop_core16_exvf_subsysid_pf1 0
ctop_core16_exvf_subsysid_pf2 0
ctop_core16_exvf_subsysid_pf3 0
ctop_core16_exvf_subsysid_pf4 0
ctop_core16_exvf_subsysid_pf5 0
ctop_core16_exvf_subsysid_pf6 0
ctop_core16_exvf_subsysid_pf7 0
ctop_core16_exvf_ats_pagealignreq_pf0 FALSE
ctop_core16_exvf_ats_pagealignreq_pf1 FALSE
ctop_core16_exvf_ats_pagealignreq_pf2 FALSE
ctop_core16_exvf_ats_pagealignreq_pf3 FALSE
ctop_core16_exvf_ats_pagealignreq_pf4 FALSE
ctop_core16_exvf_ats_pagealignreq_pf5 FALSE
ctop_core16_exvf_ats_pagealignreq_pf6 FALSE
ctop_core16_exvf_ats_pagealignreq_pf7 FALSE
ctop_core16_pf0_acs_cap_acs_at_block DISABLE
ctop_core16_pf0_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf0_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf0_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf0_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf0_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf0_acs_cap_acs_src_valid DISABLE
ctop_core16_pf0_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf0_auto_lane_flip_ctrl_en ENABLE
ctop_core16_pf0_bar0_prefetch FALSE
ctop_core16_pf0_bar0_type CTOP_CORE16_PF0_BAR0_MEM32
ctop_core16_pf0_bar1_prefetch FALSE
ctop_core16_pf0_bar2_prefetch FALSE
ctop_core16_pf0_bar2_type CTOP_CORE16_PF0_BAR2_MEM32
ctop_core16_pf0_bar3_prefetch FALSE
ctop_core16_pf0_bar4_prefetch FALSE
ctop_core16_pf0_bar4_type CTOP_CORE16_PF0_BAR4_MEM32
ctop_core16_pf0_bar5_prefetch FALSE
ctop_core16_pf0_base_class_code 0
ctop_core16_pf0_eq_redo ENABLE
ctop_core16_pf0_eq_redo_atg4 ENABLE
ctop_core16_pf0_int_pin CTOP_CORE16_PF0_INTA
ctop_core16_pf0_gen3_eq_pset_req_vec 4
ctop_core16_pf0_gen3_eq_pset_req_vec_atg4 624
ctop_core16_pf0_loopback_enable FALSE
ctop_core16_pf0_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf0_pasid_cap_max_pasid_width 0
ctop_core16_pf0_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf0_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf0_pci_msi_ext_data_cap TRUE
ctop_core16_pf0_pci_msi_multiple_msg_cap CTOP_CORE16_PF0_MSI_VEC_32
ctop_core16_pf0_pci_msix_bir 0
ctop_core16_pf0_pci_msix_pba 0
ctop_core16_pf0_pci_msix_pba_offset 0
ctop_core16_pf0_pci_msix_table_offset 0
ctop_core16_pf0_pci_msix_table_size 255
ctop_core16_pf0_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf0_pci_type0_bar0_enabled ENABLE
ctop_core16_pf0_pci_type0_bar1_enabled ENABLE
ctop_core16_pf0_pci_type0_bar2_enabled ENABLE
ctop_core16_pf0_pci_type0_bar3_enabled ENABLE
ctop_core16_pf0_pci_type0_bar4_enabled ENABLE
ctop_core16_pf0_pci_type0_bar5_enabled ENABLE
ctop_core16_pf0_pci_type0_device_id 43981
ctop_core16_pf0_pci_type0_vendor_id 5827
ctop_core16_pf0_pcie_cap_attention_indicator FALSE
ctop_core16_pf0_pcie_cap_attention_indicator_button FALSE
ctop_core16_pf0_pcie_cap_electromech_interlock FALSE
ctop_core16_pf0_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf0_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf0_pcie_cap_ext_tag_supp CTOP_CORE16_PF0_SUPPORTED
ctop_core16_pf0_pcie_cap_flr_cap CTOP_CORE16_PF0_CAPABLE
ctop_core16_pf0_pcie_cap_hot_plug_capable FALSE
ctop_core16_pf0_pcie_cap_hot_plug_surprise FALSE
ctop_core16_pf0_pcie_cap_mrl_sensor FALSE
ctop_core16_pf0_pcie_cap_no_cmd_cpl_support FALSE
ctop_core16_pf0_pcie_cap_phy_slot_num 0
ctop_core16_pf0_pcie_cap_port_num 0
ctop_core16_pf0_pcie_cap_power_controller FALSE
ctop_core16_pf0_pcie_cap_power_indicator FALSE
ctop_core16_pf0_pcie_cap_sel_deemphasis CTOP_CORE16_PF0_MINUS_6DB
ctop_core16_pf0_pcie_cap_slot_clk_config FALSE
ctop_core16_pf0_pcie_cap_slot_power_limit_scale 0
ctop_core16_pf0_pcie_cap_slot_power_limit_value 0
ctop_core16_pf0_pcie_slot_imp CTOP_CORE16_PF0_NOT_IMPLEMENTED
ctop_core16_pf0_pme_support 27
ctop_core16_pf0_program_interface 0
ctop_core16_pf0_revision_id 1
ctop_core16_pf0_rom_bar_enabled ENABLE
ctop_core16_pf0_rp_rom_bar_enabled ENABLE
ctop_core16_pf0_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf0_sriov_sup_page_size 1363
ctop_core16_pf0_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf0_sriov_vf_bar0_type CTOP_CORE16_PF0_SRIOV_VF_BAR0_MEM32
ctop_core16_pf0_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf0_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf0_sriov_vf_bar2_type CTOP_CORE16_PF0_SRIOV_VF_BAR2_MEM32
ctop_core16_pf0_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf0_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf0_sriov_vf_bar4_type CTOP_CORE16_PF0_SRIOV_VF_BAR4_MEM32
ctop_core16_pf0_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf0_sriov_vf_device_id 43981
ctop_core16_pf0_sriov_vf_offset_ari_cs2 2
ctop_core16_pf0_sriov_vf_offset_nonari 256
ctop_core16_pf0_sriov_vf_stride_nonari 256
ctop_core16_pf0_subclass_code 0
ctop_core16_pf0_subsys_dev_id 0
ctop_core16_pf0_subsys_vendor_id 0
ctop_core16_pf0_tph_req_cap_int_vec DISABLE
ctop_core16_pf0_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF0_IN_TPH_STRUCT_VF
ctop_core16_pf0_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF0_NOT_IN_MSIX_TABLE
ctop_core16_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF0_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf0_tph_req_cap_st_table_size 1
ctop_core16_pf0_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf0_tph_req_device_spec DISABLE
ctop_core16_pf0_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf0_prs_outstanding_capacity 0
ctop_core16_pf1_acs_cap_acs_at_block DISABLE
ctop_core16_pf1_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf1_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf1_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf1_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf1_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf1_acs_cap_acs_src_valid DISABLE
ctop_core16_pf1_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf1_bar0_prefetch FALSE
ctop_core16_pf1_bar0_type CTOP_CORE16_PF1_BAR0_MEM32
ctop_core16_pf1_bar1_prefetch FALSE
ctop_core16_pf1_bar2_prefetch FALSE
ctop_core16_pf1_bar2_type CTOP_CORE16_PF1_BAR2_MEM32
ctop_core16_pf1_bar3_prefetch FALSE
ctop_core16_pf1_bar4_prefetch FALSE
ctop_core16_pf1_bar4_type CTOP_CORE16_PF1_BAR4_MEM32
ctop_core16_pf1_bar5_prefetch FALSE
ctop_core16_pf1_base_class_code 0
ctop_core16_pf1_int_pin CTOP_CORE16_PF1_INTA
ctop_core16_pf1_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf1_pasid_cap_max_pasid_width 0
ctop_core16_pf1_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf1_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf1_pci_msi_ext_data_cap TRUE
ctop_core16_pf1_pci_msi_multiple_msg_cap CTOP_CORE16_PF1_MSI_VEC_32
ctop_core16_pf1_pci_msix_bir 0
ctop_core16_pf1_pci_msix_pba 0
ctop_core16_pf1_pci_msix_pba_offset 0
ctop_core16_pf1_pci_msix_table_offset 0
ctop_core16_pf1_pci_msix_table_size 255
ctop_core16_pf1_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf1_pci_type0_bar0_enabled ENABLE
ctop_core16_pf1_pci_type0_bar1_enabled ENABLE
ctop_core16_pf1_pci_type0_bar2_enabled ENABLE
ctop_core16_pf1_pci_type0_bar3_enabled ENABLE
ctop_core16_pf1_pci_type0_bar4_enabled ENABLE
ctop_core16_pf1_pci_type0_bar5_enabled ENABLE
ctop_core16_pf1_pci_type0_device_id 43981
ctop_core16_pf1_pci_type0_vendor_id 5827
ctop_core16_pf1_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf1_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf1_pcie_cap_ext_tag_supp CTOP_CORE16_PF1_SUPPORTED
ctop_core16_pf1_pcie_cap_flr_cap CTOP_CORE16_PF1_CAPABLE
ctop_core16_pf1_pcie_cap_slot_clk_config FALSE
ctop_core16_pf1_pme_support 27
ctop_core16_pf1_program_interface 0
ctop_core16_pf1_revision_id 1
ctop_core16_pf1_rom_bar_enabled ENABLE
ctop_core16_pf1_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf1_sriov_sup_page_size 1363
ctop_core16_pf1_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf1_sriov_vf_bar0_type CTOP_CORE16_PF1_SRIOV_VF_BAR0_MEM32
ctop_core16_pf1_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf1_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf1_sriov_vf_bar2_type CTOP_CORE16_PF1_SRIOV_VF_BAR2_MEM32
ctop_core16_pf1_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf1_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf1_sriov_vf_bar4_type CTOP_CORE16_PF1_SRIOV_VF_BAR4_MEM32
ctop_core16_pf1_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf1_sriov_vf_device_id 43981
ctop_core16_pf1_sriov_vf_offset_ari_cs2 2
ctop_core16_pf1_sriov_vf_offset_position_nonari 256
ctop_core16_pf1_sriov_vf_stride_nonari 256
ctop_core16_pf1_subclass_code 0
ctop_core16_pf1_subsys_dev_id 0
ctop_core16_pf1_subsys_vendor_id 0
ctop_core16_pf1_tph_req_cap_int_vec DISABLE
ctop_core16_pf1_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF1_IN_TPH_STRUCT_VF
ctop_core16_pf1_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF1_NOT_IN_MSIX_TABLE
ctop_core16_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF1_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf1_tph_req_cap_st_table_size 1
ctop_core16_pf1_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf1_tph_req_device_spec DISABLE
ctop_core16_pf1_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf1_prs_outstanding_capacity 0
ctop_core16_pf2_acs_cap_acs_at_block DISABLE
ctop_core16_pf2_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf2_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf2_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf2_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf2_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf2_acs_cap_acs_src_valid DISABLE
ctop_core16_pf2_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf2_bar0_prefetch FALSE
ctop_core16_pf2_bar0_type CTOP_CORE16_PF2_BAR0_MEM32
ctop_core16_pf2_bar1_prefetch FALSE
ctop_core16_pf2_bar2_prefetch FALSE
ctop_core16_pf2_bar2_type CTOP_CORE16_PF2_BAR2_MEM32
ctop_core16_pf2_bar3_prefetch FALSE
ctop_core16_pf2_bar4_prefetch FALSE
ctop_core16_pf2_bar4_type CTOP_CORE16_PF2_BAR4_MEM32
ctop_core16_pf2_bar5_prefetch FALSE
ctop_core16_pf2_base_class_code 0
ctop_core16_pf2_int_pin CTOP_CORE16_PF2_INTA
ctop_core16_pf2_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf2_pasid_cap_max_pasid_width 0
ctop_core16_pf2_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf2_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf2_pci_msi_ext_data_cap TRUE
ctop_core16_pf2_pci_msi_multiple_msg_cap CTOP_CORE16_PF2_MSI_VEC_32
ctop_core16_pf2_pci_msix_bir 0
ctop_core16_pf2_pci_msix_pba 0
ctop_core16_pf2_pci_msix_pba_offset 0
ctop_core16_pf2_pci_msix_table_offset 0
ctop_core16_pf2_pci_msix_table_size 255
ctop_core16_pf2_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf2_pci_type0_bar0_enabled ENABLE
ctop_core16_pf2_pci_type0_bar1_enabled ENABLE
ctop_core16_pf2_pci_type0_bar2_enabled ENABLE
ctop_core16_pf2_pci_type0_bar3_enabled ENABLE
ctop_core16_pf2_pci_type0_bar4_enabled ENABLE
ctop_core16_pf2_pci_type0_bar5_enabled ENABLE
ctop_core16_pf2_pci_type0_device_id 43981
ctop_core16_pf2_pci_type0_vendor_id 5827
ctop_core16_pf2_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf2_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf2_pcie_cap_ext_tag_supp CTOP_CORE16_PF2_SUPPORTED
ctop_core16_pf2_pcie_cap_flr_cap CTOP_CORE16_PF2_CAPABLE
ctop_core16_pf2_pcie_cap_slot_clk_config FALSE
ctop_core16_pf2_pme_support 27
ctop_core16_pf2_program_interface 0
ctop_core16_pf2_revision_id 1
ctop_core16_pf2_rom_bar_enabled ENABLE
ctop_core16_pf2_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf2_sriov_sup_page_size 1363
ctop_core16_pf2_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf2_sriov_vf_bar0_type CTOP_CORE16_PF2_SRIOV_VF_BAR0_MEM32
ctop_core16_pf2_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf2_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf2_sriov_vf_bar2_type CTOP_CORE16_PF2_SRIOV_VF_BAR2_MEM32
ctop_core16_pf2_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf2_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf2_sriov_vf_bar4_type CTOP_CORE16_PF2_SRIOV_VF_BAR4_MEM32
ctop_core16_pf2_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf2_sriov_vf_device_id 43981
ctop_core16_pf2_sriov_vf_offset_ari_cs2 2
ctop_core16_pf2_sriov_vf_offset_position_nonari 256
ctop_core16_pf2_sriov_vf_stride_nonari 256
ctop_core16_pf2_subclass_code 0
ctop_core16_pf2_subsys_dev_id 0
ctop_core16_pf2_subsys_vendor_id 0
ctop_core16_pf2_tph_req_cap_int_vec DISABLE
ctop_core16_pf2_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF2_IN_TPH_STRUCT_VF
ctop_core16_pf2_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF2_NOT_IN_MSIX_TABLE
ctop_core16_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF2_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf2_tph_req_cap_st_table_size 1
ctop_core16_pf2_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf2_tph_req_device_spec DISABLE
ctop_core16_pf2_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf2_prs_outstanding_capacity 0
ctop_core16_pf3_acs_cap_acs_at_block DISABLE
ctop_core16_pf3_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf3_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf3_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf3_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf3_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf3_acs_cap_acs_src_valid DISABLE
ctop_core16_pf3_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf3_bar0_prefetch FALSE
ctop_core16_pf3_bar0_type CTOP_CORE16_PF3_BAR0_MEM32
ctop_core16_pf3_bar1_prefetch FALSE
ctop_core16_pf3_bar2_prefetch FALSE
ctop_core16_pf3_bar2_type CTOP_CORE16_PF3_BAR2_MEM32
ctop_core16_pf3_bar3_prefetch FALSE
ctop_core16_pf3_bar4_prefetch FALSE
ctop_core16_pf3_bar4_type CTOP_CORE16_PF3_BAR4_MEM32
ctop_core16_pf3_bar5_prefetch FALSE
ctop_core16_pf3_base_class_code 0
ctop_core16_pf3_int_pin CTOP_CORE16_PF3_INTA
ctop_core16_pf3_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf3_pasid_cap_max_pasid_width 0
ctop_core16_pf3_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf3_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf3_pci_msi_ext_data_cap TRUE
ctop_core16_pf3_pci_msi_multiple_msg_cap CTOP_CORE16_PF3_MSI_VEC_32
ctop_core16_pf3_pci_msix_bir 0
ctop_core16_pf3_pci_msix_pba 0
ctop_core16_pf3_pci_msix_pba_offset 0
ctop_core16_pf3_pci_msix_table_offset 0
ctop_core16_pf3_pci_msix_table_size 255
ctop_core16_pf3_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf3_pci_type0_bar0_enabled ENABLE
ctop_core16_pf3_pci_type0_bar1_enabled ENABLE
ctop_core16_pf3_pci_type0_bar2_enabled ENABLE
ctop_core16_pf3_pci_type0_bar3_enabled ENABLE
ctop_core16_pf3_pci_type0_bar4_enabled ENABLE
ctop_core16_pf3_pci_type0_bar5_enabled ENABLE
ctop_core16_pf3_pci_type0_device_id 43981
ctop_core16_pf3_pci_type0_vendor_id 5827
ctop_core16_pf3_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf3_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf3_pcie_cap_ext_tag_supp CTOP_CORE16_PF3_SUPPORTED
ctop_core16_pf3_pcie_cap_flr_cap CTOP_CORE16_PF3_CAPABLE
ctop_core16_pf3_pcie_cap_slot_clk_config FALSE
ctop_core16_pf3_pme_support 27
ctop_core16_pf3_program_interface 0
ctop_core16_pf3_revision_id 1
ctop_core16_pf3_rom_bar_enabled ENABLE
ctop_core16_pf3_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf3_sriov_sup_page_size 1363
ctop_core16_pf3_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf3_sriov_vf_bar0_type CTOP_CORE16_PF3_SRIOV_VF_BAR0_MEM32
ctop_core16_pf3_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf3_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf3_sriov_vf_bar2_type CTOP_CORE16_PF3_SRIOV_VF_BAR2_MEM32
ctop_core16_pf3_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf3_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf3_sriov_vf_bar4_type CTOP_CORE16_PF3_SRIOV_VF_BAR4_MEM32
ctop_core16_pf3_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf3_sriov_vf_device_id 43981
ctop_core16_pf3_sriov_vf_offset_ari_cs2 2
ctop_core16_pf3_sriov_vf_offset_position_nonari 256
ctop_core16_pf3_sriov_vf_stride_nonari 256
ctop_core16_pf3_subclass_code 0
ctop_core16_pf3_subsys_dev_id 0
ctop_core16_pf3_subsys_vendor_id 0
ctop_core16_pf3_tph_req_cap_int_vec DISABLE
ctop_core16_pf3_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF3_IN_TPH_STRUCT_VF
ctop_core16_pf3_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF3_NOT_IN_MSIX_TABLE
ctop_core16_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF3_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf3_tph_req_cap_st_table_size 1
ctop_core16_pf3_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf3_tph_req_device_spec DISABLE
ctop_core16_pf3_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf3_prs_outstanding_capacity 0
ctop_core16_pf4_acs_cap_acs_at_block DISABLE
ctop_core16_pf4_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf4_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf4_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf4_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf4_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf4_acs_cap_acs_src_valid DISABLE
ctop_core16_pf4_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf4_bar0_prefetch FALSE
ctop_core16_pf4_bar0_type CTOP_CORE16_PF4_BAR0_MEM32
ctop_core16_pf4_bar1_prefetch FALSE
ctop_core16_pf4_bar2_prefetch FALSE
ctop_core16_pf4_bar2_type CTOP_CORE16_PF4_BAR2_MEM32
ctop_core16_pf4_bar3_prefetch FALSE
ctop_core16_pf4_bar4_prefetch FALSE
ctop_core16_pf4_bar4_type CTOP_CORE16_PF4_BAR4_MEM32
ctop_core16_pf4_bar5_prefetch FALSE
ctop_core16_pf4_base_class_code 0
ctop_core16_pf4_int_pin CTOP_CORE16_PF4_INTA
ctop_core16_pf4_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf4_pasid_cap_max_pasid_width 0
ctop_core16_pf4_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf4_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf4_pci_msi_ext_data_cap TRUE
ctop_core16_pf4_pci_msi_multiple_msg_cap CTOP_CORE16_PF4_MSI_VEC_32
ctop_core16_pf4_pci_msix_bir 0
ctop_core16_pf4_pci_msix_pba 0
ctop_core16_pf4_pci_msix_pba_offset 0
ctop_core16_pf4_pci_msix_table_offset 0
ctop_core16_pf4_pci_msix_table_size 255
ctop_core16_pf4_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf4_pci_type0_bar0_enabled ENABLE
ctop_core16_pf4_pci_type0_bar1_enabled ENABLE
ctop_core16_pf4_pci_type0_bar2_enabled ENABLE
ctop_core16_pf4_pci_type0_bar3_enabled ENABLE
ctop_core16_pf4_pci_type0_bar4_enabled ENABLE
ctop_core16_pf4_pci_type0_bar5_enabled ENABLE
ctop_core16_pf4_pci_type0_device_id 43981
ctop_core16_pf4_pci_type0_vendor_id 5827
ctop_core16_pf4_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf4_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf4_pcie_cap_ext_tag_supp CTOP_CORE16_PF4_SUPPORTED
ctop_core16_pf4_pcie_cap_flr_cap CTOP_CORE16_PF4_CAPABLE
ctop_core16_pf4_pcie_cap_slot_clk_config FALSE
ctop_core16_pf4_pme_support 27
ctop_core16_pf4_program_interface 0
ctop_core16_pf4_revision_id 1
ctop_core16_pf4_rom_bar_enabled ENABLE
ctop_core16_pf4_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf4_sriov_sup_page_size 1363
ctop_core16_pf4_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf4_sriov_vf_bar0_type CTOP_CORE16_PF4_SRIOV_VF_BAR0_MEM32
ctop_core16_pf4_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf4_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf4_sriov_vf_bar2_type CTOP_CORE16_PF4_SRIOV_VF_BAR2_MEM32
ctop_core16_pf4_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf4_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf4_sriov_vf_bar4_type CTOP_CORE16_PF4_SRIOV_VF_BAR4_MEM32
ctop_core16_pf4_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf4_sriov_vf_device_id 43981
ctop_core16_pf4_sriov_vf_offset_ari_cs2 2
ctop_core16_pf4_sriov_vf_offset_position_nonari 256
ctop_core16_pf4_sriov_vf_stride_nonari 256
ctop_core16_pf4_subclass_code 0
ctop_core16_pf4_subsys_dev_id 0
ctop_core16_pf4_subsys_vendor_id 0
ctop_core16_pf4_tph_req_cap_int_vec DISABLE
ctop_core16_pf4_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF4_IN_TPH_STRUCT_VF
ctop_core16_pf4_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF4_NOT_IN_MSIX_TABLE
ctop_core16_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF4_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf4_tph_req_cap_st_table_size 1
ctop_core16_pf4_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf4_tph_req_device_spec DISABLE
ctop_core16_pf4_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf4_prs_outstanding_capacity 0
ctop_core16_pf5_acs_cap_acs_at_block DISABLE
ctop_core16_pf5_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf5_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf5_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf5_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf5_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf5_acs_cap_acs_src_valid DISABLE
ctop_core16_pf5_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf5_bar0_prefetch FALSE
ctop_core16_pf5_bar0_type CTOP_CORE16_PF5_BAR0_MEM32
ctop_core16_pf5_bar1_prefetch FALSE
ctop_core16_pf5_bar2_prefetch FALSE
ctop_core16_pf5_bar2_type CTOP_CORE16_PF5_BAR2_MEM32
ctop_core16_pf5_bar3_prefetch FALSE
ctop_core16_pf5_bar4_prefetch FALSE
ctop_core16_pf5_bar4_type CTOP_CORE16_PF5_BAR4_MEM32
ctop_core16_pf5_bar5_prefetch FALSE
ctop_core16_pf5_base_class_code 0
ctop_core16_pf5_int_pin CTOP_CORE16_PF5_INTA
ctop_core16_pf5_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf5_pasid_cap_max_pasid_width 0
ctop_core16_pf5_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf5_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf5_pci_msi_ext_data_cap TRUE
ctop_core16_pf5_pci_msi_multiple_msg_cap CTOP_CORE16_PF5_MSI_VEC_32
ctop_core16_pf5_pci_msix_bir 0
ctop_core16_pf5_pci_msix_pba 0
ctop_core16_pf5_pci_msix_pba_offset 0
ctop_core16_pf5_pci_msix_table_offset 0
ctop_core16_pf5_pci_msix_table_size 255
ctop_core16_pf5_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf5_pci_type0_bar0_enabled ENABLE
ctop_core16_pf5_pci_type0_bar1_enabled ENABLE
ctop_core16_pf5_pci_type0_bar2_enabled ENABLE
ctop_core16_pf5_pci_type0_bar3_enabled ENABLE
ctop_core16_pf5_pci_type0_bar4_enabled ENABLE
ctop_core16_pf5_pci_type0_bar5_enabled ENABLE
ctop_core16_pf5_pci_type0_device_id 43981
ctop_core16_pf5_pci_type0_vendor_id 5827
ctop_core16_pf5_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf5_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf5_pcie_cap_ext_tag_supp CTOP_CORE16_PF5_SUPPORTED
ctop_core16_pf5_pcie_cap_flr_cap CTOP_CORE16_PF5_CAPABLE
ctop_core16_pf5_pcie_cap_slot_clk_config FALSE
ctop_core16_pf5_pme_support 27
ctop_core16_pf5_program_interface 0
ctop_core16_pf5_revision_id 1
ctop_core16_pf5_rom_bar_enabled ENABLE
ctop_core16_pf5_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf5_sriov_sup_page_size 1363
ctop_core16_pf5_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf5_sriov_vf_bar0_type CTOP_CORE16_PF5_SRIOV_VF_BAR0_MEM32
ctop_core16_pf5_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf5_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf5_sriov_vf_bar2_type CTOP_CORE16_PF5_SRIOV_VF_BAR2_MEM32
ctop_core16_pf5_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf5_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf5_sriov_vf_bar4_type CTOP_CORE16_PF5_SRIOV_VF_BAR4_MEM32
ctop_core16_pf5_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf5_sriov_vf_device_id 43981
ctop_core16_pf5_sriov_vf_offset_ari_cs2 2
ctop_core16_pf5_sriov_vf_offset_position_nonari 256
ctop_core16_pf5_sriov_vf_stride_nonari 256
ctop_core16_pf5_subclass_code 0
ctop_core16_pf5_subsys_dev_id 0
ctop_core16_pf5_subsys_vendor_id 0
ctop_core16_pf5_tph_req_cap_int_vec DISABLE
ctop_core16_pf5_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF5_IN_TPH_STRUCT_VF
ctop_core16_pf5_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF5_NOT_IN_MSIX_TABLE
ctop_core16_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF5_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf5_tph_req_cap_st_table_size 1
ctop_core16_pf5_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf5_tph_req_device_spec DISABLE
ctop_core16_pf5_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf5_prs_outstanding_capacity 0
ctop_core16_pf6_acs_cap_acs_at_block DISABLE
ctop_core16_pf6_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf6_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf6_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf6_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf6_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf6_acs_cap_acs_src_valid DISABLE
ctop_core16_pf6_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf6_bar0_prefetch FALSE
ctop_core16_pf6_bar0_type CTOP_CORE16_PF6_BAR0_MEM32
ctop_core16_pf6_bar1_prefetch FALSE
ctop_core16_pf6_bar2_prefetch FALSE
ctop_core16_pf6_bar2_type CTOP_CORE16_PF6_BAR2_MEM32
ctop_core16_pf6_bar3_prefetch FALSE
ctop_core16_pf6_bar4_prefetch FALSE
ctop_core16_pf6_bar4_type CTOP_CORE16_PF6_BAR4_MEM32
ctop_core16_pf6_bar5_prefetch FALSE
ctop_core16_pf6_base_class_code 0
ctop_core16_pf6_int_pin CTOP_CORE16_PF6_INTA
ctop_core16_pf6_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf6_pasid_cap_max_pasid_width 0
ctop_core16_pf6_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf6_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf6_pci_msi_ext_data_cap TRUE
ctop_core16_pf6_pci_msi_multiple_msg_cap CTOP_CORE16_PF6_MSI_VEC_32
ctop_core16_pf6_pci_msix_bir 0
ctop_core16_pf6_pci_msix_pba 0
ctop_core16_pf6_pci_msix_pba_offset 0
ctop_core16_pf6_pci_msix_table_offset 0
ctop_core16_pf6_pci_msix_table_size 255
ctop_core16_pf6_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf6_pci_type0_bar0_enabled ENABLE
ctop_core16_pf6_pci_type0_bar1_enabled ENABLE
ctop_core16_pf6_pci_type0_bar2_enabled ENABLE
ctop_core16_pf6_pci_type0_bar3_enabled ENABLE
ctop_core16_pf6_pci_type0_bar4_enabled ENABLE
ctop_core16_pf6_pci_type0_bar5_enabled ENABLE
ctop_core16_pf6_pci_type0_device_id 43981
ctop_core16_pf6_pci_type0_vendor_id 5827
ctop_core16_pf6_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf6_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf6_pcie_cap_ext_tag_supp CTOP_CORE16_PF6_SUPPORTED
ctop_core16_pf6_pcie_cap_flr_cap CTOP_CORE16_PF6_CAPABLE
ctop_core16_pf6_pcie_cap_slot_clk_config FALSE
ctop_core16_pf6_pme_support 27
ctop_core16_pf6_program_interface 0
ctop_core16_pf6_revision_id 1
ctop_core16_pf6_rom_bar_enabled ENABLE
ctop_core16_pf6_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf6_sriov_sup_page_size 1363
ctop_core16_pf6_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf6_sriov_vf_bar0_type CTOP_CORE16_PF6_SRIOV_VF_BAR0_MEM32
ctop_core16_pf6_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf6_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf6_sriov_vf_bar2_type CTOP_CORE16_PF6_SRIOV_VF_BAR2_MEM32
ctop_core16_pf6_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf6_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf6_sriov_vf_bar4_type CTOP_CORE16_PF6_SRIOV_VF_BAR4_MEM32
ctop_core16_pf6_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf6_sriov_vf_device_id 43981
ctop_core16_pf6_sriov_vf_offset_ari_cs2 2
ctop_core16_pf6_sriov_vf_offset_position_nonari 256
ctop_core16_pf6_sriov_vf_stride_nonari 256
ctop_core16_pf6_subclass_code 0
ctop_core16_pf6_subsys_dev_id 0
ctop_core16_pf6_subsys_vendor_id 0
ctop_core16_pf6_tph_req_cap_int_vec DISABLE
ctop_core16_pf6_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF6_IN_TPH_STRUCT_VF
ctop_core16_pf6_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF6_NOT_IN_MSIX_TABLE
ctop_core16_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF6_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf6_tph_req_cap_st_table_size 1
ctop_core16_pf6_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf6_tph_req_device_spec DISABLE
ctop_core16_pf6_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf6_prs_outstanding_capacity 0
ctop_core16_pf7_acs_cap_acs_at_block DISABLE
ctop_core16_pf7_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core16_pf7_acs_cap_acs_egress_ctrl_size 0
ctop_core16_pf7_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core16_pf7_acs_cap_acs_p2p_egress_control DISABLE
ctop_core16_pf7_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core16_pf7_acs_cap_acs_src_valid DISABLE
ctop_core16_pf7_acs_cap_acs_usp_forwarding DISABLE
ctop_core16_pf7_bar0_prefetch FALSE
ctop_core16_pf7_bar0_type CTOP_CORE16_PF7_BAR0_MEM32
ctop_core16_pf7_bar1_prefetch FALSE
ctop_core16_pf7_bar2_prefetch FALSE
ctop_core16_pf7_bar2_type CTOP_CORE16_PF7_BAR2_MEM32
ctop_core16_pf7_bar3_prefetch FALSE
ctop_core16_pf7_bar4_prefetch FALSE
ctop_core16_pf7_bar4_type CTOP_CORE16_PF7_BAR4_MEM32
ctop_core16_pf7_bar5_prefetch FALSE
ctop_core16_pf7_base_class_code 0
ctop_core16_pf7_int_pin CTOP_CORE16_PF7_INTA
ctop_core16_pf7_pasid_cap_execute_permission_supported DISABLE
ctop_core16_pf7_pasid_cap_max_pasid_width 0
ctop_core16_pf7_pasid_cap_privileged_mode_supported DISABLE
ctop_core16_pf7_pci_msi_64_bit_addr_cap TRUE
ctop_core16_pf7_pci_msi_ext_data_cap TRUE
ctop_core16_pf7_pci_msi_multiple_msg_cap CTOP_CORE16_PF7_MSI_VEC_32
ctop_core16_pf7_pci_msix_bir 0
ctop_core16_pf7_pci_msix_pba 0
ctop_core16_pf7_pci_msix_pba_offset 0
ctop_core16_pf7_pci_msix_table_offset 0
ctop_core16_pf7_pci_msix_table_size 255
ctop_core16_pf7_pci_msix_table_size_vfcomm_cs2 0
ctop_core16_pf7_pci_type0_bar0_enabled ENABLE
ctop_core16_pf7_pci_type0_bar1_enabled ENABLE
ctop_core16_pf7_pci_type0_bar2_enabled ENABLE
ctop_core16_pf7_pci_type0_bar3_enabled ENABLE
ctop_core16_pf7_pci_type0_bar4_enabled ENABLE
ctop_core16_pf7_pci_type0_bar5_enabled ENABLE
ctop_core16_pf7_pci_type0_device_id 43981
ctop_core16_pf7_pci_type0_vendor_id 5827
ctop_core16_pf7_pcie_cap_ep_l0s_accpt_latency 0
ctop_core16_pf7_pcie_cap_ep_l1_accpt_latency 0
ctop_core16_pf7_pcie_cap_ext_tag_supp CTOP_CORE16_PF7_SUPPORTED
ctop_core16_pf7_pcie_cap_flr_cap CTOP_CORE16_PF7_CAPABLE
ctop_core16_pf7_pcie_cap_slot_clk_config FALSE
ctop_core16_pf7_pme_support 27
ctop_core16_pf7_program_interface 0
ctop_core16_pf7_revision_id 1
ctop_core16_pf7_rom_bar_enabled ENABLE
ctop_core16_pf7_shadow_sriov_vf_stride_ari_cs2 2
ctop_core16_pf7_sriov_sup_page_size 1363
ctop_core16_pf7_sriov_vf_bar0_prefetch FALSE
ctop_core16_pf7_sriov_vf_bar0_type CTOP_CORE16_PF7_SRIOV_VF_BAR0_MEM32
ctop_core16_pf7_sriov_vf_bar1_prefetch FALSE
ctop_core16_pf7_sriov_vf_bar2_prefetch FALSE
ctop_core16_pf7_sriov_vf_bar2_type CTOP_CORE16_PF7_SRIOV_VF_BAR2_MEM32
ctop_core16_pf7_sriov_vf_bar3_prefetch FALSE
ctop_core16_pf7_sriov_vf_bar4_prefetch FALSE
ctop_core16_pf7_sriov_vf_bar4_type CTOP_CORE16_PF7_SRIOV_VF_BAR4_MEM32
ctop_core16_pf7_sriov_vf_bar5_prefetch FALSE
ctop_core16_pf7_sriov_vf_device_id 43981
ctop_core16_pf7_sriov_vf_offset_ari_cs2 2
ctop_core16_pf7_sriov_vf_offset_position_nonari 256
ctop_core16_pf7_sriov_vf_stride_nonari 256
ctop_core16_pf7_subclass_code 0
ctop_core16_pf7_subsys_dev_id 0
ctop_core16_pf7_subsys_vendor_id 0
ctop_core16_pf7_tph_req_cap_int_vec DISABLE
ctop_core16_pf7_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core16_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE16_PF7_IN_TPH_STRUCT_VF
ctop_core16_pf7_tph_req_cap_st_table_loc_1 CTOP_CORE16_PF7_NOT_IN_MSIX_TABLE
ctop_core16_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE16_PF7_NOT_IN_MSIX_TABLE_VF
ctop_core16_pf7_tph_req_cap_st_table_size 1
ctop_core16_pf7_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core16_pf7_tph_req_device_spec DISABLE
ctop_core16_pf7_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core16_pf7_prs_outstanding_capacity 0
ctop_core16_rxbuf_limit_bypass 0
ctop_core16_virtual_drop_vendor0_msg FALSE
ctop_core16_virtual_drop_vendor1_msg FALSE
ctop_core16_virtual_ep_native CTOP_CORE16_NATIVE
ctop_core16_virtual_link_rate CTOP_CORE16_GEN3
ctop_core16_virtual_link_width CTOP_CORE16_X16
ctop_core16_virtual_maxpayload_size CTOP_CORE16_MAX_PAYLOAD_1024
ctop_core16_virtual_num_of_lanes CTOP_CORE16_NUM_16
ctop_core16_virtual_pf0_acs_cap_enable DISABLE
ctop_core16_virtual_pf0_ats_cap_enable DISABLE
ctop_core16_virtual_pf0_dlink_cap_enable DISABLE
ctop_core16_sn_ser_num_reg_1_dw_hwtcl 0
ctop_core16_sn_ser_num_reg_2_dw_hwtcl 0
ctop_core4_0_sn_ser_num_reg_1_dw_hwtcl 0
ctop_core4_0_sn_ser_num_reg_2_dw_hwtcl 0
ctop_core4_1_sn_ser_num_reg_1_dw_hwtcl 0
ctop_core4_1_sn_ser_num_reg_2_dw_hwtcl 0
ctop_core8_sn_ser_num_reg_1_dw_hwtcl 0
ctop_core8_sn_ser_num_reg_2_dw_hwtcl 0
ctop_core16_virtual_pf0_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf0_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf0_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf0_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf0_exvf_virtio_en DISABLE
ctop_core16_virtual_pf0_io_decode CTOP_CORE16_IO32
ctop_core16_virtual_pf0_ltr_cap_enable DISABLE
ctop_core16_virtual_pf0_msi_enable DISABLE
ctop_core16_virtual_pf0_msix_enable DISABLE
ctop_core16_virtual_pf0_pasid_cap_enable DISABLE
ctop_core16_virtual_pf0_prefetch_decode CTOP_CORE16_PREF64
ctop_core16_virtual_pf0_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf0_ras_des_cap_enable DISABLE
ctop_core16_virtual_pf0_sn_cap_enable DISABLE
ctop_core16_virtual_pf0_sriov_enable DISABLE
ctop_core16_virtual_pf1_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf0_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf0_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf0_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf0_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf0_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf0_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf0_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf0_tph_cap_enable DISABLE
ctop_core16_virtual_pf0_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf0_virtio_en DISABLE
ctop_core16_virtual_pf1_acs_cap_enable DISABLE
ctop_core16_virtual_pf1_ats_cap_enable DISABLE
ctop_core16_virtual_pf1_enable DISABLE
ctop_core16_virtual_pf1_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf1_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf1_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf1_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf1_exvf_virtio_en DISABLE
ctop_core16_virtual_pf1_msi_enable DISABLE
ctop_core16_virtual_pf1_msix_enable DISABLE
ctop_core16_virtual_pf1_pasid_cap_enable DISABLE
ctop_core16_virtual_pf1_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf1_sriov_enable DISABLE
ctop_core16_virtual_pf1_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf1_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf1_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf1_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf1_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf1_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf1_tph_cap_enable DISABLE
ctop_core16_virtual_pf1_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf1_user_vsec_offset 0
ctop_core16_virtual_pf1_virtio_en DISABLE
ctop_core16_virtual_pf2_acs_cap_enable DISABLE
ctop_core16_virtual_pf2_ats_cap_enable DISABLE
ctop_core16_virtual_pf2_enable DISABLE
ctop_core16_virtual_pf2_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf2_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf2_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf2_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf2_exvf_virtio_en DISABLE
ctop_core16_virtual_pf2_msi_enable DISABLE
ctop_core16_virtual_pf2_msix_enable DISABLE
ctop_core16_virtual_pf2_pasid_cap_enable DISABLE
ctop_core16_virtual_pf2_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf2_sriov_enable DISABLE
ctop_core16_virtual_pf2_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf2_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf2_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf2_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf2_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf2_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf2_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf2_tph_cap_enable DISABLE
ctop_core16_virtual_pf2_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf2_user_vsec_offset 0
ctop_core16_virtual_pf2_virtio_en DISABLE
ctop_core16_virtual_pf3_acs_cap_enable DISABLE
ctop_core16_virtual_pf3_ats_cap_enable DISABLE
ctop_core16_virtual_pf3_enable DISABLE
ctop_core16_virtual_pf3_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf3_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf3_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf3_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf3_exvf_virtio_en DISABLE
ctop_core16_virtual_pf3_msi_enable DISABLE
ctop_core16_virtual_pf3_msix_enable DISABLE
ctop_core16_virtual_pf3_pasid_cap_enable DISABLE
ctop_core16_virtual_pf3_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf3_sriov_enable DISABLE
ctop_core16_virtual_pf3_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf3_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf3_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf3_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf3_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf3_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf3_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf3_tph_cap_enable DISABLE
ctop_core16_virtual_pf3_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf3_user_vsec_offset 0
ctop_core16_virtual_pf3_virtio_en DISABLE
ctop_core16_virtual_pf4_acs_cap_enable DISABLE
ctop_core16_virtual_pf4_ats_cap_enable DISABLE
ctop_core16_virtual_pf4_enable DISABLE
ctop_core16_virtual_pf4_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf4_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf4_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf4_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf4_exvf_virtio_en DISABLE
ctop_core16_virtual_pf4_msi_enable DISABLE
ctop_core16_virtual_pf4_msix_enable DISABLE
ctop_core16_virtual_pf4_pasid_cap_enable DISABLE
ctop_core16_virtual_pf4_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf4_sriov_enable DISABLE
ctop_core16_virtual_pf4_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf4_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf4_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf4_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf4_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf4_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf4_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf4_tph_cap_enable DISABLE
ctop_core16_virtual_pf4_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf4_user_vsec_offset 0
ctop_core16_virtual_pf4_virtio_en DISABLE
ctop_core16_virtual_pf5_acs_cap_enable DISABLE
ctop_core16_virtual_pf5_ats_cap_enable DISABLE
ctop_core16_virtual_pf5_enable DISABLE
ctop_core16_virtual_pf5_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf5_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf5_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf5_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf5_exvf_virtio_en DISABLE
ctop_core16_virtual_pf5_msi_enable DISABLE
ctop_core16_virtual_pf5_msix_enable DISABLE
ctop_core16_virtual_pf5_pasid_cap_enable DISABLE
ctop_core16_virtual_pf5_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf5_sriov_enable DISABLE
ctop_core16_virtual_pf5_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf5_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf5_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf5_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf5_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf5_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf5_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf5_tph_cap_enable DISABLE
ctop_core16_virtual_pf5_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf5_user_vsec_offset 0
ctop_core16_virtual_pf5_virtio_en DISABLE
ctop_core16_virtual_pf6_acs_cap_enable DISABLE
ctop_core16_virtual_pf6_ats_cap_enable DISABLE
ctop_core16_virtual_pf6_enable DISABLE
ctop_core16_virtual_pf6_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf6_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf6_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf6_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf6_exvf_virtio_en DISABLE
ctop_core16_virtual_pf6_msi_enable DISABLE
ctop_core16_virtual_pf6_msix_enable DISABLE
ctop_core16_virtual_pf6_pasid_cap_enable DISABLE
ctop_core16_virtual_pf6_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf6_sriov_enable DISABLE
ctop_core16_virtual_pf6_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf6_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf6_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf6_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf6_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf6_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf6_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf6_tph_cap_enable DISABLE
ctop_core16_virtual_pf6_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf6_user_vsec_offset 0
ctop_core16_virtual_pf6_virtio_en DISABLE
ctop_core16_virtual_pf7_acs_cap_enable DISABLE
ctop_core16_virtual_pf7_ats_cap_enable DISABLE
ctop_core16_virtual_pf7_enable DISABLE
ctop_core16_virtual_pf7_exvf_acs_cap_enable DISABLE
ctop_core16_virtual_pf7_exvf_ats_cap_enable DISABLE
ctop_core16_virtual_pf7_exvf_msix_cap_enable DISABLE
ctop_core16_virtual_pf7_exvf_tph_cap_enable DISABLE
ctop_core16_virtual_pf7_exvf_virtio_en DISABLE
ctop_core16_virtual_pf7_msi_enable DISABLE
ctop_core16_virtual_pf7_msix_enable DISABLE
ctop_core16_virtual_pf7_pasid_cap_enable DISABLE
ctop_core16_virtual_pf7_prs_ext_cap_enable DISABLE
ctop_core16_virtual_pf7_sriov_enable DISABLE
ctop_core16_virtual_pf7_sriov_num_vf_non_ari 0
ctop_core16_virtual_pf7_sriov_vf_bar0_enabled DISABLE
ctop_core16_virtual_pf7_sriov_vf_bar1_enabled DISABLE
ctop_core16_virtual_pf7_sriov_vf_bar2_enabled DISABLE
ctop_core16_virtual_pf7_sriov_vf_bar3_enabled DISABLE
ctop_core16_virtual_pf7_sriov_vf_bar4_enabled DISABLE
ctop_core16_virtual_pf7_sriov_vf_bar5_enabled DISABLE
ctop_core16_virtual_pf7_tph_cap_enable DISABLE
ctop_core16_virtual_pf7_user_vsec_cap_enable DISABLE
ctop_core16_virtual_pf7_user_vsec_offset 0
ctop_core16_virtual_pf7_virtio_en DISABLE
ctop_core16_virtual_rp_ep_mode CTOP_CORE16_EP
ctop_core16_virtual_txeq_mode CTOP_CORE16_EQ_DISABLE
ctop_core16_vsec_next_offset 0
ctop_virtual_x16_perst_sel CTOP_CMN_HARD_X16
ctop_core4_0_cvp_user_id 0
ctop_core16_pf0_ari_acs_fun_grp_cap FALSE
ctop_core4_0_pf0_ari_acs_fun_grp_cap FALSE
ctop_core4_1_pf0_ari_acs_fun_grp_cap FALSE
ctop_core8_pf0_ari_acs_fun_grp_cap FALSE
ctop_core16_ecrc_strip FALSE
ctop_core4_0_ecrc_strip FALSE
ctop_core4_1_ecrc_strip FALSE
ctop_core8_ecrc_strip FALSE
ctop_core4_0_pf0_acs_cap_acs_at_block DISABLE
ctop_core4_0_pf0_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core4_0_pf0_acs_cap_acs_egress_ctrl_size 0
ctop_core4_0_pf0_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core4_0_pf0_acs_cap_acs_p2p_egress_control DISABLE
ctop_core4_0_pf0_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core4_0_pf0_acs_cap_acs_src_valid DISABLE
ctop_core4_0_pf0_acs_cap_acs_usp_forwarding DISABLE
ctop_core4_0_pf0_auto_lane_flip_ctrl_en ENABLE
ctop_core4_0_pf0_base_class_code 0
ctop_core4_0_pf0_eq_redo ENABLE
ctop_core4_0_pf0_eq_redo_atg4 ENABLE
ctop_core4_0_pf0_gen3_eq_pset_req_vec 4
ctop_core4_0_pf0_gen3_eq_pset_req_vec_atg4 624
ctop_core4_0_pf0_loopback_enable FALSE
ctop_core4_0_pf0_pci_msix_bir 0
ctop_core4_0_pf0_pci_msix_pba 0
ctop_core4_0_pf0_pci_msix_pba_offset 0
ctop_core4_0_pf0_pci_msix_table_offset 0
ctop_core4_0_pf0_pci_msix_table_size 255
ctop_core4_0_pf0_pci_msix_table_size_vfcomm_cs2 0
ctop_core4_0_pf0_pci_type0_device_id 43981
ctop_core4_0_pf0_pci_type0_vendor_id 5827
ctop_core4_0_pf0_pcie_cap_attention_indicator FALSE
ctop_core4_0_pf0_pcie_cap_attention_indicator_button FALSE
ctop_core4_0_pf0_pcie_cap_electromech_interlock FALSE
ctop_core4_0_pf0_pcie_cap_ep_l0s_accpt_latency 0
ctop_core4_0_pf0_pcie_cap_ep_l1_accpt_latency 0
ctop_core4_0_pf0_pcie_cap_ext_tag_supp CTOP_CORE4_0_PF0_SUPPORTED
ctop_core4_0_pf0_pcie_cap_flr_cap CTOP_CORE4_0_PF0_CAPABLE
ctop_core4_0_pf0_pcie_cap_hot_plug_capable FALSE
ctop_core4_0_pf0_pcie_cap_hot_plug_surprise FALSE
ctop_core4_0_pf0_pcie_cap_mrl_sensor FALSE
ctop_core4_0_pf0_pcie_cap_no_cmd_cpl_support FALSE
ctop_core4_0_pf0_pcie_cap_phy_slot_num 0
ctop_core4_0_pf0_pcie_cap_port_num 0
ctop_core4_0_pf0_pcie_cap_power_controller FALSE
ctop_core4_0_pf0_pcie_cap_power_indicator FALSE
ctop_core4_0_pf0_pcie_cap_sel_deemphasis CTOP_CORE4_0_PF0_MINUS_6DB
ctop_core4_0_pf0_pcie_cap_slot_clk_config FALSE
ctop_core4_0_pf0_pcie_cap_slot_power_limit_scale 0
ctop_core4_0_pf0_pcie_cap_slot_power_limit_value 0
ctop_core4_0_pf0_pcie_slot_imp CTOP_CORE4_0_PF0_NOT_IMPLEMENTED
ctop_core4_0_pf0_pme_support 27
ctop_core4_0_pf0_program_interface 0
ctop_core4_0_pf0_revision_id 1
ctop_core4_0_pf0_rom_bar_enabled ENABLE
ctop_core4_0_pf0_rp_rom_bar_enabled ENABLE
ctop_core4_0_pf0_subclass_code 0
ctop_core4_0_pf0_subsys_dev_id 0
ctop_core4_0_pf0_subsys_vendor_id 0
ctop_core4_0_virtual_pf0_ats_cap_enable DISABLE
ctop_core4_0_pf0_tph_req_cap_int_vec DISABLE
ctop_core4_0_pf0_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core4_0_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE4_0_PF0_IN_TPH_STRUCT_VF
ctop_core4_0_pf0_tph_req_cap_st_table_loc_1 CTOP_CORE4_0_PF0_NOT_IN_MSIX_TABLE
ctop_core4_0_pf0_tph_req_cap_st_table_size 1
ctop_core4_0_pf0_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core4_0_pf0_tph_req_device_spec DISABLE
ctop_core4_0_pf0_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core4_0_pf0_prs_outstanding_capacity 0
ctop_core4_0_rxbuf_limit_bypass 0
ctop_core4_0_virtual_drop_vendor0_msg FALSE
ctop_core4_0_virtual_drop_vendor1_msg FALSE
ctop_core4_0_virtual_ep_native CTOP_CORE4_0_NATIVE
ctop_core4_0_virtual_link_rate CTOP_CORE4_0_GEN3
ctop_core4_0_virtual_maxpayload_size CTOP_CORE4_0_MAX_PAYLOAD_1024
ctop_core4_0_virtual_num_of_lanes CTOP_CORE4_0_NUM_16
ctop_core4_0_virtual_pf0_acs_cap_enable DISABLE
ctop_core4_0_virtual_pf0_dlink_cap_enable DISABLE
ctop_core4_0_virtual_pf0_io_decode CTOP_CORE4_0_IO32
ctop_core4_0_virtual_pf0_msix_enable DISABLE
ctop_core4_0_virtual_pf0_pl16g_cap_enable DISABLE
ctop_core4_0_virtual_pf0_prefetch_decode CTOP_CORE4_0_PREF64
ctop_core4_0_virtual_pf0_prs_ext_cap_enable DISABLE
ctop_core4_0_virtual_pf0_ras_des_cap_enable DISABLE
ctop_core4_0_virtual_pf0_sn_cap_enable DISABLE
ctop_core4_0_virtual_pf0_tph_cap_enable DISABLE
ctop_core4_0_virtual_pf0_user_vsec_cap_enable DISABLE
ctop_core4_0_virtual_rp_ep_mode CTOP_CORE4_0_EP
ctop_core4_0_virtual_txeq_mode CTOP_CORE4_0_EQ_DISABLE
ctop_virtual_x40_perst_sel CTOP_CMN_HARD_X40
ctop_core4_0_vsec_next_offset 0
ctop_core4_1_cvp_user_id 0
ctop_core4_1_pf0_acs_cap_acs_at_block DISABLE
ctop_core4_1_pf0_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core4_1_pf0_acs_cap_acs_egress_ctrl_size 0
ctop_core4_1_pf0_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core4_1_pf0_acs_cap_acs_p2p_egress_control DISABLE
ctop_core4_1_pf0_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core4_1_pf0_acs_cap_acs_src_valid DISABLE
ctop_core4_1_pf0_acs_cap_acs_usp_forwarding DISABLE
ctop_core4_1_pf0_auto_lane_flip_ctrl_en ENABLE
ctop_core4_1_pf0_base_class_code 0
ctop_core4_1_pf0_eq_redo ENABLE
ctop_core4_1_pf0_eq_redo_atg4 ENABLE
ctop_core4_1_pf0_gen3_eq_pset_req_vec 4
ctop_core4_1_pf0_gen3_eq_pset_req_vec_atg4 624
ctop_core4_1_pf0_loopback_enable FALSE
ctop_core4_1_pf0_pci_msix_bir 0
ctop_core4_1_pf0_pci_msix_pba 0
ctop_core4_1_pf0_pci_msix_pba_offset 0
ctop_core4_1_pf0_pci_msix_table_offset 0
ctop_core4_1_pf0_pci_msix_table_size 255
ctop_core4_1_pf0_pci_msix_table_size_vfcomm_cs2 0
ctop_core4_1_pf0_pci_type0_device_id 43981
ctop_core4_1_pf0_pci_type0_vendor_id 5827
ctop_core4_1_pf0_pcie_cap_attention_indicator FALSE
ctop_core4_1_pf0_pcie_cap_attention_indicator_button FALSE
ctop_core4_1_pf0_pcie_cap_electromech_interlock FALSE
ctop_core4_1_pf0_pcie_cap_ep_l0s_accpt_latency 0
ctop_core4_1_pf0_pcie_cap_ep_l1_accpt_latency 0
ctop_core4_1_pf0_pcie_cap_ext_tag_supp CTOP_CORE4_1_PF0_SUPPORTED
ctop_core4_1_pf0_pcie_cap_flr_cap CTOP_CORE4_1_PF0_CAPABLE
ctop_core4_1_pf0_pcie_cap_hot_plug_capable FALSE
ctop_core4_1_pf0_pcie_cap_hot_plug_surprise FALSE
ctop_core4_1_pf0_pcie_cap_mrl_sensor FALSE
ctop_core4_1_pf0_pcie_cap_no_cmd_cpl_support FALSE
ctop_core4_1_pf0_pcie_cap_phy_slot_num 0
ctop_core4_1_pf0_pcie_cap_port_num 0
ctop_core4_1_pf0_pcie_cap_power_controller FALSE
ctop_core4_1_pf0_pcie_cap_power_indicator FALSE
ctop_core4_1_pf0_pcie_cap_sel_deemphasis CTOP_CORE4_1_PF0_MINUS_6DB
ctop_core4_1_pf0_pcie_cap_slot_clk_config FALSE
ctop_core4_1_pf0_pcie_cap_slot_power_limit_scale 0
ctop_core4_1_pf0_pcie_cap_slot_power_limit_value 0
ctop_core4_1_pf0_pcie_slot_imp CTOP_CORE4_1_PF0_NOT_IMPLEMENTED
ctop_core4_1_pf0_pme_support 27
ctop_core4_1_pf0_program_interface 0
ctop_core4_1_pf0_revision_id 1
ctop_core4_1_pf0_rom_bar_enabled ENABLE
ctop_core4_1_pf0_rp_rom_bar_enabled ENABLE
ctop_core4_1_pf0_subclass_code 0
ctop_core4_1_pf0_subsys_dev_id 0
ctop_core4_1_pf0_subsys_vendor_id 0
ctop_core4_1_virtual_pf0_ats_cap_enable DISABLE
ctop_core4_1_pf0_tph_req_cap_int_vec DISABLE
ctop_core4_1_pf0_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core4_1_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE4_1_PF0_IN_TPH_STRUCT_VF
ctop_core4_1_pf0_tph_req_cap_st_table_loc_1 CTOP_CORE4_1_PF0_NOT_IN_MSIX_TABLE
ctop_core4_1_pf0_tph_req_cap_st_table_size 1
ctop_core4_1_pf0_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core4_1_pf0_tph_req_device_spec DISABLE
ctop_core4_1_pf0_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core4_1_pf0_prs_outstanding_capacity 0
ctop_core4_1_rxbuf_limit_bypass 0
ctop_core4_1_virtual_drop_vendor0_msg FALSE
ctop_core4_1_virtual_drop_vendor1_msg FALSE
ctop_core4_1_virtual_ep_native CTOP_CORE4_1_NATIVE
ctop_core4_1_virtual_link_rate CTOP_CORE4_1_GEN3
ctop_core4_1_virtual_maxpayload_size CTOP_CORE4_1_MAX_PAYLOAD_1024
ctop_core4_1_virtual_num_of_lanes CTOP_CORE4_1_NUM_16
ctop_core4_1_virtual_pf0_acs_cap_enable DISABLE
ctop_core4_1_virtual_pf0_dlink_cap_enable DISABLE
ctop_core4_1_virtual_pf0_io_decode CTOP_CORE4_1_IO32
ctop_core4_1_virtual_pf0_msix_enable DISABLE
ctop_core4_1_virtual_pf0_pl16g_cap_enable DISABLE
ctop_core4_1_virtual_pf0_prefetch_decode CTOP_CORE4_1_PREF64
ctop_core4_1_virtual_pf0_prs_ext_cap_enable DISABLE
ctop_core4_1_virtual_pf0_ras_des_cap_enable DISABLE
ctop_core4_1_virtual_pf0_sn_cap_enable DISABLE
ctop_core4_1_virtual_pf0_tph_cap_enable DISABLE
ctop_core4_1_virtual_pf0_user_vsec_cap_enable DISABLE
ctop_core4_1_virtual_rp_ep_mode CTOP_CORE4_1_EP
ctop_core4_1_virtual_txeq_mode CTOP_CORE4_1_EQ_DISABLE
ctop_core4_1_vsec_next_offset 0
ctop_virtual_x41_perst_sel CTOP_CMN_HARD_X41
ctop_core8_clrhip_not_rst_sticky FALSE
ctop_core8_cvp_user_id 0
ctop_core8_en_gpio_perst FALSE
ctop_core8_exvf_msix_tablesize_pf0 0
ctop_core8_exvf_msix_tablesize_pf1 0
ctop_core8_exvf_msix_tablesize_pf2 0
ctop_core8_exvf_msix_tablesize_pf3 0
ctop_core8_exvf_msix_tablesize_pf4 0
ctop_core8_exvf_msix_tablesize_pf5 0
ctop_core8_exvf_msix_tablesize_pf6 0
ctop_core8_exvf_msix_tablesize_pf7 0
ctop_core8_exvf_msixpba_bir_pf0 0
ctop_core8_exvf_msixpba_bir_pf1 0
ctop_core8_exvf_msixpba_bir_pf2 0
ctop_core8_exvf_msixpba_bir_pf3 0
ctop_core8_exvf_msixpba_bir_pf4 0
ctop_core8_exvf_msixpba_bir_pf5 0
ctop_core8_exvf_msixpba_bir_pf6 0
ctop_core8_exvf_msixpba_bir_pf7 0
ctop_core8_exvf_msixpba_offset_pf0 0
ctop_core8_exvf_msixpba_offset_pf1 0
ctop_core8_exvf_msixpba_offset_pf2 0
ctop_core8_exvf_msixpba_offset_pf3 0
ctop_core8_exvf_msixpba_offset_pf4 0
ctop_core8_exvf_msixpba_offset_pf5 0
ctop_core8_exvf_msixpba_offset_pf6 0
ctop_core8_exvf_msixpba_offset_pf7 0
ctop_core8_exvf_msixtable_bir_pf0 0
ctop_core8_exvf_msixtable_bir_pf1 0
ctop_core8_exvf_msixtable_bir_pf2 0
ctop_core8_exvf_msixtable_bir_pf3 0
ctop_core8_exvf_msixtable_bir_pf4 0
ctop_core8_exvf_msixtable_bir_pf5 0
ctop_core8_exvf_msixtable_bir_pf6 0
ctop_core8_exvf_msixtable_bir_pf7 0
ctop_core8_exvf_msixtable_offset_pf0 0
ctop_core8_exvf_msixtable_offset_pf1 0
ctop_core8_exvf_msixtable_offset_pf2 0
ctop_core8_exvf_msixtable_offset_pf3 0
ctop_core8_exvf_msixtable_offset_pf4 0
ctop_core8_exvf_msixtable_offset_pf5 0
ctop_core8_exvf_msixtable_offset_pf6 0
ctop_core8_exvf_msixtable_offset_pf7 0
ctop_core8_exvf_subsysid_pf0 0
ctop_core8_exvf_subsysid_pf1 0
ctop_core8_exvf_subsysid_pf2 0
ctop_core8_exvf_subsysid_pf3 0
ctop_core8_exvf_subsysid_pf4 0
ctop_core8_exvf_subsysid_pf5 0
ctop_core8_exvf_subsysid_pf6 0
ctop_core8_exvf_subsysid_pf7 0
ctop_core8_exvf_ats_pagealignreq_pf0 FALSE
ctop_core8_exvf_ats_pagealignreq_pf1 FALSE
ctop_core8_exvf_ats_pagealignreq_pf2 FALSE
ctop_core8_exvf_ats_pagealignreq_pf3 FALSE
ctop_core8_exvf_ats_pagealignreq_pf4 FALSE
ctop_core8_exvf_ats_pagealignreq_pf5 FALSE
ctop_core8_exvf_ats_pagealignreq_pf6 FALSE
ctop_core8_exvf_ats_pagealignreq_pf7 FALSE
ctop_core8_pf0_acs_cap_acs_at_block DISABLE
ctop_core8_pf0_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf0_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf0_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf0_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf0_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf0_acs_cap_acs_src_valid DISABLE
ctop_core8_pf0_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf0_auto_lane_flip_ctrl_en ENABLE
ctop_core8_pf0_bar0_prefetch FALSE
ctop_core8_pf0_bar0_type CTOP_CORE8_PF0_BAR0_MEM32
ctop_core8_pf0_bar1_prefetch FALSE
ctop_core8_pf0_bar2_prefetch FALSE
ctop_core8_pf0_bar2_type CTOP_CORE8_PF0_BAR2_MEM32
ctop_core8_pf0_bar3_prefetch FALSE
ctop_core8_pf0_bar4_prefetch FALSE
ctop_core8_pf0_bar4_type CTOP_CORE8_PF0_BAR4_MEM32
ctop_core8_pf0_bar5_prefetch FALSE
ctop_core8_pf0_base_class_code 0
ctop_core8_pf0_eq_redo ENABLE
ctop_core8_pf0_eq_redo_atg4 ENABLE
ctop_core8_pf0_int_pin CTOP_CORE8_PF0_INTA
ctop_core8_pf0_gen3_eq_pset_req_vec 4
ctop_core8_pf0_gen3_eq_pset_req_vec_atg4 624
ctop_core8_pf0_loopback_enable FALSE
ctop_core8_pf0_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf0_pasid_cap_max_pasid_width 0
ctop_core8_pf0_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf0_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf0_pci_msi_ext_data_cap TRUE
ctop_core8_pf0_pci_msi_multiple_msg_cap CTOP_CORE8_PF0_MSI_VEC_32
ctop_core8_pf0_pci_msix_bir 0
ctop_core8_pf0_pci_msix_pba 0
ctop_core8_pf0_pci_msix_pba_offset 0
ctop_core8_pf0_pci_msix_table_offset 0
ctop_core8_pf0_pci_msix_table_size 255
ctop_core8_pf0_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf0_pci_type0_bar0_enabled ENABLE
ctop_core8_pf0_pci_type0_bar1_enabled ENABLE
ctop_core8_pf0_pci_type0_bar2_enabled ENABLE
ctop_core8_pf0_pci_type0_bar3_enabled ENABLE
ctop_core8_pf0_pci_type0_bar4_enabled ENABLE
ctop_core8_pf0_pci_type0_bar5_enabled ENABLE
ctop_core8_pf0_pci_type0_device_id 43981
ctop_core8_pf0_pci_type0_vendor_id 5827
ctop_core8_pf0_pcie_cap_attention_indicator FALSE
ctop_core8_pf0_pcie_cap_attention_indicator_button FALSE
ctop_core8_pf0_pcie_cap_electromech_interlock FALSE
ctop_core8_pf0_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf0_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf0_pcie_cap_ext_tag_supp CTOP_CORE8_PF0_SUPPORTED
ctop_core8_pf0_pcie_cap_flr_cap CTOP_CORE8_PF0_CAPABLE
ctop_core8_pf0_pcie_cap_hot_plug_capable FALSE
ctop_core8_pf0_pcie_cap_hot_plug_surprise FALSE
ctop_core8_pf0_pcie_cap_mrl_sensor FALSE
ctop_core8_pf0_pcie_cap_no_cmd_cpl_support FALSE
ctop_core8_pf0_pcie_cap_phy_slot_num 0
ctop_core8_pf0_pcie_cap_port_num 0
ctop_core8_pf0_pcie_cap_power_controller FALSE
ctop_core8_pf0_pcie_cap_power_indicator FALSE
ctop_core8_pf0_pcie_cap_sel_deemphasis CTOP_CORE8_PF0_MINUS_6DB
ctop_core8_pf0_pcie_cap_slot_clk_config FALSE
ctop_core8_pf0_pcie_cap_slot_power_limit_scale 0
ctop_core8_pf0_pcie_cap_slot_power_limit_value 0
ctop_core8_pf0_pcie_slot_imp CTOP_CORE8_PF0_NOT_IMPLEMENTED
ctop_core8_pf0_pme_support 27
ctop_core8_pf0_program_interface 0
ctop_core8_pf0_revision_id 1
ctop_core8_pf0_rom_bar_enabled ENABLE
ctop_core8_pf0_rp_rom_bar_enabled ENABLE
ctop_core8_pf0_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf0_sriov_sup_page_size 1363
ctop_core8_pf0_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf0_sriov_vf_bar0_type CTOP_CORE8_PF0_SRIOV_VF_BAR0_MEM32
ctop_core8_pf0_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf0_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf0_sriov_vf_bar2_type CTOP_CORE8_PF0_SRIOV_VF_BAR2_MEM32
ctop_core8_pf0_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf0_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf0_sriov_vf_bar4_type CTOP_CORE8_PF0_SRIOV_VF_BAR4_MEM32
ctop_core8_pf0_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf0_sriov_vf_device_id 43981
ctop_core8_pf0_sriov_vf_offset_ari_cs2 2
ctop_core8_pf0_sriov_vf_offset_nonari 256
ctop_core8_pf0_sriov_vf_stride_nonari 256
ctop_core8_pf0_subclass_code 0
ctop_core8_pf0_subsys_dev_id 0
ctop_core8_pf0_subsys_vendor_id 0
ctop_core8_pf0_tph_req_cap_int_vec DISABLE
ctop_core8_pf0_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf0_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF0_IN_TPH_STRUCT_VF
ctop_core8_pf0_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF0_NOT_IN_MSIX_TABLE
ctop_core8_pf0_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF0_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf0_tph_req_cap_st_table_size 1
ctop_core8_pf0_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf0_tph_req_device_spec DISABLE
ctop_core8_pf0_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf0_prs_outstanding_capacity 0
ctop_core8_pf1_acs_cap_acs_at_block DISABLE
ctop_core8_pf1_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf1_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf1_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf1_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf1_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf1_acs_cap_acs_src_valid DISABLE
ctop_core8_pf1_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf1_bar0_prefetch FALSE
ctop_core8_pf1_bar0_type CTOP_CORE8_PF1_BAR0_MEM32
ctop_core8_pf1_bar1_prefetch FALSE
ctop_core8_pf1_bar2_prefetch FALSE
ctop_core8_pf1_bar2_type CTOP_CORE8_PF1_BAR2_MEM32
ctop_core8_pf1_bar3_prefetch FALSE
ctop_core8_pf1_bar4_prefetch FALSE
ctop_core8_pf1_bar4_type CTOP_CORE8_PF1_BAR4_MEM32
ctop_core8_pf1_bar5_prefetch FALSE
ctop_core8_pf1_base_class_code 0
ctop_core8_pf1_int_pin CTOP_CORE8_PF1_INTA
ctop_core8_pf1_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf1_pasid_cap_max_pasid_width 0
ctop_core8_pf1_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf1_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf1_pci_msi_ext_data_cap TRUE
ctop_core8_pf1_pci_msi_multiple_msg_cap CTOP_CORE8_PF1_MSI_VEC_32
ctop_core8_pf1_pci_msix_bir 0
ctop_core8_pf1_pci_msix_pba 0
ctop_core8_pf1_pci_msix_pba_offset 0
ctop_core8_pf1_pci_msix_table_offset 0
ctop_core8_pf1_pci_msix_table_size 255
ctop_core8_pf1_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf1_pci_type0_bar0_enabled ENABLE
ctop_core8_pf1_pci_type0_bar1_enabled ENABLE
ctop_core8_pf1_pci_type0_bar2_enabled ENABLE
ctop_core8_pf1_pci_type0_bar3_enabled ENABLE
ctop_core8_pf1_pci_type0_bar4_enabled ENABLE
ctop_core8_pf1_pci_type0_bar5_enabled ENABLE
ctop_core8_pf1_pci_type0_device_id 43981
ctop_core8_pf1_pci_type0_vendor_id 5827
ctop_core8_pf1_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf1_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf1_pcie_cap_ext_tag_supp CTOP_CORE8_PF1_SUPPORTED
ctop_core8_pf1_pcie_cap_flr_cap CTOP_CORE8_PF1_CAPABLE
ctop_core8_pf1_pcie_cap_slot_clk_config FALSE
ctop_core8_pf1_pme_support 27
ctop_core8_pf1_program_interface 0
ctop_core8_pf1_revision_id 1
ctop_core8_pf1_rom_bar_enabled ENABLE
ctop_core8_pf1_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf1_sriov_sup_page_size 1363
ctop_core8_pf1_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf1_sriov_vf_bar0_type CTOP_CORE8_PF1_SRIOV_VF_BAR0_MEM32
ctop_core8_pf1_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf1_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf1_sriov_vf_bar2_type CTOP_CORE8_PF1_SRIOV_VF_BAR2_MEM32
ctop_core8_pf1_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf1_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf1_sriov_vf_bar4_type CTOP_CORE8_PF1_SRIOV_VF_BAR4_MEM32
ctop_core8_pf1_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf1_sriov_vf_device_id 43981
ctop_core8_pf1_sriov_vf_offset_ari_cs2 2
ctop_core8_pf1_sriov_vf_offset_position_nonari 256
ctop_core8_pf1_sriov_vf_stride_nonari 256
ctop_core8_pf1_subclass_code 0
ctop_core8_pf1_subsys_dev_id 0
ctop_core8_pf1_subsys_vendor_id 0
ctop_core8_pf1_tph_req_cap_int_vec DISABLE
ctop_core8_pf1_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf1_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF1_IN_TPH_STRUCT_VF
ctop_core8_pf1_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF1_NOT_IN_MSIX_TABLE
ctop_core8_pf1_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF1_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf1_tph_req_cap_st_table_size 1
ctop_core8_pf1_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf1_tph_req_device_spec DISABLE
ctop_core8_pf1_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf1_prs_outstanding_capacity 0
ctop_core8_pf2_acs_cap_acs_at_block DISABLE
ctop_core8_pf2_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf2_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf2_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf2_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf2_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf2_acs_cap_acs_src_valid DISABLE
ctop_core8_pf2_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf2_bar0_prefetch FALSE
ctop_core8_pf2_bar0_type CTOP_CORE8_PF2_BAR0_MEM32
ctop_core8_pf2_bar1_prefetch FALSE
ctop_core8_pf2_bar2_prefetch FALSE
ctop_core8_pf2_bar2_type CTOP_CORE8_PF2_BAR2_MEM32
ctop_core8_pf2_bar3_prefetch FALSE
ctop_core8_pf2_bar4_prefetch FALSE
ctop_core8_pf2_bar4_type CTOP_CORE8_PF2_BAR4_MEM32
ctop_core8_pf2_bar5_prefetch FALSE
ctop_core8_pf2_base_class_code 0
ctop_core8_pf2_int_pin CTOP_CORE8_PF2_INTA
ctop_core8_pf2_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf2_pasid_cap_max_pasid_width 0
ctop_core8_pf2_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf2_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf2_pci_msi_ext_data_cap TRUE
ctop_core8_pf2_pci_msi_multiple_msg_cap CTOP_CORE8_PF2_MSI_VEC_32
ctop_core8_pf2_pci_msix_bir 0
ctop_core8_pf2_pci_msix_pba 0
ctop_core8_pf2_pci_msix_pba_offset 0
ctop_core8_pf2_pci_msix_table_offset 0
ctop_core8_pf2_pci_msix_table_size 255
ctop_core8_pf2_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf2_pci_type0_bar0_enabled ENABLE
ctop_core8_pf2_pci_type0_bar1_enabled ENABLE
ctop_core8_pf2_pci_type0_bar2_enabled ENABLE
ctop_core8_pf2_pci_type0_bar3_enabled ENABLE
ctop_core8_pf2_pci_type0_bar4_enabled ENABLE
ctop_core8_pf2_pci_type0_bar5_enabled ENABLE
ctop_core8_pf2_pci_type0_device_id 43981
ctop_core8_pf2_pci_type0_vendor_id 5827
ctop_core8_pf2_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf2_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf2_pcie_cap_ext_tag_supp CTOP_CORE8_PF2_SUPPORTED
ctop_core8_pf2_pcie_cap_flr_cap CTOP_CORE8_PF2_CAPABLE
ctop_core8_pf2_pcie_cap_slot_clk_config FALSE
ctop_core8_pf2_pme_support 27
ctop_core8_pf2_program_interface 0
ctop_core8_pf2_revision_id 1
ctop_core8_pf2_rom_bar_enabled ENABLE
ctop_core8_pf2_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf2_sriov_sup_page_size 1363
ctop_core8_pf2_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf2_sriov_vf_bar0_type CTOP_CORE8_PF2_SRIOV_VF_BAR0_MEM32
ctop_core8_pf2_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf2_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf2_sriov_vf_bar2_type CTOP_CORE8_PF2_SRIOV_VF_BAR2_MEM32
ctop_core8_pf2_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf2_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf2_sriov_vf_bar4_type CTOP_CORE8_PF2_SRIOV_VF_BAR4_MEM32
ctop_core8_pf2_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf2_sriov_vf_device_id 43981
ctop_core8_pf2_sriov_vf_offset_ari_cs2 2
ctop_core8_pf2_sriov_vf_offset_position_nonari 256
ctop_core8_pf2_sriov_vf_stride_nonari 256
ctop_core8_pf2_subclass_code 0
ctop_core8_pf2_subsys_dev_id 0
ctop_core8_pf2_subsys_vendor_id 0
ctop_core8_pf2_tph_req_cap_int_vec DISABLE
ctop_core8_pf2_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf2_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF2_IN_TPH_STRUCT_VF
ctop_core8_pf2_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF2_NOT_IN_MSIX_TABLE
ctop_core8_pf2_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF2_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf2_tph_req_cap_st_table_size 1
ctop_core8_pf2_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf2_tph_req_device_spec DISABLE
ctop_core8_pf2_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf2_prs_outstanding_capacity 0
ctop_core8_pf3_acs_cap_acs_at_block DISABLE
ctop_core8_pf3_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf3_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf3_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf3_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf3_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf3_acs_cap_acs_src_valid DISABLE
ctop_core8_pf3_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf3_bar0_prefetch FALSE
ctop_core8_pf3_bar0_type CTOP_CORE8_PF3_BAR0_MEM32
ctop_core8_pf3_bar1_prefetch FALSE
ctop_core8_pf3_bar2_prefetch FALSE
ctop_core8_pf3_bar2_type CTOP_CORE8_PF3_BAR2_MEM32
ctop_core8_pf3_bar3_prefetch FALSE
ctop_core8_pf3_bar4_prefetch FALSE
ctop_core8_pf3_bar4_type CTOP_CORE8_PF3_BAR4_MEM32
ctop_core8_pf3_bar5_prefetch FALSE
ctop_core8_pf3_base_class_code 0
ctop_core8_pf3_int_pin CTOP_CORE8_PF3_INTA
ctop_core8_pf3_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf3_pasid_cap_max_pasid_width 0
ctop_core8_pf3_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf3_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf3_pci_msi_ext_data_cap TRUE
ctop_core8_pf3_pci_msi_multiple_msg_cap CTOP_CORE8_PF3_MSI_VEC_32
ctop_core8_pf3_pci_msix_bir 0
ctop_core8_pf3_pci_msix_pba 0
ctop_core8_pf3_pci_msix_pba_offset 0
ctop_core8_pf3_pci_msix_table_offset 0
ctop_core8_pf3_pci_msix_table_size 255
ctop_core8_pf3_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf3_pci_type0_bar0_enabled ENABLE
ctop_core8_pf3_pci_type0_bar1_enabled ENABLE
ctop_core8_pf3_pci_type0_bar2_enabled ENABLE
ctop_core8_pf3_pci_type0_bar3_enabled ENABLE
ctop_core8_pf3_pci_type0_bar4_enabled ENABLE
ctop_core8_pf3_pci_type0_bar5_enabled ENABLE
ctop_core8_pf3_pci_type0_device_id 43981
ctop_core8_pf3_pci_type0_vendor_id 5827
ctop_core8_pf3_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf3_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf3_pcie_cap_ext_tag_supp CTOP_CORE8_PF3_SUPPORTED
ctop_core8_pf3_pcie_cap_flr_cap CTOP_CORE8_PF3_CAPABLE
ctop_core8_pf3_pcie_cap_slot_clk_config FALSE
ctop_core8_pf3_pme_support 27
ctop_core8_pf3_program_interface 0
ctop_core8_pf3_revision_id 1
ctop_core8_pf3_rom_bar_enabled ENABLE
ctop_core8_pf3_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf3_sriov_sup_page_size 1363
ctop_core8_pf3_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf3_sriov_vf_bar0_type CTOP_CORE8_PF3_SRIOV_VF_BAR0_MEM32
ctop_core8_pf3_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf3_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf3_sriov_vf_bar2_type CTOP_CORE8_PF3_SRIOV_VF_BAR2_MEM32
ctop_core8_pf3_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf3_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf3_sriov_vf_bar4_type CTOP_CORE8_PF3_SRIOV_VF_BAR4_MEM32
ctop_core8_pf3_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf3_sriov_vf_device_id 43981
ctop_core8_pf3_sriov_vf_offset_ari_cs2 2
ctop_core8_pf3_sriov_vf_offset_position_nonari 256
ctop_core8_pf3_sriov_vf_stride_nonari 256
ctop_core8_pf3_subclass_code 0
ctop_core8_pf3_subsys_dev_id 0
ctop_core8_pf3_subsys_vendor_id 0
ctop_core8_pf3_tph_req_cap_int_vec DISABLE
ctop_core8_pf3_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf3_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF3_IN_TPH_STRUCT_VF
ctop_core8_pf3_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF3_NOT_IN_MSIX_TABLE
ctop_core8_pf3_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF3_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf3_tph_req_cap_st_table_size 1
ctop_core8_pf3_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf3_tph_req_device_spec DISABLE
ctop_core8_pf3_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf3_prs_outstanding_capacity 0
ctop_core8_pf4_acs_cap_acs_at_block DISABLE
ctop_core8_pf4_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf4_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf4_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf4_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf4_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf4_acs_cap_acs_src_valid DISABLE
ctop_core8_pf4_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf4_bar0_prefetch FALSE
ctop_core8_pf4_bar0_type CTOP_CORE8_PF4_BAR0_MEM32
ctop_core8_pf4_bar1_prefetch FALSE
ctop_core8_pf4_bar2_prefetch FALSE
ctop_core8_pf4_bar2_type CTOP_CORE8_PF4_BAR2_MEM32
ctop_core8_pf4_bar3_prefetch FALSE
ctop_core8_pf4_bar4_prefetch FALSE
ctop_core8_pf4_bar4_type CTOP_CORE8_PF4_BAR4_MEM32
ctop_core8_pf4_bar5_prefetch FALSE
ctop_core8_pf4_base_class_code 0
ctop_core8_pf4_int_pin CTOP_CORE8_PF4_INTA
ctop_core8_pf4_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf4_pasid_cap_max_pasid_width 0
ctop_core8_pf4_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf4_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf4_pci_msi_ext_data_cap TRUE
ctop_core8_pf4_pci_msi_multiple_msg_cap CTOP_CORE8_PF4_MSI_VEC_32
ctop_core8_pf4_pci_msix_bir 0
ctop_core8_pf4_pci_msix_pba 0
ctop_core8_pf4_pci_msix_pba_offset 0
ctop_core8_pf4_pci_msix_table_offset 0
ctop_core8_pf4_pci_msix_table_size 255
ctop_core8_pf4_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf4_pci_type0_bar0_enabled ENABLE
ctop_core8_pf4_pci_type0_bar1_enabled ENABLE
ctop_core8_pf4_pci_type0_bar2_enabled ENABLE
ctop_core8_pf4_pci_type0_bar3_enabled ENABLE
ctop_core8_pf4_pci_type0_bar4_enabled ENABLE
ctop_core8_pf4_pci_type0_bar5_enabled ENABLE
ctop_core8_pf4_pci_type0_device_id 43981
ctop_core8_pf4_pci_type0_vendor_id 5827
ctop_core8_pf4_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf4_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf4_pcie_cap_ext_tag_supp CTOP_CORE8_PF4_SUPPORTED
ctop_core8_pf4_pcie_cap_flr_cap CTOP_CORE8_PF4_CAPABLE
ctop_core8_pf4_pcie_cap_slot_clk_config FALSE
ctop_core8_pf4_pme_support 27
ctop_core8_pf4_program_interface 0
ctop_core8_pf4_revision_id 1
ctop_core8_pf4_rom_bar_enabled ENABLE
ctop_core8_pf4_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf4_sriov_sup_page_size 1363
ctop_core8_pf4_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf4_sriov_vf_bar0_type CTOP_CORE8_PF4_SRIOV_VF_BAR0_MEM32
ctop_core8_pf4_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf4_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf4_sriov_vf_bar2_type CTOP_CORE8_PF4_SRIOV_VF_BAR2_MEM32
ctop_core8_pf4_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf4_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf4_sriov_vf_bar4_type CTOP_CORE8_PF4_SRIOV_VF_BAR4_MEM32
ctop_core8_pf4_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf4_sriov_vf_device_id 43981
ctop_core8_pf4_sriov_vf_offset_ari_cs2 2
ctop_core8_pf4_sriov_vf_offset_position_nonari 256
ctop_core8_pf4_sriov_vf_stride_nonari 256
ctop_core8_pf4_subclass_code 0
ctop_core8_pf4_subsys_dev_id 0
ctop_core8_pf4_subsys_vendor_id 0
ctop_core8_pf4_tph_req_cap_int_vec DISABLE
ctop_core8_pf4_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf4_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF4_IN_TPH_STRUCT_VF
ctop_core8_pf4_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF4_NOT_IN_MSIX_TABLE
ctop_core8_pf4_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF4_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf4_tph_req_cap_st_table_size 1
ctop_core8_pf4_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf4_tph_req_device_spec DISABLE
ctop_core8_pf4_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf4_prs_outstanding_capacity 0
ctop_core8_pf5_acs_cap_acs_at_block DISABLE
ctop_core8_pf5_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf5_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf5_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf5_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf5_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf5_acs_cap_acs_src_valid DISABLE
ctop_core8_pf5_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf5_bar0_prefetch FALSE
ctop_core8_pf5_bar0_type CTOP_CORE8_PF5_BAR0_MEM32
ctop_core8_pf5_bar1_prefetch FALSE
ctop_core8_pf5_bar2_prefetch FALSE
ctop_core8_pf5_bar2_type CTOP_CORE8_PF5_BAR2_MEM32
ctop_core8_pf5_bar3_prefetch FALSE
ctop_core8_pf5_bar4_prefetch FALSE
ctop_core8_pf5_bar4_type CTOP_CORE8_PF5_BAR4_MEM32
ctop_core8_pf5_bar5_prefetch FALSE
ctop_core8_pf5_base_class_code 0
ctop_core8_pf5_int_pin CTOP_CORE8_PF5_INTA
ctop_core8_pf5_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf5_pasid_cap_max_pasid_width 0
ctop_core8_pf5_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf5_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf5_pci_msi_ext_data_cap TRUE
ctop_core8_pf5_pci_msi_multiple_msg_cap CTOP_CORE8_PF5_MSI_VEC_32
ctop_core8_pf5_pci_msix_bir 0
ctop_core8_pf5_pci_msix_pba 0
ctop_core8_pf5_pci_msix_pba_offset 0
ctop_core8_pf5_pci_msix_table_offset 0
ctop_core8_pf5_pci_msix_table_size 255
ctop_core8_pf5_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf5_pci_type0_bar0_enabled ENABLE
ctop_core8_pf5_pci_type0_bar1_enabled ENABLE
ctop_core8_pf5_pci_type0_bar2_enabled ENABLE
ctop_core8_pf5_pci_type0_bar3_enabled ENABLE
ctop_core8_pf5_pci_type0_bar4_enabled ENABLE
ctop_core8_pf5_pci_type0_bar5_enabled ENABLE
ctop_core8_pf5_pci_type0_device_id 43981
ctop_core8_pf5_pci_type0_vendor_id 5827
ctop_core8_pf5_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf5_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf5_pcie_cap_ext_tag_supp CTOP_CORE8_PF5_SUPPORTED
ctop_core8_pf5_pcie_cap_flr_cap CTOP_CORE8_PF5_CAPABLE
ctop_core8_pf5_pcie_cap_slot_clk_config FALSE
ctop_core8_pf5_pme_support 27
ctop_core8_pf5_program_interface 0
ctop_core8_pf5_revision_id 1
ctop_core8_pf5_rom_bar_enabled ENABLE
ctop_core8_pf5_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf5_sriov_sup_page_size 1363
ctop_core8_pf5_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf5_sriov_vf_bar0_type CTOP_CORE8_PF5_SRIOV_VF_BAR0_MEM32
ctop_core8_pf5_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf5_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf5_sriov_vf_bar2_type CTOP_CORE8_PF5_SRIOV_VF_BAR2_MEM32
ctop_core8_pf5_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf5_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf5_sriov_vf_bar4_type CTOP_CORE8_PF5_SRIOV_VF_BAR4_MEM32
ctop_core8_pf5_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf5_sriov_vf_device_id 43981
ctop_core8_pf5_sriov_vf_offset_ari_cs2 2
ctop_core8_pf5_sriov_vf_offset_position_nonari 256
ctop_core8_pf5_sriov_vf_stride_nonari 256
ctop_core8_pf5_subclass_code 0
ctop_core8_pf5_subsys_dev_id 0
ctop_core8_pf5_subsys_vendor_id 0
ctop_core8_pf5_tph_req_cap_int_vec DISABLE
ctop_core8_pf5_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf5_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF5_IN_TPH_STRUCT_VF
ctop_core8_pf5_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF5_NOT_IN_MSIX_TABLE
ctop_core8_pf5_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF5_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf5_tph_req_cap_st_table_size 1
ctop_core8_pf5_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf5_tph_req_device_spec DISABLE
ctop_core8_pf5_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf5_prs_outstanding_capacity 0
ctop_core8_pf6_acs_cap_acs_at_block DISABLE
ctop_core8_pf6_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf6_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf6_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf6_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf6_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf6_acs_cap_acs_src_valid DISABLE
ctop_core8_pf6_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf6_bar0_prefetch FALSE
ctop_core8_pf6_bar0_type CTOP_CORE8_PF6_BAR0_MEM32
ctop_core8_pf6_bar1_prefetch FALSE
ctop_core8_pf6_bar2_prefetch FALSE
ctop_core8_pf6_bar2_type CTOP_CORE8_PF6_BAR2_MEM32
ctop_core8_pf6_bar3_prefetch FALSE
ctop_core8_pf6_bar4_prefetch FALSE
ctop_core8_pf6_bar4_type CTOP_CORE8_PF6_BAR4_MEM32
ctop_core8_pf6_bar5_prefetch FALSE
ctop_core8_pf6_base_class_code 0
ctop_core8_pf6_int_pin CTOP_CORE8_PF6_INTA
ctop_core8_pf6_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf6_pasid_cap_max_pasid_width 0
ctop_core8_pf6_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf6_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf6_pci_msi_ext_data_cap TRUE
ctop_core8_pf6_pci_msi_multiple_msg_cap CTOP_CORE8_PF6_MSI_VEC_32
ctop_core8_pf6_pci_msix_bir 0
ctop_core8_pf6_pci_msix_pba 0
ctop_core8_pf6_pci_msix_pba_offset 0
ctop_core8_pf6_pci_msix_table_offset 0
ctop_core8_pf6_pci_msix_table_size 255
ctop_core8_pf6_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf6_pci_type0_bar0_enabled ENABLE
ctop_core8_pf6_pci_type0_bar1_enabled ENABLE
ctop_core8_pf6_pci_type0_bar2_enabled ENABLE
ctop_core8_pf6_pci_type0_bar3_enabled ENABLE
ctop_core8_pf6_pci_type0_bar4_enabled ENABLE
ctop_core8_pf6_pci_type0_bar5_enabled ENABLE
ctop_core8_pf6_pci_type0_device_id 43981
ctop_core8_pf6_pci_type0_vendor_id 5827
ctop_core8_pf6_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf6_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf6_pcie_cap_ext_tag_supp CTOP_CORE8_PF6_SUPPORTED
ctop_core8_pf6_pcie_cap_flr_cap CTOP_CORE8_PF6_CAPABLE
ctop_core8_pf6_pcie_cap_slot_clk_config FALSE
ctop_core8_pf6_pme_support 27
ctop_core8_pf6_program_interface 0
ctop_core8_pf6_revision_id 1
ctop_core8_pf6_rom_bar_enabled ENABLE
ctop_core8_pf6_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf6_sriov_sup_page_size 1363
ctop_core8_pf6_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf6_sriov_vf_bar0_type CTOP_CORE8_PF6_SRIOV_VF_BAR0_MEM32
ctop_core8_pf6_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf6_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf6_sriov_vf_bar2_type CTOP_CORE8_PF6_SRIOV_VF_BAR2_MEM32
ctop_core8_pf6_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf6_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf6_sriov_vf_bar4_type CTOP_CORE8_PF6_SRIOV_VF_BAR4_MEM32
ctop_core8_pf6_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf6_sriov_vf_device_id 43981
ctop_core8_pf6_sriov_vf_offset_ari_cs2 2
ctop_core8_pf6_sriov_vf_offset_position_nonari 256
ctop_core8_pf6_sriov_vf_stride_nonari 256
ctop_core8_pf6_subclass_code 0
ctop_core8_pf6_subsys_dev_id 0
ctop_core8_pf6_subsys_vendor_id 0
ctop_core8_pf6_tph_req_cap_int_vec DISABLE
ctop_core8_pf6_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf6_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF6_IN_TPH_STRUCT_VF
ctop_core8_pf6_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF6_NOT_IN_MSIX_TABLE
ctop_core8_pf6_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF6_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf6_tph_req_cap_st_table_size 1
ctop_core8_pf6_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf6_tph_req_device_spec DISABLE
ctop_core8_pf6_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf6_prs_outstanding_capacity 0
ctop_core8_pf7_acs_cap_acs_at_block DISABLE
ctop_core8_pf7_acs_cap_acs_direct_translated_p2p DISABLE
ctop_core8_pf7_acs_cap_acs_egress_ctrl_size 0
ctop_core8_pf7_acs_cap_acs_p2p_cpl_redirect DISABLE
ctop_core8_pf7_acs_cap_acs_p2p_egress_control DISABLE
ctop_core8_pf7_acs_cap_acs_p2p_req_redirect DISABLE
ctop_core8_pf7_acs_cap_acs_src_valid DISABLE
ctop_core8_pf7_acs_cap_acs_usp_forwarding DISABLE
ctop_core8_pf7_bar0_prefetch FALSE
ctop_core8_pf7_bar0_type CTOP_CORE8_PF7_BAR0_MEM32
ctop_core8_pf7_bar1_prefetch FALSE
ctop_core8_pf7_bar2_prefetch FALSE
ctop_core8_pf7_bar2_type CTOP_CORE8_PF7_BAR2_MEM32
ctop_core8_pf7_bar3_prefetch FALSE
ctop_core8_pf7_bar4_prefetch FALSE
ctop_core8_pf7_bar4_type CTOP_CORE8_PF7_BAR4_MEM32
ctop_core8_pf7_bar5_prefetch FALSE
ctop_core8_pf7_base_class_code 0
ctop_core8_pf7_int_pin CTOP_CORE8_PF7_INTA
ctop_core8_pf7_pasid_cap_execute_permission_supported DISABLE
ctop_core8_pf7_pasid_cap_max_pasid_width 0
ctop_core8_pf7_pasid_cap_privileged_mode_supported DISABLE
ctop_core8_pf7_pci_msi_64_bit_addr_cap TRUE
ctop_core8_pf7_pci_msi_ext_data_cap TRUE
ctop_core8_pf7_pci_msi_multiple_msg_cap CTOP_CORE8_PF7_MSI_VEC_32
ctop_core8_pf7_pci_msix_bir 0
ctop_core8_pf7_pci_msix_pba 0
ctop_core8_pf7_pci_msix_pba_offset 0
ctop_core8_pf7_pci_msix_table_offset 0
ctop_core8_pf7_pci_msix_table_size 255
ctop_core8_pf7_pci_msix_table_size_vfcomm_cs2 0
ctop_core8_pf7_pci_type0_bar0_enabled ENABLE
ctop_core8_pf7_pci_type0_bar1_enabled ENABLE
ctop_core8_pf7_pci_type0_bar2_enabled ENABLE
ctop_core8_pf7_pci_type0_bar3_enabled ENABLE
ctop_core8_pf7_pci_type0_bar4_enabled ENABLE
ctop_core8_pf7_pci_type0_bar5_enabled ENABLE
ctop_core8_pf7_pci_type0_device_id 43981
ctop_core8_pf7_pci_type0_vendor_id 5827
ctop_core8_pf7_pcie_cap_ep_l0s_accpt_latency 0
ctop_core8_pf7_pcie_cap_ep_l1_accpt_latency 0
ctop_core8_pf7_pcie_cap_ext_tag_supp CTOP_CORE8_PF7_SUPPORTED
ctop_core8_pf7_pcie_cap_flr_cap CTOP_CORE8_PF7_CAPABLE
ctop_core8_pf7_pcie_cap_slot_clk_config FALSE
ctop_core8_pf7_pme_support 27
ctop_core8_pf7_program_interface 0
ctop_core8_pf7_revision_id 1
ctop_core8_pf7_rom_bar_enabled ENABLE
ctop_core8_pf7_shadow_sriov_vf_stride_ari_cs2 2
ctop_core8_pf7_sriov_sup_page_size 1363
ctop_core8_pf7_sriov_vf_bar0_prefetch FALSE
ctop_core8_pf7_sriov_vf_bar0_type CTOP_CORE8_PF7_SRIOV_VF_BAR0_MEM32
ctop_core8_pf7_sriov_vf_bar1_prefetch FALSE
ctop_core8_pf7_sriov_vf_bar2_prefetch FALSE
ctop_core8_pf7_sriov_vf_bar2_type CTOP_CORE8_PF7_SRIOV_VF_BAR2_MEM32
ctop_core8_pf7_sriov_vf_bar3_prefetch FALSE
ctop_core8_pf7_sriov_vf_bar4_prefetch FALSE
ctop_core8_pf7_sriov_vf_bar4_type CTOP_CORE8_PF7_SRIOV_VF_BAR4_MEM32
ctop_core8_pf7_sriov_vf_bar5_prefetch FALSE
ctop_core8_pf7_sriov_vf_device_id 43981
ctop_core8_pf7_sriov_vf_offset_ari_cs2 2
ctop_core8_pf7_sriov_vf_offset_position_nonari 256
ctop_core8_pf7_sriov_vf_stride_nonari 256
ctop_core8_pf7_subclass_code 0
ctop_core8_pf7_subsys_dev_id 0
ctop_core8_pf7_subsys_vendor_id 0
ctop_core8_pf7_tph_req_cap_int_vec DISABLE
ctop_core8_pf7_tph_req_cap_int_vec_vfcomm_cs2 DISABLE
ctop_core8_pf7_tph_req_cap_st_table_loc_0_vfcomm_cs2 CTOP_CORE8_PF7_IN_TPH_STRUCT_VF
ctop_core8_pf7_tph_req_cap_st_table_loc_1 CTOP_CORE8_PF7_NOT_IN_MSIX_TABLE
ctop_core8_pf7_tph_req_cap_st_table_loc_1_vfcomm_cs2 CTOP_CORE8_PF7_NOT_IN_MSIX_TABLE_VF
ctop_core8_pf7_tph_req_cap_st_table_size 1
ctop_core8_pf7_tph_req_cap_st_table_size_vfcomm_cs2 1
ctop_core8_pf7_tph_req_device_spec DISABLE
ctop_core8_pf7_tph_req_device_spec_vfcomm_cs2 DISABLE
ctop_core8_pf7_prs_outstanding_capacity 0
ctop_core8_rxbuf_limit_bypass 0
ctop_core8_virtual_drop_vendor0_msg FALSE
ctop_core8_virtual_drop_vendor1_msg FALSE
ctop_core8_virtual_ep_native CTOP_CORE8_NATIVE
ctop_core8_virtual_link_rate CTOP_CORE8_GEN3
ctop_core8_virtual_link_width CTOP_CORE8_X16
ctop_core8_virtual_maxpayload_size CTOP_CORE8_MAX_PAYLOAD_1024
ctop_core8_virtual_num_of_lanes CTOP_CORE8_NUM_16
ctop_core8_virtual_pf0_acs_cap_enable DISABLE
ctop_core8_virtual_pf0_ats_cap_enable DISABLE
ctop_core8_virtual_pf0_dlink_cap_enable DISABLE
ctop_core8_virtual_pf0_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf0_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf0_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf0_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf0_exvf_virtio_en DISABLE
ctop_core8_virtual_pf0_io_decode CTOP_CORE8_IO32
ctop_core8_virtual_pf0_ltr_cap_enable DISABLE
ctop_core8_virtual_pf0_msi_enable DISABLE
ctop_core8_virtual_pf0_msix_enable DISABLE
ctop_core8_virtual_pf0_pasid_cap_enable DISABLE
ctop_core8_virtual_pf0_prefetch_decode CTOP_CORE8_PREF64
ctop_core8_virtual_pf0_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf0_ras_des_cap_enable DISABLE
ctop_core8_virtual_pf0_sn_cap_enable DISABLE
ctop_core8_virtual_pf0_sriov_enable DISABLE
ctop_core8_virtual_pf0_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf0_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf0_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf0_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf0_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf0_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf0_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf0_tph_cap_enable DISABLE
ctop_core8_virtual_pf0_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf0_virtio_en DISABLE
ctop_core8_virtual_pf1_acs_cap_enable DISABLE
ctop_core8_virtual_pf1_ats_cap_enable DISABLE
ctop_core8_virtual_pf1_enable DISABLE
ctop_core8_virtual_pf1_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf1_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf1_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf1_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf1_exvf_virtio_en DISABLE
ctop_core8_virtual_pf1_msi_enable DISABLE
ctop_core8_virtual_pf1_msix_enable DISABLE
ctop_core8_virtual_pf1_pasid_cap_enable DISABLE
ctop_core8_virtual_pf1_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf1_sriov_enable DISABLE
ctop_core8_virtual_pf1_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf1_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf1_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf1_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf1_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf1_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf1_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf1_tph_cap_enable DISABLE
ctop_core8_virtual_pf1_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf1_user_vsec_offset 0
ctop_core8_virtual_pf1_virtio_en DISABLE
ctop_core8_virtual_pf2_acs_cap_enable DISABLE
ctop_core8_virtual_pf2_ats_cap_enable DISABLE
ctop_core8_virtual_pf2_enable DISABLE
ctop_core8_virtual_pf2_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf2_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf2_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf2_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf2_exvf_virtio_en DISABLE
ctop_core8_virtual_pf2_msi_enable DISABLE
ctop_core8_virtual_pf2_msix_enable DISABLE
ctop_core8_virtual_pf2_pasid_cap_enable DISABLE
ctop_core8_virtual_pf2_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf2_sriov_enable DISABLE
ctop_core8_virtual_pf2_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf2_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf2_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf2_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf2_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf2_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf2_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf2_tph_cap_enable DISABLE
ctop_core8_virtual_pf2_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf2_user_vsec_offset 0
ctop_core8_virtual_pf2_virtio_en DISABLE
ctop_core8_virtual_pf3_acs_cap_enable DISABLE
ctop_core8_virtual_pf3_ats_cap_enable DISABLE
ctop_core8_virtual_pf3_enable DISABLE
ctop_core8_virtual_pf3_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf3_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf3_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf3_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf3_exvf_virtio_en DISABLE
ctop_core8_virtual_pf3_msi_enable DISABLE
ctop_core8_virtual_pf3_msix_enable DISABLE
ctop_core8_virtual_pf3_pasid_cap_enable DISABLE
ctop_core8_virtual_pf3_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf3_sriov_enable DISABLE
ctop_core8_virtual_pf3_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf3_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf3_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf3_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf3_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf3_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf3_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf3_tph_cap_enable DISABLE
ctop_core8_virtual_pf3_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf3_user_vsec_offset 0
ctop_core8_virtual_pf3_virtio_en DISABLE
ctop_core8_virtual_pf4_acs_cap_enable DISABLE
ctop_core8_virtual_pf4_ats_cap_enable DISABLE
ctop_core8_virtual_pf4_enable DISABLE
ctop_core8_virtual_pf4_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf4_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf4_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf4_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf4_exvf_virtio_en DISABLE
ctop_core8_virtual_pf4_msi_enable DISABLE
ctop_core8_virtual_pf4_msix_enable DISABLE
ctop_core8_virtual_pf4_pasid_cap_enable DISABLE
ctop_core8_virtual_pf4_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf4_sriov_enable DISABLE
ctop_core8_virtual_pf4_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf4_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf4_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf4_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf4_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf4_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf4_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf4_tph_cap_enable DISABLE
ctop_core8_virtual_pf4_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf4_user_vsec_offset 0
ctop_core8_virtual_pf4_virtio_en DISABLE
ctop_core8_virtual_pf5_acs_cap_enable DISABLE
ctop_core8_virtual_pf5_ats_cap_enable DISABLE
ctop_core8_virtual_pf5_enable DISABLE
ctop_core8_virtual_pf5_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf5_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf5_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf5_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf5_exvf_virtio_en DISABLE
ctop_core8_virtual_pf5_msi_enable DISABLE
ctop_core8_virtual_pf5_msix_enable DISABLE
ctop_core8_virtual_pf5_pasid_cap_enable DISABLE
ctop_core8_virtual_pf5_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf5_sriov_enable DISABLE
ctop_core8_virtual_pf5_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf5_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf5_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf5_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf5_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf5_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf5_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf5_tph_cap_enable DISABLE
ctop_core8_virtual_pf5_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf5_user_vsec_offset 0
ctop_core8_virtual_pf5_virtio_en DISABLE
ctop_core8_virtual_pf6_acs_cap_enable DISABLE
ctop_core8_virtual_pf6_ats_cap_enable DISABLE
ctop_core8_virtual_pf6_enable DISABLE
ctop_core8_virtual_pf6_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf6_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf6_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf6_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf6_exvf_virtio_en DISABLE
ctop_core8_virtual_pf6_msi_enable DISABLE
ctop_core8_virtual_pf6_msix_enable DISABLE
ctop_core8_virtual_pf6_pasid_cap_enable DISABLE
ctop_core8_virtual_pf6_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf6_sriov_enable DISABLE
ctop_core8_virtual_pf6_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf6_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf6_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf6_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf6_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf6_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf6_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf6_tph_cap_enable DISABLE
ctop_core8_virtual_pf6_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf6_user_vsec_offset 0
ctop_core8_virtual_pf6_virtio_en DISABLE
ctop_core8_virtual_pf7_acs_cap_enable DISABLE
ctop_core8_virtual_pf7_ats_cap_enable DISABLE
ctop_core8_virtual_pf7_enable DISABLE
ctop_core8_virtual_pf7_exvf_acs_cap_enable DISABLE
ctop_core8_virtual_pf7_exvf_ats_cap_enable DISABLE
ctop_core8_virtual_pf7_exvf_msix_cap_enable DISABLE
ctop_core8_virtual_pf7_exvf_tph_cap_enable DISABLE
ctop_core8_virtual_pf7_exvf_virtio_en DISABLE
ctop_core8_virtual_pf7_msi_enable DISABLE
ctop_core8_virtual_pf7_msix_enable DISABLE
ctop_core8_virtual_pf7_pasid_cap_enable DISABLE
ctop_core8_virtual_pf7_prs_ext_cap_enable DISABLE
ctop_core8_virtual_pf7_sriov_enable DISABLE
ctop_core8_virtual_pf7_sriov_num_vf_non_ari 0
ctop_core8_virtual_pf7_sriov_vf_bar0_enabled DISABLE
ctop_core8_virtual_pf7_sriov_vf_bar1_enabled DISABLE
ctop_core8_virtual_pf7_sriov_vf_bar2_enabled DISABLE
ctop_core8_virtual_pf7_sriov_vf_bar3_enabled DISABLE
ctop_core8_virtual_pf7_sriov_vf_bar4_enabled DISABLE
ctop_core8_virtual_pf7_sriov_vf_bar5_enabled DISABLE
ctop_core8_virtual_pf7_tph_cap_enable DISABLE
ctop_core8_virtual_pf7_user_vsec_cap_enable DISABLE
ctop_core8_virtual_pf7_user_vsec_offset 0
ctop_core8_virtual_pf7_virtio_en DISABLE
ctop_core8_virtual_rp_ep_mode CTOP_CORE8_EP
ctop_core8_virtual_txeq_mode CTOP_CORE8_EQ_DISABLE
ctop_core8_vsec_next_offset 0
ctop_core16_cfg_ptm_local_clock_adj_lsb 0
ctop_core16_cfg_ptm_local_clock_adj_msb 0
ctop_core8_cfg_ptm_local_clock_adj_lsb 0
ctop_core8_cfg_ptm_local_clock_adj_msb 0
ctop_virtual_x8_perst_sel CTOP_CMN_HARD_X8
virtual_sris_enable DISABLE_SRIS
virtual_tlp_bypass_en ENABLE_TLBP
silicon_rev Unknown
ctop_virtual_ptm CTOP_DISABLED
ctop_core16_virtual_ptm_autoupdate CTOP_CORE16_AUTOUPDATE_10MS
ctop_core8_virtual_ptm_autoupdate CTOP_CORE8_AUTOUPDATE_10MS
core16_use_ast_parity_hwtcl 0
select_design_example_hwtcl PIO using MQDMA Bypass mode
mode_hwtcl BAM_MCDMA
uport_type_hwtcl AVMM
num_ports_hwtcl 1
pf0_num_dma_chan_pf_hwtcl 4
enable_user_msix_hwtcl 0
enable_user_flr_hwtcl 0
d2h_num_active_channel_hwtcl 8
d2h_max_num_desc_fetch_hwtcl 16
en_metadata_8_hwtcl 0
enable_user_hip_reconfig_sel_hwtcl 0
enable_byte_aligned_txfr_hwtcl 0
enable_pld_warm_rst_rdy_hwtcl 0
mc_pf0_bar2_type_user_hwtcl Disabled
mc_pf0_bar3_type_user_hwtcl Disabled
mc_pf0_bar4_type_user_hwtcl 64-bit prefetchable memory
mc_pf0_bar4_address_width_user_hwtcl 24
mc_pf0_bar5_type_user_hwtcl Disabled
mc_pf0_expansion_base_address_register_hwtcl 0
mc_pf4_expansion_base_address_register_hwtcl 0
mc_pf5_expansion_base_address_register_hwtcl 0
mc_pf6_expansion_base_address_register_hwtcl 0
mc_pf7_expansion_base_address_register_hwtcl 0
m1_bar2_address_width_hwtcl 22
m1_mode_hwtcl MCDMA
m1_uport_type_hwtcl AVMM
m1_num_ports_hwtcl 1
m1_pf0_num_dma_chan_pf_hwtcl 4
m1_enable_user_msix_hwtcl 0
m1_enable_user_flr_hwtcl 0
m1_d2h_num_active_channel_hwtcl 8
m1_d2h_max_num_desc_fetch_hwtcl 16
m1_en_metadata_8_hwtcl 0
m1_enable_user_hip_reconfig_sel_hwtcl 0
m1_enable_byte_aligned_txfr_hwtcl 0
m1_enable_pld_warm_rst_rdy_hwtcl 0
m1_mc_pf0_bar0_type_user_hwtcl 64-bit prefetchable memory
m1_mc_pf0_bar0_address_width_user_hwtcl 16
m1_mc_pf0_bar1_type_user_hwtcl Disabled
m1_mc_pf0_bar2_type_user_hwtcl Disabled
m1_mc_pf0_bar3_type_user_hwtcl Disabled
m1_mc_pf0_bar4_type_user_hwtcl Disabled
m1_mc_pf0_bar5_type_user_hwtcl Disabled
m1_mc_pf0_expansion_base_address_register_hwtcl 0
m1_mc_pf4_expansion_base_address_register_hwtcl 0
m1_mc_pf5_expansion_base_address_register_hwtcl 0
m1_mc_pf6_expansion_base_address_register_hwtcl 0
m1_mc_pf7_expansion_base_address_register_hwtcl 0
enable_port_bifurcation_hwtcl 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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