qsys_top

2023.01.26.22:47:13 Datasheet
Overview
Processor
   niosv_cpu Abbotts Lake 22.3.0
All Components
   fpga_m2ocm_pb altera_avalon_mm_bridge 20.0.1
   ocm altera_avalon_onchip_memory2 19.3.6
   sysid altera_avalon_sysid_qsys 19.1.2
   niosv_cpu intel_niosv_m 22.3.0
   niosv_jtag_uart altera_avalon_jtag_uart 19.2.0
   niosv_ram altera_avalon_onchip_memory2 19.3.6
   periph subsys_periph 1.0
   periph_ILC interrupt_latency_counter 19.1.0
   periph_button_pio altera_avalon_pio 19.2.0
   periph_dipsw_pio altera_avalon_pio 19.2.0
   periph_led_pio altera_avalon_pio 19.2.0
   periph_pb_cpu_0 altera_avalon_mm_bridge 20.0.1
Memory Map
jtg_mst jtg_mst_fpga_m jtg_mst_hps_m
 fpga_m_master  hps_m_master  master  master
  ocm
s1  0x80000000 0x80000000
  sysid
control_slave  0x00000000 0x00000000
  niosv_cpu
timer_sw_agent 
dm_agent 
  niosv_jtag_uart
avalon_jtag_slave 
  niosv_ram
s1 
  periph
pb_cpu_0_s0 
  periph_ILC
avalon_slave  0x00001100 0x00001100
  periph_button_pio
s1  0x00001060 0x00001060
  periph_dipsw_pio
s1  0x00001070 0x00001070
  periph_led_pio
s1  0x00001080 0x00001080

agilex_hps

intel_agilex_hps v23.0.0
jtg_mst_hps_m master   agilex_hps
  f2h_axi_slave
clk_100 out_clk  
  f2h_axi_clock
out_clk  
  h2f_axi_clock
out_clk  
  h2f_lw_axi_clock
emif_hps hps_emif  
  hps_emif
rst_in out_reset  
  f2h_axi_reset
out_reset  
  h2f_axi_reset
out_reset  
  h2f_lw_axi_reset
h2f_axi_master   ocm
  s1
h2f_lw_axi_master   sysid
  control_slave
h2f_lw_axi_master   periph_pb_cpu_0
  s0
f2h_irq0   periph_button_pio
  irq
f2h_irq0   periph_dipsw_pio
  irq


Parameters

generateLegacySim false
  

Software Assignments

(none)

clk_100

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_calbus_0

altera_emif_cal v2.6.1
emif_hps emif_calbus   emif_calbus_0
  emif_calbus_0
emif_calbus_clk   emif_hps
  emif_calbus_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_hps

altera_emif_fm_hps v2.6.1
emif_calbus_0 emif_calbus_clk   emif_hps
  emif_calbus_clk
emif_calbus   emif_calbus_0
  emif_calbus_0
hps_emif   agilex_hps
  hps_emif


Parameters

generateLegacySim false
  

Software Assignments

(none)

fpga_m2ocm_pb

altera_avalon_mm_bridge v20.0.1
jtg_mst_fpga_m master   fpga_m2ocm_pb
  s0
clk_100 out_clk  
  clk
rst_in out_reset  
  reset
m0   ocm
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

ocm

altera_avalon_onchip_memory2 v19.3.6
agilex_hps h2f_axi_master   ocm
  s1
fpga_m2ocm_pb m0  
  s1
clk_100 out_clk  
  clk1
rst_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE ocm_altera_avalon_onchip_memory2_inst
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 1
SIZE_MULTIPLE 1
SIZE_VALUE 262144
WRITABLE 1

rst_in

altera_reset_bridge v19.2.0
clk_100 out_clk   rst_in
  clk
out_reset   agilex_hps
  f2h_axi_reset
out_reset  
  h2f_axi_reset
out_reset  
  h2f_lw_axi_reset
out_reset   sysid
  reset
out_reset   jtg_mst_jtag_rst_in
  in_reset
out_reset   fpga_m2ocm_pb
  reset
out_reset   periph_periph_rst_in
  in_reset
out_reset   niosv_niosv_rst_in
  in_reset
out_reset   ocm
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)

sysid

altera_avalon_sysid_qsys v19.1.2
jtg_mst_fpga_m master   sysid
  control_slave
agilex_hps h2f_lw_axi_master  
  control_slave
clk_100 out_clk  
  clk
rst_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID -1395275010
TIMESTAMP 0

user_rst_clkgate_0

altera_s10_user_rst_clkgate v19.4.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtg_mst

subsys_jtg_mst v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtg_mst_fpga_m

altera_jtag_avalon_master v19.1
jtg_mst_jtag_clk out_clk   jtg_mst_fpga_m
  clk
jtg_mst_jtag_rst_in out_reset  
  clk_reset
master   sysid
  control_slave
master   periph_pb_cpu_0
  s0
master   fpga_m2ocm_pb
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtg_mst_hps_m

altera_jtag_avalon_master v19.1
jtg_mst_jtag_clk out_clk   jtg_mst_hps_m
  clk
jtg_mst_jtag_rst_in out_reset  
  clk_reset
master   agilex_hps
  f2h_axi_slave


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtg_mst_jtag_clk

altera_clock_bridge v19.2.0
clk_100 out_clk   jtg_mst_jtag_clk
  in_clk
out_clk   jtg_mst_fpga_m
  clk
out_clk   jtg_mst_jtag_rst_in
  clk
out_clk   jtg_mst_hps_m
  clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtg_mst_jtag_rst_in

altera_reset_bridge v19.2.0
jtg_mst_jtag_clk out_clk   jtg_mst_jtag_rst_in
  clk
rst_in out_reset  
  in_reset
out_reset   jtg_mst_fpga_m
  clk_reset
out_reset   jtg_mst_hps_m
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv

subsys_niosv v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv_cpu

intel_niosv_m v22.3.0
niosv_niosv_clk out_clk   niosv_cpu
  clk
niosv_niosv_rst_in out_reset  
  reset
niosv_niosv_issp_reset_in out_reset  
  reset
data_manager   niosv_jtag_uart
  avalon_jtag_slave
platform_irq_rx  
  irq
data_manager   niosv_ram
  s1
instruction_manager  
  s1


Parameters

generateLegacySim false
  

Software Assignments

CPU_FREQ 100000000u
DATA_ADDR_WIDTH 32
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
HAS_DEBUG_STUB
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
INST_ADDR_WIDTH 32
MTIME_OFFSET 0x00090000
NUM_GPR 32
RESET_ADDR 0x00000000
TICKS_PER_SEC no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE 2

niosv_jtag_uart

altera_avalon_jtag_uart v19.2.0
niosv_cpu data_manager   niosv_jtag_uart
  avalon_jtag_slave
platform_irq_rx  
  irq
niosv_niosv_clk out_clk  
  clk
niosv_niosv_rst_in out_reset  
  reset
niosv_niosv_issp_reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

niosv_niosv_clk

altera_clock_bridge v19.2.0
clk_100 out_clk   niosv_niosv_clk
  in_clk
out_clk   niosv_cpu
  clk
out_clk   niosv_jtag_uart
  clk
out_clk   niosv_niosv_rst_in
  clk
out_clk   niosv_niosv_issp_reset_in
  clk
out_clk   niosv_ram
  clk1
out_clk   niosv_niosv_issp_reset_out
  source_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv_niosv_issp_reset_in

altera_reset_bridge v19.2.0
niosv_niosv_clk out_clk   niosv_niosv_issp_reset_in
  clk
out_reset   niosv_cpu
  reset
out_reset   niosv_jtag_uart
  reset
out_reset   niosv_ram
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv_niosv_issp_reset_out

altera_in_system_sources_probes v19.2.1
niosv_niosv_clk out_clk   niosv_niosv_issp_reset_out
  source_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv_niosv_rst_in

altera_reset_bridge v19.2.0
niosv_niosv_clk out_clk   niosv_niosv_rst_in
  clk
rst_in out_reset  
  in_reset
out_reset   niosv_cpu
  reset
out_reset   niosv_jtag_uart
  reset
out_reset   niosv_ram
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv_ram

altera_avalon_onchip_memory2 v19.3.6
niosv_cpu data_manager   niosv_ram
  s1
instruction_manager  
  s1
niosv_niosv_clk out_clk  
  clk1
niosv_niosv_rst_in out_reset  
  reset1
niosv_niosv_issp_reset_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE ram_altera_avalon_onchip_memory2_inst
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 262144
WRITABLE 1

periph

subsys_periph v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

periph_ILC

interrupt_latency_counter v19.1.0
periph_pb_cpu_0 m0   periph_ILC
  avalon_slave
periph_periph_clk out_clk  
  clk
periph_periph_rst_in out_reset  
  reset_n
irq   periph_button_pio
  irq
irq   periph_dipsw_pio
  irq


Parameters

generateLegacySim false
  

Software Assignments

(none)

periph_button_pio

altera_avalon_pio v19.2.0
periph_pb_cpu_0 m0   periph_button_pio
  s1
periph_periph_clk out_clk  
  clk
periph_periph_rst_in out_reset  
  reset
periph_ILC irq  
  irq
agilex_hps f2h_irq0  
  irq


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

periph_dipsw_pio

altera_avalon_pio v19.2.0
periph_pb_cpu_0 m0   periph_dipsw_pio
  s1
periph_periph_clk out_clk  
  clk
periph_periph_rst_in out_reset  
  reset
periph_ILC irq  
  irq
agilex_hps f2h_irq0  
  irq


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

periph_led_pio

altera_avalon_pio v19.2.0
periph_pb_cpu_0 m0   periph_led_pio
  s1
periph_periph_clk out_clk  
  clk
periph_periph_rst_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

periph_pb_cpu_0

altera_avalon_mm_bridge v20.0.1
periph_periph_clk out_clk   periph_pb_cpu_0
  clk
periph_periph_rst_in out_reset  
  reset
jtg_mst_fpga_m master  
  s0
agilex_hps h2f_lw_axi_master  
  s0
m0   periph_ILC
  avalon_slave
m0   periph_led_pio
  s1
m0   periph_dipsw_pio
  s1
m0   periph_button_pio
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

periph_periph_clk

altera_clock_bridge v19.2.0
clk_100 out_clk   periph_periph_clk
  in_clk
out_clk   periph_pb_cpu_0
  clk
out_clk   periph_periph_rst_in
  clk
out_clk   periph_ILC
  clk
out_clk   periph_led_pio
  clk
out_clk   periph_dipsw_pio
  clk
out_clk   periph_button_pio
  clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

periph_periph_rst_in

altera_reset_bridge v19.2.0
periph_periph_clk out_clk   periph_periph_rst_in
  clk
rst_in out_reset  
  in_reset
out_reset   periph_led_pio
  reset
out_reset   periph_dipsw_pio
  reset
out_reset   periph_button_pio
  reset
out_reset   periph_pb_cpu_0
  reset
out_reset   periph_ILC
  reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)
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