2023.03.23.17:17:24 |
Datasheet |
Overview
Memory Map
BAM_INTERPRETER
intel_pcie_bam_interpreter v1.1
Software Assignments(none) |
mem
intel_onchip_memory v1.4.2
Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR |
0 |
CONTENTS_INFO |
"" |
DUAL_PORT |
1 |
GUI_RAM_BLOCK_TYPE |
AUTO |
INIT_CONTENTS_FILE |
UNUSED |
INIT_MEM_CONTENT |
0 |
INSTANCE_ID |
NONE |
NON_DEFAULT_INIT_FILE_ENABLED |
0 |
RAM_BLOCK_TYPE |
AUTO |
READ_DURING_WRITE_MODE |
DONT_CARE |
SINGLE_CLOCK_OP |
0 |
SIZE_MULTIPLE |
1 |
SIZE_VALUE |
524288 |
WRITABLE |
1 |
|
mm_bridge_bar4
altera_avalon_mm_bridge v20.0.1
Software Assignments(none) |
mm_bridge_onchip_mem
altera_avalon_mm_bridge v20.0.1
pcie_ftile_mcdma
|
p0_h2ddm_master |
mm_bridge_onchip_mem |
s0 |
app_clk |
clk |
app_nreset_status |
reset |
|
|
m0 |
mem
|
|
|
s2 |
Software Assignments(none) |
pcie_ftile_mcdma
intel_pcie_ftile_mcdma v4.0.0
systemclk_f
|
out_refclk_fgt_0 |
pcie_ftile_mcdma |
refclk0 |
out_refclk_fgt_0 |
refclk1 |
out_systempll_clk_0 |
pcie_systempll_clk |
|
resetIP
|
ninit_done |
ninit_done |
|
|
p0_bam_master |
BAM_INTERPRETER
|
|
|
AVMM_BAM_Slave |
|
|
app_clk |
|
|
clock |
|
|
app_nreset_status |
|
|
reset |
|
|
|
p0_d2hdm_master |
mem
|
|
|
s1 |
|
|
app_clk |
|
|
clk1 |
|
|
app_nreset_status |
|
|
reset1 |
|
|
|
p0_h2ddm_master |
mm_bridge_onchip_mem
|
|
|
s0 |
|
|
app_clk |
|
|
clk |
|
|
app_nreset_status |
|
|
reset |
|
|
|
app_clk |
mm_bridge_bar4
|
|
|
clk |
|
|
app_nreset_status |
|
|
reset |
|
|
|
app_clk |
pio_led
|
|
|
clk |
|
|
app_nreset_status |
|
|
reset |
|
|
|
app_clk |
pio_button
|
|
|
clk |
|
|
app_nreset_status |
|
|
reset |
Software Assignments(none) |
pio_button
altera_avalon_pio v19.2.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
2 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
0 |
HAS_IN |
1 |
HAS_OUT |
0 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
pio_led
altera_avalon_pio v19.2.0
Software Assignments
BIT_CLEARING_EDGE_REGISTER |
0 |
BIT_MODIFYING_OUTPUT_REGISTER |
0 |
CAPTURE |
0 |
DATA_WIDTH |
2 |
DO_TEST_BENCH_WIRING |
0 |
DRIVEN_SIM_VALUE |
0 |
EDGE_TYPE |
NONE |
FREQ |
0 |
HAS_IN |
0 |
HAS_OUT |
1 |
HAS_TRI |
0 |
IRQ_TYPE |
NONE |
RESET_VALUE |
0 |
|
resetIP
altera_s10_user_rst_clkgate v19.4.1
Software Assignments(none) |
systemclk_f
systemclk_f v2.2.0
Software Assignments(none) |
generation took 0.00 seconds |
rendering took 0.02 seconds |