mm_clock_crossing_bridge_ddr4

2023.03.23.17:15:34 Datasheet
Overview

All Components
   mm_clock_crossing_bridge_ddr4 mm_ccb 19.2.1
Memory Map

mm_clock_crossing_bridge_ddr4

mm_ccb v19.2.1


Parameters

DATA_WIDTH 512
SYMBOL_WIDTH 8
ADDRESS_WIDTH 33
USE_AUTO_ADDRESS_WIDTH 0
AUTO_ADDRESS_WIDTH 33
ADDRESS_UNITS SYMBOLS
MAX_BURST_SIZE 16
COMMAND_FIFO_DEPTH 64
RESPONSE_FIFO_DEPTH 512
MASTER_SYNC_DEPTH 2
SLAVE_SYNC_DEPTH 2
SYNC_RESET 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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