agilex_hps

2023.01.26.22:47:34 Datasheet
Overview

Memory Map
intel_agilex_hps_inst_arm_a9_0 intel_agilex_hps_inst_arm_a9_1
 altera_axi_master  altera_axi_master

intel_agilex_hps_inst

intel_agilex_hps v23.0.0


Parameters

MPU_EVENTS_Enable false
GP_Enable false
DEBUG_APB_Enable false
STM_Enable true
CTI_Enable false
DDR_ATB_Enable false
IPXACT_Enable false
F2S_mode 0
F2S_Width 5
F2S_ADDRESS_WIDTH 32
F2S_Route_config 1
S2F_Width 3
S2F_ADDRESS_WIDTH 32
LWH2F_Enable 1
LWH2F_ADDRESS_WIDTH 21
EMIF_CONDUIT_Enable true
EMIF_DDR_WIDTH 64
SMMU_sid_config 0
SMMU_ssd_config 0
DMA_PeriphId_DERIVED 0,1,2,3,4,5,6,7
DMA_Enable No,No,No,No,No,No,No,No
F2SINTERRUPT_Enable true
S2FINTERRUPT_CLOCKPERIPHERAL_Enable false
S2FINTERRUPT_DMA_Enable false
S2FINTERRUPT_EMAC0_Enable false
S2FINTERRUPT_EMAC1_Enable false
S2FINTERRUPT_EMAC2_Enable false
S2FINTERRUPT_GPIO_Enable false
S2FINTERRUPT_I2CEMAC0_Enable false
S2FINTERRUPT_I2CEMAC1_Enable false
S2FINTERRUPT_I2CEMAC2_Enable false
S2FINTERRUPT_I2C0_Enable false
S2FINTERRUPT_I2C1_Enable false
S2FINTERRUPT_L4TIMER_Enable false
S2FINTERRUPT_NAND_Enable false
S2FINTERRUPT_SYSTIMER_Enable false
S2FINTERRUPT_SDMMC_Enable false
S2FINTERRUPT_SPIM0_Enable false
S2FINTERRUPT_SPIM1_Enable false
S2FINTERRUPT_SPIS0_Enable false
S2FINTERRUPT_SPIS1_Enable false
S2FINTERRUPT_SYSTEMMANAGER_Enable false
S2FINTERRUPT_UART0_Enable false
S2FINTERRUPT_UART1_Enable false
S2FINTERRUPT_USB0_Enable false
S2FINTERRUPT_USB1_Enable false
S2FINTERRUPT_WATCHDOG_Enable false
eosc1_clk_mhz 25.0
F2H_FREE_CLK_Enable false
F2H_FREE_CLK_FREQ 200
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 125
DEFAULT_MPU_CLK 1200
USE_DEFAULT_MPU_CLK false
CUSTOM_MPU_CLK 800.0
H2F_USER0_CLK_Enable false
H2F_USER0_CLK_FREQ 500
H2F_USER1_CLK_Enable false
H2F_USER1_CLK_FREQ 500
L3_MAIN_FREE_CLK 400
L4_SYS_FREE_CLK 2
L4_SYS_FREE_CLK_HZ 100
NOCDIV_L4MAINCLK 0
NOCDIV_L4MAINCLK_HZ 400
NOCDIV_L4MPCLK 1
NOCDIV_L4MPCLK_HZ 200
NOCDIV_L4SPCLK 2
NOCDIV_L4SPCLK_HZ 100
NOCDIV_CS_ATCLK 0
NOCDIV_CS_ATCLK_HZ 400
NOCDIV_CS_PDBGCLK 2
NOCDIV_CS_PDBGCLK_HZ 100
NOCDIV_CS_TRACECLK 0
NOCDIV_CS_TRACECLK_HZ 400
HPS_DIV_GPIO_FREQ2 100
CONFIG_HPS_DIV_GPIO 1
EMAC0_CLK 250
EMAC1_CLK 250
EMAC2_CLK 250
MANUAL_PERPLL_CFREQ_EN false
MANUAL_PERPLL_C0 1200.0
MANUAL_PERPLL_C2 480.0
MANUAL_PERPLL_C3 200.0
CLK_MAIN_PLL_SOURCE2 0
CLK_PERI_PLL_SOURCE2 0
MANUAL_CLK_SRC_EN false
CLK_MPU_SOURCE 1
CLK_NOC_SOURCE 1
CLK_S2F_USER0_SOURCE 0
CLK_S2F_USER1_SOURCE 0
CLK_PSI_SOURCE 0
CLK_EMAC_PTP_SOURCE 1
CLK_GPIO_SOURCE 1
CLK_SDMMC_SOURCE 1
CLK_EMACA_SOURCE 0
CLK_EMACB_SOURCE 1
H2F_PENDING_RST_Enable false
H2F_COLD_RST_Enable false
watchdog_reset true
W_RESET_ACTION 0
IO_INPUT_DELAY0 0
IO_OUTPUT_DELAY0 0
IO_INPUT_DELAY1 0
IO_OUTPUT_DELAY1 0
IO_INPUT_DELAY2 0
IO_OUTPUT_DELAY2 0
IO_INPUT_DELAY3 0
IO_OUTPUT_DELAY3 0
IO_INPUT_DELAY4 0
IO_OUTPUT_DELAY4 0
IO_INPUT_DELAY5 0
IO_OUTPUT_DELAY5 0
IO_INPUT_DELAY6 0
IO_OUTPUT_DELAY6 0
IO_INPUT_DELAY7 0
IO_OUTPUT_DELAY7 0
IO_INPUT_DELAY8 0
IO_OUTPUT_DELAY8 0
IO_INPUT_DELAY9 0
IO_OUTPUT_DELAY9 0
IO_INPUT_DELAY10 0
IO_OUTPUT_DELAY10 0
IO_INPUT_DELAY11 0
IO_OUTPUT_DELAY11 0
IO_INPUT_DELAY12 0
IO_OUTPUT_DELAY12 45
IO_INPUT_DELAY13 0
IO_OUTPUT_DELAY13 0
IO_INPUT_DELAY14 0
IO_OUTPUT_DELAY14 0
IO_INPUT_DELAY15 0
IO_OUTPUT_DELAY15 0
IO_INPUT_DELAY16 0
IO_OUTPUT_DELAY16 0
IO_INPUT_DELAY17 0
IO_OUTPUT_DELAY17 0
IO_INPUT_DELAY18 0
IO_OUTPUT_DELAY18 0
IO_INPUT_DELAY19 0
IO_OUTPUT_DELAY19 0
IO_INPUT_DELAY20 0
IO_OUTPUT_DELAY20 0
IO_INPUT_DELAY21 0
IO_OUTPUT_DELAY21 0
IO_INPUT_DELAY22 0
IO_OUTPUT_DELAY22 0
IO_INPUT_DELAY23 0
IO_OUTPUT_DELAY23 0
IO_INPUT_DELAY24 0
IO_OUTPUT_DELAY24 0
IO_INPUT_DELAY25 0
IO_OUTPUT_DELAY25 0
IO_INPUT_DELAY26 0
IO_OUTPUT_DELAY26 0
IO_INPUT_DELAY27 0
IO_OUTPUT_DELAY27 0
IO_INPUT_DELAY28 0
IO_OUTPUT_DELAY28 0
IO_INPUT_DELAY29 0
IO_OUTPUT_DELAY29 0
IO_INPUT_DELAY30 0
IO_OUTPUT_DELAY30 0
IO_INPUT_DELAY31 0
IO_OUTPUT_DELAY31 0
IO_INPUT_DELAY32 0
IO_OUTPUT_DELAY32 0
IO_INPUT_DELAY33 0
IO_OUTPUT_DELAY33 0
IO_INPUT_DELAY34 0
IO_OUTPUT_DELAY34 0
IO_INPUT_DELAY35 0
IO_OUTPUT_DELAY35 0
IO_INPUT_DELAY36 0
IO_OUTPUT_DELAY36 0
IO_INPUT_DELAY37 0
IO_OUTPUT_DELAY37 0
IO_INPUT_DELAY38 0
IO_OUTPUT_DELAY38 0
IO_INPUT_DELAY39 0
IO_OUTPUT_DELAY39 0
IO_INPUT_DELAY40 0
IO_OUTPUT_DELAY40 0
IO_INPUT_DELAY41 0
IO_OUTPUT_DELAY41 0
IO_INPUT_DELAY42 0
IO_OUTPUT_DELAY42 0
IO_INPUT_DELAY43 0
IO_OUTPUT_DELAY43 0
IO_INPUT_DELAY44 0
IO_OUTPUT_DELAY44 0
IO_INPUT_DELAY45 0
IO_OUTPUT_DELAY45 0
IO_INPUT_DELAY46 0
IO_OUTPUT_DELAY46 0
IO_INPUT_DELAY47 0
IO_OUTPUT_DELAY47 0
HPS_IOA_1_open_drain_en false
HPS_IOA_2_open_drain_en false
HPS_IOA_3_open_drain_en false
HPS_IOA_4_open_drain_en false
HPS_IOA_5_open_drain_en false
HPS_IOA_6_open_drain_en false
HPS_IOA_7_open_drain_en false
HPS_IOA_8_open_drain_en false
HPS_IOA_9_open_drain_en false
HPS_IOA_10_open_drain_en false
HPS_IOA_11_open_drain_en false
HPS_IOA_12_open_drain_en false
HPS_IOA_13_open_drain_en false
HPS_IOA_14_open_drain_en false
HPS_IOA_15_open_drain_en false
HPS_IOA_16_open_drain_en false
HPS_IOA_17_open_drain_en false
HPS_IOA_18_open_drain_en false
HPS_IOA_19_open_drain_en false
HPS_IOA_20_open_drain_en false
HPS_IOA_21_open_drain_en false
HPS_IOA_22_open_drain_en false
HPS_IOA_23_open_drain_en false
HPS_IOA_24_open_drain_en false
HPS_IOB_1_open_drain_en false
HPS_IOB_2_open_drain_en false
HPS_IOB_3_open_drain_en false
HPS_IOB_4_open_drain_en false
HPS_IOB_5_open_drain_en false
HPS_IOB_6_open_drain_en false
HPS_IOB_7_open_drain_en false
HPS_IOB_8_open_drain_en false
HPS_IOB_9_open_drain_en false
HPS_IOB_10_open_drain_en false
HPS_IOB_11_open_drain_en false
HPS_IOB_12_open_drain_en false
HPS_IOB_13_open_drain_en false
HPS_IOB_14_open_drain_en false
HPS_IOB_15_open_drain_en false
HPS_IOB_16_open_drain_en false
HPS_IOB_17_open_drain_en false
HPS_IOB_18_open_drain_en false
HPS_IOB_19_open_drain_en false
HPS_IOB_20_open_drain_en false
HPS_IOB_21_open_drain_en false
HPS_IOB_22_open_drain_en false
HPS_IOB_23_open_drain_en false
HPS_IOB_24_open_drain_en false
EMAC0_PTP false
EMAC1_PTP false
EMAC2_PTP false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_fpga_interfaces

intel_agilex_interface_generator v19.1


Parameters

device_name AGFB027R24C2E2VR2
interfaceDefinition constraints {if\ \{\[get_collection_size\ \[get_nodes\ \ -nowarn\ hps_inst|s2f_module~l4_mp_clk\ \]\]\ >\ 0\}\ \{ {create_clock -name hps_l4_mp_clk_src -period 5.0 [get_nodes hps_inst|s2f_module~l4_mp_clk]} {create_generated_clock -divide_by 1 -name hps_l4_mp_clk [get_registers hps_inst|s2f_module~l4_mp_clk.reg] -master_clock [get_clocks hps_l4_mp_clk_src] -source [get_nodes hps_inst|s2f_module~l4_mp_clk]} \}} instances {hps_inst {parameters {} signal_widths {dbgapbdisable 1 f2s_pending_rst_ack 1 f2s_free_clk 1 tpiu_trace_ctl 1 pclkendbg 1} entity_name tennm_hps_hps_wrapper location HPSHPS_X334_Y333_N1 signal_terminations {dbgapbdisable {0:0 0} f2s_pending_rst_ack {0:0 1} f2s_free_clk {0:0 0} tpiu_trace_ctl {0:0 1} pclkendbg {0:0 0}} signal_default_terminations {dbgapbdisable 0 f2s_pending_rst_ack 1 f2s_free_clk 1 tpiu_trace_ctl 1 pclkendbg 0}} emif_interface {signal_widths {} parameters {} location {} entity_name one_hps_interface_ddr signal_default_terminations {} signal_terminations {}} @orderednames {hps_inst emif_interface}} interfaces {@orderednames {h2f_reset h2f_watchdog_rst f2h_stm_hw_events h2f_cs hps_emif hps_io} h2f_reset {properties {associatedResetSinks none synchronousEdges none} direction Output type reset signals {@orderednames h2f_rst h2f_rst {width 1 properties {} instance_name hps_inst internal_name s2f_rst direction Output role reset fragments {}}}} h2f_watchdog_rst {properties {associatedResetSinks none synchronousEdges none} direction Output type reset signals {@orderednames h2f_watchdog_rst h2f_watchdog_rst {width 1 properties {} instance_name hps_inst internal_name s2f_watchdog_rst direction Output role reset_n fragments {}}}} f2h_stm_hw_events {properties {} direction Input type conduit signals {@orderednames f2h_stm_hwevents f2h_stm_hwevents {width 44 properties {} instance_name hps_inst internal_name cs_hwevents_fpga direction Input role stm_hwevents fragments {}}}} h2f_cs {properties {} direction Input type conduit signals {@orderednames {h2f_cs_ntrst h2f_cs_tck h2f_cs_tdi h2f_cs_tdo h2f_cs_tdoen h2f_cs_tms} h2f_cs_ntrst {width 1 properties {} instance_name hps_inst internal_name cs_ntrst_fpga direction Input role ntrst fragments {}} h2f_cs_tck {width 1 properties {} instance_name hps_inst internal_name cs_tck_fpga direction Input role tck fragments {}} h2f_cs_tdi {width 1 properties {} instance_name hps_inst internal_name cs_tdi_fpga direction Input role tdi fragments {}} h2f_cs_tdo {width 1 properties {} instance_name hps_inst internal_name cs_tdo_fpga direction Output role tdo fragments {}} h2f_cs_tdoen {width 1 properties {} instance_name hps_inst internal_name cs_tdoen_fpga direction Output role tdoen fragments {}} h2f_cs_tms {width 1 properties {} instance_name hps_inst internal_name cs_tms_fpga direction Input role tms fragments {}}}} hps_emif {properties {} direction Output type conduit signals {@orderednames {hps_emif_emif_to_hps hps_emif_hps_to_emif hps_emif_emif_to_gp hps_emif_gp_to_emif} hps_emif_emif_to_hps {width 4096 properties {} instance_name emif_interface internal_name io48_b_cdata_pb0_in direction Input role emif_to_hps fragments {}} hps_emif_hps_to_emif {width 4096 properties {} instance_name emif_interface internal_name io48_b_iod_pb0_out direction Output role hps_to_emif fragments {}} hps_emif_emif_to_gp {width 1 properties {} instance_name hps_emif internal_name hps_emif_emif_to_gp direction Input role emif_to_gp fragments {}} hps_emif_gp_to_emif {width 2 properties {} instance_name hps_emif internal_name hps_emif_gp_to_emif direction Output role gp_to_emif fragments {}}}} hps_io {properties {} direction bidir type conduit signals {@orderednames {EMAC0_TX_CLK EMAC0_TXD0 EMAC0_TXD1 EMAC0_TXD2 EMAC0_TXD3 EMAC0_RX_CTL EMAC0_TX_CTL EMAC0_RX_CLK EMAC0_RXD0 EMAC0_RXD1 EMAC0_RXD2 EMAC0_RXD3 EMAC0_MDIO EMAC0_MDC SDMMC_CMD SDMMC_D0 SDMMC_D1 SDMMC_D2 SDMMC_D3 SDMMC_CCLK UART0_RX UART0_TX gpio1_io0 gpio1_io1 hps_osc_clk jtag_tck jtag_tms jtag_tdo jtag_tdi} EMAC0_TX_CLK {width 1 properties {} instance_name hps_io internal_name EMAC0_TX_CLK direction output bidir {{} EMAC0_TX_CLK_out} role EMAC0_TX_CLK open_drain false fragments {}} EMAC0_TXD0 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD0 direction output bidir {{} EMAC0_TXD0_out} role EMAC0_TXD0 open_drain false fragments {}} EMAC0_TXD1 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD1 direction output bidir {{} EMAC0_TXD1_out} role EMAC0_TXD1 open_drain false fragments {}} EMAC0_TXD2 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD2 direction output bidir {{} EMAC0_TXD2_out} role EMAC0_TXD2 open_drain false fragments {}} EMAC0_TXD3 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD3 direction output bidir {{} EMAC0_TXD3_out} role EMAC0_TXD3 open_drain false fragments {}} EMAC0_RX_CTL {width 1 properties {} instance_name hps_io internal_name EMAC0_RX_CTL direction input bidir {EMAC0_RX_CTL_in {}} role EMAC0_RX_CTL open_drain false fragments {}} EMAC0_TX_CTL {width 1 properties {} instance_name hps_io internal_name EMAC0_TX_CTL direction output bidir {{} EMAC0_TX_CTL_out} role EMAC0_TX_CTL open_drain false fragments {}} EMAC0_RX_CLK {width 1 properties {} instance_name hps_io internal_name EMAC0_RX_CLK direction input bidir {EMAC0_RX_CLK_in {}} role EMAC0_RX_CLK open_drain false fragments {}} EMAC0_RXD0 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD0 direction input bidir {EMAC0_RXD0_in {}} role EMAC0_RXD0 open_drain false fragments {}} EMAC0_RXD1 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD1 direction input bidir {EMAC0_RXD1_in {}} role EMAC0_RXD1 open_drain false fragments {}} EMAC0_RXD2 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD2 direction input bidir {EMAC0_RXD2_in {}} role EMAC0_RXD2 open_drain false fragments {}} EMAC0_RXD3 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD3 direction input bidir {EMAC0_RXD3_in {}} role EMAC0_RXD3 open_drain false fragments {}} EMAC0_MDIO {width 1 properties {} instance_name hps_io internal_name EMAC0_MDIO direction bidir bidir {EMAC0_MDIO_in EMAC0_MDIO_out} role EMAC0_MDIO open_drain false fragments {}} EMAC0_MDC {width 1 properties {} instance_name hps_io internal_name EMAC0_MDC direction output bidir {{} EMAC0_MDC_out} role EMAC0_MDC open_drain false fragments {}} SDMMC_CMD {width 1 properties {} instance_name hps_io internal_name SDMMC_CMD direction bidir bidir {SDMMC_CMD_in SDMMC_CMD_out} role SDMMC_CMD open_drain false fragments {}} SDMMC_D0 {width 1 properties {} instance_name hps_io internal_name SDMMC_D0 direction bidir bidir {SDMMC_D0_in SDMMC_D0_out} role SDMMC_D0 open_drain false fragments {}} SDMMC_D1 {width 1 properties {} instance_name hps_io internal_name SDMMC_D1 direction bidir bidir {SDMMC_D1_in SDMMC_D1_out} role SDMMC_D1 open_drain false fragments {}} SDMMC_D2 {width 1 properties {} instance_name hps_io internal_name SDMMC_D2 direction bidir bidir {SDMMC_D2_in SDMMC_D2_out} role SDMMC_D2 open_drain false fragments {}} SDMMC_D3 {width 1 properties {} instance_name hps_io internal_name SDMMC_D3 direction bidir bidir {SDMMC_D3_in SDMMC_D3_out} role SDMMC_D3 open_drain false fragments {}} SDMMC_CCLK {width 1 properties {} instance_name hps_io internal_name SDMMC_CCLK direction output bidir {{} SDMMC_CCLK_out} role SDMMC_CCLK open_drain false fragments {}} UART0_RX {width 1 properties {} instance_name hps_io internal_name UART0_RX direction input bidir {UART0_RX_in {}} role UART0_RX open_drain false fragments {}} UART0_TX {width 1 properties {} instance_name hps_io internal_name UART0_TX direction output bidir {{} UART0_TX_out} role UART0_TX open_drain false fragments {}} gpio1_io0 {width 1 properties {} instance_name hps_io internal_name gpio1_io0 direction bidir bidir {gpio1_io0_in gpio1_io0_out} role gpio1_io0 open_drain false fragments {}} gpio1_io1 {width 1 properties {} instance_name hps_io internal_name gpio1_io1 direction bidir bidir {gpio1_io1_in gpio1_io1_out} role gpio1_io1 open_drain false fragments {}} hps_osc_clk {width 1 properties {} instance_name hps_io internal_name hps_osc_clk direction input bidir {hps_osc_clk_in {}} role hps_osc_clk open_drain false fragments {}} jtag_tck {width 1 properties {} instance_name hps_io internal_name jtag_tck direction input bidir {jtag_tck_in {}} role jtag_tck open_drain false fragments {}} jtag_tms {width 1 properties {} instance_name hps_io internal_name jtag_tms direction input bidir {jtag_tms_in {}} role jtag_tms open_drain false fragments {}} jtag_tdo {width 1 properties {} instance_name hps_io internal_name jtag_tdo direction output bidir {{} jtag_tdo_out} role jtag_tdo open_drain false fragments {}} jtag_tdi {width 1 properties {} instance_name hps_io internal_name jtag_tdi direction input bidir {jtag_tdi_in {}} role jtag_tdi open_drain false fragments {}}}}} properties {} interface_sim_style {} raw_assigns {} intermediate_wire_count 0 raw_assign_sim_style {} wires_to_fragments {SDMMC_D3_in {input hps_inst:HPS_IOB_18_I(0:0)} EMAC0_TX_CTL_out {output hps_inst:HPS_IOA_14_O(0:0)} EMAC0_RXD1_in {input hps_inst:HPS_IOA_20_I(0:0)} jtag_tdo_out {output hps_inst:HPS_IOB_11_O(0:0)} UART0_RX_in {input hps_inst:HPS_IOB_4_I(0:0)} jtag_tdi_in {input hps_inst:HPS_IOB_12_I(0:0)} EMAC0_RXD3_in {input hps_inst:HPS_IOA_24_I(0:0)} jtag_tck_in {input hps_inst:HPS_IOB_9_I(0:0)} gpio1_io0_in {input hps_inst:HPS_IOB_1_I(0:0)} SDMMC_D0_in {input hps_inst:HPS_IOB_13_I(0:0)} SDMMC_CMD_in {input hps_inst:HPS_IOB_14_I(0:0)} EMAC0_MDIO_out {output hps_inst:HPS_IOB_23_O(0:0)} gpio1_io0_out {output hps_inst:HPS_IOB_1_O(0:0)} UART0_TX_out {output hps_inst:HPS_IOB_3_O(0:0)} SDMMC_D0_out {output hps_inst:HPS_IOB_13_O(0:0)} SDMMC_CMD_out {output hps_inst:HPS_IOB_14_O(0:0)} jtag_tms_in {input hps_inst:HPS_IOB_10_I(0:0)} gpio1_io1_out {output hps_inst:HPS_IOB_2_O(0:0)} SDMMC_CCLK_out {output hps_inst:HPS_IOB_15_O(0:0)} SDMMC_D2_in {input hps_inst:HPS_IOB_17_I(0:0)} SDMMC_D1_out {output hps_inst:HPS_IOB_16_O(0:0)} SDMMC_D2_out {output hps_inst:HPS_IOB_17_O(0:0)} EMAC0_MDC_out {output hps_inst:HPS_IOB_24_O(0:0)} SDMMC_D3_out {output hps_inst:HPS_IOB_18_O(0:0)} EMAC0_TX_CLK_out {output hps_inst:HPS_IOA_13_O(0:0)} EMAC0_RXD0_in {input hps_inst:HPS_IOA_19_I(0:0)} EMAC0_RXD2_in {input hps_inst:HPS_IOA_23_I(0:0)} EMAC0_MDIO_in {input hps_inst:HPS_IOB_23_I(0:0)} EMAC0_TXD0_out {output hps_inst:HPS_IOA_17_O(0:0)} EMAC0_TXD1_out {output hps_inst:HPS_IOA_18_O(0:0)} hps_osc_clk_in {input hps_inst:HPS_IOB_6_I(0:0)} gpio1_io1_in {input hps_inst:HPS_IOB_2_I(0:0)} SDMMC_D1_in {input hps_inst:HPS_IOB_16_I(0:0)} EMAC0_TXD2_out {output hps_inst:HPS_IOA_21_O(0:0)} EMAC0_RX_CLK_in {input hps_inst:HPS_IOA_15_I(0:0)} EMAC0_TXD3_out {output hps_inst:HPS_IOA_22_O(0:0)} EMAC0_RX_CTL_in {input hps_inst:HPS_IOA_16_I(0:0)}} wire_sim_style {}
qipEntries
ignoreSimulation false
hps_parameter_map H2F_DEBUG_APB_CLOCK_FREQ 100 quartus_ini_hps_ip_enable_jtag false EMIF_DDR_WIDTH 64 io1_delay_is_present false HPS_IO15_is_present true io11_delay_is_present false SPIS1_Mode N/A MANUAL_PERPLL_C0 1200.0 test_iface_definition {DFT_IN_APS_TEST_SI 16 input DFT_IN_ATPG_CLK_SEL_N 1 input DFT_IN_ATPG_MODE_N 1 input DFT_IN_ATSPEED_DEFAULT_EN_N 1 input DFT_IN_ATSPEED_EN 1 input DFT_IN_BIST_EN_N 1 input DFT_IN_CLKOD_SCANCLK 1 input DFT_IN_CLKOD_SCANIN 1 input DFT_IN_COMPRESS_ENABLE_N 1 input DFT_IN_DFTMCPHOLD 1 input DFT_IN_DFTRAMHOLD 1 input DFT_IN_DFTRSTDISABLE 1 input DFT_IN_IO_CONFIG_N 32 input DFT_IN_IO_TEST_MODE_N 1 input DFT_IN_JTAG_HIGHZ_N 1 input DFT_IN_JTAG_MODE_N 1 input RST_DFX_OUT_DATA 23 output DFT_IN_MBIST_TCK 1 input DFT_IN_MBIST_TDI 1 input DFT_IN_MBIST_TMS 1 input DFT_IN_MBIST_TRST_N 1 input DFT_IN_MEM_DFTCLKEN 1 input DFT_IN_MEM_DFTMASK 1 input DFT_IN_MEMCONTROL_SHIFT_EN 1 input DFT_IN_MEMCONTROL_SHIFT_IN 1 input DFT_IN_MEMCONTROL_SHIFT_OUT 1 output DFT_IN_PSI_LINK_SHIFT_OUT_EN 1 input DFT_IN_PSI_LINK_TEST_EN_N 1 input DFT_IN_PSI_SCAN_MODE_N 1 input DFT_IN_PSI_SI 40 input DFT_IN_PSI_TEST_CLK 1 input DFT_IN_SCANEN_N 1 input DFT_OUT_APS_TEST_SO 4 output DFT_OUT_CLKOD_SCANOUT 1 output DFT_OUT_MAIN_MEM_REF_SO 3 output DFT_OUT_MAIN_MOD_SO 1 output DFT_OUT_MAIN_TDO 1 output DFT_OUT_MAINPLL_CLKOUT 1 output DFT_OUT_MBIST_TDO 1 output DFT_OUT_MPU_TEST_SO 5 output DFT_OUT_OSC_CLKOUT 1 output DFT_OUT_PERI_MEM_REF_SO 3 output DFT_OUT_PERI_MOD_SO 1 output DFT_OUT_PERI_REF_SO 5 output DFT_OUT_PERI_TDO 1 output DFT_OUT_PERIPLL_CLKOUT 1 output DFT_OUT_PSS_TEST_SO 6 output DFT_OUT_RAMRPR_CHAIN0_RSCOUT 1 output DFT_OUT_RAMRPR_CHAIN1_RSCOUT 1 output DFT_OUT_RAMRPR_CHAIN2_RSCOUT 1 output DFT_OUT_RAMRPR_CHAIN3_RSCOUT 1 output DFT_OUT_TDO 1 output DFT_OUT_PSI_SO 1 output DFT_OUT_MAIN_REF_SO 5 output DFT_OUT_TEST_OCC_SO 3 output DFT_OUT_TESTMODE_STATUS_N 1 output DFT_OUT_SPARE_OUT 32 output DFT_IN_MPU_TEST_SI 40 input DFT_IN_OCC_ENABLE_N 1 input DFT_IN_PERI_JTAG_ID 8 input DFT_IN_PERI_JTAG_RST_N 1 input DFT_IN_PERI_MEM_REF_SI 3 input DFT_IN_PERI_MOD_SI 1 input DFT_IN_PERI_PD_N 1 input DFT_IN_PERI_REF_SI 5 input DFT_IN_PERI_RST_N 1 input DFT_IN_PERI_TCK 1 input DFT_IN_PERI_TDI 1 input DFT_IN_PERI_TMS 1 input DFT_IN_PIPELINE_SCAN_EN_N 1 input DFT_IN_PLL_CLK_TESTBUS_SEL 2 input DFT_IN_PLL_DEBUG_TESTBUS_SEL 1 input DFT_IN_PLL_SCAN_MODE_EN 1 input DFT_IN_PLLBYPASS_SEL 1 input DFT_IN_PLLTEST_INPUT_EN 1 input DFT_IN_JTAG_SHFTDR_N 1 input DFT_IN_JTAG_UPDATE_DR_N 1 input DFT_IN_L4MPCLK_DIV_CTL_N 1 input DFT_IN_LOAN_IO_ENABLE_N 1 input DFT_IN_MAIN_JTAG_ID 8 input DFT_IN_MAIN_JTAG_RST_N 1 input DFT_IN_MAIN_MEM_REF_SI 3 input DFT_IN_MAIN_MOD_SI 1 input DFT_IN_MAIN_PD_N 1 input DFT_IN_MAIN_REF_SI 5 input DFT_IN_MAIN_RST_N 1 input DFT_IN_MAIN_SCAN_RST_N 1 input DFT_IN_MAIN_TCK 1 input DFT_IN_MAIN_TDI 1 input DFT_IN_MAIN_TMS 1 input DFT_IN_PSS_TEST_SI 24 input DFT_IN_RAMRPR_CHAIN0_FISO 1 input DFT_IN_RAMRPR_CHAIN0_RSCEN 1 input DFT_IN_RAMRPR_CHAIN0_RSCIN 1 input DFT_IN_RAMRPR_CHAIN0_RSCLK 1 input DFT_IN_RAMRPR_CHAIN0_RSCRST 1 input DFT_IN_RAMRPR_CHAIN1_FISO 1 input DFT_IN_RAMRPR_CHAIN1_RSCEN 1 input DFT_IN_RAMRPR_CHAIN1_RSCIN 1 input DFT_IN_RAMRPR_CHAIN1_RSCLK 1 input DFT_IN_RAMRPR_CHAIN1_RSCRST 1 input DFT_IN_RAMRPR_CHAIN2_FISO 1 input DFT_IN_RAMRPR_CHAIN2_RSCEN 1 input DFT_IN_RAMRPR_CHAIN2_RSCIN 1 input DFT_IN_RAMRPR_CHAIN2_RSCLK 1 input DFT_IN_RAMRPR_CHAIN2_RSCRST 1 input DFT_IN_RAMRPR_CHAIN3_FISO 1 input DFT_IN_RAMRPR_CHAIN3_RSCEN 1 input DFT_IN_RAMRPR_CHAIN3_RSCIN 1 input DFT_IN_RAMRPR_CHAIN3_RSCLK 1 input DFT_IN_RAMRPR_CHAIN3_RSCRST 1 input DFT_IN_RAMRPR_SEL 1 input DFT_IN_S2F_TEST_INPUT 1 input DFT_IN_S2F_TEST_OVERRIDE_N 1 input DFT_IN_SPARE_IN 32 input DFT_IN_TCK 1 input DFT_IN_TDI 1 input DFT_IN_TEST_CLOCK 1 input DFT_IN_TEST_INIT_N 1 input DFT_IN_TEST_OCC_SI 3 input DFT_IN_TEST_RESET_N 1 input DFT_IN_TESTMODE_N 1 input DFT_IN_PERI_SCAN_RST_N 1 input DFT_OUT_PLL_LOCKOUT 1 output} MANUAL_PERPLL_C2 480.0 HPS_IOB_6_open_drain_en false H2F_AXI_CLOCK_FREQ 100000000 PERPLL_FDIV_EN false MANUAL_PERPLL_C3 200.0 I2CEMAC0_PinMuxing Unused io27_delay_is_present false MAINPLLGRP_C0_CNT 3 JAVA_WARNING_MSG {} CLK_SDMMC_SOURCE 1 HPS_IOB_21_open_drain_en false S2FINTERRUPT_NAND_Enable false mdio2_usefpga_is_present false HPS_IO38_is_present true JAVA_ERROR_MSG {} io44_delay_is_present false I2CEMAC2_Mode N/A vccl_hps 810 CLK_EMAC_PTP_SOURCE 1 DB_iface_ports {emac0_tx_clk_in {@orderednames emac0_clk_tx_i emac0_clk_tx_i {direction Input atom_signal_name emac0_phy_txclk_i role clk}} emac0_gtx_clk {emac0_phy_txclk_o {direction Output atom_signal_name emac0_phy_txclk_o_hio role clk} @orderednames emac0_phy_txclk_o} spim0 {spim0_ss3_n_o {direction Output atom_signal_name spim0_ss3_n_o role ss3_n_o} spim0_miso_i {direction Input atom_signal_name spim0_miso_i role miso_i} @orderednames {spim0_mosi_o spim0_miso_i spim0_ss_in_n spim0_mosi_oe spim0_ss0_n_o spim0_ss1_n_o spim0_ss2_n_o spim0_ss3_n_o} spim0_ss_in_n {direction Input atom_signal_name spim0_ss_in_n role ss_in_n} spim0_ss0_n_o {direction Output atom_signal_name spim0_ss0_n_o role ss0_n_o} spim0_ss1_n_o {direction Output atom_signal_name spim0_ss1_n_o role ss1_n_o} spim0_mosi_o {direction Output atom_signal_name spim0_mosi_o role mosi_o} spim0_mosi_oe {direction Output atom_signal_name spim0_mosi_oe role mosi_oe} spim0_ss2_n_o {direction Output atom_signal_name spim0_ss2_n_o role ss2_n_o}} emac1_gtx_clk {@orderednames emac1_phy_txclk_o emac1_phy_txclk_o {direction Output atom_signal_name emac1_phy_txclk_o_hio role clk}} spim1 {spim1_mosi_oe {direction Output atom_signal_name spim1_mosi_oe role mosi_oe} spim1_ss2_n_o {direction Output atom_signal_name spim1_ss2_n_o role ss2_n_o} spim1_ss3_n_o {direction Output atom_signal_name spim1_ss3_n_o role ss3_n_o} spim1_miso_i {direction Input atom_signal_name spim1_miso_i role miso_i} @orderednames {spim1_mosi_o spim1_miso_i spim1_ss_in_n spim1_mosi_oe spim1_ss0_n_o spim1_ss1_n_o spim1_ss2_n_o spim1_ss3_n_o} spim1_ss_in_n {direction Input atom_signal_name spim1_ss_in_n role ss_in_n} spim1_ss0_n_o {direction Output atom_signal_name spim1_ss0_n_o role ss0_n_o} spim1_ss1_n_o {direction Output atom_signal_name spim1_ss1_n_o role ss1_n_o} spim1_mosi_o {direction Output atom_signal_name spim1_mosi_o role mosi_o}} emac2_gtx_clk {@orderednames emac2_phy_txclk_o emac2_phy_txclk_o {direction Output atom_signal_name emac2_phy_txclk_o_hio role clk}} i2cemac1_scl_in {i2c_emac1_scl_i {direction Input atom_signal_name i2c_emac1_scl_i role clk} @orderednames i2c_emac1_scl_i} spim0_sclk_out {spim0_sclk_out {direction Output atom_signal_name spim0_sclk_out_hio role clk} @orderednames spim0_sclk_out} i2cemac1_clk {i2c_emac1_scl_oe {direction Output atom_signal_name i2c_emac1_scl_oe role clk} @orderednames i2c_emac1_scl_oe} emac0 {emac0_ptp_aux_ts_trig_i {direction Input atom_signal_name emac0_ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac0_ptp_pps_o {direction Output atom_signal_name emac0_ptp_pps_o role ptp_pps_o} @orderednames {emac0_phy_txd_o emac0_phy_mac_speed_o emac0_phy_txen_o emac0_phy_txer_o emac0_phy_rxdv_i emac0_phy_rxer_i emac0_phy_rxd_i emac0_phy_col_i emac0_phy_crs_i emac0_gmii_mdo_o emac0_gmii_mdo_o_e emac0_gmii_mdi_i emac0_ptp_pps_o emac0_ptp_aux_ts_trig_i s2f_emac0_ptp_tstmp_data s2f_emac0_ptp_tstmp_en} emac0_phy_rxdv_i {direction Input atom_signal_name emac0_phy_rxdv_i role phy_rxdv_i} emac0_phy_rxd_i {direction Input atom_signal_name emac0_phy_rxd_i role phy_rxd_i} emac0_phy_mac_speed_o {direction Output atom_signal_name emac0_phy_mac_speed_o role phy_mac_speed_o} emac0_gmii_mdo_o_e {direction Output atom_signal_name emac0_gmii_mdo_o_e role gmii_mdo_o_e} emac0_phy_rxer_i {direction Input atom_signal_name emac0_phy_rxer_i role phy_rxer_i} emac0_gmii_mdo_o {direction Output atom_signal_name emac0_gmii_mdo_o role gmii_mdo_o} emac0_phy_txen_o {direction Output atom_signal_name emac0_phy_txen_o role phy_txen_o} emac0_phy_txd_o {direction Output atom_signal_name emac0_phy_txd_o role phy_txd_o} s2f_emac0_ptp_tstmp_data {direction Output atom_signal_name s2f_emac0_ptp_tstmp_data role ptp_tstmp_data} emac0_phy_col_i {direction Input atom_signal_name emac0_phy_col_i role phy_col_i} s2f_emac0_ptp_tstmp_en {direction Output atom_signal_name s2f_emac0_ptp_tstmp_en role ptp_tstmp_en} emac0_gmii_mdi_i {direction Input atom_signal_name emac0_gmii_mdi_i role gmii_mdi_i} emac0_phy_crs_i {direction Input atom_signal_name emac0_phy_crs_i role phy_crs_i} emac0_phy_txer_o {direction Output atom_signal_name emac0_phy_txer_o role phy_txer_o}} emac1 {emac1_gmii_mdo_o {direction Output atom_signal_name emac1_gmii_mdo_o role gmii_mdo_o} @orderednames {emac1_phy_mac_speed_o emac1_phy_txd_o emac1_phy_txen_o emac1_phy_txer_o emac1_phy_rxdv_i emac1_phy_rxer_i emac1_phy_rxd_i emac1_phy_col_i emac1_phy_crs_i emac1_gmii_mdo_o emac1_gmii_mdo_o_e emac1_gmii_mdi_i emac1_ptp_pps_o emac1_ptp_aux_ts_trig_i s2f_emac1_ptp_tstmp_data s2f_emac1_ptp_tstmp_en} emac1_ptp_aux_ts_trig_i {direction Input atom_signal_name emac1_ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac1_ptp_pps_o {direction Output atom_signal_name emac1_ptp_pps_o role ptp_pps_o} emac1_phy_txen_o {direction Output atom_signal_name emac1_phy_txen_o role phy_txen_o} s2f_emac1_ptp_tstmp_data {direction Output atom_signal_name s2f_emac1_ptp_tstmp_data role ptp_tstmp_data} emac1_phy_rxd_i {direction Input atom_signal_name emac1_phy_rxd_i role phy_rxd_i} s2f_emac1_ptp_tstmp_en {direction Output atom_signal_name s2f_emac1_ptp_tstmp_en role ptp_tstmp_en} emac1_gmii_mdi_i {direction Input atom_signal_name emac1_gmii_mdi_i role gmii_mdi_i} emac1_phy_mac_speed_o {direction Output atom_signal_name emac1_phy_mac_speed_o role phy_mac_speed_o} emac1_phy_txer_o {direction Output atom_signal_name emac1_phy_txer_o role phy_txer_o} emac1_phy_rxdv_i {direction Input atom_signal_name emac1_phy_rxdv_i role phy_rxdv_i} emac1_phy_txd_o {direction Output atom_signal_name emac1_phy_txd_o role phy_txd_o} emac1_phy_col_i {direction Input atom_signal_name emac1_phy_col_i role phy_col_i} emac1_gmii_mdo_o_e {direction Output atom_signal_name emac1_gmii_mdo_o_e role gmii_mdo_o_e} emac1_phy_crs_i {direction Input atom_signal_name emac1_phy_crs_i role phy_crs_i} emac1_phy_rxer_i {direction Input atom_signal_name emac1_phy_rxer_i role phy_rxer_i}} emac2 {emac2_phy_txer_o {direction Output atom_signal_name emac2_phy_txer_o role phy_txer_o} @orderednames {emac2_phy_mac_speed_o emac2_phy_txd_o emac2_phy_txen_o emac2_phy_txer_o emac2_phy_rxdv_i emac2_phy_rxer_i emac2_phy_rxd_i emac2_phy_col_i emac2_phy_crs_i emac2_gmii_mdo_o emac2_gmii_mdo_o_e emac2_gmii_mdi_i emac2_ptp_pps_o emac2_ptp_aux_ts_trig_i s2f_emac2_ptp_tstmp_data s2f_emac2_ptp_tstmp_en} emac2_ptp_aux_ts_trig_i {direction Input atom_signal_name emac2_ptp_aux_ts_trig_i role ptp_aux_ts_trig_i} emac2_ptp_pps_o {direction Output atom_signal_name emac2_ptp_pps_o role ptp_pps_o} emac2_phy_rxdv_i {direction Input atom_signal_name emac2_phy_rxdv_i role phy_rxdv_i} emac2_phy_rxd_i {direction Input atom_signal_name emac2_phy_rxd_i role phy_rxd_i} emac2_phy_mac_speed_o {direction Output atom_signal_name emac2_phy_mac_speed_o role phy_mac_speed_o} emac2_gmii_mdo_o_e {direction Output atom_signal_name emac2_gmii_mdo_o_e role gmii_mdo_o_e} emac2_phy_rxer_i {direction Input atom_signal_name emac2_phy_rxer_i role phy_rxer_i} emac2_gmii_mdo_o {direction Output atom_signal_name emac2_gmii_mdo_o role gmii_mdo_o} emac2_phy_txen_o {direction Output atom_signal_name emac2_phy_txen_o role phy_txen_o} emac2_phy_col_i {direction Input atom_signal_name emac2_phy_col_i role phy_col_i} emac2_phy_txd_o {direction Output atom_signal_name emac2_phy_txd_o role phy_txd_o} s2f_emac2_ptp_tstmp_data {direction Output atom_signal_name s2f_emac2_ptp_tstmp_data role ptp_tstmp_data} s2f_emac2_ptp_tstmp_en {direction Output atom_signal_name s2f_emac2_ptp_tstmp_en role ptp_tstmp_en} emac2_gmii_mdi_i {direction Input atom_signal_name emac2_gmii_mdi_i role gmii_mdi_i} emac2_phy_crs_i {direction Input atom_signal_name emac2_phy_crs_i role phy_crs_i}} spis0_sclk_in {spis0_sclk_in {direction Input atom_signal_name spis0_clk role clk} @orderednames spis0_sclk_in} spis1_sclk_in {@orderednames spis1_sclk_in spis1_sclk_in {direction Input atom_signal_name spis1_clk role clk}} trace_s2f_clk {@orderednames trace_s2f_clk trace_s2f_clk {direction Output atom_signal_name tpiu_trace_clk_hio role clk}} emac0_tx_reset {emac0_rst_clk_tx_n_o {direction Output atom_signal_name emac0_rst_clk_tx_n_o role reset_n} @orderednames emac0_rst_clk_tx_n_o} i2cemac0_scl_in {i2c_emac0_scl_i {direction Input atom_signal_name i2c_emac0_scl_i role clk} @orderednames i2c_emac0_scl_i} sdmmc {@orderednames {sdmmc_vs_o sdmmc_pwr_ena_o sdmmc_wp_i sdmmc_cdn_i sdmmc_card_intn_i sdmmc_cmd_i sdmmc_cmd_o sdmmc_cmd_oe sdmmc_data_i sdmmc_data_o sdmmc_data_oe} sdmmc_cmd_oe {direction Output atom_signal_name sdmmc_cmd_oe role cmd_oe} sdmmc_pwr_ena_o {direction Output atom_signal_name sdmmc_pwr_ena_o role pwr_ena_o} sdmmc_card_intn_i {direction Input atom_signal_name sdmmc_card_intn_i role card_intn_i} sdmmc_cmd_o {direction Output atom_signal_name sdmmc_cmd_o role cmd_o} sdmmc_data_i {direction Input atom_signal_name sdmmc_data_i role data_i} sdmmc_cdn_i {direction Input atom_signal_name sdmmc_cdn_i role cdn_i} sdmmc_data_oe {direction Output atom_signal_name sdmmc_data_oe role data_oe} sdmmc_vs_o {direction Output atom_signal_name sdmmc_vs_o role vs_o} sdmmc_wp_i {direction Input atom_signal_name sdmmc_wp_i role wp_i} sdmmc_data_o {direction Output atom_signal_name sdmmc_data_o role data_o} sdmmc_cmd_i {direction Input atom_signal_name sdmmc_cmd_i role cmd_i}} spim1_sclk_out {spim1_sclk_out {direction Output atom_signal_name spim1_sclk_out_hio role clk} @orderednames spim1_sclk_out} emac1_rx_clk_in {emac1_clk_rx_i {direction Input atom_signal_name emac1_phy_rxclk_i role clk} @orderednames emac1_clk_rx_i} i2c0_clk {@orderednames i2c0_scl_oe i2c0_scl_oe {direction Output atom_signal_name i2c0_scl_oe role clk}} emac1_tx_clk_in {@orderednames emac1_clk_tx_i emac1_clk_tx_i {direction Input atom_signal_name emac1_phy_txclk_i role clk}} i2cemac0 {i2c_emac0_sda_oe {direction Output atom_signal_name i2c_emac0_sda_oe role sda_oe} @orderednames {i2c_emac0_sda_i i2c_emac0_sda_oe} i2c_emac0_sda_i {direction Input atom_signal_name i2c_emac0_sda_i role sda_i}} emac1_tx_reset {@orderednames emac1_rst_clk_tx_n_o emac1_rst_clk_tx_n_o {direction Output atom_signal_name emac1_rst_clk_tx_n_o role reset_n}} i2cemac1 {@orderednames {i2c_emac1_sda_i i2c_emac1_sda_oe} i2c_emac1_sda_oe {direction Output atom_signal_name i2c_emac1_sda_oe role sda_oe} i2c_emac1_sda_i {direction Input atom_signal_name i2c_emac1_sda_i role sda_i}} i2cemac2 {i2c_emac2_sda_i {direction Input atom_signal_name i2c_emac2_sda_i role sda_i} @orderednames {i2c_emac2_sda_i i2c_emac2_sda_oe} i2c_emac2_sda_oe {direction Output atom_signal_name i2c_emac2_sda_oe role sda_oe}} emac0_rx_reset {@orderednames emac0_rst_clk_rx_n_o emac0_rst_clk_rx_n_o {direction Output atom_signal_name emac0_rst_clk_rx_n_o role reset_n}} emac2_tx_reset {@orderednames emac2_rst_clk_tx_n_o emac2_rst_clk_tx_n_o {direction Output atom_signal_name emac2_rst_clk_tx_n_o role reset_n}} i2c1_scl_in {i2c1_scl_i {direction Input atom_signal_name i2c1_scl_i role clk} @orderednames i2c1_scl_i} emac2_rx_clk_in {@orderednames emac2_clk_rx_i emac2_clk_rx_i {direction Input atom_signal_name emac2_phy_rxclk_i role clk}} sdmmc_cclk {@orderednames sdmmc_cclk_out sdmmc_cclk_out {direction Output atom_signal_name sdmmc_cclk_o role clk}} emac2_md_clk {@orderednames emac2_gmii_mdc_o emac2_gmii_mdc_o {direction Output atom_signal_name emac2_gmii_mdc_o role clk}} emac1_rx_reset {emac1_rst_clk_rx_n_o {direction Output atom_signal_name emac1_rst_clk_rx_n_o role reset_n} @orderednames emac1_rst_clk_rx_n_o} emac2_tx_clk_in {emac2_clk_tx_i {direction Input atom_signal_name emac2_phy_txclk_i role clk} @orderednames emac2_clk_tx_i} uart0 {uart0_out1_n {direction Output atom_signal_name uart0_out1_n role out1_n} uart0_dsr_n {direction Input atom_signal_name uart0_dsr_n role dsr_n} @orderednames {uart0_cts_n uart0_dsr_n uart0_dcd_n uart0_ri_n uart0_rx uart0_dtr_n uart0_rts_n uart0_out1_n uart0_out2_n uart0_tx} uart0_rx {direction Input atom_signal_name uart0_rx role rx} uart0_rts_n {direction Output atom_signal_name uart0_rts_n role rts_n} uart0_dtr_n {direction Output atom_signal_name uart0_dtr_n role dtr_n} uart0_cts_n {direction Input atom_signal_name uart0_cts_n role cts_n} uart0_out2_n {direction Output atom_signal_name uart0_out2_n role out2_n} uart0_tx {direction Output atom_signal_name uart0_tx role tx} uart0_ri_n {direction Input atom_signal_name uart0_ri_n role ri_n} uart0_dcd_n {direction Input atom_signal_name uart0_dcd_n role dcd_n}} i2cemac0_clk {@orderednames i2c_emac0_scl_oe i2c_emac0_scl_oe {direction Output atom_signal_name i2c_emac0_scl_oe role clk}} uart1 {uart1_tx {direction Output atom_signal_name uart1_tx role tx} uart1_ri_n {direction Input atom_signal_name uart1_ri_n role ri_n} uart1_dcd_n {direction Input atom_signal_name uart1_dcd_n role dcd_n} @orderednames {uart1_cts_n uart1_dsr_n uart1_dcd_n uart1_ri_n uart1_rx uart1_dtr_n uart1_rts_n uart1_out1_n uart1_out2_n uart1_tx} uart1_out1_n {direction Output atom_signal_name uart1_out1_n role out1_n} uart1_dsr_n {direction Input atom_signal_name uart1_dsr_n role dsr_n} uart1_rx {direction Input atom_signal_name uart1_rx role rx} uart1_rts_n {direction Output atom_signal_name uart1_rts_n role rts_n} uart1_dtr_n {direction Output atom_signal_name uart1_dtr_n role dtr_n} uart1_cts_n {direction Input atom_signal_name uart1_cts_n role cts_n} uart1_out2_n {direction Output atom_signal_name uart1_out2_n role out2_n}} i2c0_scl_in {@orderednames i2c0_scl_i i2c0_scl_i {direction Input atom_signal_name i2c0_scl_i role clk}} i2cemac2_clk {i2c_emac2_scl_oe {direction Output atom_signal_name i2c_emac2_scl_oe role clk} @orderednames i2c_emac2_scl_oe} trace {trace_data {direction Output atom_signal_name tpiu_trace_data role data} @orderednames trace_data} emac1_md_clk {emac1_gmii_mdc_o {direction Output atom_signal_name emac1_gmii_mdc_o role clk} @orderednames emac1_gmii_mdc_o} emac2_rx_reset {emac2_rst_clk_rx_n_o {direction Output atom_signal_name emac2_rst_clk_rx_n_o role reset_n} @orderednames emac2_rst_clk_rx_n_o} emac0_md_clk {emac0_gmii_mdc_o {direction Output atom_signal_name emac0_gmii_mdc_o role clk} @orderednames emac0_gmii_mdc_o} i2c1_clk {@orderednames i2c1_scl_oe i2c1_scl_oe {direction Output atom_signal_name i2c1_scl_oe role clk}} nand {nand_ale_o {direction Output atom_signal_name nand_ale_o role ale_o} nand_adq_o {direction Output atom_signal_name nand_adq_o role adq_o} nand_wp_o {direction Output atom_signal_name nand_wp_n_o role wp_n_o} nand_rdy_busy_i {direction Input atom_signal_name nand_rdy_busy_i role rdy_busy_i} nand_adq_oe {direction Output atom_signal_name nand_adq_oe role adq_oe} @orderednames {nand_adq_i nand_adq_oe nand_adq_o nand_ale_o nand_ce_o nand_cle_o nand_re_o nand_rdy_busy_i nand_we_o nand_wp_o} nand_re_o {direction Output atom_signal_name nand_re_n_o role re_n_o} nand_cle_o {direction Output atom_signal_name nand_cle_o role cle_o} nand_adq_i {direction Input atom_signal_name nand_adq_i role adq_i} nand_ce_o {direction Output atom_signal_name nand_ce_n_o role ce_n_o} nand_we_o {direction Output atom_signal_name nand_we_n_o role we_n_o}} usb0 {usb0_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} usb0_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb0_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} @orderednames {usb0_ulpi_dir usb0_ulpi_nxt usb0_ulpi_data_i usb0_ulpi_stp usb0_ulpi_data_o usb0_ulpi_data_oe} usb0_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb0_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o} usb0_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe}} usb1_clk_in {usb1_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb1_ulpi_clk} usb1 {usb1_ulpi_data_oe {direction Output atom_signal_name ulpi_data_oe role ulpi_data_oe} usb1_ulpi_nxt {direction Input atom_signal_name ulpi_nxt role ulpi_nxt} @orderednames {usb1_ulpi_dir usb1_ulpi_nxt usb1_ulpi_data_i usb1_ulpi_stp usb1_ulpi_data_o usb1_ulpi_data_oe} usb1_ulpi_data_i {direction Input atom_signal_name ulpi_data_i role ulpi_data_i} usb1_ulpi_stp {direction Output atom_signal_name ulpi_stp role ulpi_stp} usb1_ulpi_dir {direction Input atom_signal_name ulpi_dir role ulpi_dir} usb1_ulpi_data_o {direction Output atom_signal_name ulpi_data_o role ulpi_data_o}} sdmmc_reset {sdmmc_rstn_o {direction Output atom_signal_name sdmmc_rstn_o role reset} @orderednames sdmmc_rstn_o} spis0 {spis0_miso_o {direction Output atom_signal_name spis0_miso_o role miso_o} spis0_miso_oe {direction Output atom_signal_name spis0_miso_oe role miso_oe} @orderednames {spis0_mosi_i spis0_ss_in_n spis0_miso_o spis0_miso_oe} spis0_mosi_i {direction Input atom_signal_name spis0_mosi_i role mosi_i} spis0_ss_in_n {direction Input atom_signal_name spis0_ss_in_n role ss_in_n}} spis1 {spis1_ss_in_n {direction Input atom_signal_name spis1_ss_in_n role ss_in_n} @orderednames {spis1_mosi_i spis1_ss_in_n spis1_miso_o spis1_miso_oe} spis1_miso_o {direction Output atom_signal_name spis1_miso_o role miso_o} spis1_miso_oe {direction Output atom_signal_name spis1_miso_oe role miso_oe} spis1_mosi_i {direction Input atom_signal_name spis1_mosi_i role mosi_i}} usb0_clk_in {usb0_ulpi_clk {direction Input atom_signal_name ulpi_clk role clk} @orderednames usb0_ulpi_clk} i2cemac2_scl_in {@orderednames i2c_emac2_scl_i i2c_emac2_scl_i {direction Input atom_signal_name i2c_emac2_scl_i role clk}} emac0_rx_clk_in {emac0_clk_rx_i {direction Input atom_signal_name emac0_phy_rxclk_i role clk} @orderednames emac0_clk_rx_i} i2c0 {i2c0_sda_oe {direction Output atom_signal_name i2c0_sda_oe role sda_oe} @orderednames {i2c0_sda_i i2c0_sda_oe} i2c0_sda_i {direction Input atom_signal_name i2c0_sda_i role sda_i}} i2c1 {i2c1_sda_oe {direction Output atom_signal_name i2c1_sda_oe role sda_oe} @orderednames {i2c1_sda_i i2c1_sda_oe} i2c1_sda_i {direction Input atom_signal_name i2c1_sda_i role sda_i}}} HPS_IO7_is_present false EMAC2_Mode N/A HPS_IOB_1_open_drain_en false io3_delay_is_present false SMMU_wsb_ssd_const 0 io13_delay_is_present false HPS_IO27_is_present true DB_periph_ifaces {@orderednames {EMAC0 EMAC1 EMAC2 NAND SDMMC USB0 USB1 SPIM0 SPIM1 SPIS0 SPIS1 TRACE UART0 UART1 I2C0 I2C1 I2CEMAC0 I2CEMAC1 I2CEMAC2} NAND {interfaces {nand {properties {} direction Input @no_export 0 type conduit} @orderednames nand} atom_name hps_hps} SPIM0 {interfaces {spim0_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim0 spim0_sclk_out} spim0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_hps} USB0 {interfaces {usb0_clk_in {properties {} direction Input @no_export 0 type clock} @orderednames {usb0 usb0_clk_in} usb0 {properties {} direction Input @no_export 0 type conduit}}} SPIM1 {interfaces {spim1_sclk_out {properties {} direction Output @no_export 0 type clock} @orderednames {spim1 spim1_sclk_out} spim1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_hps} USB1 {interfaces {@orderednames {usb1 usb1_clk_in} usb1_clk_in {properties {} direction Input @no_export 0 type clock} usb1 {properties {} direction Input @no_export 0 type conduit}}} I2CEMAC0 {interfaces {i2cemac0 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac0_scl_in i2cemac0_clk i2cemac0} i2cemac0_clk {properties {} direction Output @no_export 0 type clock} i2cemac0_scl_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_hps} UART0 {interfaces {uart0 {properties {} direction Input @no_export 0 type conduit} @orderednames uart0} atom_name hps_hps} I2CEMAC1 {interfaces {i2cemac1_scl_in {properties {} direction Input @no_export 0 type clock} i2cemac1 {properties {} direction Input @no_export 0 type conduit} @orderednames {i2cemac1_scl_in i2cemac1_clk i2cemac1} i2cemac1_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_hps} UART1 {interfaces {uart1 {properties {} direction Input @no_export 0 type conduit} @orderednames uart1} atom_name hps_hps} I2CEMAC2 {interfaces {i2cemac2_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2cemac2_scl_in i2cemac2_clk i2cemac2} i2cemac2 {properties {} direction Input @no_export 0 type conduit} i2cemac2_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_hps} EMAC0 {interfaces {emac0_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac0_rx_reset {properties {associatedClock emac0_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac0_gtx_clk {properties {} direction Output @no_export 0 type clock} @orderednames {emac0 emac0_md_clk emac0_rx_clk_in emac0_tx_clk_in emac0_gtx_clk emac0_tx_reset emac0_rx_reset} emac0_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac0 {properties {} direction Input @no_export 0 type conduit} emac0_md_clk {properties {} direction Output @no_export 0 type clock} emac0_tx_reset {properties {associatedClock emac0_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset}} atom_name hps_hps} TRACE {interfaces {@orderednames {trace_s2f_clk trace} trace_s2f_clk {properties {} direction Output @no_export 0 type clock} trace {properties {} direction Input @no_export 0 type conduit}} atom_name hps_hps} EMAC1 {interfaces {emac1_md_clk {properties {} direction Output @no_export 0 type clock} emac1_tx_reset {properties {associatedClock emac1_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} @orderednames {emac1 emac1_md_clk emac1_rx_clk_in emac1_tx_clk_in emac1_gtx_clk emac1_tx_reset emac1_rx_reset} emac1_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac1_rx_reset {properties {associatedClock emac1_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac1_gtx_clk {properties {} direction Output @no_export 0 type clock} emac1_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_hps} SPIS0 {interfaces {spis0_sclk_in {properties {} direction Input @no_export 0 type clock} @orderednames {spis0 spis0_sclk_in} spis0 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_hps} EMAC2 {interfaces {emac2_rx_clk_in {properties {} direction Input @no_export 0 type clock} emac2 {properties {} direction Input @no_export 0 type conduit} @orderednames {emac2 emac2_md_clk emac2_rx_clk_in emac2_tx_clk_in emac2_gtx_clk emac2_tx_reset emac2_rx_reset} emac2_md_clk {properties {} direction Output @no_export 0 type clock} emac2_tx_reset {properties {associatedClock emac2_tx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_tx_clk_in {properties {} direction Input @no_export 0 type clock} emac2_rx_reset {properties {associatedClock emac2_rx_clk_in associatedResetSinks none} direction Output @no_export 0 type reset} emac2_gtx_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_hps} SPIS1 {interfaces {spis1 {properties {} direction Input @no_export 0 type conduit} @orderednames {spis1 spis1_sclk_in} spis1_sclk_in {properties {} direction Input @no_export 0 type clock}} atom_name hps_hps} SDMMC {interfaces {sdmmc_cclk {properties {} direction Output @no_export 0 type clock} sdmmc {properties {} direction Input @no_export 0 type conduit} @orderednames {sdmmc sdmmc_reset sdmmc_cclk} sdmmc_reset {properties {synchronousEdges none} direction Output @no_export 0 type reset}} atom_name hps_hps} I2C0 {interfaces {i2c0_scl_in {properties {} direction Input @no_export 0 type clock} @orderednames {i2c0_scl_in i2c0_clk i2c0} i2c0 {properties {} direction Input @no_export 0 type conduit} i2c0_clk {properties {} direction Output @no_export 0 type clock}} atom_name hps_hps} I2C1 {interfaces {i2c1_clk {properties {} direction Output @no_export 0 type clock} @orderednames {i2c1_scl_in i2c1_clk i2c1} i2c1_scl_in {properties {} direction Input @no_export 0 type clock} i2c1 {properties {} direction Input @no_export 0 type conduit}} atom_name hps_hps}} NOCDIV_L4SPCLK 2 SDMMC_Mode 4-bit HPS_IOA_24_open_drain_en false HPS_IOB_15_open_drain_en false UART0_PinMuxing IO F2S_Width 5 dev_database {} HPS_IOA_9_open_drain_en false HPS_IO16_is_present true io30_delay_is_present false io29_delay_is_present false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 125 perpll_max_c0 1200 DDR_ATB_Enable false F2H_SDRAM0_CLOCK_FREQ 100 NOCDIV_CS_ATCLK 0 perpll_max_c1 400 EMAC2_SWITCH_Enable false F2S_mode 0 CLK_MPU_CNT 0 perpll_max_c2 1000 S2FINTERRUPT_USB1_Enable false perpll_max_c3 1000 SDMMC_PinMuxing IO CLK_S2F_USER0_SOURCE 0 DB_port_pins {spim0_miso_i {0 rxd} usb0_ulpi_stp {0 ulpi_stp} emac0_ptp_aux_ts_trig_i {0 ts_trig} uart1_dsr_n {0 dsr_n} spim0_ss1_n_o {0 ss_cs1} emac1_ptp_pps_o {0 ptp_pps} emac1_phy_txclk_o {0 tx_clk_o} spim1_ss1_n_o {0 ss_cs1} emac0_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_clk_tx_i {0 tx_clk_i} uart1_dcd_n {0 dcd_n} spim0_ss3_n_o {0 ss_cs3} spim0_sclk_out {0 sclk_out} spis1_miso_o {0 txd} spim1_ss3_n_o {0 ss_cs3} emac1_gmii_mdi_i {0 mdi} emac0_phy_rxer_i {0 rxer} emac1_rst_clk_tx_n_o {0 rst_clk_tx_n_o} emac0_clk_rx_i {0 rx_clk} uart0_rts_n {0 rts_n} spis0_sclk_in {0 sclk_in} trace_s2f_clk {0 s2f_clk} i2c_emac0_sda_i {0 ic_data_in_a} spis1_sclk_in {0 sclk_in} usb1_ulpi_stp {0 ulpi_stp} emac2_gmii_mdo_o {0 mdo} emac1_phy_rxdv_i {0 rxdv} i2c1_scl_oe {0 ic_clk_oe} uart1_cts_n {0 cts_n} emac0_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} uart1_ri_n {0 ri_n} spis0_miso_o {0 txd} emac2_clk_tx_i {0 tx_clk_i} emac0_gmii_mdc_o {0 mdc} emac1_phy_col_i {0 col} emac2_phy_txen_o {0 txen} uart0_rx {0 sin} spim1_sclk_out {0 sclk_out} emac0_rst_clk_tx_n_o {0 rst_clk_tx_n_o} i2c_emac2_scl_i {0 ic_clk_in_a} i2c1_sda_i {0 ic_data_in_a} s2f_emac2_ptp_tstmp_en {0 ptp_tstmp_en} emac1_phy_crs_i {0 crs} usb0_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} sdmmc_cmd_i {0 ccmd_i} emac2_phy_txer_o {0 txer} uart0_dsr_n {0 dsr_n} spis0_miso_oe {0 ssi_oe_n} emac1_clk_rx_i {0 rx_clk} i2c0_scl_oe {0 ic_clk_oe} spis1_miso_oe {0 ssi_oe_n} emac1_ptp_aux_ts_trig_i {0 ts_trig} uart0_dcd_n {0 dcd_n} emac2_ptp_pps_o {0 ptp_pps} usb0_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} usb0_ulpi_nxt {0 ulpi_nxt} emac0_gmii_mdo_o_e {0 mdo_en} emac0_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac1_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} sdmmc_cmd_o {0 ccmd_o} sdmmc_card_intn_i {0 card_int_n} sdmmc_pwr_ena_o {0 pwer_en_o} emac1_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} emac2_phy_mac_speed_o {0 mac_speed0 1 mac_speed1} sdmmc_cclk_out {0 cclk_out} sdmmc_rstn_o {0 rst_out_n} sdmmc_cdn_i {0 cd_i_n} emac0_gmii_mdo_o {0 mdo} i2c_emac2_scl_oe {0 ic_clk_oe} i2c1_sda_oe {0 ic_data_oe} uart0_cts_n {0 cts_n} usb0_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} sdmmc_vs_o {0 vs_o} emac2_clk_rx_i {0 rx_clk} emac0_phy_txen_o {0 txen} uart1_dtr_n {0 dtr_n} emac1_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_scl_i {0 ic_clk_in_a} i2c0_sda_i {0 ic_data_in_a} usb1_ulpi_nxt {0 ulpi_nxt} emac2_phy_col_i {0 col} nand_adq_i {0 adq_in0 1 adq_in1 2 adq_in2 3 adq_in3 4 adq_in4 5 adq_in5 6 adq_in6 7 adq_in7 8 adq_in8 10 adq_in10 9 adq_in9 11 adq_in11 12 adq_in12 13 adq_in13 14 adq_in14 15 adq_in15} emac2_gmii_mdi_i {0 mdi} emac0_phy_txer_o {0 txer} uart0_tx {0 sout} spis1_mosi_i {0 rxd} spis0_ss_in_n {0 ss_in_n} spim1_mosi_o {0 txd} emac2_phy_crs_i {0 crs} emac1_phy_rxer_i {0 rxer} i2c_emac1_scl_oe {0 ic_clk_oe} i2c0_sda_oe {0 ic_data_oe} spis1_ss_in_n {0 ss_in_n} nand_ale_o {0 ale_out} spim0_ss0_n_o {0 ss_cs0} usb0_ulpi_dir {0 ulpi_dir} emac0_phy_txclk_o {0 tx_clk_o} uart1_out1_n {0 out1_n} spim1_ss0_n_o {0 ss_cs0} sdmmc_cmd_oe {0 ccmd_en} nand_cle_o {0 cle_out} uart0_ri_n {0 ri_n} spim0_ss2_n_o {0 ss_cs2} emac2_phy_txclk_o {0 tx_clk_o} emac2_ptp_aux_ts_trig_i {0 ts_trig} emac2_phy_rxdv_i {0 rxdv} spim1_ss2_n_o {0 ss_cs2} usb0_ulpi_clk {0 ulpi_clk} nand_adq_o {0 adq_out0 1 adq_out1 2 adq_out2 3 adq_out3 4 adq_out4 5 adq_out5 6 adq_out6 7 adq_out7 8 adq_out8 10 adq_out10 9 adq_out9 11 adq_out11 12 adq_out12 13 adq_out13 14 adq_out14 15 adq_out15} sdmmc_data_i {0 cdata_in0 4 cdata_in4 5 cdata_in5 1 cdata_in1 2 cdata_in2 6 cdata_in6 7 cdata_in7 3 cdata_in3} emac2_phy_rxd_i {0 rxd0 4 rxd4 5 rxd5 1 rxd1 2 rxd2 6 rxd6 7 rxd7 3 rxd3} emac1_gmii_mdc_o {0 mdc} s2f_emac1_ptp_tstmp_en {0 ptp_tstmp_en} uart1_rx {0 sin} spis0_mosi_i {0 rxd} spim0_mosi_o {0 txd} emac2_gmii_mdo_o_e {0 mdo_en} i2c_emac2_sda_oe {0 ic_data_oe} i2c_emac0_scl_oe {0 ic_clk_oe} trace_data {35 d35 36 d36 37 d37 38 d38 40 d40 39 d39 41 d41 42 d42 43 d43 44 d44 45 d45 46 d46 47 d47 48 d48 50 d50 49 d49 51 d51 52 d52 53 d53 54 d54 55 d55 56 d56 57 d57 58 d58 60 d60 59 d59 61 d61 62 d62 63 d63 10 d10 11 d11 12 d12 13 d13 14 d14 15 d15 16 d16 0 d0 17 d17 1 d1 18 d18 2 d2 19 d19 20 d20 3 d3 21 d21 22 d22 4 d4 5 d5 23 d23 24 d24 6 d6 7 d7 25 d25 26 d26 8 d8 9 d9 27 d27 28 d28 29 d29 30 d30 31 d31 32 d32 33 d33 34 d34} sdmmc_data_oe {0 cdata_out_en0 4 cdata_out_en4 5 cdata_out_en5 1 cdata_out_en1 2 cdata_out_en2 6 cdata_out_en6 7 cdata_out_en7 3 cdata_out_en3} uart0_out1_n {0 out1_n} spim0_ss_in_n {0 ss_in_n} nand_rdy_busy_i {0 rdy_bsy_in0 1 rdy_bsy_in1 2 rdy_bsy_in2 3 rdy_bsy_in3} nand_adq_oe {0 adq_oe0} uart0_dtr_n {0 dtr_n} spim1_ss_in_n {0 ss_in_n} usb1_ulpi_dir {0 ulpi_dir} sdmmc_data_o {0 cdata_out0 4 cdata_out4 5 cdata_out5 1 cdata_out1 2 cdata_out2 6 cdata_out6 7 cdata_out7 3 cdata_out3} i2c_emac2_sda_i {0 ic_data_in_a} i2c_emac0_scl_i {0 ic_clk_in_a} emac0_gmii_mdi_i {0 mdi} usb1_ulpi_clk {0 ulpi_clk} nand_wp_o {0 wp_outn} emac2_rst_clk_rx_n_o {0 rst_clk_rx_n_o} s2f_emac2_ptp_tstmp_data {0 ptp_tstmp_data} emac2_phy_txd_o {0 txd0 4 txd4 5 txd5 1 txd1 2 txd2 6 txd6 7 txd7 3 txd3} i2c_emac1_sda_oe {0 ic_data_oe} i2c1_scl_i {0 ic_clk_in_a} emac0_phy_rxdv_i {0 rxdv} emac0_ptp_pps_o {0 ptp_pps} emac1_gmii_mdo_o {0 mdo} nand_we_o {0 we_outn} uart1_out2_n {0 out2_n} emac1_phy_txen_o {0 txen} s2f_emac1_ptp_tstmp_data {0 ptp_tstmp_data} emac1_rst_clk_rx_n_o {0 rst_clk_rx_n_o} i2c_emac0_sda_oe {0 ic_data_oe} usb1_ulpi_data_i {0 ulpi_datain0 4 ulpi_datain4 5 ulpi_datain5 1 ulpi_datain1 2 ulpi_datain2 6 ulpi_datain6 7 ulpi_datain7 3 ulpi_datain3} nand_re_o {0 re_outn} emac1_phy_txer_o {0 txer} uart1_tx {0 sout} usb1_ulpi_data_oe {0 ulpi_data_out_en0 4 ulpi_data_out_en4 5 ulpi_data_out_en5 1 ulpi_data_out_en1 2 ulpi_data_out_en2 6 ulpi_data_out_en6 7 ulpi_data_out_en7 3 ulpi_data_out_en3} emac2_phy_rxer_i {0 rxer} spim1_miso_i {0 rxd} uart1_rts_n {0 rts_n} uart0_out2_n {0 out2_n} sdmmc_wp_i {0 wp_i} emac0_clk_tx_i {0 tx_clk_i} i2c_emac1_sda_i {0 ic_data_in_a} spim0_mosi_oe {0 ssi_oe_n} usb1_ulpi_data_o {0 ulpi_dataout0 4 ulpi_dataout4 5 ulpi_dataout5 1 ulpi_dataout1 2 ulpi_dataout2 6 ulpi_dataout6 7 ulpi_dataout7 3 ulpi_dataout3} emac0_phy_col_i {0 col} s2f_emac0_ptp_tstmp_data {0 ptp_tstmp_data} emac0_rst_clk_rx_n_o {0 rst_clk_rx_n_o} spim1_mosi_oe {0 ssi_oe_n} s2f_emac0_ptp_tstmp_en {0 ptp_tstmp_en} emac0_phy_crs_i {0 crs} emac1_gmii_mdo_o_e {0 mdo_en} nand_ce_o {0 ce_outn0 1 ce_outn1 2 ce_outn2 3 ce_outn3} emac2_gmii_mdc_o {0 mdc} i2c0_scl_i {0 ic_clk_in_a} emac2_rst_clk_tx_n_o {0 rst_clk_tx_n_o}} HPS_IOA_18_open_drain_en false io46_delay_is_present false HPS_IOB_10_open_drain_en false HPS_IOA_4_open_drain_en false io5_delay_is_present false io15_delay_is_present false MANUAL_CLK_EMAC_PTP_SOURCE 1 MAINPLLGRP_VCO_DENOM 1 USB0_PinMuxing Unused HPS_IO40_is_present true HPS_IO39_is_present true S2F_Width 3 TRACE_Mode N/A I2CEMAC2_PinMuxing Unused S2FINTERRUPT_I2C1_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC2_SCL_IN 100 HPS_IO8_is_present false S2FINTERRUPT_CLOCKPERIPHERAL_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN 100 HPS_IOA_13_open_drain_en false io32_delay_is_present false HPS_IO28_is_present true IO_OUTPUT_DELAY10 0 H2F_COLD_RST_Enable false DEFAULT_MPU_CLK 1200 IO_OUTPUT_DELAY11 0 IO_OUTPUT_DELAY12 45 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5 IO_OUTPUT_DELAY13 0 S2FINTERRUPT_I2CEMAC1_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125 IO_OUTPUT_DELAY14 0 PERI_PLL_AUTO_VCO_FREQ 2000 IO_OUTPUT_DELAY15 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN 100 HPS_IO17_is_present true IO_OUTPUT_DELAY16 0 IO_OUTPUT_DELAY17 0 IO_OUTPUT_DELAY18 0 F2H_SDRAM1_CLOCK_FREQ 100 EMAC0_CLK 250 IO_OUTPUT_DELAY20 0 IO_OUTPUT_DELAY19 0 io7_delay_is_present false PERPLLGRP_C2_CNT 5 DMA_PeriphId_DERIVED {0 1 2 3 4 5 6 7} SMMU_ssd_config 0 IO_OUTPUT_DELAY21 0 io17_delay_is_present false HPS_IOB_7_open_drain_en false IO_OUTPUT_DELAY22 0 MAINPLL_DREFCLKDIV 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC0_SCL_IN 100 IO_OUTPUT_DELAY23 0 IO_OUTPUT_DELAY24 0 IO_OUTPUT_DELAY25 0 IO_OUTPUT_DELAY26 0 HPS_IOB_22_open_drain_en false IO_OUTPUT_DELAY27 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5 MAINPLL_FDIV_EN false io34_delay_is_present false IO_OUTPUT_DELAY28 0 DMA_Enable {No No No No No No No No} FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN 100 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 125 IO_OUTPUT_DELAY30 0 IO_OUTPUT_DELAY29 0 FP_EMIF_CONDUIT_Enable true HPS_IO41_is_present true EMAC1_PTP false IO_OUTPUT_DELAY31 0 eosc1_clk_mhz 25.0 PSI_CLK_FREQ 500 IO_OUTPUT_DELAY32 0 IO_OUTPUT_DELAY33 0 mainpll_max_c0 1200 HPS_IOB_2_open_drain_en false IO_OUTPUT_DELAY34 0 mainpll_max_c1 400 HPS_IO9_is_present false IO_OUTPUT_DELAY35 0 mainpll_max_c2 1000 IO_OUTPUT_DELAY36 0 mainpll_max_c3 1000 HPS_IO30_is_present true HPS_IO29_is_present false IO_OUTPUT_DELAY37 0 TPIU_Select {HPS Clock Manager} IO_OUTPUT_DELAY38 0 HPS_IOB_16_open_drain_en false IO_OUTPUT_DELAY40 0 IO_OUTPUT_DELAY39 0 io9_delay_is_present false IO_OUTPUT_DELAY41 0 io20_delay_is_present false io19_delay_is_present false perpll_max_vco 3000 IO_OUTPUT_DELAY42 0 S2FINTERRUPT_GPIO_Enable false H2F_USER0_CLK_FREQ 500 IO_OUTPUT_DELAY43 0 EMIF_Topology 0 H2F_USER0_CLK_Enable false HPS_IO18_is_present true IO_OUTPUT_DELAY44 0 MAINPLLGRP_C2_CNT 6 IO_OUTPUT_DELAY45 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_RX_CLK_IN 100 UART0_Mode No_flow_control IO_OUTPUT_DELAY46 0 F2H_SDRAM2_CLOCK_FREQ 100 IO_OUTPUT_DELAY47 0 NOCDIV_L4MPCLK 1 io36_delay_is_present false H2F_PENDING_RST_Enable false I2C0_PinMuxing Unused HPS_IOA_20_open_drain_en false HPS_IOA_19_open_drain_en false HPS_IOB_11_open_drain_en false S2FINTERRUPT_SPIS1_Enable false S2FINTERRUPT_SPIM0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 125 MANUAL_PERPLL_CFREQ_EN false USB1_Mode N/A HPS_IOA_5_open_drain_en false S2FINTERRUPT_DMA_Enable false FP_F2S_Width 0 H2F_CTI_CLOCK_FREQ 100 SPIM1_PinMuxing Unused MANUAL_CLK_S2F_USER1_SOURCE 0 CLK_EMACB_SOURCE 1 CLK_SDMMC_CNT 0 SMMU_wsb_sid_const 0 HPS_IO42_is_present true SPIS0_Mode N/A MAINPLLGRP_VCO_NUMER 120 EMAC0_PinMuxing IO SPIS0_PinMuxing Unused io22_delay_is_present false mdio0_usefpga_is_present false CM_PinMuxing Unused SPIM1_Mode N/A HPS_IOA_14_open_drain_en false F2S_ADDRESS_WIDTH 32 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK 100 NOCDIV_CS_ATCLK_HZ 400 HPS_IO31_is_present false S2FINTERRUPT_UART0_Enable false CLK_PSI_CNT 0 TESTIOCTRL_PERICLKSEL 8 MANUAL_CLK_PSI_SOURCE 0 pin_muxing_check {} io38_delay_is_present false S2FINTERRUPT_SYSTIMER_Enable false S2FINTERRUPT_EMAC2_Enable false H2F_USER1_CLK_Enable false CLK_EMAC_PTP_CNT 1 HPS_IO20_is_present true HPS_IO19_is_present true RUN_INTERNAL_BUILD_CHECKS 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN 100 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN 100 I2CEMAC1_Mode N/A TESTIOCTRL_DEBUGCLKSEL 16 F2H_AXI_CLOCK_FREQ 100000000 F2H_SDRAM3_CLOCK_FREQ 100 CLK_NOC_SOURCE 1 NOCDIV_L4MAINCLK_HZ 400 EMAC1_Mode N/A HPS_IOB_8_open_drain_en false USE_DEFAULT_MPU_CLK false GP_Enable false eosc1_clk_hz 0 IO_INPUT_DELAY10 0 io24_delay_is_present false IO_INPUT_DELAY11 0 S2F_ADDRESS_WIDTH 32 HPS_IOB_23_open_drain_en false IO_INPUT_DELAY12 0 NOCDIV_L4SPCLK_HZ 100 MANUAL_CLK_MPU_SOURCE 0 IO_INPUT_DELAY13 0 IO_INPUT_DELAY14 0 IO_INPUT_DELAY15 0 PERPLL_MODCLKDIV 4 S2FINTERRUPT_EMAC0_Enable false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 125 HPS_IO43_is_present false IO_INPUT_DELAY16 0 PERPLL_DREFCLKDIV 0 MANUAL_MAINPLL_C0 1000.0 IO_INPUT_DELAY17 0 MAINPLLGRP_PERIPH_REF_CNT 999 HPS_IOB_3_open_drain_en false io41_delay_is_present false IO_INPUT_DELAY18 0 MANUAL_MAINPLL_C2 500.0 NAND_PinMuxing Unused IO_INPUT_DELAY20 0 IO_INPUT_DELAY19 0 MANUAL_MAINPLL_C3 200.0 IO_INPUT_DELAY21 0 IO_INPUT_DELAY22 0 io0_delay_is_present false EMAC2_CLK 250 HPS_IO32_is_present false IO_INPUT_DELAY23 0 io10_delay_is_present false HPS_IOB_17_open_drain_en false IO_INPUT_DELAY24 0 IO_INPUT_DELAY25 0 OVERIDE_PERI_PLL false IO_INPUT_DELAY26 0 MANUAL_CLK_EMACA_SOURCE 0 HPS_IO1_is_present false EMAC2_PinMuxing Unused IO_INPUT_DELAY27 0 IO_INPUT_DELAY28 0 LWH2F_ADDRESS_WIDTH 21 DEBUG_APB_Enable false HPS_IO21_is_present true IO_INPUT_DELAY30 0 IO_INPUT_DELAY29 0 F2H_FREE_CLK_Enable false IO_INPUT_DELAY31 0 io26_delay_is_present false PERPLLGRP_VCO_DENOM 1 IO_INPUT_DELAY32 0 F2H_SDRAM4_CLOCK_FREQ 100 IO_INPUT_DELAY33 0 IO_INPUT_DELAY34 0 EMAC2SEL 0 HPS_IOA_21_open_drain_en false IO_INPUT_DELAY35 0 CLK_EMACB_CNT 3 HPS_IO10_is_present false HPS_IOB_12_open_drain_en false IO_INPUT_DELAY36 0 W_RESET_ACTION 0 CTI_Enable false IO_INPUT_DELAY37 0 HPS_IOA_6_open_drain_en false io43_delay_is_present false IO_INPUT_DELAY38 0 IO_INPUT_DELAY40 0 IO_INPUT_DELAY39 0 MAINPLL_MODCLKDIV 5 SDMMC_REF_CLK 200 IO_INPUT_DELAY41 0 IO_INPUT_DELAY42 0 io2_delay_is_present false H2F_LW_AXI_CLOCK_FREQ 100000000 IO_INPUT_DELAY43 0 io12_delay_is_present true HPS_IO44_is_present false IO_INPUT_DELAY44 0 IO_INPUT_DELAY45 0 IO_INPUT_DELAY46 0 F2H_FREE_CLK_FREQ 200 HPS_IOA_15_open_drain_en false IO_INPUT_DELAY47 0 NOCDIV_CS_TRACECLK_HZ 400 HPS_IO33_is_present true HPS_IOA_1_open_drain_en false io28_delay_is_present false H2F_USER1_CLK_FREQ 500 MANUAL_CLK_GPIO_SOURCE 1 HPS_IO2_is_present false PERPLLGRP_C1_CNT 6 CLK_S2F_USER1_CNT 0 L4_SYS_FREE_CLK 2 quartus_ini_hps_ip_l2_at_12000 false HPS_IO22_is_present true LWH2F_Enable 1 io45_delay_is_present false NOCDIV_L4MPCLK_HZ 200 I2CEMAC1_PinMuxing Unused HPS_IOA_10_open_drain_en false F2H_SDRAM5_CLOCK_FREQ 100 CLK_S2F_USER1_SOURCE 0 HPS_IOB_9_open_drain_en false io4_delay_is_present false io14_delay_is_present false TEST_Enable false NOCDIV_CS_PDBGCLK 2 HPS_IO11_is_present false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 125 NOCDIV_CS_TRACECLK 0 CLK_GPIO_SOURCE 1 EMAC0_PTP false HPS_IOB_24_open_drain_en false mainpll_max_vco 3000 NOCDIV_L4MAINCLK 0 I2C1_Mode N/A io31_delay_is_present false S2FINTERRUPT_SYSTEMMANAGER_Enable false HPS_IO45_is_present false HPS_IOB_4_open_drain_en false IPXACT_Enable false S2FINTERRUPT_USB0_Enable false PIN_TO_BALL_MAP {35 AL11 36 AC11 37 AT10 38 AD8 40 AC9 39 AP10 41 AM10 42 AB10 43 AJ13 44 AB14 45 AH14 46 AB12 47 AJ9 10 AH10 11 AU15 12 AJ7 13 AL13 14 AH8 15 AM14 16 AD14 0 AC15 17 AN13 1 AL15 18 AG11 2 AJ11 19 AP14 20 AG9 3 AM16 21 AT14 4 AH12 22 AF12 5 AN15 23 AU13 6 AG13 24 AF10 7 AP16 25 AU11 8 AF14 26 AF8 9 AT16 27 AT12 28 AG7 29 AP12 30 AC13 31 AN11 32 AD12 33 AM12 34 AD10} HPS_IO_Enable {NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE NONE EMAC0:TX_CLK EMAC0:TX_CTL EMAC0:RX_CLK EMAC0:RX_CTL EMAC0:TXD0 EMAC0:TXD1 EMAC0:RXD0 EMAC0:RXD1 EMAC0:TXD2 EMAC0:TXD3 EMAC0:RXD2 EMAC0:RXD3 GPIO GPIO UART0:TX UART0:RX NONE HPS_OSC_CLK NONE NONE JTAG:TCK JTAG:TMS JTAG:TDO JTAG:TDI SDMMC:D0 SDMMC:CMD SDMMC:CCLK SDMMC:D1 SDMMC:D2 SDMMC:D3 NONE NONE NONE NONE MDIO0:MDIO MDIO0:MDC} MANUAL_CLK_SRC_EN false S2FINTERRUPT_SDMMC_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN 100 MANUAL_CLK_SDMMC_SOURCE 1 UART1_PinMuxing Unused S2FINTERRUPT_I2CEMAC2_Enable false EMAC1SEL 0 HPS_IO34_is_present true HPS_IOB_18_open_drain_en false io47_delay_is_present false TRACE_PinMuxing Unused FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN 100 MAINPLLGRP_C1_CNT 8 USB0_Mode N/A SMMU_sid_config 0 io6_delay_is_present false SMMU_rsb_ssd_const 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN 100 HPS_IO3_is_present false io16_delay_is_present false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 125 HPS_IO23_is_present true DISABLE_PERI_PLL false CLK_PERI_PLL_SOURCE2 0 S2FINTERRUPT_I2C0_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC1_SCL_IN 100 EMIF_CONDUIT_Enable true SPIM0_Mode N/A PERPLLGRP_VCO_NUMER 96 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 125 HPS_IOA_22_open_drain_en false S2FINTERRUPT_L4TIMER_Enable false mdio1_usefpga_is_present false HPS_IOB_13_open_drain_en false io33_delay_is_present false H2F_TPIU_CLOCK_IN_FREQ 100 HPS_IO12_is_present false FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5 USB1_PinMuxing Unused HPS_IOA_7_open_drain_en false S2FINTERRUPT_I2CEMAC0_Enable false CLK_GPIO_DB_CNT 0 EMAC0_SWITCH_Enable false S2FINTERRUPT_WATCHDOG_Enable false FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN 100 HPS_IO46_is_present false I2CEMAC0_Mode N/A HPS_IOA_16_open_drain_en false io8_delay_is_present false EMAC0_Mode RGMII_with_MDIO io18_delay_is_present false HPS_IOA_2_open_drain_en false HNOC_Interface_Mode 0 HPS_IO35_is_present true MAINPLLGRP_VCO_FDIV 0 pin_muxing {} IO_OUTPUT_DELAY0 0 INTERNAL_OSCILLATOR_ENABLE 60 SPIM0_PinMuxing Unused IO_OUTPUT_DELAY1 0 IO_OUTPUT_DELAY2 0 PERI_PLL_MANUAL_VCO_FREQ 2000 HPS_IO4_is_present false io35_delay_is_present false IO_OUTPUT_DELAY3 0 L4_SYS_FREE_CLK_HZ 100 IO_OUTPUT_DELAY4 0 HPS_IO24_is_present true IO_OUTPUT_DELAY5 0 HPS_IOA_11_open_drain_en false IO_OUTPUT_DELAY6 0 IO_OUTPUT_DELAY7 0 IO_INPUT_DELAY0 0 CUSTOM_MPU_CLK 800.0 L3_MAIN_FREE_CLK 400 IO_OUTPUT_DELAY8 0 IO_INPUT_DELAY1 0 F2SINTERRUPT_Enable true IO_OUTPUT_DELAY9 0 IO_INPUT_DELAY2 0 PERPLLGRP_VCO_FDIV 0 S2FINTERRUPT_SPIM1_Enable false device_name AGFB027R24C2E2VR2 IO_INPUT_DELAY3 0 HPS_IO13_is_present true IO_INPUT_DELAY4 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_TX_CLK_IN 100 IO_INPUT_DELAY5 0 HPS_DIV_GPIO_FREQ2 100 EMAC0SEL 0 IO_INPUT_DELAY6 0 io21_delay_is_present false IO_INPUT_DELAY7 0 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 125 IO_INPUT_DELAY8 0 CLK_PSI_SOURCE 0 IO_INPUT_DELAY9 0 F2S_Route_config 1 HPS_IO47_is_present true HPS_IOB_5_open_drain_en false CONFIG_HPS_DIV_GPIO 1 EMAC1_CLK 250 PERPLLGRP_C3_CNT 12 S2FINTERRUPT_UART1_Enable false io37_delay_is_present false watchdog_reset true MPU_EVENTS_Enable false S2FINTERRUPT_SPIS0_Enable false HPS_IOB_20_open_drain_en false HPS_IOB_19_open_drain_en false HPS_IO36_is_present true EMAC_PTP_REF_CLK 100 NOCDIV_CS_PDBGCLK_HZ 100 MANUAL_CLK_S2F_USER0_SOURCE 0 CLK_EMACA_SOURCE 0 FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN 100 HPS_IO5_is_present false hps_device_family Agilex EMAC2_PTP false CLK_MPU_SOURCE 1 HPS_IO25_is_present true MANUAL_MAINPLL_CFREQ_EN false CLK_EMACA_CNT 1 I2C1_PinMuxing Unused NAND_Mode N/A quartus_ini_hps_ip_enable_fm_advanced_options false io23_delay_is_present false HPS_IOA_23_open_drain_en false HPS_IOB_14_open_drain_en false HPS_IO14_is_present true HPS_IOA_8_open_drain_en false S2FINTERRUPT_EMAC1_Enable false EMAC1_PinMuxing Unused io40_delay_is_present false io39_delay_is_present false SPIS1_PinMuxing Unused EMAC1_SWITCH_Enable false MAINPLLGRP_C3_CNT 15 HPS_IO48_is_present true PLL_CLK0 Unused FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125 PLL_CLK1 Unused HPS_IOA_17_open_drain_en false quartus_ini_hps_ip_enable_test_interface false PLL_CLK2 Unused quartus_ini_hps_ip_enable_ace_interface false PLL_CLK3 Unused CM_Mode N/A PLL_CLK4 Unused HPS_IOA_3_open_drain_en false SMMU_rsb_sid_const 0 PERPLLGRP_C0_CNT 2 MANUAL_CLK_NOC_SOURCE 1 MANUAL_CLK_EMACB_SOURCE 1 CLK_S2F_USER0_CNT 0 HPS_IO37_is_present true TESTIOCTRL_MAINCLKSEL 8 FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 125 CLK_MAIN_PLL_SOURCE2 0 io25_delay_is_present false max_mpu_clk 1200 UART1_Mode N/A I2C0_Mode N/A STM_Enable true HPS_IO6_is_present false HPS_IO26_is_present true HPS_IOA_12_open_drain_en false io42_delay_is_present false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_clk_0

hps_clk_src v19.1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_bridges

falconmesa_hps_bridge_avalon v20.1.0
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_bridges
  clock_sink
clk_reset  
  reset_sink


Parameters

device_name AGFB027R24C2E2VR2
address_map
F2S_mode 0
F2S_Width 5
FP_F2S_Width 0
S2F_Width 3
LWH2F_Enable 1
F2S_ADDRESS_WIDTH 32
S2F_ADDRESS_WIDTH 32
F2S_Route_config 1
LWH2F_ADDRESS_WIDTH 21
IPXACT_Enable false
quartus_ini_hps_ip_enable_ace_interface false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_eosc1

hps_virt_clk v19.1


Parameters

clockFrequency 25000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_cb_intosc_hs_div2_clk

hps_virt_clk v19.1


Parameters

clockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_cb_intosc_ls_clk

hps_virt_clk v19.1


Parameters

clockFrequency 60000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_f2s_free_clk

hps_virt_clk v19.1


Parameters

clockFrequency 200000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_arm_a9_0

arm_a9 v19.1
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_arm_a9_0
  clock_sink
clk_reset  
  reset_sink
altera_axi_master   intel_agilex_hps_inst_arm_gic_0
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

address_map <address-map><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /></address-map>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_arm_a9_1

arm_a9 v19.1
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_arm_a9_1
  clock_sink
clk_reset  
  reset_sink
altera_axi_master   intel_agilex_hps_inst_arm_gic_0
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

address_map <address-map><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /></address-map>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_arm_gic_0

falconmesa_arm_gic v19.1
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_arm_gic_0
  clock_sink
clk_reset  
  reset_sink
intel_agilex_hps_inst_arm_a9_0 altera_axi_master  
  axi_slave0
altera_axi_master  
  axi_slave1
intel_agilex_hps_inst_arm_a9_1 altera_axi_master  
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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