emif_hps

2023.01.26.22:47:20 Datasheet
Overview

Memory Map

altera_emif_fm_hps_inst

altera_emif_fm_hps v2.6.1


Parameters

PROTOCOL_ENUM PROTOCOL_DDR4
PHY_FPGA_SPEEDGRADE_GUI E2V (ES3) - change device under 'View'->'Device Family'
PHY_RZQ 240
PHY_DDR4_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_DDR4_MEM_CLK_FREQ_MHZ 1333.333
PHY_DDR4_DEFAULT_REF_CLK_FREQ false
PHY_DDR4_USER_REF_CLK_FREQ_MHZ 33.333
PHY_DDR4_REF_CLK_JITTER_PS 10.0
PHY_DDR4_RATE_ENUM RATE_QUARTER
PHY_DDR4_IO_VOLTAGE 1.2
PHY_DDR4_DEFAULT_IO true
PHY_DDR4_CLAMSHELL_EN false
PHY_DDR4_AC_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_AC_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_AC_SLEW_RATE_ENUM SLEW_RATE_FM_FAST
PHY_DDR4_AC_DEEMPHASIS_ENUM DEEMPHASIS_MODE_OFF
PHY_DDR4_CK_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_CK_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_CK_SLEW_RATE_ENUM SLEW_RATE_FM_FAST
PHY_DDR4_CK_DEEMPHASIS_ENUM DEEMPHASIS_MODE_OFF
PHY_DDR4_DATA_IO_STD_ENUM IO_STD_POD_12
PHY_DDR4_DATA_OUT_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM SLEW_RATE_FM_FAST
PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM DEEMPHASIS_MODE_HIGH
PHY_DDR4_DATA_IN_MODE_ENUM IN_OCT_60_CAL
PHY_DDR4_STARTING_VREFIN 68.0
PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM IO_STD_TRUE_DIFF_SIGNALING
PHY_DDR4_RZQ_IO_STD_ENUM IO_STD_CMOS_12
MEM_DDR4_FORMAT_ENUM MEM_FORMAT_SODIMM
MEM_DDR4_DQ_WIDTH 72
MEM_DDR4_DQ_PER_DQS 8
MEM_DDR4_NUM_OF_DIMMS 1
MEM_DDR4_RANKS_PER_DIMM 1
MEM_DDR4_CK_WIDTH 1
MEM_DDR4_ROW_ADDR_WIDTH 16
MEM_DDR4_COL_ADDR_WIDTH 10
MEM_DDR4_BANK_ADDR_WIDTH 2
MEM_DDR4_BANK_GROUP_WIDTH 2
MEM_DDR4_DM_EN true
MEM_DDR4_ALERT_N_PLACEMENT_ENUM DDR4_ALERT_N_PLACEMENT_AUTO
MEM_DDR4_INTEL_DEFAULT_TERM true
MEM_DDR4_TCL 22
MEM_DDR4_ATCL_ENUM DDR4_ATCL_DISABLED
MEM_DDR4_WTCL 18
MEM_DDR4_FINE_GRANULARITY_REFRESH DDR4_FINE_REFRESH_FIXED_1X
MEM_DDR4_AC_PARITY_LATENCY DDR4_AC_PARITY_LATENCY_DISABLE
MEM_DDR4_WRITE_DBI false
MEM_DDR4_READ_DBI true
MEM_DDR4_DEFAULT_VREFOUT true
MEM_DDR4_DQS_WIDTH 9
MEM_DDR4_CS_PER_DIMM 1
MEM_DDR4_VREFDQ_TRAINING_VALUE 70.0
MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP Range 1 - 60% to 92.5%
MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP RZQ/7 (34 Ohm)
MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP Dynamic ODT off
MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP ODT Disabled
MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP RZQ/4 (60 Ohm)
MEM_DDR4_USE_DEFAULT_ODT false
MEM_DDR4_R_ODTN_1X1 Rank 0
MEM_DDR4_R_ODT0_1X1 off
MEM_DDR4_W_ODTN_1X1 Rank 0
MEM_DDR4_W_ODT0_1X1 off
MEM_DDR4_R_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_R_ODT0_2X2 off,off
MEM_DDR4_R_ODT1_2X2 off,off
MEM_DDR4_W_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_W_ODT0_2X2 on,off
MEM_DDR4_W_ODT1_2X2 off,on
MEM_DDR4_R_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X2 off,off,on,on
MEM_DDR4_R_ODT1_4X2 on,on,off,off
MEM_DDR4_W_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X2 off,off,on,on
MEM_DDR4_W_ODT1_4X2 on,on,off,off
MEM_DDR4_R_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X4 off,off,on,off
MEM_DDR4_R_ODT1_4X4 off,off,off,on
MEM_DDR4_R_ODT2_4X4 on,off,off,off
MEM_DDR4_R_ODT3_4X4 off,on,off,off
MEM_DDR4_W_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X4 on,off,on,off
MEM_DDR4_W_ODT1_4X4 off,on,off,on
MEM_DDR4_W_ODT2_4X4 on,off,on,off
MEM_DDR4_W_ODT3_4X4 off,on,off,on
MEM_DDR4_R_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR4_R_DERIVED_ODT0 (Drive) RZQ/7 (34 Ohm),-,-,-
MEM_DDR4_R_DERIVED_ODT1 -,-,-,-
MEM_DDR4_R_DERIVED_ODT2 -,-,-,-
MEM_DDR4_R_DERIVED_ODT3 -,-,-,-
MEM_DDR4_R_DERIVED_BODTN
MEM_DDR4_R_DERIVED_BODT0
MEM_DDR4_R_DERIVED_BODT1
MEM_DDR4_W_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR4_W_DERIVED_ODT0 (Park) RZQ/4 (60 Ohm),-,-,-
MEM_DDR4_W_DERIVED_ODT1 -,-,-,-
MEM_DDR4_W_DERIVED_ODT2 -,-,-,-
MEM_DDR4_W_DERIVED_ODT3 -,-,-,-
MEM_DDR4_W_DERIVED_BODTN
MEM_DDR4_W_DERIVED_BODT0
MEM_DDR4_W_DERIVED_BODT1
MEM_DDR4_SPEEDBIN_ENUM DDR4_SPEEDBIN_3200
MEM_DDR4_TIS_PS 40
MEM_DDR4_TIS_AC_MV 90
MEM_DDR4_TIH_PS 65
MEM_DDR4_TIH_DC_MV 65
MEM_DDR4_TDIVW_TOTAL_UI 0.23
MEM_DDR4_VDIVW_TOTAL 110
MEM_DDR4_TDQSQ_UI 0.2
MEM_DDR4_TQH_UI 0.7
MEM_DDR4_TDVWP_UI 0.72
MEM_DDR4_TDQSCK_PS 160
MEM_DDR4_TDQSS_CYC 0.27
MEM_DDR4_TQSH_CYC 0.4
MEM_DDR4_TDSH_CYC 0.18
MEM_DDR4_TDSS_CYC 0.18
MEM_DDR4_TWLS_CYC 0.13
MEM_DDR4_TWLH_CYC 0.13
MEM_DDR4_TINIT_US 500
MEM_DDR4_TMRD_CK_CYC 8
MEM_DDR4_TRAS_NS 32.0
MEM_DDR4_TRCD_NS 13.75
MEM_DDR4_TRP_NS 13.75
MEM_DDR4_TREFI_US 7.8
MEM_DDR4_TRFC_NS 350.0
MEM_DDR4_TWR_NS 15.0
MEM_DDR4_TWTR_L_CYC 10
MEM_DDR4_TWTR_S_CYC 4
MEM_DDR4_TFAW_NS 21.0
MEM_DDR4_TRRD_L_CYC 7
MEM_DDR4_TRRD_S_CYC 4
MEM_DDR4_TCCD_L_CYC 7
MEM_DDR4_TCCD_S_CYC 4
CTRL_DDR4_AUTO_POWER_DOWN_EN false
CTRL_DDR4_AUTO_POWER_DOWN_CYCS 32
CTRL_DDR4_USER_REFRESH_EN false
CTRL_DDR4_USER_PRIORITY_EN false
CTRL_DDR4_AUTO_PRECHARGE_EN false
CTRL_DDR4_ADDR_ORDER_ENUM DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG
CTRL_DDR4_ECC_EN true
CTRL_DDR4_ECC_AUTO_CORRECTION_EN true
CTRL_DDR4_ECC_READDATAERROR_EN false
CTRL_DDR4_ECC_STATUS_EN false
CTRL_DDR4_REORDER_EN true
CTRL_DDR4_STARVE_LIMIT 10
CTRL_DDR4_MMR_EN false
CTRL_DDR4_MAJOR_MODE_EN false
CTRL_DDR4_POST_REFRESH_EN false
CTRL_DDR4_PRE_REFRESH_EN false
CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS 0
DIAG_EXPORT_PLL_LOCKED false
DIAG_DDR4_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_DDR4_EX_DESIGN_ISSP_EN false
DIAG_DDR4_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_DDR4_USE_TG_AVL_2 false
DIAG_DDR4_ENABLE_DEFAULT_MODE false
DIAG_DDR4_ENABLE_USER_MODE true
DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE TG_CFG_AMM_EXPORT_MODE_JTAG
DIAG_DDR4_TG2_TEST_DURATION SHORT
DIAG_DDR4_SKIP_AC_PARITY_CHECK false
EX_DESIGN_GUI_DDR4_SEL_DESIGN AVAIL_EX_DESIGNS_GEN_DESIGN
EX_DESIGN_GUI_DDR4_GEN_SIM true
EX_DESIGN_GUI_DDR4_GEN_SYNTH true
EX_DESIGN_GUI_DDR4_GEN_BSI false
EX_DESIGN_GUI_DDR4_GEN_CDC false
EX_DESIGN_GUI_DDR4_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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