emif_fm_ddr4a

2023.03.23.17:15:35 Datasheet
Overview

All Components
   emif_fm_ddr4a altera_emif_fm 2.6.1
   emif_fm_ddr4a_ecc_core altera_emif_ecc 19.1
Memory Map
  emif_fm_ddr4a
ctrl_amm_0 
  emif_fm_ddr4a_ecc_core
ctrl_amm_0 

emif_fm_ddr4a

altera_emif_fm v2.6.1


Parameters

PROTOCOL_ENUM PROTOCOL_DDR4
PHY_FPGA_SPEEDGRADE_GUI E2V (ES3) - change device under 'View'->'Device Family'
PHY_RZQ 240
PLL_ADD_EXTRA_CLKS false
PHY_DDR4_CONFIG_ENUM CONFIG_PHY_AND_HARD_CTRL
PHY_DDR4_MEM_CLK_FREQ_MHZ 1333.333
PHY_DDR4_DEFAULT_REF_CLK_FREQ false
PHY_DDR4_USER_REF_CLK_FREQ_MHZ 33.333
PHY_DDR4_REF_CLK_JITTER_PS 10.0
PHY_DDR4_RATE_ENUM RATE_QUARTER
PHY_DDR4_IO_VOLTAGE 1.2
PHY_DDR4_DEFAULT_IO true
PHY_DDR4_MIMIC_HPS_EMIF true
PHY_DDR4_CLAMSHELL_EN false
PHY_DDR4_AC_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_AC_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_AC_SLEW_RATE_ENUM SLEW_RATE_FM_FAST
PHY_DDR4_AC_DEEMPHASIS_ENUM DEEMPHASIS_MODE_OFF
PHY_DDR4_CK_IO_STD_ENUM IO_STD_SSTL_12
PHY_DDR4_CK_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_CK_SLEW_RATE_ENUM SLEW_RATE_FM_FAST
PHY_DDR4_CK_DEEMPHASIS_ENUM DEEMPHASIS_MODE_OFF
PHY_DDR4_DATA_IO_STD_ENUM IO_STD_POD_12
PHY_DDR4_DATA_OUT_MODE_ENUM OUT_OCT_40_CAL
PHY_DDR4_DATA_OUT_SLEW_RATE_ENUM SLEW_RATE_FM_FAST
PHY_DDR4_DATA_OUT_DEEMPHASIS_ENUM DEEMPHASIS_MODE_HIGH
PHY_DDR4_DATA_IN_MODE_ENUM IN_OCT_60_CAL
PHY_DDR4_STARTING_VREFIN 68.0
PHY_DDR4_PLL_REF_CLK_IO_STD_ENUM IO_STD_TRUE_DIFF_SIGNALING
PHY_DDR4_RZQ_IO_STD_ENUM IO_STD_CMOS_12
MEM_DDR4_FORMAT_ENUM MEM_FORMAT_SODIMM
MEM_DDR4_DQ_WIDTH 72
MEM_DDR4_DQ_PER_DQS 8
MEM_DDR4_NUM_OF_DIMMS 1
MEM_DDR4_RANKS_PER_DIMM 1
MEM_DDR4_CK_WIDTH 1
MEM_DDR4_ROW_ADDR_WIDTH 16
MEM_DDR4_COL_ADDR_WIDTH 10
MEM_DDR4_BANK_ADDR_WIDTH 2
MEM_DDR4_BANK_GROUP_WIDTH 2
MEM_DDR4_DM_EN true
MEM_DDR4_ALERT_N_PLACEMENT_ENUM DDR4_ALERT_N_PLACEMENT_AUTO
MEM_DDR4_INTEL_DEFAULT_TERM true
MEM_DDR4_TCL 22
MEM_DDR4_ATCL_ENUM DDR4_ATCL_DISABLED
MEM_DDR4_WTCL 18
MEM_DDR4_FINE_GRANULARITY_REFRESH DDR4_FINE_REFRESH_FIXED_1X
MEM_DDR4_AC_PARITY_LATENCY DDR4_AC_PARITY_LATENCY_DISABLE
MEM_DDR4_WRITE_DBI false
MEM_DDR4_READ_DBI true
MEM_DDR4_DEFAULT_VREFOUT true
MEM_DDR4_DQS_WIDTH 9
MEM_DDR4_CS_PER_DIMM 1
MEM_DDR4_VREFDQ_TRAINING_VALUE 70.0
MEM_DDR4_VREFDQ_TRAINING_RANGE_DISP Range 1 - 60% to 92.5%
MEM_DDR4_INTEL_DEFAULT_DRV_STR_ENUM_DISP RZQ/7 (34 Ohm)
MEM_DDR4_INTEL_DEFAULT_RTT_WR_ENUM_DISP Dynamic ODT off
MEM_DDR4_INTEL_DEFAULT_RTT_NOM_ENUM_DISP ODT Disabled
MEM_DDR4_INTEL_DEFAULT_RTT_PARK_ENUM_DISP RZQ/4 (60 Ohm)
MEM_DDR4_USE_DEFAULT_ODT true
MEM_DDR4_R_ODTN_1X1 Rank 0
MEM_DDR4_R_ODT0_1X1 off
MEM_DDR4_W_ODTN_1X1 Rank 0
MEM_DDR4_W_ODT0_1X1 on
MEM_DDR4_R_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_R_ODT0_2X2 off,off
MEM_DDR4_R_ODT1_2X2 off,off
MEM_DDR4_W_ODTN_2X2 Rank 0,Rank 1
MEM_DDR4_W_ODT0_2X2 on,off
MEM_DDR4_W_ODT1_2X2 off,on
MEM_DDR4_R_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X2 off,off,on,on
MEM_DDR4_R_ODT1_4X2 on,on,off,off
MEM_DDR4_W_ODTN_4X2 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X2 off,off,on,on
MEM_DDR4_W_ODT1_4X2 on,on,off,off
MEM_DDR4_R_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_R_ODT0_4X4 off,off,on,off
MEM_DDR4_R_ODT1_4X4 off,off,off,on
MEM_DDR4_R_ODT2_4X4 on,off,off,off
MEM_DDR4_R_ODT3_4X4 off,on,off,off
MEM_DDR4_W_ODTN_4X4 Rank 0,Rank 1,Rank 2,Rank 3
MEM_DDR4_W_ODT0_4X4 on,off,on,off
MEM_DDR4_W_ODT1_4X4 off,on,off,on
MEM_DDR4_W_ODT2_4X4 on,off,on,off
MEM_DDR4_W_ODT3_4X4 off,on,off,on
MEM_DDR4_R_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR4_R_DERIVED_ODT0 (Drive) RZQ/7 (34 Ohm),-,-,-
MEM_DDR4_R_DERIVED_ODT1 -,-,-,-
MEM_DDR4_R_DERIVED_ODT2 -,-,-,-
MEM_DDR4_R_DERIVED_ODT3 -,-,-,-
MEM_DDR4_R_DERIVED_BODTN
MEM_DDR4_R_DERIVED_BODT0
MEM_DDR4_R_DERIVED_BODT1
MEM_DDR4_W_DERIVED_ODTN Rank 0,-,-,-
MEM_DDR4_W_DERIVED_ODT0 (Park) RZQ/4 (60 Ohm),-,-,-
MEM_DDR4_W_DERIVED_ODT1 -,-,-,-
MEM_DDR4_W_DERIVED_ODT2 -,-,-,-
MEM_DDR4_W_DERIVED_ODT3 -,-,-,-
MEM_DDR4_W_DERIVED_BODTN
MEM_DDR4_W_DERIVED_BODT0
MEM_DDR4_W_DERIVED_BODT1
MEM_DDR4_SPEEDBIN_ENUM DDR4_SPEEDBIN_3200
MEM_DDR4_TIS_PS 40
MEM_DDR4_TIS_AC_MV 90
MEM_DDR4_TIH_PS 65
MEM_DDR4_TIH_DC_MV 65
MEM_DDR4_TDIVW_TOTAL_UI 0.23
MEM_DDR4_VDIVW_TOTAL 110
MEM_DDR4_TDQSQ_UI 0.2
MEM_DDR4_TQH_UI 0.7
MEM_DDR4_TDVWP_UI 0.72
MEM_DDR4_TDQSCK_PS 160
MEM_DDR4_TDQSS_CYC 0.27
MEM_DDR4_TQSH_CYC 0.4
MEM_DDR4_TDSH_CYC 0.18
MEM_DDR4_TDSS_CYC 0.18
MEM_DDR4_TWLS_CYC 0.13
MEM_DDR4_TWLH_CYC 0.13
MEM_DDR4_TINIT_US 500
MEM_DDR4_TMRD_CK_CYC 8
MEM_DDR4_TRAS_NS 32.0
MEM_DDR4_TRCD_NS 13.75
MEM_DDR4_TRP_NS 13.75
MEM_DDR4_TREFI_US 7.8
MEM_DDR4_TRFC_NS 350.0
MEM_DDR4_TWR_NS 15.0
MEM_DDR4_TWTR_L_CYC 10
MEM_DDR4_TWTR_S_CYC 4
MEM_DDR4_TFAW_NS 21.0
MEM_DDR4_TRRD_L_CYC 7
MEM_DDR4_TRRD_S_CYC 4
MEM_DDR4_TCCD_L_CYC 7
MEM_DDR4_TCCD_S_CYC 4
CTRL_DDR4_AUTO_POWER_DOWN_EN false
CTRL_DDR4_AUTO_POWER_DOWN_CYCS 32
CTRL_DDR4_USER_REFRESH_EN false
CTRL_DDR4_USER_PRIORITY_EN false
CTRL_DDR4_AUTO_PRECHARGE_EN false
CTRL_DDR4_ADDR_ORDER_ENUM DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG
CTRL_DDR4_ECC_EN true
CTRL_DDR4_ECC_AUTO_CORRECTION_EN true
CTRL_DDR4_ECC_READDATAERROR_EN false
CTRL_DDR4_ECC_STATUS_EN false
CTRL_DDR4_REORDER_EN true
CTRL_DDR4_STARVE_LIMIT 10
CTRL_DDR4_MMR_EN false
CTRL_DDR4_MAJOR_MODE_EN false
CTRL_DDR4_POST_REFRESH_EN false
CTRL_DDR4_PRE_REFRESH_EN false
CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS 0
CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS 0
DIAG_EXPORT_PLL_LOCKED false
DIAG_DDR4_SIM_CAL_MODE_ENUM SIM_CAL_MODE_SKIP
DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE CAL_DEBUG_EXPORT_MODE_DISABLED
DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES 1
DIAG_DDR4_EX_DESIGN_ISSP_EN true
DIAG_DDR4_EFFICIENCY_MONITOR EFFMON_MODE_DISABLED
DIAG_DDR4_USE_TG_AVL_2 false
DIAG_DDR4_ENABLE_DEFAULT_MODE false
DIAG_DDR4_ENABLE_USER_MODE true
DIAG_DDR4_EXPORT_TG_CFG_AVALON_SLAVE TG_CFG_AMM_EXPORT_MODE_JTAG
DIAG_DDR4_TG2_TEST_DURATION SHORT
DIAG_DDR4_AC_PARITY_ERR false
DIAG_DDR4_SKIP_AC_PARITY_CHECK false
NUM_IPS 1
EX_DESIGN_GUI_DDR4_GEN_SIM true
EX_DESIGN_GUI_DDR4_GEN_SYNTH true
EX_DESIGN_GUI_DDR4_GEN_BSI false
EX_DESIGN_GUI_DDR4_GEN_CDC false
EX_DESIGN_GUI_DDR4_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT TARGET_DEV_KIT_NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

emif_fm_ddr4a_arch

altera_emif_arch_fm v19.1
emif_fm_ddr4a_ecc_core ctrl_ecc_0   emif_fm_ddr4a_arch
  ctrl_ecc_0
ctrl_ast_cmd_0  
  ctrl_ast_cmd_0
ctrl_ast_wr_0  
  ctrl_ast_wr_0
emif_usr_clk   emif_fm_ddr4a_ecc_core
  emif_usr_clk_in
emif_usr_reset_n  
  emif_usr_reset_n_in
ctrl_ast_rd_0  
  ctrl_ast_rd_0


Parameters

SILICON_REV 14nm5
IS_HPS false
USER_CLK_RATIO 4
C2P_P2C_CLK_RATIO 4
PHY_HMC_CLK_RATIO 2
DIAG_ABSTRACT_PHY_WLAT 9
DIAG_ABSTRACT_PHY_RLAT 20
DIAG_CPA_OUT_1_EN false
DIAG_USE_CPA_LOCK true
DQS_BUS_MODE_ENUM DQS_BUS_MODE_X8_X9
AC_PIN_MAP_SCHEME use_0_1_2_lane
NUM_OF_HMC_PORTS 1
HMC_AVL_PROTOCOL_ENUM CTRL_AVL_PROTOCOL_ST
HMC_READY_LATENCY 2
HMC_CTRL_DIMM_TYPE dimm_type_udimm
SEQ_PT_SYN_CONTENT 00024c400000000000000301000a2c2b01121608480909010102110902000101001401000903033400000000000000000d00c08100b0000000000000000000004066008000c40707016c00d40000012300001e780000015e00000000000000080814040c000b0a091003020100131211000000060000000400020301000000002b2a290012111000161514131a1918172524231b0000272600280b0000000908000000004434241474645404352515846555054526168575560646361086766618131211201b1a1928232221302b2a2938333231403b3a3948434241004b4a4908030201500b0a0958535251605b5a5968636261706b6a6978737271807b7a7988838281008b8a8900000a50000100010002003000030400000408000005146000060c0f
SEQ_PT_SIM_CONTENT 00024c400000000000000301000a2c2b01121608480909010102110902000101001401000903033400000000000000000d20e08100b0000000000000000000004077d58000c40707016c00d40000012300001e780000015e00000000000000080814040c000b0a091003020100131211000000060000000400020301000000002b2a290012111000161514131a1918172524231b0000272600280b0000000908000000004434241474645404352515846555054526168575560646361086766618131211201b1a1928232221302b2a2938333231403b3a3948434241004b4a4908030201500b0a0958535251605b5a5968636261706b6a6978737271807b7a7988838281008b8a8900000a50000100010002003000030400000408000005146000060c0f
REGISTER_AFI_C2P 1
REGISTER_AFI_P2C 1
REGISTER_AMM_P2C 1
REGISTER_AMM_C2P 1
NUM_OF_RTL_TILES 3
PRI_RDATA_TILE_INDEX 1
PRI_RDATA_LANE_INDEX 3
PRI_WDATA_TILE_INDEX 1
PRI_WDATA_LANE_INDEX 3
PRI_AC_TILE_INDEX 1
SEC_RDATA_TILE_INDEX 1
SEC_RDATA_LANE_INDEX 3
SEC_WDATA_TILE_INDEX 1
SEC_WDATA_LANE_INDEX 3
SEC_AC_TILE_INDEX 1
LANES_USAGE_0 765762413
LANES_USAGE_1 45
LANES_USAGE_2 0
LANES_USAGE_3 0
LANES_USAGE_AUTOGEN_WCNT 4
PINS_USAGE_0 1073217407
PINS_USAGE_1 763355133
PINS_USAGE_2 1073713151
PINS_USAGE_3 1040179197
PINS_USAGE_4 16252799
PINS_USAGE_5 0
PINS_USAGE_6 0
PINS_USAGE_7 0
PINS_USAGE_8 0
PINS_USAGE_9 0
PINS_USAGE_10 0
PINS_USAGE_11 0
PINS_USAGE_12 0
PINS_USAGE_AUTOGEN_WCNT 13
LANE_PIN_USAGE_0 20058385
LANE_PIN_USAGE_1 71582788
LANE_PIN_USAGE_2 286266145
LANE_PIN_USAGE_3 209994820
LANE_PIN_USAGE_4 286331137
LANE_PIN_USAGE_5 67422276
LANE_PIN_USAGE_6 71581969
LANE_PIN_USAGE_7 269828353
LANE_PIN_USAGE_8 71582788
LANE_PIN_USAGE_9 69905
LANE_PIN_USAGE_10 71582788
LANE_PIN_USAGE_11 209994833
LANE_PIN_USAGE_12 286331137
LANE_PIN_USAGE_13 67422276
LANE_PIN_USAGE_14 554766609
LANE_PIN_USAGE_15 71581772
LANE_PIN_USAGE_16 20058385
LANE_PIN_USAGE_17 71582788
LANE_PIN_USAGE_18 286266145
LANE_PIN_USAGE_19 4
LANE_PIN_USAGE_20 0
LANE_PIN_USAGE_21 0
LANE_PIN_USAGE_22 0
LANE_PIN_USAGE_23 0
LANE_PIN_USAGE_24 0
LANE_PIN_USAGE_25 0
LANE_PIN_USAGE_26 0
LANE_PIN_USAGE_27 0
LANE_PIN_USAGE_28 0
LANE_PIN_USAGE_29 0
LANE_PIN_USAGE_30 0
LANE_PIN_USAGE_31 0
LANE_PIN_USAGE_32 0
LANE_PIN_USAGE_33 0
LANE_PIN_USAGE_34 0
LANE_PIN_USAGE_35 0
LANE_PIN_USAGE_36 0
LANE_PIN_USAGE_37 0
LANE_PIN_USAGE_38 0
LANE_PIN_USAGE_39 0
LANE_PIN_USAGE_40 0
LANE_PIN_USAGE_41 0
LANE_PIN_USAGE_42 0
LANE_PIN_USAGE_43 0
LANE_PIN_USAGE_44 0
LANE_PIN_USAGE_45 0
LANE_PIN_USAGE_46 0
LANE_PIN_USAGE_47 0
LANE_PIN_USAGE_48 0
LANE_PIN_USAGE_49 0
LANE_PIN_USAGE_50 0
LANE_PIN_USAGE_51 0
LANE_PIN_USAGE_AUTOGEN_WCNT 52
PINS_RATE_0 0
PINS_RATE_1 561774592
PINS_RATE_2 16748543
PINS_RATE_3 0
PINS_RATE_4 0
PINS_RATE_5 0
PINS_RATE_6 0
PINS_RATE_7 0
PINS_RATE_8 0
PINS_RATE_9 0
PINS_RATE_10 0
PINS_RATE_11 0
PINS_RATE_12 0
PINS_RATE_AUTOGEN_WCNT 13
DB_PINS_PROC_MODE_0 275876963
DB_PINS_PROC_MODE_1 103911395
DB_PINS_PROC_MODE_2 275876963
DB_PINS_PROC_MODE_3 103911395
DB_PINS_PROC_MODE_4 275876963
DB_PINS_PROC_MODE_5 103911395
DB_PINS_PROC_MODE_6 275876963
DB_PINS_PROC_MODE_7 103911395
DB_PINS_PROC_MODE_8 1041269793
DB_PINS_PROC_MODE_9 66230241
DB_PINS_PROC_MODE_10 34636833
DB_PINS_PROC_MODE_11 34636833
DB_PINS_PROC_MODE_12 34668543
DB_PINS_PROC_MODE_13 34656289
DB_PINS_PROC_MODE_14 275876963
DB_PINS_PROC_MODE_15 103911395
DB_PINS_PROC_MODE_16 275876963
DB_PINS_PROC_MODE_17 103911395
DB_PINS_PROC_MODE_18 275876963
DB_PINS_PROC_MODE_19 103911395
DB_PINS_PROC_MODE_20 275876963
DB_PINS_PROC_MODE_21 103911395
DB_PINS_PROC_MODE_22 275876963
DB_PINS_PROC_MODE_23 103911395
DB_PINS_PROC_MODE_24 0
DB_PINS_PROC_MODE_25 0
DB_PINS_PROC_MODE_26 0
DB_PINS_PROC_MODE_27 0
DB_PINS_PROC_MODE_28 0
DB_PINS_PROC_MODE_29 0
DB_PINS_PROC_MODE_30 0
DB_PINS_PROC_MODE_31 0
DB_PINS_PROC_MODE_32 0
DB_PINS_PROC_MODE_33 0
DB_PINS_PROC_MODE_34 0
DB_PINS_PROC_MODE_35 0
DB_PINS_PROC_MODE_36 0
DB_PINS_PROC_MODE_37 0
DB_PINS_PROC_MODE_38 0
DB_PINS_PROC_MODE_39 0
DB_PINS_PROC_MODE_40 0
DB_PINS_PROC_MODE_41 0
DB_PINS_PROC_MODE_42 0
DB_PINS_PROC_MODE_43 0
DB_PINS_PROC_MODE_44 0
DB_PINS_PROC_MODE_45 0
DB_PINS_PROC_MODE_46 0
DB_PINS_PROC_MODE_47 0
DB_PINS_PROC_MODE_48 0
DB_PINS_PROC_MODE_49 0
DB_PINS_PROC_MODE_50 0
DB_PINS_PROC_MODE_51 0
DB_PINS_PROC_MODE_52 0
DB_PINS_PROC_MODE_53 0
DB_PINS_PROC_MODE_54 0
DB_PINS_PROC_MODE_55 0
DB_PINS_PROC_MODE_56 0
DB_PINS_PROC_MODE_57 0
DB_PINS_PROC_MODE_58 0
DB_PINS_PROC_MODE_59 0
DB_PINS_PROC_MODE_60 0
DB_PINS_PROC_MODE_61 0
DB_PINS_PROC_MODE_62 0
DB_PINS_PROC_MODE_63 0
DB_PINS_PROC_MODE_AUTOGEN_WCNT 64
PINS_DATA_IN_MODE_0 151515721
PINS_DATA_IN_MODE_1 33329737
PINS_DATA_IN_MODE_2 1059361353
PINS_DATA_IN_MODE_3 153391681
PINS_DATA_IN_MODE_4 153391231
PINS_DATA_IN_MODE_5 150736969
PINS_DATA_IN_MODE_6 153391689
PINS_DATA_IN_MODE_7 153387017
PINS_DATA_IN_MODE_8 1059361353
PINS_DATA_IN_MODE_9 153391681
PINS_DATA_IN_MODE_10 153391231
PINS_DATA_IN_MODE_11 153362377
PINS_DATA_IN_MODE_12 151515721
PINS_DATA_IN_MODE_13 33329737
PINS_DATA_IN_MODE_14 585
PINS_DATA_IN_MODE_15 0
PINS_DATA_IN_MODE_16 0
PINS_DATA_IN_MODE_17 0
PINS_DATA_IN_MODE_18 0
PINS_DATA_IN_MODE_19 0
PINS_DATA_IN_MODE_20 0
PINS_DATA_IN_MODE_21 0
PINS_DATA_IN_MODE_22 0
PINS_DATA_IN_MODE_23 0
PINS_DATA_IN_MODE_24 0
PINS_DATA_IN_MODE_25 0
PINS_DATA_IN_MODE_26 0
PINS_DATA_IN_MODE_27 0
PINS_DATA_IN_MODE_28 0
PINS_DATA_IN_MODE_29 0
PINS_DATA_IN_MODE_30 0
PINS_DATA_IN_MODE_31 0
PINS_DATA_IN_MODE_32 0
PINS_DATA_IN_MODE_33 0
PINS_DATA_IN_MODE_34 0
PINS_DATA_IN_MODE_35 0
PINS_DATA_IN_MODE_36 0
PINS_DATA_IN_MODE_37 0
PINS_DATA_IN_MODE_38 0
PINS_DATA_IN_MODE_AUTOGEN_WCNT 39
PINS_C2L_DRIVEN_0 267714383
PINS_C2L_DRIVEN_1 250877
PINS_C2L_DRIVEN_2 251658240
PINS_C2L_DRIVEN_3 1027593213
PINS_C2L_DRIVEN_4 16056143
PINS_C2L_DRIVEN_5 0
PINS_C2L_DRIVEN_6 0
PINS_C2L_DRIVEN_7 0
PINS_C2L_DRIVEN_8 0
PINS_C2L_DRIVEN_9 0
PINS_C2L_DRIVEN_10 0
PINS_C2L_DRIVEN_11 0
PINS_C2L_DRIVEN_12 0
PINS_C2L_DRIVEN_AUTOGEN_WCNT 13
PINS_OCT_MODE_0 1073217407
PINS_OCT_MODE_1 253949
PINS_OCT_MODE_2 1056964608
PINS_OCT_MODE_3 1040179197
PINS_OCT_MODE_4 16252799
PINS_OCT_MODE_5 0
PINS_OCT_MODE_6 0
PINS_OCT_MODE_7 0
PINS_OCT_MODE_8 0
PINS_OCT_MODE_9 0
PINS_OCT_MODE_10 0
PINS_OCT_MODE_11 0
PINS_OCT_MODE_12 0
PINS_OCT_MODE_AUTOGEN_WCNT 13
PINS_DCC_SPLIT_0 805503024
PINS_DCC_SPLIT_1 201329664
PINS_DCC_SPLIT_2 805306368
PINS_DCC_SPLIT_3 12585984
PINS_DCC_SPLIT_4 196656
PINS_DCC_SPLIT_5 0
PINS_DCC_SPLIT_6 0
PINS_DCC_SPLIT_7 0
PINS_DCC_SPLIT_8 0
PINS_DCC_SPLIT_9 0
PINS_DCC_SPLIT_10 0
PINS_DCC_SPLIT_11 0
PINS_DCC_SPLIT_12 0
PINS_DCC_SPLIT_AUTOGEN_WCNT 13
UNUSED_MEM_PINS_PINLOC_0 133311503
UNUSED_MEM_PINS_PINLOC_1 95526003
UNUSED_MEM_PINS_PINLOC_2 75572298
UNUSED_MEM_PINS_PINLOC_3 55630906
UNUSED_MEM_PINS_PINLOC_4 19954731
UNUSED_MEM_PINS_PINLOC_5 7
UNUSED_MEM_PINS_PINLOC_6 0
UNUSED_MEM_PINS_PINLOC_7 0
UNUSED_MEM_PINS_PINLOC_8 0
UNUSED_MEM_PINS_PINLOC_9 0
UNUSED_MEM_PINS_PINLOC_10 0
UNUSED_MEM_PINS_PINLOC_11 0
UNUSED_MEM_PINS_PINLOC_12 0
UNUSED_MEM_PINS_PINLOC_13 0
UNUSED_MEM_PINS_PINLOC_14 0
UNUSED_MEM_PINS_PINLOC_15 0
UNUSED_MEM_PINS_PINLOC_16 0
UNUSED_MEM_PINS_PINLOC_17 0
UNUSED_MEM_PINS_PINLOC_18 0
UNUSED_MEM_PINS_PINLOC_19 0
UNUSED_MEM_PINS_PINLOC_20 0
UNUSED_MEM_PINS_PINLOC_21 0
UNUSED_MEM_PINS_PINLOC_22 0
UNUSED_MEM_PINS_PINLOC_23 0
UNUSED_MEM_PINS_PINLOC_24 0
UNUSED_MEM_PINS_PINLOC_25 0
UNUSED_MEM_PINS_PINLOC_26 0
UNUSED_MEM_PINS_PINLOC_27 0
UNUSED_MEM_PINS_PINLOC_28 0
UNUSED_MEM_PINS_PINLOC_29 0
UNUSED_MEM_PINS_PINLOC_30 0
UNUSED_MEM_PINS_PINLOC_31 0
UNUSED_MEM_PINS_PINLOC_32 0
UNUSED_MEM_PINS_PINLOC_33 0
UNUSED_MEM_PINS_PINLOC_34 0
UNUSED_MEM_PINS_PINLOC_35 0
UNUSED_MEM_PINS_PINLOC_36 0
UNUSED_MEM_PINS_PINLOC_37 0
UNUSED_MEM_PINS_PINLOC_38 0
UNUSED_MEM_PINS_PINLOC_39 0
UNUSED_MEM_PINS_PINLOC_40 0
UNUSED_MEM_PINS_PINLOC_41 0
UNUSED_MEM_PINS_PINLOC_42 0
UNUSED_MEM_PINS_PINLOC_43 0
UNUSED_MEM_PINS_PINLOC_44 0
UNUSED_MEM_PINS_PINLOC_45 0
UNUSED_MEM_PINS_PINLOC_46 0
UNUSED_MEM_PINS_PINLOC_47 0
UNUSED_MEM_PINS_PINLOC_48 0
UNUSED_MEM_PINS_PINLOC_49 0
UNUSED_MEM_PINS_PINLOC_50 0
UNUSED_MEM_PINS_PINLOC_51 0
UNUSED_MEM_PINS_PINLOC_52 0
UNUSED_MEM_PINS_PINLOC_53 0
UNUSED_MEM_PINS_PINLOC_54 0
UNUSED_MEM_PINS_PINLOC_55 0
UNUSED_MEM_PINS_PINLOC_56 0
UNUSED_MEM_PINS_PINLOC_57 0
UNUSED_MEM_PINS_PINLOC_58 0
UNUSED_MEM_PINS_PINLOC_59 0
UNUSED_MEM_PINS_PINLOC_60 0
UNUSED_MEM_PINS_PINLOC_61 0
UNUSED_MEM_PINS_PINLOC_62 0
UNUSED_MEM_PINS_PINLOC_63 0
UNUSED_MEM_PINS_PINLOC_64 0
UNUSED_MEM_PINS_PINLOC_65 0
UNUSED_MEM_PINS_PINLOC_66 0
UNUSED_MEM_PINS_PINLOC_67 0
UNUSED_MEM_PINS_PINLOC_68 0
UNUSED_MEM_PINS_PINLOC_69 0
UNUSED_MEM_PINS_PINLOC_70 0
UNUSED_MEM_PINS_PINLOC_71 0
UNUSED_MEM_PINS_PINLOC_72 0
UNUSED_MEM_PINS_PINLOC_73 0
UNUSED_MEM_PINS_PINLOC_74 0
UNUSED_MEM_PINS_PINLOC_75 0
UNUSED_MEM_PINS_PINLOC_76 0
UNUSED_MEM_PINS_PINLOC_77 0
UNUSED_MEM_PINS_PINLOC_78 0
UNUSED_MEM_PINS_PINLOC_79 0
UNUSED_MEM_PINS_PINLOC_80 0
UNUSED_MEM_PINS_PINLOC_81 0
UNUSED_MEM_PINS_PINLOC_82 0
UNUSED_MEM_PINS_PINLOC_83 0
UNUSED_MEM_PINS_PINLOC_84 0
UNUSED_MEM_PINS_PINLOC_85 0
UNUSED_MEM_PINS_PINLOC_86 0
UNUSED_MEM_PINS_PINLOC_87 0
UNUSED_MEM_PINS_PINLOC_88 0
UNUSED_MEM_PINS_PINLOC_89 0
UNUSED_MEM_PINS_PINLOC_90 0
UNUSED_MEM_PINS_PINLOC_91 0
UNUSED_MEM_PINS_PINLOC_92 0
UNUSED_MEM_PINS_PINLOC_93 0
UNUSED_MEM_PINS_PINLOC_94 0
UNUSED_MEM_PINS_PINLOC_95 0
UNUSED_MEM_PINS_PINLOC_96 0
UNUSED_MEM_PINS_PINLOC_97 0
UNUSED_MEM_PINS_PINLOC_98 0
UNUSED_MEM_PINS_PINLOC_99 0
UNUSED_MEM_PINS_PINLOC_100 0
UNUSED_MEM_PINS_PINLOC_101 0
UNUSED_MEM_PINS_PINLOC_102 0
UNUSED_MEM_PINS_PINLOC_103 0
UNUSED_MEM_PINS_PINLOC_104 0
UNUSED_MEM_PINS_PINLOC_105 0
UNUSED_MEM_PINS_PINLOC_106 0
UNUSED_MEM_PINS_PINLOC_107 0
UNUSED_MEM_PINS_PINLOC_108 0
UNUSED_MEM_PINS_PINLOC_109 0
UNUSED_MEM_PINS_PINLOC_110 0
UNUSED_MEM_PINS_PINLOC_111 0
UNUSED_MEM_PINS_PINLOC_112 0
UNUSED_MEM_PINS_PINLOC_113 0
UNUSED_MEM_PINS_PINLOC_114 0
UNUSED_MEM_PINS_PINLOC_115 0
UNUSED_MEM_PINS_PINLOC_116 0
UNUSED_MEM_PINS_PINLOC_117 0
UNUSED_MEM_PINS_PINLOC_118 0
UNUSED_MEM_PINS_PINLOC_119 0
UNUSED_MEM_PINS_PINLOC_120 0
UNUSED_MEM_PINS_PINLOC_121 0
UNUSED_MEM_PINS_PINLOC_122 0
UNUSED_MEM_PINS_PINLOC_123 0
UNUSED_MEM_PINS_PINLOC_124 0
UNUSED_MEM_PINS_PINLOC_125 0
UNUSED_MEM_PINS_PINLOC_126 0
UNUSED_MEM_PINS_PINLOC_127 0
UNUSED_MEM_PINS_PINLOC_128 0
UNUSED_MEM_PINS_PINLOC_AUTOGEN_WCNT 129
UNUSED_DQS_BUSES_LANELOC_0 5249027
UNUSED_DQS_BUSES_LANELOC_1 4
UNUSED_DQS_BUSES_LANELOC_2 0
UNUSED_DQS_BUSES_LANELOC_3 0
UNUSED_DQS_BUSES_LANELOC_4 0
UNUSED_DQS_BUSES_LANELOC_5 0
UNUSED_DQS_BUSES_LANELOC_6 0
UNUSED_DQS_BUSES_LANELOC_7 0
UNUSED_DQS_BUSES_LANELOC_8 0
UNUSED_DQS_BUSES_LANELOC_9 0
UNUSED_DQS_BUSES_LANELOC_10 0
UNUSED_DQS_BUSES_LANELOC_AUTOGEN_WCNT 11
DBC_EXTRA_PIPE_STAGE_EN disable
DBC_PIPE_LATS_0 286335522
DBC_PIPE_LATS_1 34952
DBC_PIPE_LATS_2 0
DBC_PIPE_LATS_3 0
DBC_PIPE_LATS_4 0
DBC_PIPE_LATS_AUTOGEN_WCNT 5
DB_PTR_PIPELINE_DEPTHS_0 268435456
DB_PTR_PIPELINE_DEPTHS_1 0
DB_PTR_PIPELINE_DEPTHS_2 0
DB_PTR_PIPELINE_DEPTHS_3 0
DB_PTR_PIPELINE_DEPTHS_4 0
DB_PTR_PIPELINE_DEPTHS_AUTOGEN_WCNT 5
DB_SEQ_RD_EN_FULL_PIPELINES_0 572662306
DB_SEQ_RD_EN_FULL_PIPELINES_1 34952
DB_SEQ_RD_EN_FULL_PIPELINES_2 0
DB_SEQ_RD_EN_FULL_PIPELINES_3 0
DB_SEQ_RD_EN_FULL_PIPELINES_4 0
DB_SEQ_RD_EN_FULL_PIPELINES_AUTOGEN_WCNT 5
CENTER_TIDS_0 5249028
CENTER_TIDS_1 0
CENTER_TIDS_2 0
CENTER_TIDS_AUTOGEN_WCNT 3
HMC_TIDS_0 5511685
HMC_TIDS_1 0
HMC_TIDS_2 0
HMC_TIDS_AUTOGEN_WCNT 3
LANE_TIDS_0 403177984
LANE_TIDS_1 168067584
LANE_TIDS_2 35717208
LANE_TIDS_3 9746
LANE_TIDS_4 0
LANE_TIDS_5 0
LANE_TIDS_6 0
LANE_TIDS_7 0
LANE_TIDS_8 0
LANE_TIDS_9 0
LANE_TIDS_AUTOGEN_WCNT 10
PREAMBLE_MODE preamble_one_cycle
DBI_WR_ENABLE dbi_wr_dis
DBI_RD_ENABLE dbi_rd_ena
SWAP_DQS_A_B false
DQS_PACK_MODE packed
OCT_SIZE 3
DQSA_LGC_MODE dqs_diff_in_1_a
DQSB_LGC_MODE dqs_constant_b
DBC_WB_RESERVED_ENTRY 52
DLL_MODE dll_ctl_dynamic
DLL_CODEWORD 0
ABPHY_WRITE_PROTOCOL 0
PHY_USERMODE_OCT false
PHY_PERIODIC_OCT_RECAL false
GENERATE_PHYLITE false
HPRX_CTLE_EN on
HPRX_OFFSET_CAL true
CPA_FB_MUX_1_SEL local_p_clk
ENABLE_RD_TYPE false
AMM_C2P_UFI_MODE pin_ufi_use_in_direct_out_direct
AMM_P2C_UFI_MODE pin_ufi_use_in_direct_out_direct
MMR_C2P_UFI_MODE pin_ufi_use_in_direct_out_direct
MMR_P2C_UFI_MODE pin_ufi_use_in_direct_out_direct
SIDEBAND_C2P_UFI_MODE pin_ufi_use_in_direct_out_direct
SIDEBAND_P2C_UFI_MODE pin_ufi_use_in_direct_out_direct
SEQ_C2P_UFI_MODE pin_ufi_use_in_direct_out_direct
SEQ_P2C_UFI_MODE pin_ufi_use_in_direct_out_direct
ECC_C2P_UFI_MODE pin_ufi_use_in_direct_out_direct
ECC_P2C_UFI_MODE pin_ufi_use_in_direct_out_direct
LANE_C2P_UFI_MODE pin_ufi_use_in_direct_out_direct
LANE_P2C_UFI_MODE pin_ufi_use_in_direct_out_direct
AMM_HIPI_DELAY 350
MMR_HIPI_DELAY 350
SIDEBAND_HIPI_DELAY 350
SEQ_HIPI_DELAY 350
ECC_HIPI_DELAY 350
LANE_HIPI_DELAY 350
PRI_HMC_CFG_PING_PONG_MODE pingpong_off
PRI_HMC_CFG_CS_ADDR_WIDTH cs_width_0
PRI_HMC_CFG_COL_ADDR_WIDTH col_width_10
PRI_HMC_CFG_ROW_ADDR_WIDTH row_width_16
PRI_HMC_CFG_BANK_ADDR_WIDTH bank_width_2
PRI_HMC_CFG_BANK_GROUP_ADDR_WIDTH bank_group_width_2
PRI_HMC_CFG_ADDR_ORDER addr_order_cs_row_ba_col
PRI_HMC_CFG_ARBITER_TYPE arbiter_type_2t
PRI_HMC_CFG_OPEN_PAGE_EN disable
PRI_HMC_CFG_CTRL_ENABLE_RC enable
PRI_HMC_CFG_DBC0_ENABLE_RC enable
PRI_HMC_CFG_DBC1_ENABLE_RC enable
PRI_HMC_CFG_DBC2_ENABLE_RC enable
PRI_HMC_CFG_DBC3_ENABLE_RC enable
PRI_HMC_CFG_CTRL_ENABLE_ECC enable
PRI_HMC_CFG_DBC0_ENABLE_ECC enable
PRI_HMC_CFG_DBC1_ENABLE_ECC enable
PRI_HMC_CFG_DBC2_ENABLE_ECC enable
PRI_HMC_CFG_DBC3_ENABLE_ECC enable
PRI_HMC_CFG_REORDER_DATA enable
PRI_HMC_CFG_REORDER_READ disable
PRI_HMC_CFG_CTRL_REORDER_RDATA disable
PRI_HMC_CFG_DBC0_REORDER_RDATA disable
PRI_HMC_CFG_DBC1_REORDER_RDATA disable
PRI_HMC_CFG_DBC2_REORDER_RDATA disable
PRI_HMC_CFG_DBC3_REORDER_RDATA disable
PRI_HMC_CFG_CTRL_SLOT_OFFSET 2
PRI_HMC_CFG_DBC0_SLOT_OFFSET 2
PRI_HMC_CFG_DBC1_SLOT_OFFSET 2
PRI_HMC_CFG_DBC2_SLOT_OFFSET 2
PRI_HMC_CFG_DBC3_SLOT_OFFSET 2
PRI_HMC_CFG_CTRL_SLOT_ROTATE_EN ctrl_disable
PRI_HMC_CFG_DBC0_SLOT_ROTATE_EN dbc0_disable
PRI_HMC_CFG_DBC1_SLOT_ROTATE_EN dbc1_disable
PRI_HMC_CFG_DBC2_SLOT_ROTATE_EN dbc2_disable
PRI_HMC_CFG_DBC3_SLOT_ROTATE_EN dbc3_disable
PRI_HMC_CFG_COL_CMD_SLOT 2
PRI_HMC_CFG_ROW_CMD_SLOT 1
PRI_HMC_CFG_ROW_TO_COL_OFFSET -1
PRI_HMC_CFG_ROW_TO_ROW_OFFSET 0
PRI_HMC_CFG_COL_TO_COL_OFFSET 0
PRI_HMC_CFG_COL_TO_DIFF_COL_OFFSET 0
PRI_HMC_CFG_COL_TO_ROW_OFFSET 1
PRI_HMC_CFG_SIDEBAND_OFFSET 1
PRI_HMC_CFG_CS_TO_CHIP_MAPPING 33825
PRI_HMC_CFG_CTL_ODT_ENABLED 1
PRI_HMC_CFG_RD_ODT_ON 3
PRI_HMC_CFG_RD_ODT_PERIOD 7
PRI_HMC_CFG_READ_ODT_CHIP 0
PRI_HMC_CFG_WR_ODT_ON 0
PRI_HMC_CFG_WR_ODT_PERIOD 6
PRI_HMC_CFG_WRITE_ODT_CHIP 0
PRI_HMC_CFG_CMD_FIFO_RESERVE_EN enable
PRI_HMC_CFG_RB_RESERVED_ENTRY 8
PRI_HMC_CFG_WB_RESERVED_ENTRY 52
PRI_HMC_CFG_STARVE_LIMIT 10
PRI_HMC_CFG_PHY_DELAY_MISMATCH 0
PRI_HMC_CFG_DQSTRK_EN disable
PRI_HMC_CFG_DQSTRK_TO_VALID 4
PRI_HMC_CFG_DQSTRK_TO_VALID_LAST 28
PRI_HMC_CFG_CTL_SHORT_DQSTRK_EN 0
PRI_HMC_CFG_PERIOD_DQSTRK_CTRL_EN disable
PRI_HMC_CFG_PERIOD_DQSTRK_INTERVAL 0
PRI_HMC_CFG_SHORT_DQSTRK_CTRL_EN disable
PRI_HMC_CFG_ENABLE_FAST_EXIT_PPD 0
PRI_HMC_CFG_USER_RFSH_EN disable
PRI_HMC_CFG_GEAR_DOWN_EN disable
PRI_HMC_CFG_MEM_AUTO_PD_CYCLES 0
PRI_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC 16
PRI_HMC_MEMCLKGATE_SETTING 0
PRI_HMC_CFG_TCL 22
PRI_HMC_CFG_16_ACT_TO_ACT 0
PRI_HMC_CFG_4_ACT_TO_ACT 13
PRI_HMC_MEM_IF_AL 0
PRI_HMC_MEM_IF_CS_PER_DIMM 0
PRI_HMC_MEM_IF_RD_PREAMBLE 0
PRI_HMC_MEM_IF_TCCD 0
PRI_HMC_MEM_IF_TCCD_S 0
PRI_HMC_MEM_IF_TCKESR 0
PRI_HMC_MEM_IF_TCKSRX 0
PRI_HMC_MEM_IF_TCL 0
PRI_HMC_MEM_IF_TCWL 0
PRI_HMC_MEM_IF_TDQSCKMAX 0
PRI_HMC_MEM_IF_TFAW 0
PRI_HMC_MEM_IF_TMOD 0
PRI_HMC_MEM_IF_TPL 0
PRI_HMC_MEM_IF_TRAS 0
PRI_HMC_MEM_IF_TRC 0
PRI_HMC_MEM_IF_TRCD 0
PRI_HMC_MEM_IF_TREFI 0
PRI_HMC_MEM_IF_TRFC 0
PRI_HMC_MEM_IF_TRP 0
PRI_HMC_MEM_IF_TRRD 0
PRI_HMC_MEM_IF_TRRD_S 0
PRI_HMC_MEM_IF_TRTP 0
PRI_HMC_MEM_IF_TWR 0
PRI_HMC_MEM_IF_TWR_CRC_DM 0
PRI_HMC_MEM_IF_TWTR 0
PRI_HMC_MEM_IF_TWTR_L_CRC_DM 0
PRI_HMC_MEM_IF_TWTR_S 0
PRI_HMC_MEM_IF_TWTR_S_CRC_DM 0
PRI_HMC_MEM_IF_TXP 0
PRI_HMC_MEM_IF_TXPDLL 0
PRI_HMC_MEM_IF_TXSR 0
PRI_HMC_MEM_IF_TZQCS 0
PRI_HMC_MEM_IF_TZQOPER 0
PRI_HMC_MEM_IF_WR_CRC 0
PRI_HMC_MEM_IF_WR_PREAMBLE 0
PRI_HMC_CFG_ACT_TO_ACT 31
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BANK 4
PRI_HMC_CFG_ACT_TO_ACT_DIFF_BG 2
PRI_HMC_CFG_ACT_TO_PCH 22
PRI_HMC_CFG_ACT_TO_RDWR 9
PRI_HMC_CFG_ARF_PERIOD 5201
PRI_HMC_CFG_ARF_TO_VALID 234
PRI_HMC_CFG_MMR_CMD_TO_VALID 16
PRI_HMC_CFG_MPR_TO_VALID 16
PRI_HMC_CFG_MPS_DQSTRK_DISABLE disable
PRI_HMC_CFG_MPS_EXIT_CKE_TO_CS 6
PRI_HMC_CFG_MPS_EXIT_CS_TO_CKE 5
PRI_HMC_CFG_MPS_TO_VALID 768
PRI_HMC_CFG_MPS_ZQCAL_DISABLE disable
PRI_HMC_CFG_MRR_TO_VALID 0
PRI_HMC_CFG_MRS_TO_VALID 13
PRI_HMC_CFG_PCH_ALL_TO_VALID 10
PRI_HMC_CFG_PCH_TO_VALID 10
PRI_HMC_CFG_PDN_PERIOD 0
PRI_HMC_CFG_PDN_TO_VALID 5
PRI_HMC_CFG_POWER_SAVING_EXIT_CYC 3
PRI_HMC_CFG_RD_AP_TO_VALID 15
PRI_HMC_CFG_RD_TO_PCH 6
PRI_HMC_CFG_RD_TO_RD 4
PRI_HMC_CFG_RD_TO_RD_DIFF_BG 2
PRI_HMC_CFG_RD_TO_RD_DIFF_CHIP 4
PRI_HMC_CFG_RD_TO_WR 10
PRI_HMC_CFG_RD_TO_WR_DIFF_BG 10
PRI_HMC_CFG_RD_TO_WR_DIFF_CHIP 10
PRI_HMC_CFG_RFSH_WARN_THRESHOLD 0
PRI_HMC_CFG_RLD3_MULTIBANK_REF_DELAY 0
PRI_HMC_CFG_RLD3_REFRESH_SEQ0 0
PRI_HMC_CFG_RLD3_REFRESH_SEQ1 0
PRI_HMC_CFG_RLD3_REFRESH_SEQ2 0
PRI_HMC_CFG_RLD3_REFRESH_SEQ3 0
PRI_HMC_CFG_SB_CG_DISABLE disable
PRI_HMC_CFG_SB_DDR4_MR3 197632
PRI_HMC_CFG_SB_DDR4_MR4 264192
PRI_HMC_CFG_SB_DDR4_MR5 5216
PRI_HMC_CFG_DDR4_MPS_ADDRMIRROR disable
PRI_HMC_CFG_SRF_AUTOEXIT_EN disable
PRI_HMC_CFG_SRF_ENTRY_EXIT_BLOCK 0
PRI_HMC_CFG_SRF_TO_VALID 513
PRI_HMC_CFG_SRF_TO_ZQ_CAL 385
PRI_HMC_CFG_SRF_ZQCAL_DISABLE disable
PRI_HMC_TEMP_4_ACT_TO_ACT 0
PRI_HMC_TEMP_RD_TO_RD_DIFF_BG 0
PRI_HMC_TEMP_WR_TO_RD 0
PRI_HMC_TEMP_WR_TO_RD_DIFF_BG 0
PRI_HMC_TEMP_WR_TO_RD_DIFF_CHIP 0
PRI_HMC_TEMP_WR_TO_WR_DIFF_BG 0
PRI_HMC_CFG_WR_AP_TO_VALID 31
PRI_HMC_CFG_WR_TO_PCH 22
PRI_HMC_CFG_WR_TO_RD 20
PRI_HMC_CFG_WR_TO_RD_DIFF_BG 18
PRI_HMC_CFG_WR_TO_RD_DIFF_CHIP 17
PRI_HMC_CFG_WR_TO_WR 4
PRI_HMC_CFG_WR_TO_WR_DIFF_BG 2
PRI_HMC_CFG_WR_TO_WR_DIFF_CHIP 3
PRI_HMC_CFG_ZQCL_TO_VALID 257
PRI_HMC_CFG_ZQCS_TO_VALID 127
PRI_HMC_CHIP_ID 273
PRI_HMC_CID_ADDR_WIDTH 0
PRI_HMC_3DS_EN disable
PRI_HMC_3DS_LR_NUM0 0
PRI_HMC_3DS_LR_NUM1 0
PRI_HMC_3DS_LR_NUM2 0
PRI_HMC_3DS_LR_NUM3 0
PRI_HMC_3DS_PR_STAG_ENABLE disable
PRI_HMC_3DS_REF2REF_DLR 1
PRI_HMC_3DSREF_ACK_ON_DONE disable
PRI_HMC_CFG_MAJOR_MODE_EN disable
PRI_HMC_CFG_REFRESH_TYPE 0
PRI_HMC_CFG_PRE_REFRESH_EN disable
PRI_HMC_CFG_PRE_REFRESH_UPPER_LIMIT 1
PRI_HMC_CFG_POST_REFRESH_EN disable
PRI_HMC_CFG_POST_REFRESH_LOWER_LIMIT 0
PRI_HMC_CFG_POST_REFRESH_UPPER_LIMIT 2
SEC_HMC_CFG_PING_PONG_MODE pingpong_off
SEC_HMC_CFG_CS_ADDR_WIDTH cs_width_0
SEC_HMC_CFG_COL_ADDR_WIDTH col_width_10
SEC_HMC_CFG_ROW_ADDR_WIDTH row_width_16
SEC_HMC_CFG_BANK_ADDR_WIDTH bank_width_2
SEC_HMC_CFG_BANK_GROUP_ADDR_WIDTH bank_group_width_2
SEC_HMC_CFG_ADDR_ORDER addr_order_cs_row_ba_col
SEC_HMC_CFG_ARBITER_TYPE arbiter_type_2t
SEC_HMC_CFG_OPEN_PAGE_EN disable
SEC_HMC_CFG_CTRL_ENABLE_RC enable
SEC_HMC_CFG_DBC0_ENABLE_RC enable
SEC_HMC_CFG_DBC1_ENABLE_RC enable
SEC_HMC_CFG_DBC2_ENABLE_RC enable
SEC_HMC_CFG_DBC3_ENABLE_RC enable
SEC_HMC_CFG_CTRL_ENABLE_ECC enable
SEC_HMC_CFG_DBC0_ENABLE_ECC enable
SEC_HMC_CFG_DBC1_ENABLE_ECC enable
SEC_HMC_CFG_DBC2_ENABLE_ECC enable
SEC_HMC_CFG_DBC3_ENABLE_ECC enable
SEC_HMC_CFG_REORDER_DATA enable
SEC_HMC_CFG_REORDER_READ disable
SEC_HMC_CFG_CTRL_REORDER_RDATA disable
SEC_HMC_CFG_DBC0_REORDER_RDATA disable
SEC_HMC_CFG_DBC1_REORDER_RDATA disable
SEC_HMC_CFG_DBC2_REORDER_RDATA disable
SEC_HMC_CFG_DBC3_REORDER_RDATA disable
SEC_HMC_CFG_CTRL_SLOT_OFFSET 2
SEC_HMC_CFG_DBC0_SLOT_OFFSET 2
SEC_HMC_CFG_DBC1_SLOT_OFFSET 2
SEC_HMC_CFG_DBC2_SLOT_OFFSET 2
SEC_HMC_CFG_DBC3_SLOT_OFFSET 2
SEC_HMC_CFG_CTRL_SLOT_ROTATE_EN ctrl_disable
SEC_HMC_CFG_DBC0_SLOT_ROTATE_EN dbc0_disable
SEC_HMC_CFG_DBC1_SLOT_ROTATE_EN dbc1_disable
SEC_HMC_CFG_DBC2_SLOT_ROTATE_EN dbc2_disable
SEC_HMC_CFG_DBC3_SLOT_ROTATE_EN dbc3_disable
SEC_HMC_CFG_COL_CMD_SLOT 2
SEC_HMC_CFG_ROW_CMD_SLOT 1
SEC_HMC_CFG_ROW_TO_COL_OFFSET -1
SEC_HMC_CFG_ROW_TO_ROW_OFFSET 0
SEC_HMC_CFG_COL_TO_COL_OFFSET 0
SEC_HMC_CFG_COL_TO_DIFF_COL_OFFSET 0
SEC_HMC_CFG_COL_TO_ROW_OFFSET 1
SEC_HMC_CFG_SIDEBAND_OFFSET 1
SEC_HMC_CFG_CS_TO_CHIP_MAPPING 33825
SEC_HMC_CFG_CTL_ODT_ENABLED 1
SEC_HMC_CFG_RD_ODT_ON 3
SEC_HMC_CFG_RD_ODT_PERIOD 7
SEC_HMC_CFG_READ_ODT_CHIP 0
SEC_HMC_CFG_WR_ODT_ON 0
SEC_HMC_CFG_WR_ODT_PERIOD 6
SEC_HMC_CFG_WRITE_ODT_CHIP 0
SEC_HMC_CFG_CMD_FIFO_RESERVE_EN enable
SEC_HMC_CFG_RB_RESERVED_ENTRY 8
SEC_HMC_CFG_WB_RESERVED_ENTRY 52
SEC_HMC_CFG_STARVE_LIMIT 10
SEC_HMC_CFG_PHY_DELAY_MISMATCH 0
SEC_HMC_CFG_DQSTRK_EN disable
SEC_HMC_CFG_DQSTRK_TO_VALID 4
SEC_HMC_CFG_DQSTRK_TO_VALID_LAST 28
SEC_HMC_CFG_CTL_SHORT_DQSTRK_EN 0
SEC_HMC_CFG_PERIOD_DQSTRK_CTRL_EN disable
SEC_HMC_CFG_PERIOD_DQSTRK_INTERVAL 0
SEC_HMC_CFG_SHORT_DQSTRK_CTRL_EN disable
SEC_HMC_CFG_ENABLE_FAST_EXIT_PPD 0
SEC_HMC_CFG_USER_RFSH_EN disable
SEC_HMC_CFG_GEAR_DOWN_EN disable
SEC_HMC_CFG_MEM_AUTO_PD_CYCLES 0
SEC_HMC_CFG_MEM_CLK_DISABLE_ENTRY_CYC 16
SEC_HMC_MEMCLKGATE_SETTING 0
SEC_HMC_CFG_TCL 22
SEC_HMC_CFG_16_ACT_TO_ACT 0
SEC_HMC_CFG_4_ACT_TO_ACT 13
SEC_HMC_MEM_IF_AL 0
SEC_HMC_MEM_IF_CS_PER_DIMM 0
SEC_HMC_MEM_IF_RD_PREAMBLE 0
SEC_HMC_MEM_IF_TCCD 0
SEC_HMC_MEM_IF_TCCD_S 0
SEC_HMC_MEM_IF_TCKESR 0
SEC_HMC_MEM_IF_TCKSRX 0
SEC_HMC_MEM_IF_TCL 0
SEC_HMC_MEM_IF_TCWL 0
SEC_HMC_MEM_IF_TDQSCKMAX 0
SEC_HMC_MEM_IF_TFAW 0
SEC_HMC_MEM_IF_TMOD 0
SEC_HMC_MEM_IF_TPL 0
SEC_HMC_MEM_IF_TRAS 0
SEC_HMC_MEM_IF_TRC 0
SEC_HMC_MEM_IF_TRCD 0
SEC_HMC_MEM_IF_TREFI 0
SEC_HMC_MEM_IF_TRFC 0
SEC_HMC_MEM_IF_TRP 0
SEC_HMC_MEM_IF_TRRD 0
SEC_HMC_MEM_IF_TRRD_S 0
SEC_HMC_MEM_IF_TRTP 0
SEC_HMC_MEM_IF_TWR 0
SEC_HMC_MEM_IF_TWR_CRC_DM 0
SEC_HMC_MEM_IF_TWTR 0
SEC_HMC_MEM_IF_TWTR_L_CRC_DM 0
SEC_HMC_MEM_IF_TWTR_S 0
SEC_HMC_MEM_IF_TWTR_S_CRC_DM 0
SEC_HMC_MEM_IF_TXP 0
SEC_HMC_MEM_IF_TXPDLL 0
SEC_HMC_MEM_IF_TXSR 0
SEC_HMC_MEM_IF_TZQCS 0
SEC_HMC_MEM_IF_TZQOPER 0
SEC_HMC_MEM_IF_WR_CRC 0
SEC_HMC_MEM_IF_WR_PREAMBLE 0
SEC_HMC_CFG_ACT_TO_ACT 31
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BANK 4
SEC_HMC_CFG_ACT_TO_ACT_DIFF_BG 2
SEC_HMC_CFG_ACT_TO_PCH 22
SEC_HMC_CFG_ACT_TO_RDWR 9
SEC_HMC_CFG_ARF_PERIOD 5201
SEC_HMC_CFG_ARF_TO_VALID 234
SEC_HMC_CFG_MMR_CMD_TO_VALID 16
SEC_HMC_CFG_MPR_TO_VALID 16
SEC_HMC_CFG_MPS_DQSTRK_DISABLE disable
SEC_HMC_CFG_MPS_EXIT_CKE_TO_CS 6
SEC_HMC_CFG_MPS_EXIT_CS_TO_CKE 5
SEC_HMC_CFG_MPS_TO_VALID 768
SEC_HMC_CFG_MPS_ZQCAL_DISABLE disable
SEC_HMC_CFG_MRR_TO_VALID 0
SEC_HMC_CFG_MRS_TO_VALID 13
SEC_HMC_CFG_PCH_ALL_TO_VALID 10
SEC_HMC_CFG_PCH_TO_VALID 10
SEC_HMC_CFG_PDN_PERIOD 0
SEC_HMC_CFG_PDN_TO_VALID 5
SEC_HMC_CFG_POWER_SAVING_EXIT_CYC 3
SEC_HMC_CFG_RD_AP_TO_VALID 15
SEC_HMC_CFG_RD_TO_PCH 6
SEC_HMC_CFG_RD_TO_RD 4
SEC_HMC_CFG_RD_TO_RD_DIFF_BG 2
SEC_HMC_CFG_RD_TO_RD_DIFF_CHIP 4
SEC_HMC_CFG_RD_TO_WR 10
SEC_HMC_CFG_RD_TO_WR_DIFF_BG 10
SEC_HMC_CFG_RD_TO_WR_DIFF_CHIP 10
SEC_HMC_CFG_RFSH_WARN_THRESHOLD 0
SEC_HMC_CFG_RLD3_MULTIBANK_REF_DELAY 0
SEC_HMC_CFG_RLD3_REFRESH_SEQ0 0
SEC_HMC_CFG_RLD3_REFRESH_SEQ1 0
SEC_HMC_CFG_RLD3_REFRESH_SEQ2 0
SEC_HMC_CFG_RLD3_REFRESH_SEQ3 0
SEC_HMC_CFG_SB_CG_DISABLE disable
SEC_HMC_CFG_SB_DDR4_MR3 197632
SEC_HMC_CFG_SB_DDR4_MR4 264192
SEC_HMC_CFG_SB_DDR4_MR5 5216
SEC_HMC_CFG_DDR4_MPS_ADDRMIRROR disable
SEC_HMC_CFG_SRF_AUTOEXIT_EN disable
SEC_HMC_CFG_SRF_ENTRY_EXIT_BLOCK 0
SEC_HMC_CFG_SRF_TO_VALID 513
SEC_HMC_CFG_SRF_TO_ZQ_CAL 385
SEC_HMC_CFG_SRF_ZQCAL_DISABLE disable
SEC_HMC_TEMP_4_ACT_TO_ACT 0
SEC_HMC_TEMP_RD_TO_RD_DIFF_BG 0
SEC_HMC_TEMP_WR_TO_RD 0
SEC_HMC_TEMP_WR_TO_RD_DIFF_BG 0
SEC_HMC_TEMP_WR_TO_RD_DIFF_CHIP 0
SEC_HMC_TEMP_WR_TO_WR_DIFF_BG 0
SEC_HMC_CFG_WR_AP_TO_VALID 31
SEC_HMC_CFG_WR_TO_PCH 22
SEC_HMC_CFG_WR_TO_RD 20
SEC_HMC_CFG_WR_TO_RD_DIFF_BG 18
SEC_HMC_CFG_WR_TO_RD_DIFF_CHIP 17
SEC_HMC_CFG_WR_TO_WR 4
SEC_HMC_CFG_WR_TO_WR_DIFF_BG 2
SEC_HMC_CFG_WR_TO_WR_DIFF_CHIP 3
SEC_HMC_CFG_ZQCL_TO_VALID 257
SEC_HMC_CFG_ZQCS_TO_VALID 127
SEC_HMC_CHIP_ID 273
SEC_HMC_CID_ADDR_WIDTH 0
SEC_HMC_3DS_EN disable
SEC_HMC_3DS_LR_NUM0 0
SEC_HMC_3DS_LR_NUM1 0
SEC_HMC_3DS_LR_NUM2 0
SEC_HMC_3DS_LR_NUM3 0
SEC_HMC_3DS_PR_STAG_ENABLE disable
SEC_HMC_3DS_REF2REF_DLR 1
SEC_HMC_3DSREF_ACK_ON_DONE disable
SEC_HMC_CFG_MAJOR_MODE_EN disable
SEC_HMC_CFG_REFRESH_TYPE 0
SEC_HMC_CFG_PRE_REFRESH_EN disable
SEC_HMC_CFG_PRE_REFRESH_UPPER_LIMIT 1
SEC_HMC_CFG_POST_REFRESH_EN disable
SEC_HMC_CFG_POST_REFRESH_LOWER_LIMIT 0
SEC_HMC_CFG_POST_REFRESH_UPPER_LIMIT 2
PINS_PER_LANE 12
LANES_PER_TILE 4
OCT_CONTROL_WIDTH 16
PORT_MEM_CK_WIDTH 1
PORT_MEM_CK_PINLOC_0 57345
PORT_MEM_CK_PINLOC_1 0
PORT_MEM_CK_PINLOC_2 0
PORT_MEM_CK_PINLOC_3 0
PORT_MEM_CK_PINLOC_4 0
PORT_MEM_CK_PINLOC_5 0
PORT_MEM_CK_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CK_N_WIDTH 1
PORT_MEM_CK_N_PINLOC_0 58369
PORT_MEM_CK_N_PINLOC_1 0
PORT_MEM_CK_N_PINLOC_2 0
PORT_MEM_CK_N_PINLOC_3 0
PORT_MEM_CK_N_PINLOC_4 0
PORT_MEM_CK_N_PINLOC_5 0
PORT_MEM_CK_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CK_BIDIR_WIDTH 1
PORT_MEM_CK_BIDIR_PINLOC_0 0
PORT_MEM_CK_BIDIR_PINLOC_1 0
PORT_MEM_CK_BIDIR_PINLOC_2 0
PORT_MEM_CK_BIDIR_PINLOC_3 0
PORT_MEM_CK_BIDIR_PINLOC_4 0
PORT_MEM_CK_BIDIR_PINLOC_5 0
PORT_MEM_CK_BIDIR_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CK_BIDIR_N_WIDTH 1
PORT_MEM_CK_BIDIR_N_PINLOC_0 0
PORT_MEM_CK_BIDIR_N_PINLOC_1 0
PORT_MEM_CK_BIDIR_N_PINLOC_2 0
PORT_MEM_CK_BIDIR_N_PINLOC_3 0
PORT_MEM_CK_BIDIR_N_PINLOC_4 0
PORT_MEM_CK_BIDIR_N_PINLOC_5 0
PORT_MEM_CK_BIDIR_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DK_WIDTH 1
PORT_MEM_DK_PINLOC_0 0
PORT_MEM_DK_PINLOC_1 0
PORT_MEM_DK_PINLOC_2 0
PORT_MEM_DK_PINLOC_3 0
PORT_MEM_DK_PINLOC_4 0
PORT_MEM_DK_PINLOC_5 0
PORT_MEM_DK_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DK_N_WIDTH 1
PORT_MEM_DK_N_PINLOC_0 0
PORT_MEM_DK_N_PINLOC_1 0
PORT_MEM_DK_N_PINLOC_2 0
PORT_MEM_DK_N_PINLOC_3 0
PORT_MEM_DK_N_PINLOC_4 0
PORT_MEM_DK_N_PINLOC_5 0
PORT_MEM_DK_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKA_WIDTH 1
PORT_MEM_DKA_PINLOC_0 0
PORT_MEM_DKA_PINLOC_1 0
PORT_MEM_DKA_PINLOC_2 0
PORT_MEM_DKA_PINLOC_3 0
PORT_MEM_DKA_PINLOC_4 0
PORT_MEM_DKA_PINLOC_5 0
PORT_MEM_DKA_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKA_N_WIDTH 1
PORT_MEM_DKA_N_PINLOC_0 0
PORT_MEM_DKA_N_PINLOC_1 0
PORT_MEM_DKA_N_PINLOC_2 0
PORT_MEM_DKA_N_PINLOC_3 0
PORT_MEM_DKA_N_PINLOC_4 0
PORT_MEM_DKA_N_PINLOC_5 0
PORT_MEM_DKA_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKB_WIDTH 1
PORT_MEM_DKB_PINLOC_0 0
PORT_MEM_DKB_PINLOC_1 0
PORT_MEM_DKB_PINLOC_2 0
PORT_MEM_DKB_PINLOC_3 0
PORT_MEM_DKB_PINLOC_4 0
PORT_MEM_DKB_PINLOC_5 0
PORT_MEM_DKB_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_DKB_N_WIDTH 1
PORT_MEM_DKB_N_PINLOC_0 0
PORT_MEM_DKB_N_PINLOC_1 0
PORT_MEM_DKB_N_PINLOC_2 0
PORT_MEM_DKB_N_PINLOC_3 0
PORT_MEM_DKB_N_PINLOC_4 0
PORT_MEM_DKB_N_PINLOC_5 0
PORT_MEM_DKB_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_K_WIDTH 1
PORT_MEM_K_PINLOC_0 0
PORT_MEM_K_PINLOC_1 0
PORT_MEM_K_PINLOC_2 0
PORT_MEM_K_PINLOC_3 0
PORT_MEM_K_PINLOC_4 0
PORT_MEM_K_PINLOC_5 0
PORT_MEM_K_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_K_N_WIDTH 1
PORT_MEM_K_N_PINLOC_0 0
PORT_MEM_K_N_PINLOC_1 0
PORT_MEM_K_N_PINLOC_2 0
PORT_MEM_K_N_PINLOC_3 0
PORT_MEM_K_N_PINLOC_4 0
PORT_MEM_K_N_PINLOC_5 0
PORT_MEM_K_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_A_WIDTH 17
PORT_MEM_A_PINLOC_0 64024593
PORT_MEM_A_PINLOC_1 67173438
PORT_MEM_A_PINLOC_2 70322241
PORT_MEM_A_PINLOC_3 73471044
PORT_MEM_A_PINLOC_4 79768647
PORT_MEM_A_PINLOC_5 82917453
PORT_MEM_A_PINLOC_6 0
PORT_MEM_A_PINLOC_7 0
PORT_MEM_A_PINLOC_8 0
PORT_MEM_A_PINLOC_9 0
PORT_MEM_A_PINLOC_10 0
PORT_MEM_A_PINLOC_11 0
PORT_MEM_A_PINLOC_12 0
PORT_MEM_A_PINLOC_13 0
PORT_MEM_A_PINLOC_14 0
PORT_MEM_A_PINLOC_15 0
PORT_MEM_A_PINLOC_16 0
PORT_MEM_A_PINLOC_AUTOGEN_WCNT 17
PORT_MEM_BA_WIDTH 2
PORT_MEM_BA_PINLOC_0 86066178
PORT_MEM_BA_PINLOC_1 0
PORT_MEM_BA_PINLOC_2 0
PORT_MEM_BA_PINLOC_3 0
PORT_MEM_BA_PINLOC_4 0
PORT_MEM_BA_PINLOC_5 0
PORT_MEM_BA_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_BG_WIDTH 2
PORT_MEM_BG_PINLOC_0 50416642
PORT_MEM_BG_PINLOC_1 0
PORT_MEM_BG_PINLOC_2 0
PORT_MEM_BG_PINLOC_3 0
PORT_MEM_BG_PINLOC_4 0
PORT_MEM_BG_PINLOC_5 0
PORT_MEM_BG_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_C_WIDTH 1
PORT_MEM_C_PINLOC_0 0
PORT_MEM_C_PINLOC_1 0
PORT_MEM_C_PINLOC_2 0
PORT_MEM_C_PINLOC_3 0
PORT_MEM_C_PINLOC_4 0
PORT_MEM_C_PINLOC_5 0
PORT_MEM_C_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CKE_WIDTH 1
PORT_MEM_CKE_PINLOC_0 55297
PORT_MEM_CKE_PINLOC_1 0
PORT_MEM_CKE_PINLOC_2 0
PORT_MEM_CKE_PINLOC_3 0
PORT_MEM_CKE_PINLOC_4 0
PORT_MEM_CKE_PINLOC_5 0
PORT_MEM_CKE_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CS_N_WIDTH 1
PORT_MEM_CS_N_PINLOC_0 51201
PORT_MEM_CS_N_PINLOC_1 0
PORT_MEM_CS_N_PINLOC_2 0
PORT_MEM_CS_N_PINLOC_3 0
PORT_MEM_CS_N_PINLOC_4 0
PORT_MEM_CS_N_PINLOC_5 0
PORT_MEM_CS_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_RM_WIDTH 1
PORT_MEM_RM_PINLOC_0 0
PORT_MEM_RM_PINLOC_1 0
PORT_MEM_RM_PINLOC_2 0
PORT_MEM_RM_PINLOC_3 0
PORT_MEM_RM_PINLOC_4 0
PORT_MEM_RM_PINLOC_5 0
PORT_MEM_RM_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_ODT_WIDTH 1
PORT_MEM_ODT_PINLOC_0 53249
PORT_MEM_ODT_PINLOC_1 0
PORT_MEM_ODT_PINLOC_2 0
PORT_MEM_ODT_PINLOC_3 0
PORT_MEM_ODT_PINLOC_4 0
PORT_MEM_ODT_PINLOC_5 0
PORT_MEM_ODT_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_REQ_N_WIDTH 1
PORT_MEM_REQ_N_PINLOC_0 0
PORT_MEM_REQ_N_PINLOC_1 0
PORT_MEM_REQ_N_PINLOC_2 0
PORT_MEM_REQ_N_PINLOC_3 0
PORT_MEM_REQ_N_PINLOC_4 0
PORT_MEM_REQ_N_PINLOC_5 0
PORT_MEM_REQ_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_GNT_N_WIDTH 1
PORT_MEM_GNT_N_PINLOC_0 0
PORT_MEM_GNT_N_PINLOC_1 0
PORT_MEM_GNT_N_PINLOC_2 0
PORT_MEM_GNT_N_PINLOC_3 0
PORT_MEM_GNT_N_PINLOC_4 0
PORT_MEM_GNT_N_PINLOC_5 0
PORT_MEM_GNT_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_ERR_N_WIDTH 1
PORT_MEM_ERR_N_PINLOC_0 0
PORT_MEM_ERR_N_PINLOC_1 0
PORT_MEM_ERR_N_PINLOC_2 0
PORT_MEM_ERR_N_PINLOC_3 0
PORT_MEM_ERR_N_PINLOC_4 0
PORT_MEM_ERR_N_PINLOC_5 0
PORT_MEM_ERR_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_RAS_N_WIDTH 1
PORT_MEM_RAS_N_PINLOC_0 0
PORT_MEM_RAS_N_PINLOC_1 0
PORT_MEM_RAS_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_CAS_N_WIDTH 1
PORT_MEM_CAS_N_PINLOC_0 0
PORT_MEM_CAS_N_PINLOC_1 0
PORT_MEM_CAS_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_WE_N_WIDTH 1
PORT_MEM_WE_N_PINLOC_0 0
PORT_MEM_WE_N_PINLOC_1 0
PORT_MEM_WE_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_RESET_N_WIDTH 1
PORT_MEM_RESET_N_PINLOC_0 50177
PORT_MEM_RESET_N_PINLOC_1 0
PORT_MEM_RESET_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_ACT_N_WIDTH 1
PORT_MEM_ACT_N_PINLOC_0 52225
PORT_MEM_ACT_N_PINLOC_1 0
PORT_MEM_ACT_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_PAR_WIDTH 1
PORT_MEM_PAR_PINLOC_0 60417
PORT_MEM_PAR_PINLOC_1 0
PORT_MEM_PAR_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_CA_WIDTH 1
PORT_MEM_CA_PINLOC_0 0
PORT_MEM_CA_PINLOC_1 0
PORT_MEM_CA_PINLOC_2 0
PORT_MEM_CA_PINLOC_3 0
PORT_MEM_CA_PINLOC_4 0
PORT_MEM_CA_PINLOC_5 0
PORT_MEM_CA_PINLOC_6 0
PORT_MEM_CA_PINLOC_7 0
PORT_MEM_CA_PINLOC_8 0
PORT_MEM_CA_PINLOC_9 0
PORT_MEM_CA_PINLOC_10 0
PORT_MEM_CA_PINLOC_11 0
PORT_MEM_CA_PINLOC_12 0
PORT_MEM_CA_PINLOC_13 0
PORT_MEM_CA_PINLOC_14 0
PORT_MEM_CA_PINLOC_15 0
PORT_MEM_CA_PINLOC_16 0
PORT_MEM_CA_PINLOC_AUTOGEN_WCNT 17
PORT_MEM_REF_N_WIDTH 1
PORT_MEM_REF_N_PINLOC_0 0
PORT_MEM_REF_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_WPS_N_WIDTH 1
PORT_MEM_WPS_N_PINLOC_0 0
PORT_MEM_WPS_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_RPS_N_WIDTH 1
PORT_MEM_RPS_N_PINLOC_0 0
PORT_MEM_RPS_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_DOFF_N_WIDTH 1
PORT_MEM_DOFF_N_PINLOC_0 0
PORT_MEM_DOFF_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LDA_N_WIDTH 1
PORT_MEM_LDA_N_PINLOC_0 0
PORT_MEM_LDA_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LDB_N_WIDTH 1
PORT_MEM_LDB_N_PINLOC_0 0
PORT_MEM_LDB_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_RWA_N_WIDTH 1
PORT_MEM_RWA_N_PINLOC_0 0
PORT_MEM_RWA_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_RWB_N_WIDTH 1
PORT_MEM_RWB_N_PINLOC_0 0
PORT_MEM_RWB_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LBK0_N_WIDTH 1
PORT_MEM_LBK0_N_PINLOC_0 0
PORT_MEM_LBK0_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_LBK1_N_WIDTH 1
PORT_MEM_LBK1_N_PINLOC_0 0
PORT_MEM_LBK1_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_CFG_N_WIDTH 1
PORT_MEM_CFG_N_PINLOC_0 0
PORT_MEM_CFG_N_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_AP_WIDTH 1
PORT_MEM_AP_PINLOC_0 0
PORT_MEM_AP_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_AINV_WIDTH 1
PORT_MEM_AINV_PINLOC_0 0
PORT_MEM_AINV_PINLOC_AUTOGEN_WCNT 1
PORT_MEM_DM_WIDTH 1
PORT_MEM_DM_PINLOC_0 0
PORT_MEM_DM_PINLOC_1 0
PORT_MEM_DM_PINLOC_2 0
PORT_MEM_DM_PINLOC_3 0
PORT_MEM_DM_PINLOC_4 0
PORT_MEM_DM_PINLOC_5 0
PORT_MEM_DM_PINLOC_6 0
PORT_MEM_DM_PINLOC_7 0
PORT_MEM_DM_PINLOC_8 0
PORT_MEM_DM_PINLOC_9 0
PORT_MEM_DM_PINLOC_10 0
PORT_MEM_DM_PINLOC_11 0
PORT_MEM_DM_PINLOC_12 0
PORT_MEM_DM_PINLOC_AUTOGEN_WCNT 13
PORT_MEM_BWS_N_WIDTH 1
PORT_MEM_BWS_N_PINLOC_0 0
PORT_MEM_BWS_N_PINLOC_1 0
PORT_MEM_BWS_N_PINLOC_2 0
PORT_MEM_BWS_N_PINLOC_AUTOGEN_WCNT 3
PORT_MEM_D_WIDTH 1
PORT_MEM_D_PINLOC_0 0
PORT_MEM_D_PINLOC_1 0
PORT_MEM_D_PINLOC_2 0
PORT_MEM_D_PINLOC_3 0
PORT_MEM_D_PINLOC_4 0
PORT_MEM_D_PINLOC_5 0
PORT_MEM_D_PINLOC_6 0
PORT_MEM_D_PINLOC_7 0
PORT_MEM_D_PINLOC_8 0
PORT_MEM_D_PINLOC_9 0
PORT_MEM_D_PINLOC_10 0
PORT_MEM_D_PINLOC_11 0
PORT_MEM_D_PINLOC_12 0
PORT_MEM_D_PINLOC_13 0
PORT_MEM_D_PINLOC_14 0
PORT_MEM_D_PINLOC_15 0
PORT_MEM_D_PINLOC_16 0
PORT_MEM_D_PINLOC_17 0
PORT_MEM_D_PINLOC_18 0
PORT_MEM_D_PINLOC_19 0
PORT_MEM_D_PINLOC_20 0
PORT_MEM_D_PINLOC_21 0
PORT_MEM_D_PINLOC_22 0
PORT_MEM_D_PINLOC_23 0
PORT_MEM_D_PINLOC_24 0
PORT_MEM_D_PINLOC_25 0
PORT_MEM_D_PINLOC_26 0
PORT_MEM_D_PINLOC_27 0
PORT_MEM_D_PINLOC_28 0
PORT_MEM_D_PINLOC_29 0
PORT_MEM_D_PINLOC_30 0
PORT_MEM_D_PINLOC_31 0
PORT_MEM_D_PINLOC_32 0
PORT_MEM_D_PINLOC_33 0
PORT_MEM_D_PINLOC_34 0
PORT_MEM_D_PINLOC_35 0
PORT_MEM_D_PINLOC_36 0
PORT_MEM_D_PINLOC_37 0
PORT_MEM_D_PINLOC_38 0
PORT_MEM_D_PINLOC_39 0
PORT_MEM_D_PINLOC_40 0
PORT_MEM_D_PINLOC_41 0
PORT_MEM_D_PINLOC_42 0
PORT_MEM_D_PINLOC_43 0
PORT_MEM_D_PINLOC_44 0
PORT_MEM_D_PINLOC_45 0
PORT_MEM_D_PINLOC_46 0
PORT_MEM_D_PINLOC_47 0
PORT_MEM_D_PINLOC_48 0
PORT_MEM_D_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DQ_WIDTH 72
PORT_MEM_DQ_PINLOC_0 1048648
PORT_MEM_DQ_PINLOC_1 8391682
PORT_MEM_DQ_PINLOC_2 11544585
PORT_MEM_DQ_PINLOC_3 14693388
PORT_MEM_DQ_PINLOC_4 22040591
PORT_MEM_DQ_PINLOC_5 25189398
PORT_MEM_DQ_PINLOC_6 28338201
PORT_MEM_DQ_PINLOC_7 35685408
PORT_MEM_DQ_PINLOC_8 38834211
PORT_MEM_DQ_PINLOC_9 46177318
PORT_MEM_DQ_PINLOC_10 49330221
PORT_MEM_DQ_PINLOC_11 90264660
PORT_MEM_DQ_PINLOC_12 97611863
PORT_MEM_DQ_PINLOC_13 100760670
PORT_MEM_DQ_PINLOC_14 103909473
PORT_MEM_DQ_PINLOC_15 111256680
PORT_MEM_DQ_PINLOC_16 114405483
PORT_MEM_DQ_PINLOC_17 121748590
PORT_MEM_DQ_PINLOC_18 124901493
PORT_MEM_DQ_PINLOC_19 128050296
PORT_MEM_DQ_PINLOC_20 135397499
PORT_MEM_DQ_PINLOC_21 138546306
PORT_MEM_DQ_PINLOC_22 141695109
PORT_MEM_DQ_PINLOC_23 149042316
PORT_MEM_DQ_PINLOC_24 143
PORT_MEM_DQ_PINLOC_25 0
PORT_MEM_DQ_PINLOC_26 0
PORT_MEM_DQ_PINLOC_27 0
PORT_MEM_DQ_PINLOC_28 0
PORT_MEM_DQ_PINLOC_29 0
PORT_MEM_DQ_PINLOC_30 0
PORT_MEM_DQ_PINLOC_31 0
PORT_MEM_DQ_PINLOC_32 0
PORT_MEM_DQ_PINLOC_33 0
PORT_MEM_DQ_PINLOC_34 0
PORT_MEM_DQ_PINLOC_35 0
PORT_MEM_DQ_PINLOC_36 0
PORT_MEM_DQ_PINLOC_37 0
PORT_MEM_DQ_PINLOC_38 0
PORT_MEM_DQ_PINLOC_39 0
PORT_MEM_DQ_PINLOC_40 0
PORT_MEM_DQ_PINLOC_41 0
PORT_MEM_DQ_PINLOC_42 0
PORT_MEM_DQ_PINLOC_43 0
PORT_MEM_DQ_PINLOC_44 0
PORT_MEM_DQ_PINLOC_45 0
PORT_MEM_DQ_PINLOC_46 0
PORT_MEM_DQ_PINLOC_47 0
PORT_MEM_DQ_PINLOC_48 0
PORT_MEM_DQ_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DBI_N_WIDTH 9
PORT_MEM_DBI_N_PINLOC_0 18880521
PORT_MEM_DBI_N_PINLOC_1 94414878
PORT_MEM_DBI_N_PINLOC_2 132237414
PORT_MEM_DBI_N_PINLOC_3 138
PORT_MEM_DBI_N_PINLOC_4 0
PORT_MEM_DBI_N_PINLOC_5 0
PORT_MEM_DBI_N_PINLOC_6 0
PORT_MEM_DBI_N_PINLOC_AUTOGEN_WCNT 7
PORT_MEM_DQA_WIDTH 1
PORT_MEM_DQA_PINLOC_0 0
PORT_MEM_DQA_PINLOC_1 0
PORT_MEM_DQA_PINLOC_2 0
PORT_MEM_DQA_PINLOC_3 0
PORT_MEM_DQA_PINLOC_4 0
PORT_MEM_DQA_PINLOC_5 0
PORT_MEM_DQA_PINLOC_6 0
PORT_MEM_DQA_PINLOC_7 0
PORT_MEM_DQA_PINLOC_8 0
PORT_MEM_DQA_PINLOC_9 0
PORT_MEM_DQA_PINLOC_10 0
PORT_MEM_DQA_PINLOC_11 0
PORT_MEM_DQA_PINLOC_12 0
PORT_MEM_DQA_PINLOC_13 0
PORT_MEM_DQA_PINLOC_14 0
PORT_MEM_DQA_PINLOC_15 0
PORT_MEM_DQA_PINLOC_16 0
PORT_MEM_DQA_PINLOC_17 0
PORT_MEM_DQA_PINLOC_18 0
PORT_MEM_DQA_PINLOC_19 0
PORT_MEM_DQA_PINLOC_20 0
PORT_MEM_DQA_PINLOC_21 0
PORT_MEM_DQA_PINLOC_22 0
PORT_MEM_DQA_PINLOC_23 0
PORT_MEM_DQA_PINLOC_24 0
PORT_MEM_DQA_PINLOC_25 0
PORT_MEM_DQA_PINLOC_26 0
PORT_MEM_DQA_PINLOC_27 0
PORT_MEM_DQA_PINLOC_28 0
PORT_MEM_DQA_PINLOC_29 0
PORT_MEM_DQA_PINLOC_30 0
PORT_MEM_DQA_PINLOC_31 0
PORT_MEM_DQA_PINLOC_32 0
PORT_MEM_DQA_PINLOC_33 0
PORT_MEM_DQA_PINLOC_34 0
PORT_MEM_DQA_PINLOC_35 0
PORT_MEM_DQA_PINLOC_36 0
PORT_MEM_DQA_PINLOC_37 0
PORT_MEM_DQA_PINLOC_38 0
PORT_MEM_DQA_PINLOC_39 0
PORT_MEM_DQA_PINLOC_40 0
PORT_MEM_DQA_PINLOC_41 0
PORT_MEM_DQA_PINLOC_42 0
PORT_MEM_DQA_PINLOC_43 0
PORT_MEM_DQA_PINLOC_44 0
PORT_MEM_DQA_PINLOC_45 0
PORT_MEM_DQA_PINLOC_46 0
PORT_MEM_DQA_PINLOC_47 0
PORT_MEM_DQA_PINLOC_48 0
PORT_MEM_DQA_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DQB_WIDTH 1
PORT_MEM_DQB_PINLOC_0 0
PORT_MEM_DQB_PINLOC_1 0
PORT_MEM_DQB_PINLOC_2 0
PORT_MEM_DQB_PINLOC_3 0
PORT_MEM_DQB_PINLOC_4 0
PORT_MEM_DQB_PINLOC_5 0
PORT_MEM_DQB_PINLOC_6 0
PORT_MEM_DQB_PINLOC_7 0
PORT_MEM_DQB_PINLOC_8 0
PORT_MEM_DQB_PINLOC_9 0
PORT_MEM_DQB_PINLOC_10 0
PORT_MEM_DQB_PINLOC_11 0
PORT_MEM_DQB_PINLOC_12 0
PORT_MEM_DQB_PINLOC_13 0
PORT_MEM_DQB_PINLOC_14 0
PORT_MEM_DQB_PINLOC_15 0
PORT_MEM_DQB_PINLOC_16 0
PORT_MEM_DQB_PINLOC_17 0
PORT_MEM_DQB_PINLOC_18 0
PORT_MEM_DQB_PINLOC_19 0
PORT_MEM_DQB_PINLOC_20 0
PORT_MEM_DQB_PINLOC_21 0
PORT_MEM_DQB_PINLOC_22 0
PORT_MEM_DQB_PINLOC_23 0
PORT_MEM_DQB_PINLOC_24 0
PORT_MEM_DQB_PINLOC_25 0
PORT_MEM_DQB_PINLOC_26 0
PORT_MEM_DQB_PINLOC_27 0
PORT_MEM_DQB_PINLOC_28 0
PORT_MEM_DQB_PINLOC_29 0
PORT_MEM_DQB_PINLOC_30 0
PORT_MEM_DQB_PINLOC_31 0
PORT_MEM_DQB_PINLOC_32 0
PORT_MEM_DQB_PINLOC_33 0
PORT_MEM_DQB_PINLOC_34 0
PORT_MEM_DQB_PINLOC_35 0
PORT_MEM_DQB_PINLOC_36 0
PORT_MEM_DQB_PINLOC_37 0
PORT_MEM_DQB_PINLOC_38 0
PORT_MEM_DQB_PINLOC_39 0
PORT_MEM_DQB_PINLOC_40 0
PORT_MEM_DQB_PINLOC_41 0
PORT_MEM_DQB_PINLOC_42 0
PORT_MEM_DQB_PINLOC_43 0
PORT_MEM_DQB_PINLOC_44 0
PORT_MEM_DQB_PINLOC_45 0
PORT_MEM_DQB_PINLOC_46 0
PORT_MEM_DQB_PINLOC_47 0
PORT_MEM_DQB_PINLOC_48 0
PORT_MEM_DQB_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DINVA_WIDTH 1
PORT_MEM_DINVA_PINLOC_0 0
PORT_MEM_DINVA_PINLOC_1 0
PORT_MEM_DINVA_PINLOC_2 0
PORT_MEM_DINVA_PINLOC_AUTOGEN_WCNT 3
PORT_MEM_DINVB_WIDTH 1
PORT_MEM_DINVB_PINLOC_0 0
PORT_MEM_DINVB_PINLOC_1 0
PORT_MEM_DINVB_PINLOC_2 0
PORT_MEM_DINVB_PINLOC_AUTOGEN_WCNT 3
PORT_MEM_Q_WIDTH 1
PORT_MEM_Q_PINLOC_0 0
PORT_MEM_Q_PINLOC_1 0
PORT_MEM_Q_PINLOC_2 0
PORT_MEM_Q_PINLOC_3 0
PORT_MEM_Q_PINLOC_4 0
PORT_MEM_Q_PINLOC_5 0
PORT_MEM_Q_PINLOC_6 0
PORT_MEM_Q_PINLOC_7 0
PORT_MEM_Q_PINLOC_8 0
PORT_MEM_Q_PINLOC_9 0
PORT_MEM_Q_PINLOC_10 0
PORT_MEM_Q_PINLOC_11 0
PORT_MEM_Q_PINLOC_12 0
PORT_MEM_Q_PINLOC_13 0
PORT_MEM_Q_PINLOC_14 0
PORT_MEM_Q_PINLOC_15 0
PORT_MEM_Q_PINLOC_16 0
PORT_MEM_Q_PINLOC_17 0
PORT_MEM_Q_PINLOC_18 0
PORT_MEM_Q_PINLOC_19 0
PORT_MEM_Q_PINLOC_20 0
PORT_MEM_Q_PINLOC_21 0
PORT_MEM_Q_PINLOC_22 0
PORT_MEM_Q_PINLOC_23 0
PORT_MEM_Q_PINLOC_24 0
PORT_MEM_Q_PINLOC_25 0
PORT_MEM_Q_PINLOC_26 0
PORT_MEM_Q_PINLOC_27 0
PORT_MEM_Q_PINLOC_28 0
PORT_MEM_Q_PINLOC_29 0
PORT_MEM_Q_PINLOC_30 0
PORT_MEM_Q_PINLOC_31 0
PORT_MEM_Q_PINLOC_32 0
PORT_MEM_Q_PINLOC_33 0
PORT_MEM_Q_PINLOC_34 0
PORT_MEM_Q_PINLOC_35 0
PORT_MEM_Q_PINLOC_36 0
PORT_MEM_Q_PINLOC_37 0
PORT_MEM_Q_PINLOC_38 0
PORT_MEM_Q_PINLOC_39 0
PORT_MEM_Q_PINLOC_40 0
PORT_MEM_Q_PINLOC_41 0
PORT_MEM_Q_PINLOC_42 0
PORT_MEM_Q_PINLOC_43 0
PORT_MEM_Q_PINLOC_44 0
PORT_MEM_Q_PINLOC_45 0
PORT_MEM_Q_PINLOC_46 0
PORT_MEM_Q_PINLOC_47 0
PORT_MEM_Q_PINLOC_48 0
PORT_MEM_Q_PINLOC_AUTOGEN_WCNT 49
PORT_MEM_DQS_WIDTH 9
PORT_MEM_DQS_PINLOC_0 16781321
PORT_MEM_DQS_PINLOC_1 92315676
PORT_MEM_DQS_PINLOC_2 130138212
PORT_MEM_DQS_PINLOC_3 136
PORT_MEM_DQS_PINLOC_4 0
PORT_MEM_DQS_PINLOC_5 0
PORT_MEM_DQS_PINLOC_6 0
PORT_MEM_DQS_PINLOC_7 0
PORT_MEM_DQS_PINLOC_8 0
PORT_MEM_DQS_PINLOC_9 0
PORT_MEM_DQS_PINLOC_10 0
PORT_MEM_DQS_PINLOC_11 0
PORT_MEM_DQS_PINLOC_12 0
PORT_MEM_DQS_PINLOC_AUTOGEN_WCNT 13
PORT_MEM_DQS_N_WIDTH 9
PORT_MEM_DQS_N_PINLOC_0 17830921
PORT_MEM_DQS_N_PINLOC_1 93365277
PORT_MEM_DQS_N_PINLOC_2 131187813
PORT_MEM_DQS_N_PINLOC_3 137
PORT_MEM_DQS_N_PINLOC_4 0
PORT_MEM_DQS_N_PINLOC_5 0
PORT_MEM_DQS_N_PINLOC_6 0
PORT_MEM_DQS_N_PINLOC_7 0
PORT_MEM_DQS_N_PINLOC_8 0
PORT_MEM_DQS_N_PINLOC_9 0
PORT_MEM_DQS_N_PINLOC_10 0
PORT_MEM_DQS_N_PINLOC_11 0
PORT_MEM_DQS_N_PINLOC_12 0
PORT_MEM_DQS_N_PINLOC_AUTOGEN_WCNT 13
PORT_MEM_QK_WIDTH 1
PORT_MEM_QK_PINLOC_0 0
PORT_MEM_QK_PINLOC_1 0
PORT_MEM_QK_PINLOC_2 0
PORT_MEM_QK_PINLOC_3 0
PORT_MEM_QK_PINLOC_4 0
PORT_MEM_QK_PINLOC_5 0
PORT_MEM_QK_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QK_N_WIDTH 1
PORT_MEM_QK_N_PINLOC_0 0
PORT_MEM_QK_N_PINLOC_1 0
PORT_MEM_QK_N_PINLOC_2 0
PORT_MEM_QK_N_PINLOC_3 0
PORT_MEM_QK_N_PINLOC_4 0
PORT_MEM_QK_N_PINLOC_5 0
PORT_MEM_QK_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKA_WIDTH 1
PORT_MEM_QKA_PINLOC_0 0
PORT_MEM_QKA_PINLOC_1 0
PORT_MEM_QKA_PINLOC_2 0
PORT_MEM_QKA_PINLOC_3 0
PORT_MEM_QKA_PINLOC_4 0
PORT_MEM_QKA_PINLOC_5 0
PORT_MEM_QKA_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKA_N_WIDTH 1
PORT_MEM_QKA_N_PINLOC_0 0
PORT_MEM_QKA_N_PINLOC_1 0
PORT_MEM_QKA_N_PINLOC_2 0
PORT_MEM_QKA_N_PINLOC_3 0
PORT_MEM_QKA_N_PINLOC_4 0
PORT_MEM_QKA_N_PINLOC_5 0
PORT_MEM_QKA_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKB_WIDTH 1
PORT_MEM_QKB_PINLOC_0 0
PORT_MEM_QKB_PINLOC_1 0
PORT_MEM_QKB_PINLOC_2 0
PORT_MEM_QKB_PINLOC_3 0
PORT_MEM_QKB_PINLOC_4 0
PORT_MEM_QKB_PINLOC_5 0
PORT_MEM_QKB_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_QKB_N_WIDTH 1
PORT_MEM_QKB_N_PINLOC_0 0
PORT_MEM_QKB_N_PINLOC_1 0
PORT_MEM_QKB_N_PINLOC_2 0
PORT_MEM_QKB_N_PINLOC_3 0
PORT_MEM_QKB_N_PINLOC_4 0
PORT_MEM_QKB_N_PINLOC_5 0
PORT_MEM_QKB_N_PINLOC_AUTOGEN_WCNT 6
PORT_MEM_CQ_WIDTH 1
PORT_MEM_CQ_PINLOC_0 0
PORT_MEM_CQ_PINLOC_1 0
PORT_MEM_CQ_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_CQ_N_WIDTH 1
PORT_MEM_CQ_N_PINLOC_0 0
PORT_MEM_CQ_N_PINLOC_1 0
PORT_MEM_CQ_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_ALERT_N_WIDTH 1
PORT_MEM_ALERT_N_PINLOC_0 81921
PORT_MEM_ALERT_N_PINLOC_1 0
PORT_MEM_ALERT_N_PINLOC_AUTOGEN_WCNT 2
PORT_MEM_PE_N_WIDTH 1
PORT_MEM_PE_N_PINLOC_0 0
PORT_MEM_PE_N_PINLOC_1 0
PORT_MEM_PE_N_PINLOC_AUTOGEN_WCNT 2
PORT_CLKS_SHARING_MASTER_OUT_WIDTH 32
PORT_CLKS_SHARING_SLAVE_IN_WIDTH 32
PORT_CLKS_SHARING_SLAVE_OUT_WIDTH 32
PORT_AFI_RLAT_WIDTH 6
PORT_AFI_WLAT_WIDTH 6
PORT_AFI_SEQ_BUSY_WIDTH 4
PORT_AFI_ADDR_WIDTH 1
PORT_AFI_BA_WIDTH 1
PORT_AFI_BG_WIDTH 1
PORT_AFI_C_WIDTH 1
PORT_AFI_CKE_WIDTH 1
PORT_AFI_CS_N_WIDTH 1
PORT_AFI_RM_WIDTH 1
PORT_AFI_ODT_WIDTH 1
PORT_AFI_RAS_N_WIDTH 1
PORT_AFI_CAS_N_WIDTH 1
PORT_AFI_WE_N_WIDTH 1
PORT_AFI_RST_N_WIDTH 1
PORT_AFI_ACT_N_WIDTH 1
PORT_AFI_REQ_N_WIDTH 1
PORT_AFI_GNT_N_WIDTH 1
PORT_AFI_ERR_N_WIDTH 1
PORT_AFI_PAR_WIDTH 1
PORT_AFI_CA_WIDTH 1
PORT_AFI_REF_N_WIDTH 1
PORT_AFI_WPS_N_WIDTH 1
PORT_AFI_RPS_N_WIDTH 1
PORT_AFI_DOFF_N_WIDTH 1
PORT_AFI_LD_N_WIDTH 1
PORT_AFI_RW_N_WIDTH 1
PORT_AFI_LBK0_N_WIDTH 1
PORT_AFI_LBK1_N_WIDTH 1
PORT_AFI_CFG_N_WIDTH 1
PORT_AFI_AP_WIDTH 1
PORT_AFI_AINV_WIDTH 1
PORT_AFI_DM_WIDTH 1
PORT_AFI_DM_N_WIDTH 1
PORT_AFI_BWS_N_WIDTH 1
PORT_AFI_RDATA_DBI_N_WIDTH 1
PORT_AFI_WDATA_DBI_N_WIDTH 1
PORT_AFI_RDATA_DINV_WIDTH 1
PORT_AFI_WDATA_DINV_WIDTH 1
PORT_AFI_DQS_BURST_WIDTH 1
PORT_AFI_WDATA_VALID_WIDTH 1
PORT_AFI_WDATA_WIDTH 1
PORT_AFI_RDATA_EN_FULL_WIDTH 1
PORT_AFI_RDATA_WIDTH 1
PORT_AFI_RDATA_VALID_WIDTH 1
PORT_AFI_RRANK_WIDTH 1
PORT_AFI_WRANK_WIDTH 1
PORT_AFI_ALERT_N_WIDTH 1
PORT_AFI_PE_N_WIDTH 1
PORT_CTRL_AST_CMD_DATA_WIDTH 61
PORT_CTRL_AST_WR_DATA_WIDTH 648
PORT_CTRL_AST_RD_DATA_WIDTH 576
PORT_CTRL_AMM_ADDRESS_WIDTH 1
PORT_CTRL_AMM_RDATA_WIDTH 1
PORT_CTRL_AMM_WDATA_WIDTH 1
PORT_CTRL_AMM_BCOUNT_WIDTH 1
PORT_CTRL_AMM_BYTEEN_WIDTH 1
PORT_CTRL_STROBE_WIDTH 1
PORT_CTRL_STROBE_OE_WIDTH 1
PORT_CTRL_DATA_OE_WIDTH 1
PORT_CTRL_DATA_OUT_WIDTH 1
PORT_CTRL_DATA_IN_WIDTH 1
PORT_CTRL_RDATA_VALID_WIDTH 1
PORT_CTRL_LOCKED_WIDTH 1
PORT_CTRL_RDATA_ENABLE_WIDTH 1
PORT_CTRL_USER_REFRESH_REQ_WIDTH 4
PORT_CTRL_USER_REFRESH_BANK_WIDTH 16
PORT_CTRL_SELF_REFRESH_REQ_WIDTH 4
PORT_CTRL_ECC_WRITE_INFO_WIDTH 15
PORT_CTRL_ECC_RDATA_ID_WIDTH 13
PORT_CTRL_ECC_READ_INFO_WIDTH 3
PORT_CTRL_ECC_CMD_INFO_WIDTH 3
PORT_CTRL_ECC_WB_POINTER_WIDTH 12
PORT_CTRL_MMR_SLAVE_ADDRESS_WIDTH 10
PORT_CTRL_MMR_SLAVE_RDATA_WIDTH 32
PORT_CTRL_MMR_SLAVE_WDATA_WIDTH 32
PORT_CTRL_MMR_SLAVE_BCOUNT_WIDTH 2
PORT_HPS_EMIF_H2E_WIDTH 4096
PORT_HPS_EMIF_E2H_WIDTH 4096
PORT_HPS_EMIF_H2E_GP_WIDTH 2
PORT_HPS_EMIF_E2H_GP_WIDTH 1
PORT_DFT_ND_PA_DPRIO_REG_ADDR_WIDTH 9
PORT_DFT_ND_PA_DPRIO_WRITEDATA_WIDTH 8
PORT_DFT_ND_PA_DPRIO_READDATA_WIDTH 8
PORT_DFT_ND_PLL_CNTSEL_WIDTH 4
PORT_DFT_ND_PLL_NUM_SHIFT_WIDTH 3
PORT_DFT_ND_PLL_CORE_REFCLK_WIDTH 4
PORT_DFT_ND_CORE_CLK_BUF_OUT_WIDTH 2
PORT_DFT_ND_CORE_CLK_LOCKED_WIDTH 2
PORT_CALBUS_ADDRESS_WIDTH 20
PORT_CALBUS_WDATA_WIDTH 32
PORT_CALBUS_RDATA_WIDTH 32
PORT_CALBUS_SEQ_PARAM_TBL_WIDTH 4096
PLL_VCO_FREQ_MHZ_INT 1333
PLL_VCO_TO_MEM_CLK_FREQ_RATIO 1
PLL_MEM_CLK_FREQ_PS 750
PLL_PHY_CLK_VCO_PHASE 0
PLL_VCO_FREQ_PS_STR 750 ps
PLL_VCO_FREQ_MHZ_STR 1333 MHz
PLL_REF_CLK_FREQ_PS_STR 30000 ps
PLL_REF_CLK_FREQ_MHZ_STR 33.333 MHz
PLL_REF_CLK_FREQ_PS 30000
PLL_SIM_VCO_FREQ_PS 752
PLL_SIM_PHYCLK_0_FREQ_PS 1504
PLL_SIM_PHYCLK_1_FREQ_PS 3008
PLL_SIM_PHYCLK_FB_FREQ_PS 3008
PLL_SIM_PHY_CLK_VCO_PHASE_PS 0
PLL_M_CNT_HIGH 20
PLL_M_CNT_LOW 20
PLL_N_CNT_HIGH 256
PLL_N_CNT_LOW 256
PLL_M_CNT_BYPASS_EN false
PLL_N_CNT_BYPASS_EN true
PLL_M_CNT_EVEN_DUTY_EN false
PLL_N_CNT_EVEN_DUTY_EN false
PLL_FBCLK_MUX_1 pll_fbclk_mux_1_glb
PLL_FBCLK_MUX_2 pll_fbclk_mux_2_m_cnt
PLL_M_CNT_IN_SRC c_m_cnt_in_src_ph_mux_clk
PLL_CP_SETTING pll_cp_setting12
PLL_BW_CTRL pll_bw_res_setting4
PLL_BW_SEL high
PLL_C_CNT_HIGH_0 2
PLL_C_CNT_LOW_0 2
PLL_C_CNT_PRST_0 1
PLL_C_CNT_PH_MUX_PRST_0 0
PLL_C_CNT_BYPASS_EN_0 false
PLL_C_CNT_EVEN_DUTY_EN_0 false
PLL_C_CNT_FREQ_PS_STR_0 3000 ps
PLL_C_CNT_FREQ_MHZ_STR_0 333.33325 MHz
PLL_C_CNT_PHASE_PS_STR_0 0 ps
PLL_C_CNT_DUTY_CYCLE_0 50
PLL_C_CNT_OUT_EN_0 true
PLL_C_CNT_HIGH_1 1
PLL_C_CNT_LOW_1 1
PLL_C_CNT_PRST_1 1
PLL_C_CNT_PH_MUX_PRST_1 0
PLL_C_CNT_BYPASS_EN_1 false
PLL_C_CNT_EVEN_DUTY_EN_1 false
PLL_C_CNT_FREQ_PS_STR_1 1500 ps
PLL_C_CNT_FREQ_MHZ_STR_1 666.6665 MHz
PLL_C_CNT_PHASE_PS_STR_1 0 ps
PLL_C_CNT_DUTY_CYCLE_1 50
PLL_C_CNT_OUT_EN_1 true
PLL_C_CNT_HIGH_2 2
PLL_C_CNT_LOW_2 2
PLL_C_CNT_PRST_2 1
PLL_C_CNT_PH_MUX_PRST_2 0
PLL_C_CNT_BYPASS_EN_2 false
PLL_C_CNT_EVEN_DUTY_EN_2 false
PLL_C_CNT_FREQ_PS_STR_2 3000 ps
PLL_C_CNT_FREQ_MHZ_STR_2 333.33325 MHz
PLL_C_CNT_PHASE_PS_STR_2 0 ps
PLL_C_CNT_DUTY_CYCLE_2 50
PLL_C_CNT_OUT_EN_2 true
PLL_C_CNT_HIGH_3 1
PLL_C_CNT_LOW_3 1
PLL_C_CNT_PRST_3 1
PLL_C_CNT_PH_MUX_PRST_3 0
PLL_C_CNT_BYPASS_EN_3 false
PLL_C_CNT_EVEN_DUTY_EN_3 false
PLL_C_CNT_FREQ_PS_STR_3 1500 ps
PLL_C_CNT_FREQ_MHZ_STR_3 666.6665 MHz
PLL_C_CNT_PHASE_PS_STR_3 0 ps
PLL_C_CNT_DUTY_CYCLE_3 50
PLL_C_CNT_OUT_EN_3 true
PLL_C_CNT_HIGH_4 2
PLL_C_CNT_LOW_4 2
PLL_C_CNT_PRST_4 1
PLL_C_CNT_PH_MUX_PRST_4 0
PLL_C_CNT_BYPASS_EN_4 false
PLL_C_CNT_EVEN_DUTY_EN_4 false
PLL_C_CNT_FREQ_PS_STR_4 3000 ps
PLL_C_CNT_FREQ_MHZ_STR_4 333.33325 MHz
PLL_C_CNT_PHASE_PS_STR_4 0 ps
PLL_C_CNT_DUTY_CYCLE_4 50
PLL_C_CNT_OUT_EN_4 true
PLL_C_CNT_HIGH_5 256
PLL_C_CNT_LOW_5 256
PLL_C_CNT_PRST_5 1
PLL_C_CNT_PH_MUX_PRST_5 0
PLL_C_CNT_BYPASS_EN_5 true
PLL_C_CNT_EVEN_DUTY_EN_5 false
PLL_C_CNT_FREQ_PS_STR_5 0 ps
PLL_C_CNT_FREQ_MHZ_STR_5 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_5 0 ps
PLL_C_CNT_DUTY_CYCLE_5 50
PLL_C_CNT_OUT_EN_5 false
PLL_C_CNT_HIGH_6 256
PLL_C_CNT_LOW_6 256
PLL_C_CNT_PRST_6 1
PLL_C_CNT_PH_MUX_PRST_6 0
PLL_C_CNT_BYPASS_EN_6 true
PLL_C_CNT_EVEN_DUTY_EN_6 false
PLL_C_CNT_FREQ_PS_STR_6 0 ps
PLL_C_CNT_FREQ_MHZ_STR_6 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_6 0 ps
PLL_C_CNT_DUTY_CYCLE_6 50
PLL_C_CNT_OUT_EN_6 false
PLL_C_CNT_HIGH_7 256
PLL_C_CNT_LOW_7 256
PLL_C_CNT_PRST_7 1
PLL_C_CNT_PH_MUX_PRST_7 0
PLL_C_CNT_BYPASS_EN_7 true
PLL_C_CNT_EVEN_DUTY_EN_7 false
PLL_C_CNT_FREQ_PS_STR_7 0 ps
PLL_C_CNT_FREQ_MHZ_STR_7 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_7 0 ps
PLL_C_CNT_DUTY_CYCLE_7 50
PLL_C_CNT_OUT_EN_7 false
PLL_C_CNT_HIGH_8 256
PLL_C_CNT_LOW_8 256
PLL_C_CNT_PRST_8 1
PLL_C_CNT_PH_MUX_PRST_8 0
PLL_C_CNT_BYPASS_EN_8 true
PLL_C_CNT_EVEN_DUTY_EN_8 false
PLL_C_CNT_FREQ_PS_STR_8 0 ps
PLL_C_CNT_FREQ_MHZ_STR_8 0.0 MHz
PLL_C_CNT_PHASE_PS_STR_8 0 ps
PLL_C_CNT_DUTY_CYCLE_8 50
PLL_C_CNT_OUT_EN_8 false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

emif_fm_ddr4a_ecc_core

altera_emif_ecc v19.1
emif_fm_ddr4a_arch emif_usr_clk   emif_fm_ddr4a_ecc_core
  emif_usr_clk_in
emif_usr_reset_n  
  emif_usr_reset_n_in
ctrl_ast_rd_0  
  ctrl_ast_rd_0
ctrl_ecc_0   emif_fm_ddr4a_arch
  ctrl_ecc_0
ctrl_ast_cmd_0  
  ctrl_ast_cmd_0
ctrl_ast_wr_0  
  ctrl_ast_wr_0


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.06 seconds