subsys_periph

2023.01.26.22:47:06 Datasheet
Overview

All Components
   ILC interrupt_latency_counter 19.1.0
   button_pio altera_avalon_pio 19.2.0
   dipsw_pio altera_avalon_pio 19.2.0
   led_pio altera_avalon_pio 19.2.0
   pb_cpu_0 altera_avalon_mm_bridge 20.0.1
Memory Map
  ILC
avalon_slave 
  button_pio
s1 
  dipsw_pio
s1 
  led_pio
s1 

ILC

interrupt_latency_counter v19.1.0
pb_cpu_0 m0   ILC
  avalon_slave
periph_clk out_clk  
  clk
periph_rst_in out_reset  
  reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

button_pio

altera_avalon_pio v19.2.0
pb_cpu_0 m0   button_pio
  s1
periph_clk out_clk  
  clk
periph_rst_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

dipsw_pio

altera_avalon_pio v19.2.0
pb_cpu_0 m0   dipsw_pio
  s1
periph_clk out_clk  
  clk
periph_rst_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

led_pio

altera_avalon_pio v19.2.0
pb_cpu_0 m0   led_pio
  s1
periph_clk out_clk  
  clk
periph_rst_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

pb_cpu_0

altera_avalon_mm_bridge v20.0.1
periph_clk out_clk   pb_cpu_0
  clk
periph_rst_in out_reset  
  reset
m0   ILC
  avalon_slave
m0   led_pio
  s1
m0   dipsw_pio
  s1
m0   button_pio
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

periph_clk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

periph_rst_in

altera_reset_bridge v19.2.0
periph_clk out_clk   periph_rst_in
  clk
out_reset   led_pio
  reset
out_reset   dipsw_pio
  reset
out_reset   button_pio
  reset
out_reset   pb_cpu_0
  reset
out_reset   ILC
  reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)
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