phy_fmcp

2023.09.15.13:02:46 Datasheet
Overview

All Components
   directphy_f_0_f_dphy_adme directphy_f_ftile_adme 4.5.0
   directphy_f_0_f_dphy_adme_f_dphy_adme ftile_adme 1.0.0
Memory Map
directphy_f_0_f_dphy_adme directphy_f_0_f_dphy_adme_f_dphy_adme
 avmm2_address_tile  avmm2_byte_enable_tile  avmm2_write_tile  avmm2_read_tile  avmm2_write_data_tile  avmm2_read_data_user  avmm2_waitrequest_user  avmm2_read_data_valid_user  avmm1_address_tile  avmm1_byte_enable_tile  avmm1_write_tile  avmm1_read_tile  avmm1_write_data_tile  avmm1_read_data_user  avmm1_waitrequest_user  avmm1_read_data_valid_user  avmm2_address_tile  avmm2_byte_enable_tile  avmm2_write_tile  avmm2_read_tile  avmm2_write_data_tile  avmm2_read_data_user  avmm2_waitrequest_user  avmm2_read_data_valid_user  avmm1_address_tile  avmm1_byte_enable_tile  avmm1_write_tile  avmm1_read_tile  avmm1_write_data_tile  avmm1_read_data_user  avmm1_waitrequest_user  avmm1_read_data_valid_user
  directphy_f_0_f_dphy_adme
avmm2_address_user 
avmm2_byte_enable_user 
avmm2_write_user 
avmm2_read_user 
avmm2_write_data_user 
avmm2_read_data_tile 
avmm2_waitrequest_tile 
avmm2_read_data_valid_tile 
avmm1_address_user 
avmm1_byte_enable_user 
avmm1_write_user 
avmm1_read_user 
avmm1_write_data_user 
avmm1_read_data_tile 
avmm1_waitrequest_tile 
avmm1_read_data_valid_tile 
  directphy_f_0_f_dphy_adme_f_dphy_adme
avmm2_address_user 
avmm2_byte_enable_user 
avmm2_write_user 
avmm2_read_user 
avmm2_write_data_user 
avmm2_read_data_tile 
avmm2_waitrequest_tile 
avmm2_read_data_valid_tile 
avmm1_address_user 
avmm1_byte_enable_user 
avmm1_write_user 
avmm1_read_user 
avmm1_write_data_user 
avmm1_read_data_tile 
avmm1_waitrequest_tile 
avmm1_read_data_valid_tile 

directphy_f_0

directphy_f v4.5.0


Parameters

fgt_tx_pll_fout_hz 2500.000000
fgt_tx_pll_vco_MHz 10000.000000
fgt_tx_pll_cascade_enable 0
fgt_tx_pll_frac_mode_enable 0
fgt_tx_pll_refclk_freq_mhz 156.250000
fgt_tx_pll_refclk_freq_itxt 156.250000
fgt_rx_pll_fout_hz 0
fgt_rx_pll_vco_MHz
fgt_rx_pll_refclk_freq_mhz 156.250000
num_sys_cop 1
xcvr_type FGT
fgt_protocol_mode DISABLED
num_xcvr_per_sys 1
clocking_mode syspll
syspll_outclk_freq_mhz 900
duplex_mode tx
ed_sel None
ed_ack 0
ed_hdl_sel Verilog
ed_board None
pma_modulation NRZ
pma_data_rate 5000
pma_outclk_freq_mhz 156.25
pma_width 32
rx_deskew_en 1
enable_simple_interface 0
enable_split_interface 0
fgt_serdes_lpbk_mode LOOPBACK_MODE_DISABLED
fgt_tx_serdes_gray_coding_enable 0
fgt_tx_serdes_pre_coding_enable 0
fgt_tx_serdes_prbs_gen_mode disable
enable_port_fgt_tx_beacon 0
enable_tx_ssc_interface 0
fgt_tx_pll_txuserclk1_enable 1
fgt_tx_pll_txuserclk2_enable 0
fgt_tx_pll_txuserclk_div 100
fgt_rx_serdes_gray_coding_enable 0
fgt_rx_serdes_pre_coding_enable 0
fgt_rx_serdes_prbs_mon_mode disable
fgt_rx_sata_squelch_det_enable 0
enable_port_fgt_rx_signal_detect 0
enable_port_fgt_rx_signal_detect_lfps 0
enable_port_fgt_rx_cdr_divclk_link0 0
fgt_rx_cdr_divclk_link0_sel 0
fgt_rx_serdes_adapt_mode auto
enable_fgt_rx_cdr_fast_freeze_sel 0
enable_fgt_rx_cdr_set_locktoref 0
fgt_rx_cdr_lock_mode auto
enable_port_fgt_rx_set_locktoref 0
enable_port_fgt_rx_set_locktodata 0
enable_port_fgt_rx_cdr_freeze 0
fgt_rx_cdr_rxuserclk_enable 0
fgt_rx_cdr_rxuserclk_div 100
bk_loopback_mode SERIAL_EXT_LOOPBACK
bk_tx_invert_p_and_n TX_INVERT_PN_DIS
bk_refclk_source_lane_pll REF_TO_GND
bk_pll_pcs3334_ratio DIV_33_BY_2
bk_tx_precode_en 0
bk_tx_predivider_en 0
bk_tx_user_clk1_en 0
bk_tx_user_clk1_sel 0
bk_tx_user_clk2_en 0
bk_tx_user_clk2_sel 0
bk_alt_pam4_grey_code 0
bk_rx_invert_p_and_n RX_INVERT_PN_DIS
bk_en_rxdat_profile RXDAT_PROF_EN
bk_pll_rx_pcs3334_ratio RX_DIV_33_BY_2
bk_rx_precode_en 0
bk_rx_user_clk1_en 0
bk_rx_user_clk1_sel 0
bk_rx_user_clk2_en 0
bk_rx_user_clk2_sel 0
pmaif_tx_fifo_mode_s elastic
enable_port_tx_pmaif_fifo_empty 0
enable_port_tx_pmaif_fifo_pempty 0
enable_port_tx_pmaif_fifo_pfull 0
fec_en 0
l_fec_mode IEEE 802.3 RS(528,514) (CL 91,KR)
enable_cwbin_gui 0
refclk_cwbin_gui 100.0
fec_802p3ck 0
l_av1_enable 0
avmm1_soft_csr_enable 0
avmm1_readdv_enable 0
avmm1_split 0
avmm1_jtag_enable 0
avmm2_enable 0
avmm2_readdv_enable 0
avmm2_split 0
avmm2_jtag_enable 0
enable_port_latency_measurement 0
tx_custom_cadence_enable 0
enable_port_tx_cadence_slow_clk_locked 0
pldif_tx_fifo_mode phase_comp
pldif_tile_tx_fifo_mode phase_comp
pldif_tx_double_width_transfer_enable 1
pldif_tx_fifo_pfull_thld 10
pldif_tx_fifo_pempty_thld 2
enable_port_tx_fifo_full 0
enable_port_tx_fifo_empty 0
enable_port_tx_fifo_pfull 0
enable_port_tx_fifo_pempty 0
enable_port_tx_dll_lock 0
pldif_tx_clkout_sel PLL_DIV2
pldif_tx_clkout_freq_mhz 450.0
enable_port_tx_clkout2 0
pldif_tx_clkout2_sel TX_WORD_CLK
pldif_tx_clkout2_div 1
pldif_tx_clkout2_freq_mhz Disabled
pldif_tx_coreclkin_clock_network dedicated
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

directphy_f_0_f_dphy_adme

directphy_f_ftile_adme v4.5.0


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

directphy_f_0_f_dphy_adme_f_dphy_adme

ftile_adme v1.0.0


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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