alt_cpriphy_c3_channel_pll

2022.04.22.11:04:25 Datasheet
Overview

Memory Map

xcvrnphy_fme_0

xcvrnphy_fme v4.1.0


Parameters

hssi_aib_ssm_silicon_rev 14nm5
hssi_aibcr_rx_aib_datasel_gr0 aib_datasel0_setting0
hssi_aibcr_rx_aib_datasel_gr1 aib_datasel1_setting0
hssi_aibcr_rx_aib_datasel_gr2 aib_datasel2_setting1
hssi_aibcr_rx_aib_ddrctrl_gr0 aib_ddr0_setting1
hssi_aibcr_rx_aib_ddrctrl_gr1 aib_ddr1_setting1
hssi_aibcr_rx_aib_iinasyncen aib_inasyncen_setting2
hssi_aibcr_rx_aib_iinclken aib_inclken_setting3
hssi_aibcr_rx_aib_outctrl_gr0 aib_outen0_setting1
hssi_aibcr_rx_aib_outctrl_gr1 aib_outen1_setting1
hssi_aibcr_rx_aib_outctrl_gr2 aib_outen2_setting1
hssi_aibcr_rx_aib_outctrl_gr3 aib_outen3_setting1
hssi_aibcr_rx_aib_outndrv_r12 aib_ndrv12_setting1
hssi_aibcr_rx_aib_outndrv_r56 aib_ndrv56_setting1
hssi_aibcr_rx_aib_outndrv_r78 aib_ndrv78_setting1
hssi_aibcr_rx_aib_outpdrv_r12 aib_pdrv12_setting1
hssi_aibcr_rx_aib_outpdrv_r56 aib_pdrv56_setting1
hssi_aibcr_rx_aib_outpdrv_r78 aib_pdrv78_setting1
hssi_aibcr_rx_aib_red_rx_shiften aib_red_rx_shift_disable
hssi_aibcr_rx_aib_rx_clkdiv aib_rx_clkdiv_setting1
hssi_aibcr_rx_aib_rx_dcc_byp aib_rx_dcc_byp_enable
hssi_aibcr_rx_aib_rx_dcc_byp_iocsr_unused aib_rx_dcc_byp_disable_iocsr_unused
hssi_aibcr_rx_aib_rx_dcc_cont_cal aib_rx_dcc_cal_cont
hssi_aibcr_rx_aib_rx_dcc_cont_cal_iocsr_unused aib_rx_dcc_cal_single_iocsr_unused
hssi_aibcr_rx_aib_rx_dcc_dft aib_rx_dcc_dft_disable
hssi_aibcr_rx_aib_rx_dcc_dft_sel aib_rx_dcc_dft_mode0
hssi_aibcr_rx_aib_rx_dcc_dll_entest aib_rx_dcc_dll_test_disable
hssi_aibcr_rx_aib_rx_dcc_dy_ctl_static aib_rx_dcc_dy_ctl_static_setting1
hssi_aibcr_rx_aib_rx_dcc_dy_ctlsel aib_rx_dcc_dy_ctlsel_setting0
hssi_aibcr_rx_aib_rx_dcc_en aib_rx_dcc_disable
hssi_aibcr_rx_aib_rx_dcc_en_iocsr_unused aib_rx_dcc_disable_iocsr_unused
hssi_aibcr_rx_aib_rx_dcc_manual_dn aib_rx_dcc_manual_dn0
hssi_aibcr_rx_aib_rx_dcc_manual_up aib_rx_dcc_manual_up0
hssi_aibcr_rx_aib_rx_dcc_rst_prgmnvrt aib_rx_dcc_st_rst_prgmnvrt_setting0
hssi_aibcr_rx_aib_rx_dcc_st_core_dn_prgmnvrt aib_rx_dcc_st_core_dn_prgmnvrt_setting0
hssi_aibcr_rx_aib_rx_dcc_st_core_up_prgmnvrt aib_rx_dcc_st_core_up_prgmnvrt_setting0
hssi_aibcr_rx_aib_rx_dcc_st_core_updnen aib_rx_dcc_st_core_updnen_setting0
hssi_aibcr_rx_aib_rx_dcc_st_dftmuxsel aib_rx_dcc_st_dftmuxsel_setting0
hssi_aibcr_rx_aib_rx_dcc_st_dly_pst aib_rx_dcc_st_dly_pst_setting0
hssi_aibcr_rx_aib_rx_dcc_st_en aib_rx_dcc_st_en_setting1
hssi_aibcr_rx_aib_rx_dcc_st_lockreq_muxsel aib_rx_dcc_st_lockreq_muxsel_setting0
hssi_aibcr_rx_aib_rx_dcc_st_new_dll aib_rx_dcc_new_dll_setting0
hssi_aibcr_rx_aib_rx_dcc_st_new_dll2 aib_rx_dcc_new_dll2_setting0
hssi_aibcr_rx_aib_rx_dcc_st_rst aib_rx_dcc_st_rst_setting0
hssi_aibcr_rx_aib_rx_dcc_test_clk_pll_en_n aib_rx_dcc_test_clk_pll_en_n_disable
hssi_aibcr_rx_aib_rx_halfcode aib_rx_halfcode_enable
hssi_aibcr_rx_aib_rx_selflock aib_rx_selflock_enable
hssi_aibcr_rx_dft_hssitestip_dll_dcc_en disable_dft
hssi_aibcr_rx_op_mode rx_dcc_disable
hssi_aibcr_rx_powermode_ac rxdatapath_low_speed_pwr
hssi_aibcr_rx_powermode_dc rxdatapath_powerup
hssi_aibcr_rx_redundancy_en disable
hssi_aibcr_rx_rx_transfer_clk_duty_cycle rx_trsf_clk_dc_50_50
hssi_aibcr_rx_rx_transfer_clk_freq 310000000
hssi_aibcr_rx_rx_transfer_clk_freq_hz 310000000
hssi_aibcr_rx_sup_mode user_mode
hssi_aibcr_rx_silicon_rev 10nm6bcr3a
hssi_aibcr_tx_aib_datasel_gr0 aib_datasel0_setting0
hssi_aibcr_tx_aib_datasel_gr1 aib_datasel1_setting1
hssi_aibcr_tx_aib_datasel_gr2 aib_datasel2_setting0
hssi_aibcr_tx_aib_dllstr_align_clkdiv aib_dllstr_align_clkdiv_setting1
hssi_aibcr_tx_aib_dllstr_align_dcc_dll_dft_sel aib_dllstr_align_dcc_dll_dft_sel_setting0
hssi_aibcr_tx_aib_dllstr_align_dft_ch_muxsel aib_dllstr_align_dft_ch_muxsel_setting0
hssi_aibcr_tx_aib_dllstr_align_dly_pst aib_dllstr_align_dly_pst_setting0
hssi_aibcr_tx_aib_dllstr_align_dy_ctl_static aib_dllstr_align_dy_ctl_static_setting1
hssi_aibcr_tx_aib_dllstr_align_dy_ctlsel aib_dllstr_align_dy_ctlsel_setting0
hssi_aibcr_tx_aib_dllstr_align_entest aib_dllstr_align_test_disable
hssi_aibcr_tx_aib_dllstr_align_halfcode aib_dllstr_align_halfcode_enable
hssi_aibcr_tx_aib_dllstr_align_selflock aib_dllstr_align_selflock_enable
hssi_aibcr_tx_aib_dllstr_align_st_core_dn_prgmnvrt aib_dllstr_align_st_core_dn_prgmnvrt_setting0
hssi_aibcr_tx_aib_dllstr_align_st_core_up_prgmnvrt aib_dllstr_align_st_core_up_prgmnvrt_setting0
hssi_aibcr_tx_aib_dllstr_align_st_core_updnen aib_dllstr_align_st_core_updnen_setting0
hssi_aibcr_tx_aib_dllstr_align_st_dftmuxsel aib_dllstr_align_st_dftmuxsel_setting0
hssi_aibcr_tx_aib_dllstr_align_st_en aib_dllstr_align_st_en_setting1
hssi_aibcr_tx_aib_dllstr_align_st_lockreq_muxsel aib_dllstr_align_st_lockreq_muxsel_setting0
hssi_aibcr_tx_aib_dllstr_align_st_new_dll aib_dllstr_align_new_dll_setting0
hssi_aibcr_tx_aib_dllstr_align_st_new_dll2 aib_dllstr_align_new_dll2_setting0
hssi_aibcr_tx_aib_dllstr_align_st_rst aib_dllstr_align_st_rst_setting0
hssi_aibcr_tx_aib_dllstr_align_st_rst_prgmnvrt aib_dllstr_align_st_rst_prgmnvrt_setting0
hssi_aibcr_tx_aib_dllstr_align_test_clk_pll_en_n aib_dllstr_align_test_clk_pll_en_n_disable
hssi_aibcr_tx_aib_inctrl_gr0 aib_inctrl0_setting1
hssi_aibcr_tx_aib_inctrl_gr1 aib_inctrl1_setting3
hssi_aibcr_tx_aib_inctrl_gr2 aib_inctrl2_setting2
hssi_aibcr_tx_aib_inctrl_gr3 aib_inctrl3_setting2
hssi_aibcr_tx_aib_outctrl_gr0 aib_outen0_setting1
hssi_aibcr_tx_aib_outctrl_gr1 aib_outen1_setting1
hssi_aibcr_tx_aib_outctrl_gr2 aib_outen2_setting1
hssi_aibcr_tx_aib_outndrv_r12 aib_ndrv12_setting1
hssi_aibcr_tx_aib_outndrv_r34 aib_ndrv34_setting1
hssi_aibcr_tx_aib_outndrv_r56 aib_ndrv56_setting1
hssi_aibcr_tx_aib_outndrv_r78 aib_ndrv78_setting1
hssi_aibcr_tx_aib_outpdrv_r12 aib_pdrv12_setting1
hssi_aibcr_tx_aib_outpdrv_r34 aib_pdrv34_setting1
hssi_aibcr_tx_aib_outpdrv_r56 aib_pdrv56_setting1
hssi_aibcr_tx_aib_outpdrv_r78 aib_pdrv78_setting1
hssi_aibcr_tx_aib_red_dirclkn_shiften aib_red_dirclkn_shift_disable
hssi_aibcr_tx_aib_red_dirclkp_shiften aib_red_dirclkp_shift_disable
hssi_aibcr_tx_aib_red_drx_shiften aib_red_drx_shift_disable
hssi_aibcr_tx_aib_red_dtx_shiften aib_red_dtx_shift_disable
hssi_aibcr_tx_aib_red_pinp_shiften aib_red_pinp_shift_disable
hssi_aibcr_tx_aib_red_rx_shiften aib_red_rx_shift_disable
hssi_aibcr_tx_aib_red_tx_shiften aib_red_tx_shift_disable
hssi_aibcr_tx_aib_red_txferclkout_shiften aib_red_txferclkout_shift_disable
hssi_aibcr_tx_aib_red_txferclkoutn_shiften aib_red_txferclkoutn_shift_disable
hssi_aibcr_tx_dfd_dll_dcc_en disable_dfd
hssi_aibcr_tx_dft_hssitestip_dll_dcc_en disable_dft
hssi_aibcr_tx_op_mode tx_dll_enable
hssi_aibcr_tx_powermode_ac txdatapath_high_speed_pwr
hssi_aibcr_tx_powermode_dc txdatapath_powerup
hssi_aibcr_tx_redundancy_en disable
hssi_aibcr_tx_sup_mode user_mode
hssi_aibcr_tx_tx_transfer_clk_freq 805664062
hssi_aibcr_tx_tx_transfer_clk_freq_hz 805664062
hssi_aibcr_tx_silicon_rev 10nm6bcr3a
hssi_aibnd_rx_aib_ber_margining_ctrl aib_ber_margining_setting0
hssi_aibnd_rx_aib_datasel_gr0 aib_datasel0_setting0
hssi_aibnd_rx_aib_datasel_gr1 aib_datasel1_setting1
hssi_aibnd_rx_aib_datasel_gr2 aib_datasel2_setting1
hssi_aibnd_rx_aib_dllstr_align_clkdiv aib_dllstr_align_clkdiv_setting1
hssi_aibnd_rx_aib_dllstr_align_dly_pst aib_dllstr_align_dly_pst_setting0
hssi_aibnd_rx_aib_dllstr_align_dy_ctl_static aib_dllstr_align_dy_ctl_static_setting1
hssi_aibnd_rx_aib_dllstr_align_dy_ctlsel aib_dllstr_align_dy_ctlsel_setting1
hssi_aibnd_rx_aib_dllstr_align_entest aib_dllstr_align_test_disable
hssi_aibnd_rx_aib_dllstr_align_halfcode aib_dllstr_align_halfcode_enable
hssi_aibnd_rx_aib_dllstr_align_selflock aib_dllstr_align_selflock_enable
hssi_aibnd_rx_aib_dllstr_align_st_core_dn_prgmnvrt aib_dllstr_align_st_core_dn_prgmnvrt_setting0
hssi_aibnd_rx_aib_dllstr_align_st_core_up_prgmnvrt aib_dllstr_align_st_core_up_prgmnvrt_setting0
hssi_aibnd_rx_aib_dllstr_align_st_core_updnen aib_dllstr_align_st_core_updnen_setting0
hssi_aibnd_rx_aib_dllstr_align_st_dftmuxsel aib_dllstr_align_st_dftmuxsel_setting0
hssi_aibnd_rx_aib_dllstr_align_st_en aib_dllstr_align_st_en_setting1
hssi_aibnd_rx_aib_dllstr_align_st_hps_ctrl_en aib_dllstr_align_hps_ctrl_en_setting0
hssi_aibnd_rx_aib_dllstr_align_st_lockreq_muxsel aib_dllstr_align_st_lockreq_muxsel_setting0
hssi_aibnd_rx_aib_dllstr_align_st_new_dll aib_dllstr_align_new_dll_setting0
hssi_aibnd_rx_aib_dllstr_align_st_rst aib_dllstr_align_st_rst_setting0
hssi_aibnd_rx_aib_dllstr_align_st_rst_prgmnvrt aib_dllstr_align_st_rst_prgmnvrt_setting0
hssi_aibnd_rx_aib_dllstr_align_test_clk_pll_en_n aib_dllstr_align_test_clk_pll_en_n_disable
hssi_aibnd_rx_aib_inctrl_gr0 aib_inctrl0_setting1
hssi_aibnd_rx_aib_inctrl_gr1 aib_inctrl1_setting3
hssi_aibnd_rx_aib_inctrl_gr2 aib_inctrl2_setting2
hssi_aibnd_rx_aib_inctrl_gr3 aib_inctrl3_setting3
hssi_aibnd_rx_aib_outctrl_gr0 aib_outen0_setting1
hssi_aibnd_rx_aib_outctrl_gr1 aib_outen1_setting1
hssi_aibnd_rx_aib_outctrl_gr2 aib_outen2_setting1
hssi_aibnd_rx_aib_outndrv_r12 aib_ndrv12_setting2
hssi_aibnd_rx_aib_outndrv_r34 aib_ndrv34_setting2
hssi_aibnd_rx_aib_outndrv_r56 aib_ndrv56_setting2
hssi_aibnd_rx_aib_outndrv_r78 aib_ndrv78_setting2
hssi_aibnd_rx_aib_outpdrv_r12 aib_pdrv12_setting2
hssi_aibnd_rx_aib_outpdrv_r34 aib_pdrv34_setting2
hssi_aibnd_rx_aib_outpdrv_r56 aib_pdrv56_setting2
hssi_aibnd_rx_aib_outpdrv_r78 aib_pdrv78_setting2
hssi_aibnd_rx_aib_red_shift_en aib_red_shift_disable
hssi_aibnd_rx_dft_hssitestip_dll_dcc_en disable_dft
hssi_aibnd_rx_op_mode rx_dll_disable
hssi_aibnd_rx_powerdown_mode false
hssi_aibnd_rx_powermode_ac rxdatapath_low_speed_pwr
hssi_aibnd_rx_powermode_dc powerup
hssi_aibnd_rx_powermode_freq_hz_aib_hssi_rx_transfer_clk 310000000
hssi_aibnd_rx_redundancy_en disable
hssi_aibnd_rx_sup_mode user_mode
hssi_aibnd_rx_silicon_rev 10nm6bcr3a
hssi_aibnd_tx_aib_datasel_gr0 aib_datasel0_setting0
hssi_aibnd_tx_aib_datasel_gr1 aib_datasel1_setting0
hssi_aibnd_tx_aib_datasel_gr2 aib_datasel2_setting1
hssi_aibnd_tx_aib_datasel_gr3 aib_datasel3_setting1
hssi_aibnd_tx_aib_ddrctrl_gr0 aib_ddr0_setting1
hssi_aibnd_tx_aib_hssi_tx_transfer_clk_hz 0
hssi_aibnd_tx_aib_iinasyncen aib_inasyncen_setting2
hssi_aibnd_tx_aib_iinclken aib_inclken_setting3
hssi_aibnd_tx_aib_outctrl_gr0 aib_outen0_setting1
hssi_aibnd_tx_aib_outctrl_gr1 aib_outen1_setting1
hssi_aibnd_tx_aib_outctrl_gr2 aib_outen2_setting1
hssi_aibnd_tx_aib_outctrl_gr3 aib_outen3_setting1
hssi_aibnd_tx_aib_outndrv_r34 aib_ndrv34_setting2
hssi_aibnd_tx_aib_outndrv_r56 aib_ndrv56_setting2
hssi_aibnd_tx_aib_outpdrv_r34 aib_pdrv34_setting2
hssi_aibnd_tx_aib_outpdrv_r56 aib_pdrv56_setting2
hssi_aibnd_tx_aib_red_dirclkn_shiften aib_red_dirclkn_shift_disable
hssi_aibnd_tx_aib_red_dirclkp_shiften aib_red_dirclkp_shift_disable
hssi_aibnd_tx_aib_red_drx_shiften aib_red_drx_shift_disable
hssi_aibnd_tx_aib_red_dtx_shiften aib_red_dtx_shift_disable
hssi_aibnd_tx_aib_red_pout_shiften aib_red_pout_shift_disable
hssi_aibnd_tx_aib_red_rx_shiften aib_red_rx_shift_disable
hssi_aibnd_tx_aib_red_tx_shiften aib_red_tx_shift_disable
hssi_aibnd_tx_aib_red_txferclkout_shiften aib_red_txferclkout_shift_disable
hssi_aibnd_tx_aib_red_txferclkoutn_shiften aib_red_txferclkoutn_shift_disable
hssi_aibnd_tx_aib_tx_clkdiv aib_tx_clkdiv_setting1
hssi_aibnd_tx_aib_tx_dcc_byp aib_tx_dcc_byp_disable
hssi_aibnd_tx_aib_tx_dcc_byp_iocsr_unused aib_tx_dcc_byp_disable_iocsr_unused
hssi_aibnd_tx_aib_tx_dcc_cont_cal aib_tx_dcc_cal_cont
hssi_aibnd_tx_aib_tx_dcc_cont_cal_iocsr_unused aib_tx_dcc_cal_single_iocsr_unused
hssi_aibnd_tx_aib_tx_dcc_dft aib_tx_dcc_dft_disable
hssi_aibnd_tx_aib_tx_dcc_dft_sel aib_tx_dcc_dft_mode0
hssi_aibnd_tx_aib_tx_dcc_dll_dft_sel aib_tx_dcc_dll_dft_sel_setting0
hssi_aibnd_tx_aib_tx_dcc_dll_entest aib_tx_dcc_dll_test_disable
hssi_aibnd_tx_aib_tx_dcc_dy_ctl_static aib_tx_dcc_dy_ctl_static_setting1
hssi_aibnd_tx_aib_tx_dcc_dy_ctlsel aib_tx_dcc_dy_ctlsel_setting0
hssi_aibnd_tx_aib_tx_dcc_en aib_tx_dcc_enable
hssi_aibnd_tx_aib_tx_dcc_en_iocsr_unused aib_tx_dcc_disable_iocsr_unused
hssi_aibnd_tx_aib_tx_dcc_manual_dn aib_tx_dcc_manual_dn0
hssi_aibnd_tx_aib_tx_dcc_manual_up aib_tx_dcc_manual_up0
hssi_aibnd_tx_aib_tx_dcc_rst_prgmnvrt aib_tx_dcc_st_rst_prgmnvrt_setting0
hssi_aibnd_tx_aib_tx_dcc_st_core_dn_prgmnvrt aib_tx_dcc_st_core_dn_prgmnvrt_setting0
hssi_aibnd_tx_aib_tx_dcc_st_core_up_prgmnvrt aib_tx_dcc_st_core_up_prgmnvrt_setting0
hssi_aibnd_tx_aib_tx_dcc_st_core_updnen aib_tx_dcc_st_core_updnen_setting0
hssi_aibnd_tx_aib_tx_dcc_st_dftmuxsel aib_tx_dcc_st_dftmuxsel_setting0
hssi_aibnd_tx_aib_tx_dcc_st_dly_pst aib_tx_dcc_st_dly_pst_setting0
hssi_aibnd_tx_aib_tx_dcc_st_en aib_tx_dcc_st_en_setting1
hssi_aibnd_tx_aib_tx_dcc_st_hps_ctrl_en aib_tx_dcc_hps_ctrl_en_setting0
hssi_aibnd_tx_aib_tx_dcc_st_lockreq_muxsel aib_tx_dcc_st_lockreq_muxsel_setting0
hssi_aibnd_tx_aib_tx_dcc_st_new_dll aib_tx_dcc_new_dll_setting0
hssi_aibnd_tx_aib_tx_dcc_st_rst aib_tx_dcc_st_rst_setting0
hssi_aibnd_tx_aib_tx_dcc_test_clk_pll_en_n aib_tx_dcc_test_clk_pll_en_n_disable
hssi_aibnd_tx_aib_tx_halfcode aib_tx_halfcode_enable
hssi_aibnd_tx_aib_tx_selflock aib_tx_selflock_enable
hssi_aibnd_tx_dfd_dll_dcc_en disable_dfd
hssi_aibnd_tx_dft_hssitestip_dll_dcc_en disable_dft
hssi_aibnd_tx_op_mode tx_dcc_enable
hssi_aibnd_tx_powerdown_mode false
hssi_aibnd_tx_powermode_ac txdatapath_high_speed_pwr
hssi_aibnd_tx_powermode_dc powerup
hssi_aibnd_tx_powermode_freq_hz_aib_hssi_tx_transfer_clk 805664062
hssi_aibnd_tx_redundancy_en disable
hssi_aibnd_tx_sup_mode user_mode
hssi_aibnd_tx_silicon_rev 10nm6bcr3a
hssi_avmm1_if_pcs_arbiter_ctrl avmm1_arbiter_uc_sel
hssi_avmm1_if_hssiadapt_avmm_clk_dcg_en disable
hssi_avmm1_if_hssiadapt_avmm_clk_scg_en disable
hssi_avmm1_if_pldadapt_avmm_clk_scg_en disable
hssi_avmm1_if_pcs_cal_done avmm1_cal_done_assert
hssi_avmm1_if_pcs_cal_reserved 0
hssi_avmm1_if_pcs_calibration_feature_en avmm1_pcs_calibration_dis
hssi_avmm1_if_pldadapt_gate_dis disable
hssi_avmm1_if_pcs_hip_cal_en disable
hssi_avmm1_if_hssiadapt_nfhssi_calibratio_feature_en disable
hssi_avmm1_if_pldadapt_nfhssi_calibratio_feature_en disable
hssi_avmm1_if_hssiadapt_osc_clk_scg_en disable
hssi_avmm1_if_pldadapt_osc_clk_scg_en disable
hssi_avmm1_if_hssiadapt_read_blocking_enable enable
hssi_avmm1_if_pldadapt_read_blocking_enable enable
hssi_avmm1_if_hssiadapt_uc_blocking_enable enable
hssi_avmm1_if_pldadapt_uc_blocking_enable enable
hssi_avmm1_if_hssiadapt_write_resp_en disable
hssi_avmm1_if_hssiadapt_avmm_osc_clock_setting osc_clk_div_by1
hssi_avmm1_if_pldadapt_avmm_osc_clock_setting osc_clk_div_by1
hssi_avmm1_if_hssiadapt_avmm_testbus_sel avmm1_transfer_testbus
hssi_avmm1_if_pldadapt_avmm_testbus_sel avmm1_transfer_testbus
hssi_avmm1_if_func_mode c3adpt_pmadir
hssi_avmm1_if_hssiadapt_sr_hip_mode disable_hip
hssi_avmm1_if_hssiadapt_hip_mode user_chnl
hssi_avmm1_if_pldadapt_hip_mode user_chnl
hssi_avmm1_if_hssiadapt_sr_powerdown_mode powerup
hssi_avmm1_if_hssiadapt_sr_sr_free_run_div_clk out_of_reset_sync
hssi_avmm1_if_hssiadapt_sr_sr_hip_en enable
hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_div_sel non_div
hssi_avmm1_if_hssiadapt_sr_sr_osc_clk_scg_en disable
hssi_avmm1_if_hssiadapt_sr_sr_parity_en disable
hssi_avmm1_if_hssiadapt_sr_sr_reserved_in_en enable
hssi_avmm1_if_hssiadapt_sr_sr_reserved_out_en enable
hssi_avmm1_if_hssiadapt_sr_sup_mode user_mode
hssi_avmm1_if_topology pmadir_pllch
hssi_avmm1_if_silicon_rev 10nm6bcr3a
hssi_avmm1_if_calibration_type one_time
hssi_avmm2_if_pcs_arbiter_ctrl avmm2_arbiter_uc_sel
hssi_avmm2_if_hssiadapt_avmm_clk_dcg_en disable
hssi_avmm2_if_hssiadapt_avmm_clk_scg_en disable
hssi_avmm2_if_pldadapt_avmm_clk_scg_en disable
hssi_avmm2_if_pcs_cal_done avmm2_cal_done_assert
hssi_avmm2_if_pcs_cal_reserved 0
hssi_avmm2_if_pcs_calibration_feature_en avmm2_pcs_calibration_dis
hssi_avmm2_if_pldadapt_gate_dis disable
hssi_avmm2_if_pcs_hip_cal_en disable
hssi_avmm2_if_hssiadapt_osc_clk_scg_en disable
hssi_avmm2_if_pldadapt_osc_clk_scg_en disable
hssi_avmm2_if_hssiadapt_avmm_osc_clock_setting osc_clk_div_by1
hssi_avmm2_if_pldadapt_avmm_osc_clock_setting osc_clk_div_by1
hssi_avmm2_if_hssiadapt_avmm_testbus_sel avmm1_transfer_testbus
hssi_avmm2_if_pldadapt_avmm_testbus_sel avmm1_transfer_testbus
hssi_avmm2_if_func_mode c3adpt_pmadir
hssi_avmm2_if_hssiadapt_hip_mode user_chnl
hssi_avmm2_if_pldadapt_hip_mode user_chnl
hssi_avmm2_if_topology pmadir_pllch
hssi_avmm2_if_silicon_rev 10nm6bcr3a
hssi_avmm2_if_calibration_type one_time
hssi_adapt_rx_adapter_lpbk_mode loopback_disabled
hssi_adapt_rx_c3aibadapt_aib_hssi_pld_sclk_hz 0
hssi_adapt_rx_c3aibadapt_aib_hssi_rx_sr_clk_in_hz 900000000
hssi_adapt_rx_c3aibadapt_aib_hssi_rx_transfer_clk_hz 310000000
hssi_adapt_rx_aib_lpbk_mode disable
hssi_adapt_rx_async_direct_hip_en disable
hssi_adapt_rx_clock_del_measure_enable disable
hssi_adapt_rx_c3aibadapt_csr_clk_hz 0
hssi_adapt_rx_datapath_mapping_mode map_rx_pmadir_mode
hssi_adapt_rx_fifo_double_write fifo_double_write_dis
hssi_adapt_rx_fifo_mode bypass
hssi_adapt_rx_fifo_rd_clk_scg_en enable
hssi_adapt_rx_fifo_rd_clk_sel fifo_rd_rx_pma_clk
hssi_adapt_rx_fifo_stop_rd rd_empty
hssi_adapt_rx_fifo_stop_wr n_wr_full
hssi_adapt_rx_fifo_width fifo_single_width
hssi_adapt_rx_fifo_wr_clk_scg_en enable
hssi_adapt_rx_fifo_wr_clk_sel fifo_wr_ehip_rx_clk
hssi_adapt_rx_free_run_div_clk out_of_reset_sync
hssi_adapt_rx_fsr_pld_10g_rx_crc32_err_rst_val reset_to_zero_crc32
hssi_adapt_rx_fsr_pld_8g_sigdet_out_rst_val reset_to_zero_sigdet
hssi_adapt_rx_fsr_pld_ltd_b_rst_val reset_to_one_ltdb
hssi_adapt_rx_fsr_pld_ltr_rst_val reset_to_zero_ltr
hssi_adapt_rx_fsr_pld_rx_fifo_align_clr_rst_val reset_to_zero_alignclr
hssi_adapt_rx_func_mode c3adpt_pmadir
hssi_adapt_rx_c3aibadapt_hip_aib_clk_2x_hz 0
hssi_adapt_rx_hrdrst_dcd_cal_done_bypass disable
hssi_adapt_rx_hrdrst_rst_sm_dis enable_rx_rst_sm
hssi_adapt_rx_hrdrst_rx_osc_clk_scg_en disable
hssi_adapt_rx_hrdrst_user_ctl_en disable
hssi_adapt_rx_c3aibadapt_icm 0
hssi_adapt_rx_internal_clk1_sel feedthru_clk0_clk1
hssi_adapt_rx_internal_clk1_sel0 feedthru_clks_or_txfifowr_post_ct_or_txfiford_pre_or_post_ct_mux_clk1_mux0
hssi_adapt_rx_internal_clk1_sel1 feedthru_clks_or_txfiford_pre_or_post_ct_mux_clk1_mux1
hssi_adapt_rx_internal_clk1_sel2 pma_clks_or_txfiford_pre_ct_mux_clk1_mux2
hssi_adapt_rx_internal_clk1_sel3 pma_clks_clk1_mux3
hssi_adapt_rx_internal_clk2_sel feedthru_clk0_clk2
hssi_adapt_rx_internal_clk2_sel0 pma_clks_or_rxfiford_post_ct_or_rxfifowr_pre_or_post_ct_mux_clk2_mux0
hssi_adapt_rx_internal_clk2_sel1 pma_clks_or_rxfifowr_pre_or_post_ct_mux_clk2_mux1
hssi_adapt_rx_internal_clk2_sel2 pma_clks_or_rxfifowr_pre_ct_mux_clk2_mux2
hssi_adapt_rx_internal_clk2_sel3 pma_clks_clk2_mux3
hssi_adapt_rx_loopback_mode loopback_disable
hssi_adapt_rx_msb_pipeline_byp msb_pipe_byp_enable
hssi_adapt_rx_osc_clk_scg_en disable
hssi_adapt_rx_phcomp_rd_del phcomp_rd_del2
hssi_adapt_rx_c3aibadapt_pld_pcs_rx_clk_out_hz 0
hssi_adapt_rx_c3aibadapt_pld_pma_hclk_hz 0
hssi_adapt_rx_pma_aib_rx_clk_expected_setting not_used
hssi_adapt_rx_c3aibadapt_pma_aib_rx_clk_hz 0
hssi_adapt_rx_pma_coreclkin_sel pma_coreclkin_pld_sel
hssi_adapt_rx_powerdown_mode powerup
hssi_adapt_rx_c3aibadapt_powermode_ac_avmm1 avmm1_on
hssi_adapt_rx_c3aibadapt_powermode_ac_avmm2 avmm2_off
hssi_adapt_rx_c3aibadapt_powermode_ac_rx_datapath rx_datapath_pmadir
hssi_adapt_rx_c3aibadapt_powermode_ac_sr sr_pmadir
hssi_adapt_rx_c3aibadapt_powermode_dc powerdown_dc
hssi_adapt_rx_rx_10g_krfec_rx_diag_data_status_polling_bypass disable
hssi_adapt_rx_rx_datapath_tb_sel aib_dcc_dll_tb
hssi_adapt_rx_rx_fifo_power_mode half_width_half_depth
hssi_adapt_rx_rx_fifo_read_latency_adjust disable
hssi_adapt_rx_rx_fifo_write_latency_adjust disable
hssi_adapt_rx_rx_osc_clock_setting osc_clk_div_by1
hssi_adapt_rx_rx_parity_sel func_sel
hssi_adapt_rx_rx_pcs_testbus_sel direct_tr_tb_bit0_sel
hssi_adapt_rx_rx_pcspma_testbus_sel enable
hssi_adapt_rx_rx_pld_8g_a1a2_k1k2_flag_polling_bypass disable
hssi_adapt_rx_rx_pld_8g_wa_boundary_polling_bypass disable
hssi_adapt_rx_rx_pld_pma_pcie_sw_done_polling_bypass disable
hssi_adapt_rx_rx_pld_pma_reser_in_polling_bypass disable
hssi_adapt_rx_rx_pld_pma_testbus_polling_bypass disable
hssi_adapt_rx_rx_pld_test_data_polling_bypass disable
hssi_adapt_rx_rx_rmfflag_stretch_enable enable
hssi_adapt_rx_rx_rmfflag_stretch_num_stages rmfflag_two_stage
hssi_adapt_rx_rx_usertest_sel direct_tr_usertest3_sel
hssi_adapt_rx_rxfifo_empty empty_default
hssi_adapt_rx_rxfifo_full full_sw
hssi_adapt_rx_rxfifo_mode rxbypass_mode
hssi_adapt_rx_rxfifo_pempty 2
hssi_adapt_rx_rxfifo_pfull 5
hssi_adapt_rx_rxfiford_post_ct_sel rxfiford_sclk_post_ct
hssi_adapt_rx_rxfiford_to_aib_sel rxfiford_sclk_to_aib
hssi_adapt_rx_rxfifowr_post_ct_sel rxfifowr_sclk_post_ct
hssi_adapt_rx_rxfifowr_pre_ct_sel rxfifowr_sclk_pre_ct
hssi_adapt_rx_c3aibadapt_speed_grade dash_1
hssi_adapt_rx_stretch_num_stages seven_stage
hssi_adapt_rx_sup_mode user_mode
hssi_adapt_rx_topology pmadir_pllch
hssi_adapt_rx_txfiford_post_ct_sel txfiford_sclk_post_ct
hssi_adapt_rx_txfiford_pre_ct_sel txfiford_sclk_pre_ct
hssi_adapt_rx_txfifowr_from_aib_sel txfifowr_sclk_from_aib
hssi_adapt_rx_txfifowr_post_ct_sel txfifowr_sclk_post_ct
hssi_adapt_rx_word_align_enable disable
hssi_adapt_rx_word_mark wm_dis
hssi_adapt_rx_silicon_rev 10nm6bcr3a
hssi_adapt_tx_c3aibadapt_aib_hssi_pld_sclk_hz 0
hssi_adapt_tx_c3aibadapt_aib_hssi_tx_sr_clk_in_hz 900000000
hssi_adapt_tx_c3aibadapt_aib_hssi_tx_transfer_clk_hz 805664062
hssi_adapt_tx_c3aibadapt_csr_clk_hz 0
hssi_adapt_tx_datapath_mapping_mode map_tx_pmadir
hssi_adapt_tx_duplex_mode disable
hssi_adapt_tx_dv_gating disable
hssi_adapt_tx_fifo_double_read fifo_double_read_dis
hssi_adapt_tx_fifo_mode bypass
hssi_adapt_tx_fifo_rd_clk_scg_en enable
hssi_adapt_tx_fifo_rd_clk_sel fifo_rd_transfer_div2_clk
hssi_adapt_tx_fifo_stop_rd rd_empty
hssi_adapt_tx_fifo_stop_wr wr_full
hssi_adapt_tx_fifo_width fifo_single_width
hssi_adapt_tx_fifo_wr_clk_scg_en enable
hssi_adapt_tx_free_run_div_clk out_of_reset_sync
hssi_adapt_tx_fsr_hip_fsr_in_bit0_rst_val reset_to_one_hfsrin0
hssi_adapt_tx_fsr_hip_fsr_in_bit1_rst_val reset_to_one_hfsrin1
hssi_adapt_tx_fsr_hip_fsr_in_bit2_rst_val reset_to_one_hfsrin2
hssi_adapt_tx_fsr_hip_fsr_in_bit3_rst_val reset_to_zero_hfsrin3
hssi_adapt_tx_fsr_hip_fsr_out_bit0_rst_val reset_to_one_hfsrout0
hssi_adapt_tx_fsr_hip_fsr_out_bit1_rst_val reset_to_one_hfsrout1
hssi_adapt_tx_fsr_hip_fsr_out_bit2_rst_val reset_to_zero_hfsrout2
hssi_adapt_tx_fsr_hip_fsr_out_bit3_rst_val reset_to_zero_hfsrout3
hssi_adapt_tx_fsr_mask_tx_pll_rst_val reset_to_zero_maskpll
hssi_adapt_tx_fsr_pld_txelecidle_rst_val reset_to_zero_txelec
hssi_adapt_tx_func_mode c3adpt_pmadir
hssi_adapt_tx_c3aibadapt_hip_aib_clk_2x_hz 0
hssi_adapt_tx_c3aibadapt_hip_aib_txeq_clk_out_hz 0
hssi_adapt_tx_hip_osc_clk_scg_en disable
hssi_adapt_tx_hrdrst_align_bypass enable
hssi_adapt_tx_hrdrst_dcd_cal_done_bypass disable
hssi_adapt_tx_hrdrst_dll_lock_bypass disable
hssi_adapt_tx_hrdrst_rst_sm_dis enable_tx_rst_sm
hssi_adapt_tx_hrdrst_rx_osc_clk_scg_en disable
hssi_adapt_tx_hrdrst_user_ctl_en disable
hssi_adapt_tx_c3aibadapt_icm 0
hssi_adapt_tx_loopback_mode loopback_disable
hssi_adapt_tx_osc_clk_scg_en disable
hssi_adapt_tx_phcomp_rd_del phcomp_rd_del2
hssi_adapt_tx_c3aibadapt_pld_pcs_tx_clk_out_hz 0
hssi_adapt_tx_c3aibadapt_pld_pma_hclk_hz 0
hssi_adapt_tx_c3aibadapt_pma_aib_tx_clk_hz 0
hssi_adapt_tx_powerdown_mode powerup
hssi_adapt_tx_c3aibadapt_powermode_ac_avmm1 avmm1_on
hssi_adapt_tx_c3aibadapt_powermode_ac_avmm2 avmm2_off
hssi_adapt_tx_c3aibadapt_powermode_ac_sr sr_pmadir
hssi_adapt_tx_c3aibadapt_powermode_ac_tx_datapath tx_datapath_pmadir
hssi_adapt_tx_c3aibadapt_powermode_dc powerdown_dc
hssi_adapt_tx_c3aibadapt_speed_grade dash_1
hssi_adapt_tx_stretch_num_stages seven_stage
hssi_adapt_tx_sup_mode user_mode
hssi_adapt_tx_topology pmadir_pllch
hssi_adapt_tx_tx_datapath_tb_sel cp_bond
hssi_adapt_tx_tx_fifo_power_mode half_width_half_depth
hssi_adapt_tx_tx_fifo_read_latency_adjust disable
hssi_adapt_tx_tx_fifo_write_latency_adjust disable
hssi_adapt_tx_tx_osc_clock_setting osc_clk_div_by1
hssi_adapt_tx_tx_rev_lpbk disable
hssi_adapt_tx_tx_usertest_sel enable
hssi_adapt_tx_txfifo_empty empty_default
hssi_adapt_tx_txfifo_full full_dw
hssi_adapt_tx_txfifo_pempty 2
hssi_adapt_tx_txfifo_pfull 5
hssi_adapt_tx_word_align wa_dis
hssi_adapt_tx_word_align_enable disable
hssi_adapt_tx_silicon_rev 10nm6bcr3a
hssi_ehip_lane_am_encoding40g_0 9467463
hssi_ehip_lane_am_encoding40g_1 15779046
hssi_ehip_lane_am_encoding40g_2 12936603
hssi_ehip_lane_am_encoding40g_3 10647869
hssi_ehip_lane_ber_invalid_count 97
hssi_ehip_lane_cfgonly_bypass_select 1
hssi_ehip_lane_check_random_idles disable
hssi_ehip_lane_crete_type crete3
hssi_ehip_lane_deskew_clear enable
hssi_ehip_lane_disable_link_fault_rf disable
hssi_ehip_lane_ehip_clk_hz 402832031
hssi_ehip_lane_ehip_clk_sel no_clock
hssi_ehip_lane_ehip_dist_clk_sel 0
hssi_ehip_lane_ehip_mode ehip_disable
hssi_ehip_lane_ehip_rate rate_25gx1
hssi_ehip_lane_ehip_type single_lane
hssi_ehip_lane_enable_rx_stats_snapshot disable
hssi_ehip_lane_enable_serialliteiv false
hssi_ehip_lane_enable_tx_stats_snapshot disable
hssi_ehip_lane_enforce_max_frame_size disable
hssi_ehip_lane_fec_dist_clk_sel 0
hssi_ehip_lane_flow_control none
hssi_ehip_lane_flow_control_holdoff_mode per_queue
hssi_ehip_lane_force_deskew_done enable
hssi_ehip_lane_force_hip_ready disable
hssi_ehip_lane_force_link_fault_rf disable
hssi_ehip_lane_forward_rx_pause_requests disable
hssi_ehip_lane_func_mode disable
hssi_ehip_lane_hi_ber_monitor enable
hssi_ehip_lane_holdoff_quanta 65535
hssi_ehip_lane_ipg_removed_per_am_period 20
hssi_ehip_lane_is_usr_avmm false
hssi_ehip_lane_keep_rx_crc disable
hssi_ehip_lane_link_fault_mode lf_off
hssi_ehip_lane_pause_quanta 65535
hssi_ehip_lane_pfc_holdoff_quanta_0 65535
hssi_ehip_lane_pfc_holdoff_quanta_1 65535
hssi_ehip_lane_pfc_holdoff_quanta_2 65535
hssi_ehip_lane_pfc_holdoff_quanta_3 65535
hssi_ehip_lane_pfc_holdoff_quanta_4 65535
hssi_ehip_lane_pfc_holdoff_quanta_5 65535
hssi_ehip_lane_pfc_holdoff_quanta_6 65535
hssi_ehip_lane_pfc_holdoff_quanta_7 65535
hssi_ehip_lane_pfc_pause_quanta_0 65535
hssi_ehip_lane_pfc_pause_quanta_1 65535
hssi_ehip_lane_pfc_pause_quanta_2 65535
hssi_ehip_lane_pfc_pause_quanta_3 65535
hssi_ehip_lane_pfc_pause_quanta_4 65535
hssi_ehip_lane_pfc_pause_quanta_5 65535
hssi_ehip_lane_pfc_pause_quanta_6 65535
hssi_ehip_lane_pfc_pause_quanta_7 65535
hssi_ehip_lane_powerdown_mode powerup
hssi_ehip_lane_powermode_ac_mac mac_off
hssi_ehip_lane_powermode_ac_misc misc_off
hssi_ehip_lane_powermode_ac_pcs pcs_off
hssi_ehip_lane_powermode_ac_pld pld_off
hssi_ehip_lane_powermode_dc powerup_dc
hssi_ehip_lane_ptp_debug 0
hssi_ehip_lane_ptp_timestamp_format v2
hssi_ehip_lane_ptp_tx_timestamp_method ptp_2step
hssi_ehip_lane_remove_pads enable
hssi_ehip_lane_request_tx_pause 0
hssi_ehip_lane_reset_rx_stats disable
hssi_ehip_lane_reset_rx_stats_parity_error disable
hssi_ehip_lane_reset_tx_stats disable
hssi_ehip_lane_reset_tx_stats_parity_error disable
hssi_ehip_lane_rx_aib_dp_latency 0
hssi_ehip_lane_rx_am_interval no_rx_am_interval
hssi_ehip_lane_rx_clock_period 162689
hssi_ehip_lane_rx_datapath_soft_rst enable
hssi_ehip_lane_rx_length_checking enable
hssi_ehip_lane_rx_mac_soft_rst enable
hssi_ehip_lane_rx_max_frame_size 1518
hssi_ehip_lane_rx_pause_daddr 1652522221569
hssi_ehip_lane_rx_pcs_max_skew 47
hssi_ehip_lane_rx_pcs_soft_rst enable
hssi_ehip_lane_rx_preamble_passthrough disable
hssi_ehip_lane_rx_ptp_dp_latency 0
hssi_ehip_lane_rx_ptp_extra_latency 0
hssi_ehip_lane_rx_vlan_detection enable
hssi_ehip_lane_rxcrc_covers_preamble disable
hssi_ehip_lane_sim_mode enable
hssi_ehip_lane_source_address_insertion disable
hssi_ehip_lane_strict_preamble_checking disable
hssi_ehip_lane_strict_sfd_checking disable
hssi_ehip_lane_sup_mode user_mode
hssi_ehip_lane_topology disabled_block
hssi_ehip_lane_tx_aib_dp_latency 0
hssi_ehip_lane_tx_am_period sim_only_25g_am_period
hssi_ehip_lane_tx_clock_period 162689
hssi_ehip_lane_tx_datapath_soft_rst enable
hssi_ehip_lane_tx_ipg_size ipg_12
hssi_ehip_lane_tx_mac_data_flow disable
hssi_ehip_lane_tx_mac_soft_rst enable
hssi_ehip_lane_tx_max_frame_size 1518
hssi_ehip_lane_tx_pause_daddr 1652522221569
hssi_ehip_lane_tx_pause_saddr 247393538562781
hssi_ehip_lane_tx_pcs_soft_rst enable
hssi_ehip_lane_tx_pld_fifo_almost_full_level 1
hssi_ehip_lane_tx_preamble_passthrough disable
hssi_ehip_lane_tx_ptp_asym_latency 0
hssi_ehip_lane_tx_ptp_dp_latency 0
hssi_ehip_lane_tx_ptp_extra_latency 0
hssi_ehip_lane_tx_vlan_detection enable
hssi_ehip_lane_txcrc_covers_preamble disable
hssi_ehip_lane_txmac_saddr 73588229205
hssi_ehip_lane_uniform_holdoff_quanta 65535
hssi_ehip_lane_use_am_insert enable
hssi_ehip_lane_use_factory_settings true
hssi_ehip_lane_use_lane_ptp disable
hssi_ehip_lane_use_testbus disable
hssi_ehip_lane_xus_timer_window 806451
hssi_ehip_lane_silicon_rev 10nm6bcr3a
hssi_pldadapt_rx_aib_clk1_sel aib_clk1_rx_transfer_clk
hssi_pldadapt_rx_aib_clk2_sel aib_clk2_pld_pcs_rx_clk_out
hssi_pldadapt_rx_hdpldadapt_aib_fabric_pld_pma_hclk_hz 0
hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_sr_clk_in_hz 0
hssi_pldadapt_rx_hdpldadapt_aib_fabric_rx_transfer_clk_hz 0
hssi_pldadapt_rx_asn_bypass_pma_pcie_sw_done disable
hssi_pldadapt_rx_asn_en disable
hssi_pldadapt_rx_asn_wait_for_dll_reset_cnt 64
hssi_pldadapt_rx_asn_wait_for_fifo_flush_cnt 64
hssi_pldadapt_rx_asn_wait_for_pma_pcie_sw_done_cnt 64
hssi_pldadapt_rx_bonding_dft_en dft_dis
hssi_pldadapt_rx_bonding_dft_val dft_0
hssi_pldadapt_rx_chnl_bonding disable
hssi_pldadapt_rx_clock_del_measure_enable disable
hssi_pldadapt_rx_comp_cnt 0
hssi_pldadapt_rx_compin_sel compin_master
hssi_pldadapt_rx_hdpldadapt_csr_clk_hz 0
hssi_pldadapt_rx_ctrl_plane_bonding individual
hssi_pldadapt_rx_ds_bypass_pipeln ds_bypass_pipeln_dis
hssi_pldadapt_rx_ds_last_chnl ds_last_chnl
hssi_pldadapt_rx_ds_master ds_master_en
hssi_pldadapt_rx_duplex_mode disable
hssi_pldadapt_rx_dv_mode dv_mode_dis
hssi_pldadapt_rx_fifo_double_read fifo_double_read_dis
hssi_pldadapt_rx_fifo_mode phase_comp
hssi_pldadapt_rx_fifo_rd_clk_ins_sm_scg_en enable
hssi_pldadapt_rx_fifo_rd_clk_scg_en disable
hssi_pldadapt_rx_fifo_rd_clk_sel fifo_rd_clk_pld_rx_clk1
hssi_pldadapt_rx_fifo_stop_rd rd_empty
hssi_pldadapt_rx_fifo_stop_wr n_wr_full
hssi_pldadapt_rx_fifo_width fifo_single_width
hssi_pldadapt_rx_fifo_wr_clk_del_sm_scg_en enable
hssi_pldadapt_rx_fifo_wr_clk_scg_en disable
hssi_pldadapt_rx_fifo_wr_clk_sel fifo_wr_clk_rx_transfer_clk
hssi_pldadapt_rx_free_run_div_clk out_of_reset_sync
hssi_pldadapt_rx_fsr_pld_10g_rx_crc32_err_rst_val reset_to_zero_crc32
hssi_pldadapt_rx_fsr_pld_8g_sigdet_out_rst_val reset_to_zero_sigdet
hssi_pldadapt_rx_fsr_pld_ltd_b_rst_val reset_to_one_ltdb
hssi_pldadapt_rx_fsr_pld_ltr_rst_val reset_to_zero_ltr
hssi_pldadapt_rx_fsr_pld_rx_fifo_align_clr_rst_val reset_to_zero_alignclr
hssi_pldadapt_rx_gb_rx_idwidth idwidth_64
hssi_pldadapt_rx_gb_rx_odwidth odwidth_64
hssi_pldadapt_rx_hip_mode disable_hip
hssi_pldadapt_rx_hrdrst_align_bypass enable
hssi_pldadapt_rx_hrdrst_dll_lock_bypass disable
hssi_pldadapt_rx_hrdrst_rst_sm_dis enable_rx_rst_sm
hssi_pldadapt_rx_hrdrst_rx_osc_clk_scg_en disable
hssi_pldadapt_rx_hrdrst_user_ctl_en disable
hssi_pldadapt_rx_indv indv_en
hssi_pldadapt_rx_internal_clk1_sel1 pma_clks_or_txfiford_post_ct_mux_clk1_mux1
hssi_pldadapt_rx_internal_clk1_sel2 pma_clks_clk1_mux2
hssi_pldadapt_rx_internal_clk2_sel1 pma_clks_or_rxfifowr_post_ct_mux_clk2_mux1
hssi_pldadapt_rx_internal_clk2_sel2 pma_clks_clk2_mux2
hssi_pldadapt_rx_is_paired_with other
hssi_pldadapt_rx_loopback_mode disable
hssi_pldadapt_rx_low_latency_en disable
hssi_pldadapt_rx_lpbk_mode disable
hssi_pldadapt_rx_osc_clk_scg_en disable
hssi_pldadapt_rx_phcomp_rd_del phcomp_rd_del2
hssi_pldadapt_rx_pipe_enable disable
hssi_pldadapt_rx_pipe_mode disable_pipe
hssi_pldadapt_rx_hdpldadapt_pld_avmm1_clk_rowclk_hz 0
hssi_pldadapt_rx_hdpldadapt_pld_avmm2_clk_rowclk_hz 0
hssi_pldadapt_rx_pld_clk1_delay_en enable
hssi_pldadapt_rx_pld_clk1_delay_sel delay_path0
hssi_pldadapt_rx_pld_clk1_inv_en disable
hssi_pldadapt_rx_pld_clk1_sel pld_clk1_rowclk
hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_dcm_hz 0
hssi_pldadapt_rx_hdpldadapt_pld_rx_clk1_rowclk_hz 0
hssi_pldadapt_rx_hdpldadapt_pld_sclk1_rowclk_hz 0
hssi_pldadapt_rx_hdpldadapt_pld_sclk2_rowclk_hz 0
hssi_pldadapt_rx_pma_hclk_scg_en enable
hssi_pldadapt_rx_powerdown_mode false
hssi_pldadapt_rx_powermode_dc powerup
hssi_pldadapt_rx_powermode_freq_hz_aib_fabric_rx_sr_clk_in 900000000
hssi_pldadapt_rx_powermode_freq_hz_pld_rx_clk1_dcm 310000000
hssi_pldadapt_rx_rx_datapath_tb_sel cp_bond
hssi_pldadapt_rx_rx_fastbond_rden rden_ds_fast_us_fast
hssi_pldadapt_rx_rx_fastbond_wren wren_ds_del_us_del
hssi_pldadapt_rx_rx_fifo_power_mode full_width_ps_sw
hssi_pldadapt_rx_rx_fifo_read_latency_adjust disable
hssi_pldadapt_rx_rx_fifo_write_ctrl blklock_ignore
hssi_pldadapt_rx_rx_fifo_write_latency_adjust disable
hssi_pldadapt_rx_rx_osc_clock_setting osc_clk_div_by1
hssi_pldadapt_rx_rx_pld_8g_eidleinfersel_polling_bypass disable
hssi_pldadapt_rx_rx_pld_pma_eye_monitor_polling_bypass disable
hssi_pldadapt_rx_rx_pld_pma_pcie_switch_polling_bypass disable
hssi_pldadapt_rx_rx_pld_pma_reser_out_polling_bypass disable
hssi_pldadapt_rx_rx_prbs_flags_sr_enable disable
hssi_pldadapt_rx_rx_true_b2b b2b
hssi_pldadapt_rx_rx_usertest_sel enable
hssi_pldadapt_rx_rxfifo_empty empty_sw
hssi_pldadapt_rx_rxfifo_full full_pc_sw
hssi_pldadapt_rx_rxfifo_mode rxphase_comp
hssi_pldadapt_rx_rxfifo_pempty 2
hssi_pldadapt_rx_rxfifo_pfull 5
hssi_pldadapt_rx_rxfiford_post_ct_sel rxfiford_sclk_post_ct
hssi_pldadapt_rx_rxfifowr_post_ct_sel rxfifowr_sclk_post_ct
hssi_pldadapt_rx_sclk_sel sclk1_rowclk
hssi_pldadapt_rx_hdpldadapt_speed_grade dash_3
hssi_pldadapt_rx_hdpldadapt_sr_sr_testbus_sel ssr_testbus
hssi_pldadapt_rx_stretch_num_stages one_stage
hssi_pldadapt_rx_sup_mode user_mode
hssi_pldadapt_rx_txfiford_post_ct_sel txfiford_sclk_post_ct
hssi_pldadapt_rx_txfifowr_post_ct_sel txfifowr_sclk_post_ct
hssi_pldadapt_rx_us_bypass_pipeln us_bypass_pipeln_dis
hssi_pldadapt_rx_us_last_chnl us_last_chnl
hssi_pldadapt_rx_us_master us_master_en
hssi_pldadapt_rx_word_align wa_dis
hssi_pldadapt_rx_word_align_enable disable
hssi_pldadapt_rx_silicon_rev 10nm6bcr3a
hssi_pldadapt_rx_reconfig_settings {}
hssi_pldadapt_tx_aib_clk1_sel aib_clk1_pma_aib_tx_clk
hssi_pldadapt_tx_aib_clk2_sel aib_clk2_pld_pcs_tx_clk_out
hssi_pldadapt_tx_hdpldadapt_aib_fabric_pld_pma_hclk_hz 0
hssi_pldadapt_tx_hdpldadapt_aib_fabric_pma_aib_tx_clk_hz 805664062
hssi_pldadapt_tx_hdpldadapt_aib_fabric_tx_sr_clk_in_hz 0
hssi_pldadapt_tx_bonding_dft_en dft_dis
hssi_pldadapt_tx_bonding_dft_val dft_0
hssi_pldadapt_tx_chnl_bonding disable
hssi_pldadapt_tx_comp_cnt 0
hssi_pldadapt_tx_compin_sel compin_master
hssi_pldadapt_tx_hdpldadapt_csr_clk_hz 0
hssi_pldadapt_tx_ctrl_plane_bonding individual
hssi_pldadapt_tx_ds_bypass_pipeln ds_bypass_pipeln_dis
hssi_pldadapt_tx_ds_last_chnl ds_last_chnl
hssi_pldadapt_tx_ds_master ds_master_en
hssi_pldadapt_tx_duplex_mode disable
hssi_pldadapt_tx_dv_bond dv_bond_dis
hssi_pldadapt_tx_dv_gen dv_gen_dis
hssi_pldadapt_tx_fifo_double_write fifo_double_write_en
hssi_pldadapt_tx_fifo_mode phase_comp
hssi_pldadapt_tx_fifo_rd_clk_frm_gen_scg_en enable
hssi_pldadapt_tx_fifo_rd_clk_scg_en disable
hssi_pldadapt_tx_fifo_rd_clk_sel fifo_rd_pma_aib_tx_clk
hssi_pldadapt_tx_fifo_stop_rd rd_empty
hssi_pldadapt_tx_fifo_stop_wr wr_full
hssi_pldadapt_tx_fifo_width fifo_double_width
hssi_pldadapt_tx_fifo_wr_clk_scg_en disable
hssi_pldadapt_tx_fpll_shared_direct_async_in_sel fpll_shared_direct_async_in_rowclk
hssi_pldadapt_tx_frmgen_burst frmgen_burst_dis
hssi_pldadapt_tx_frmgen_bypass frmgen_bypass_en
hssi_pldadapt_tx_frmgen_mfrm_length 2048
hssi_pldadapt_tx_frmgen_pipeln frmgen_pipeln_en
hssi_pldadapt_tx_frmgen_pyld_ins frmgen_pyld_ins_dis
hssi_pldadapt_tx_frmgen_wordslip frmgen_wordslip_dis
hssi_pldadapt_tx_fsr_hip_fsr_in_bit0_rst_val reset_to_one_hfsrin0
hssi_pldadapt_tx_fsr_hip_fsr_in_bit1_rst_val reset_to_one_hfsrin1
hssi_pldadapt_tx_fsr_hip_fsr_in_bit2_rst_val reset_to_one_hfsrin2
hssi_pldadapt_tx_fsr_hip_fsr_in_bit3_rst_val reset_to_zero_hfsrin3
hssi_pldadapt_tx_fsr_hip_fsr_out_bit0_rst_val reset_to_one_hfsrout0
hssi_pldadapt_tx_fsr_hip_fsr_out_bit1_rst_val reset_to_one_hfsrout1
hssi_pldadapt_tx_fsr_hip_fsr_out_bit2_rst_val reset_to_zero_hfsrout2
hssi_pldadapt_tx_fsr_hip_fsr_out_bit3_rst_val reset_to_zero_hfsrout3
hssi_pldadapt_tx_fsr_mask_tx_pll_rst_val reset_to_zero_maskpll
hssi_pldadapt_tx_fsr_pld_txelecidle_rst_val reset_to_zero_txelec
hssi_pldadapt_tx_gb_tx_idwidth idwidth_64
hssi_pldadapt_tx_gb_tx_odwidth odwidth_64
hssi_pldadapt_tx_hip_mode disable_hip
hssi_pldadapt_tx_hip_osc_clk_scg_en disable
hssi_pldadapt_tx_hrdrst_dcd_cal_done_bypass disable
hssi_pldadapt_tx_hrdrst_rst_sm_dis enable_tx_rst_sm
hssi_pldadapt_tx_hrdrst_rx_osc_clk_scg_en disable
hssi_pldadapt_tx_hrdrst_user_ctl_en disable
hssi_pldadapt_tx_indv indv_en
hssi_pldadapt_tx_is_paired_with other
hssi_pldadapt_tx_loopback_mode disable
hssi_pldadapt_tx_low_latency_en disable
hssi_pldadapt_tx_osc_clk_scg_en disable
hssi_pldadapt_tx_phcomp_rd_del phcomp_rd_del3
hssi_pldadapt_tx_pipe_mode disable_pipe
hssi_pldadapt_tx_hdpldadapt_pld_avmm1_clk_rowclk_hz 0
hssi_pldadapt_tx_hdpldadapt_pld_avmm2_clk_rowclk_hz 0
hssi_pldadapt_tx_pld_clk1_delay_en enable
hssi_pldadapt_tx_pld_clk1_delay_sel delay_path3
hssi_pldadapt_tx_pld_clk1_inv_en disable
hssi_pldadapt_tx_pld_clk1_sel pld_clk1_dcm
hssi_pldadapt_tx_pld_clk2_sel pld_clk2_dcm
hssi_pldadapt_tx_hdpldadapt_pld_sclk1_rowclk_hz 0
hssi_pldadapt_tx_hdpldadapt_pld_sclk2_rowclk_hz 0
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_dcm_hz 402832031
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk1_rowclk_hz 402832031
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_dcm_hz 0
hssi_pldadapt_tx_hdpldadapt_pld_tx_clk2_rowclk_hz 0
hssi_pldadapt_tx_pma_aib_tx_clk_expected_setting x2
hssi_pldadapt_tx_powerdown_mode false
hssi_pldadapt_tx_powermode_dc powerup
hssi_pldadapt_tx_powermode_freq_hz_aib_fabric_rx_sr_clk_in 900000000
hssi_pldadapt_tx_powermode_freq_hz_pld_tx_clk1_dcm 402832031
hssi_pldadapt_tx_sh_err sh_err_dis
hssi_pldadapt_tx_hdpldadapt_speed_grade dash_3
hssi_pldadapt_tx_hdpldadapt_sr_sr_testbus_sel ssr_testbus
hssi_pldadapt_tx_stretch_num_stages two_stage
hssi_pldadapt_tx_sup_mode user_mode
hssi_pldadapt_tx_tx_datapath_tb_sel cp_bond
hssi_pldadapt_tx_tx_fastbond_rden rden_ds_fast_us_fast
hssi_pldadapt_tx_tx_fastbond_wren wren_ds_fast_us_fast
hssi_pldadapt_tx_tx_fifo_power_mode full_width_ps_dw
hssi_pldadapt_tx_tx_fifo_read_latency_adjust disable
hssi_pldadapt_tx_tx_fifo_write_latency_adjust disable
hssi_pldadapt_tx_tx_hip_aib_ssr_in_polling_bypass disable
hssi_pldadapt_tx_tx_osc_clock_setting osc_clk_div_by1
hssi_pldadapt_tx_tx_pld_10g_tx_bitslip_polling_bypass disable
hssi_pldadapt_tx_tx_pld_8g_tx_boundary_sel_polling_bypass disable
hssi_pldadapt_tx_tx_pld_pma_fpll_cnt_sel_polling_bypass disable
hssi_pldadapt_tx_tx_pld_pma_fpll_num_phase_shifts_polling_bypass disable
hssi_pldadapt_tx_tx_usertest_sel enable
hssi_pldadapt_tx_txfifo_empty empty_default
hssi_pldadapt_tx_txfifo_full full_pc_dw
hssi_pldadapt_tx_txfifo_mode txphase_comp
hssi_pldadapt_tx_txfifo_pempty 2
hssi_pldadapt_tx_txfifo_pfull 10
hssi_pldadapt_tx_us_bypass_pipeln us_bypass_pipeln_dis
hssi_pldadapt_tx_us_last_chnl us_last_chnl
hssi_pldadapt_tx_us_master us_master_en
hssi_pldadapt_tx_word_align_enable enable
hssi_pldadapt_tx_word_mark wm_en
hssi_pldadapt_tx_silicon_rev 10nm6bcr3a
hssi_pldadapt_tx_reconfig_settings {}
hssi_rsfec_clocking_mode no_clk
hssi_rsfec_core_eng_2lane_ena false
hssi_rsfec_core_eng_am_5bad_dis 0
hssi_rsfec_core_eng_blk_chk_dis 0
hssi_rsfec_core_eng_cons_25g 0
hssi_rsfec_core_eng_cust_am_1st_0 0
hssi_rsfec_core_eng_cust_am_1st_1 0
hssi_rsfec_core_eng_cust_am_1st_2 0
hssi_rsfec_core_eng_cust_am_1st_3 0
hssi_rsfec_core_eng_cust_am_2nd_0 0
hssi_rsfec_core_eng_cust_am_2nd_1 0
hssi_rsfec_core_eng_cust_am_2nd_2 0
hssi_rsfec_core_eng_cust_am_2nd_3 0
hssi_rsfec_core_eng_cust_am_en 0
hssi_rsfec_core_eng_cust_log2_mrk 0
hssi_rsfec_core_eng_enter_align 0
hssi_rsfec_core_eng_exit_align 0
hssi_rsfec_core_eng_fec_3bad_dis 0
hssi_rsfec_core_eng_sf_dis 0
hssi_rsfec_core_eng_swaps 0
hssi_rsfec_core_eng_test 0
hssi_rsfec_core_eng_trans_byp 0
hssi_rsfec_core_fibre_channel0 false
hssi_rsfec_core_fibre_channel1 false
hssi_rsfec_core_fibre_channel2 false
hssi_rsfec_core_fibre_channel3 false
hssi_rsfec_core_indic_byp 0
hssi_rsfec_core_rs544_0 false
hssi_rsfec_core_rs544_1 false
hssi_rsfec_core_rs544_2 false
hssi_rsfec_core_rs544_3 false
hssi_rsfec_core_scrambling0 false
hssi_rsfec_core_scrambling1 false
hssi_rsfec_core_scrambling2 false
hssi_rsfec_core_scrambling3 false
hssi_rsfec_core_tx_pcs_bypass0 false
hssi_rsfec_core_tx_pcs_bypass1 false
hssi_rsfec_core_tx_pcs_bypass2 false
hssi_rsfec_core_tx_pcs_bypass3 false
hssi_rsfec_deskew_channels_active dsk_ln_none
hssi_rsfec_deskew_channels_clear false
hssi_rsfec_fec_tx2rx_loopback0 tx_rx_loopback_none0
hssi_rsfec_fec_tx2rx_loopback1 tx_rx_loopback_none1
hssi_rsfec_fec_tx2rx_loopback2 tx_rx_loopback_none2
hssi_rsfec_fec_tx2rx_loopback3 tx_rx_loopback_none3
hssi_rsfec_first_lane_sel first_lane0
hssi_rsfec_force_deskew_done false
hssi_rsfec_force_fec_ready false
hssi_rsfec_func_mode disabled
hssi_rsfec_hwcfg_ena false
hssi_rsfec_hwcfg_mode 0
hssi_rsfec_lane_func_mode0 lane_mode_disable0
hssi_rsfec_lane_func_mode1 lane_mode_disable1
hssi_rsfec_lane_func_mode2 lane_mode_disable2
hssi_rsfec_lane_func_mode3 lane_mode_disable3
hssi_rsfec_operation_mode oper_aggr
hssi_rsfec_powerdown_mode true
hssi_rsfec_source_clk_sel adp0_clk
hssi_rsfec_source_lane_ena0 false
hssi_rsfec_source_lane_ena1 false
hssi_rsfec_source_lane_ena2 false
hssi_rsfec_source_lane_ena3 false
hssi_rsfec_spare_bits 0
hssi_rsfec_sup_mode user_mode
hssi_rsfec_topology pmadir_pllch
hssi_rsfec_tx_data_source_sel0 fec_tx_lane_off0
hssi_rsfec_tx_data_source_sel1 fec_tx_lane_off1
hssi_rsfec_tx_data_source_sel2 fec_tx_lane_off2
hssi_rsfec_tx_data_source_sel3 fec_tx_lane_off3
hssi_rsfec_silicon_rev 10nm6bcr3a
hssi_rsfec_u_rsfec_rx_mux0_rx_data_source xcvr_rx_data
hssi_rsfec_u_rsfec_rx_mux1_rx_data_source xcvr_rx_data
hssi_rsfec_u_rsfec_rx_mux2_rx_data_source xcvr_rx_data
hssi_rsfec_u_rsfec_rx_mux3_rx_data_source xcvr_rx_data
hssi_rsfecrx_mux_rx_data_source xcvr_rx_data
hssi_rsfecrx_mux_silicon_rev 10nm6bcr3a
hssi_xcvr_an_mode an_mode_dis
hssi_xcvr_bonding_mode nonbonded
hssi_xcvr_bti_protected false
hssi_xcvr_cfg_c_revbitorder rev_bit_order_false
hssi_xcvr_cfg_clk_en_div66_tx tx_clk_en_div66_dis
hssi_xcvr_cfg_clk_en_sclk_rx det_lat_dis_sclk_rx
hssi_xcvr_cfg_clk_en_sclk_tx det_lat_tx_sclk_dis
hssi_xcvr_cfg_core_int_request core_int_req_dis
hssi_xcvr_cfg_dcc_csr_core_rst_en dcc_core_rst_dis
hssi_xcvr_cfg_dcc_csr_dft_msel 0
hssi_xcvr_cfg_dcc_csr_dll_sel dcc_dll_follow_fsm
hssi_xcvr_cfg_dcc_csr_dly_ovr 0
hssi_xcvr_cfg_dcc_csr_dly_ovr_10 dcc_dly_ovr_msb_0
hssi_xcvr_cfg_dcc_csr_dn_invert dcc_no_invert_dn
hssi_xcvr_cfg_dcc_csr_en_fsm dcc_dis_fsm
hssi_xcvr_cfg_dcc_csr_mux_sel dcc_req_sel_adapter
hssi_xcvr_cfg_dcc_csr_resv 0
hssi_xcvr_cfg_dcc_csr_resv_10 dcc_resv_msb_0
hssi_xcvr_cfg_dcc_csr_rst_invert dcc_no_invert_rst
hssi_xcvr_cfg_dcc_csr_up_invert dcc_no_invert_up
hssi_xcvr_cfg_dcc_csr_updn_en dcc_updn_dis
hssi_xcvr_cfg_hw_mode_sel hwdec_disabled_block
hssi_xcvr_cfg_idll_entest dcc_test_dis
hssi_xcvr_cfg_mem_pbist 0
hssi_xcvr_cfg_mem_ulp_tmg_mode 726
hssi_xcvr_cfg_rb_clkdiv dcc_ckdiv_16
hssi_xcvr_cfg_rb_cont_cal dcc_cont_cal_dis
hssi_xcvr_cfg_rb_dcc_byp dcc_byp_en
hssi_xcvr_cfg_rb_dcc_dft dcc_dft_dis
hssi_xcvr_cfg_rb_dcc_dft_sel dcc_dft_mode0
hssi_xcvr_cfg_rb_dcc_en dcc_mast_dis
hssi_xcvr_cfg_rb_dcc_manual_dn 0
hssi_xcvr_cfg_rb_dcc_manual_up 0
hssi_xcvr_cfg_rb_dcc_req dcc_req_dis
hssi_xcvr_cfg_rb_dcc_req_ovr dcc_req_no_ovr
hssi_xcvr_cfg_rb_half_code dcc_en_half_code
hssi_xcvr_cfg_rb_nfrzdrv dcc_freeze
hssi_xcvr_cfg_rb_selflock dcc_en_cntr_lock
hssi_xcvr_cfg_reset_rx_bit_counter reset_rxbit_cnt
hssi_xcvr_cfg_restart_seq_sm seq_sm_idle
hssi_xcvr_cfg_revbitorder rev_bit_order_dis
hssi_xcvr_cfg_rx_bit_counter_rollover 0
hssi_xcvr_cfg_rx_fifo_lat_en 0
hssi_xcvr_cfg_rx_pcs_data_sel sel_rx_fifo_data
hssi_xcvr_cfg_rxbit_cntr_pma sel_async_cnt_fec
hssi_xcvr_cfg_sel_bit_counter_adder ser_fact_dis
hssi_xcvr_cfg_sel_hw_decode_mode hwdec_disable
hssi_xcvr_cfg_tbus_sel tbus_sel_zero
hssi_xcvr_cfg_test_clk_pll_en_n dcc_tclk_pll_dis
hssi_xcvr_cfg_tx_fifo_lat_en 0
hssi_xcvr_channel_mode xcvr_txonly
hssi_xcvr_clk_en_direct_tx dis_tx_direct_clk
hssi_xcvr_clk_en_div66_rx dis_rx_div66_clk
hssi_xcvr_clk_en_ehip_d2_tx dis_tx_ehip_clk
hssi_xcvr_clk_en_fec_d2_tx dis_tx_fec_clk
hssi_xcvr_clk_en_fifo_rd_rx dis_rx_fifo_rd_clk
hssi_xcvr_clk_en_fifo_rx dis_fifo_clk_rx
hssi_xcvr_clk_en_full_rx dis_rx_full_clk
hssi_xcvr_clk_en_full_tx en_tx_full_clk
hssi_xcvr_clk_en_half_rx dis_rx_half_clk
hssi_xcvr_clk_en_pcs_d2_tx dis_tx_pcs_clk
hssi_xcvr_clk_en_rx dis_rx_clk
hssi_xcvr_clk_en_rx_adapt dis_rx_adapt_clk
hssi_xcvr_clk_en_tx en_tx_clk
hssi_xcvr_clk_en_tx_datapath dis_tx_datapath_clk
hssi_xcvr_clk_en_tx_gbx dis_tx_gb_clk
hssi_xcvr_en_tx_deskew dis_tx_deskew
hssi_xcvr_enable_lowpower_mode false
hssi_xcvr_func_mode xcvr_pll
hssi_xcvr_int_core_to_cntl 0
hssi_xcvr_int_if_code 0
hssi_xcvr_int_if_data 0
hssi_xcvr_int_seq10_txeq_amp 0
hssi_xcvr_int_seq11_txeq_post 0
hssi_xcvr_int_seq12_txeq_broadcast 0
hssi_xcvr_int_seq13_rx_pll_recal rx_pll_recal_en
hssi_xcvr_int_seq13_tx_pll_recal tx_pll_recal_en
hssi_xcvr_int_seq1_tx_clk_slip_cnt 0
hssi_xcvr_int_seq1_tx_phase_load_cnt 0
hssi_xcvr_int_seq1_tx_slip_always_on dis_tx_always_on
hssi_xcvr_int_seq2_rx_clk_slip_cnt 28
hssi_xcvr_int_seq2_rx_phase_load_cnt 0
hssi_xcvr_int_seq2_rx_slip_always_on en_rx_always_on
hssi_xcvr_int_seq3_refclk_cfg_both refclk_cfg_tx
hssi_xcvr_int_seq3_refclk_sync_master refclk_sync_master
hssi_xcvr_int_seq3_tx_bit_rate tx_full_rate
hssi_xcvr_int_seq3_tx_refclk_ratio 165
hssi_xcvr_int_seq3_txpll_refclk_sel tx_refclk_sel_rck0
hssi_xcvr_int_seq4_refclk_cfg_both refclk_cfg_rx
hssi_xcvr_int_seq4_rx_bit_rate rx_full_rate
hssi_xcvr_int_seq4_rx_refclk_ratio 8
hssi_xcvr_int_seq4_rxpll_refclk_sel rx_refclk_sel_rck0
hssi_xcvr_int_seq5_ph_opt dis_phase_opt
hssi_xcvr_int_seq6_rx_sr_enc rx_enc_is_nrz
hssi_xcvr_int_seq6_rx_width rx_width_32b
hssi_xcvr_int_seq6_tx_sr_enc tx_enc_is_nrz
hssi_xcvr_int_seq6_tx_width tx_width_32b
hssi_xcvr_int_seq7_txeq_pre1 0
hssi_xcvr_int_seq8_txeq_slew 0
hssi_xcvr_int_seq9_txeq_atten 0
hssi_xcvr_interrupt_cntl_ovr_en aib_ovr_if_cntl
hssi_xcvr_interrupt_core_stat_sel_msw sel_core_stat_msw
hssi_xcvr_interrupt_in_prog_assert dis_int_in_prog_assert
hssi_xcvr_interrupt_window_enable en_window_logic
hssi_xcvr_interrupt_window_grpid int_if_en_grp0
hssi_xcvr_is_dyn_reconfigurable false
hssi_xcvr_lpbk_mode lpbk_disable
hssi_xcvr_powerdown_mode false
hssi_xcvr_powermode_ac_avmm_freq_hz 150000000
hssi_xcvr_powermode_ac_csr ac_xcvr_csr_on
hssi_xcvr_powermode_ac_serdes_rx ac_rx_serdes_pll_only
hssi_xcvr_powermode_ac_serdes_rx_enc_par_freq_hz 0
hssi_xcvr_powermode_ac_serdes_rx_par_freq_hz 0
hssi_xcvr_powermode_ac_serdes_rx_ui_freq_hz 0
hssi_xcvr_powermode_ac_serdes_tx ac_tx_serdes_pll_only
hssi_xcvr_powermode_ac_serdes_tx_enc_par_freq_hz 805664062
hssi_xcvr_powermode_ac_serdes_tx_par_freq_hz 805664062
hssi_xcvr_powermode_ac_serdes_tx_ui_freq_hz 25781250000
hssi_xcvr_powermode_ac_xcvrif_rx ac_rxif_off
hssi_xcvr_powermode_ac_xcvrif_tx ac_txif_off
hssi_xcvr_powermode_dc_csr dc_xcvr_csr_on
hssi_xcvr_powermode_dc_serdes_rx powerdown_dc_rx_serdes
hssi_xcvr_powermode_dc_serdes_tx dc_tx_serdes_on
hssi_xcvr_powermode_dc_xcvrif_rx powerdown_dc_rxif
hssi_xcvr_powermode_dc_xcvrif_tx dc_txif_on
hssi_xcvr_rst_en_rx rx_dis_ehip_fec_pcs
hssi_xcvr_rx_adapt_order_sel rx_adapt_order_sel_0
hssi_xcvr_rx_adapter_sel rx_adapter_sel_data_reg
hssi_xcvr_rx_bitslip dis_rx_user_bitslip
hssi_xcvr_rx_c_revbitorder dis_rx_c_revbitorder
hssi_xcvr_rx_datarate_bps 1000000000
hssi_xcvr_rx_det_latency_en rx_det_dis
hssi_xcvr_rx_fifo_clk_sel fifo_clk_sel3
hssi_xcvr_rx_gb_idwidth rx_gb_idwidth_64b
hssi_xcvr_rx_gb_mode rx_gb_64_64
hssi_xcvr_rx_gb_odwidth rx_gb_odwidth_64b
hssi_xcvr_rx_interleave_mode rx_il_disable
hssi_xcvr_rx_ml_sel rx_ml_sel_0
hssi_xcvr_rx_pma_width rx_width_32
hssi_xcvr_rx_pma_width_sd 32
hssi_xcvr_rx_rden_sel rden_frm_fifo
hssi_xcvr_rx_refclk_freq 125000000
hssi_xcvr_rx_revbitorder dis_rx_revbitorder
hssi_xcvr_rx_sh_location rx_sh_location_1_0
hssi_xcvr_rx_tag_sel rx_tag_sel_b67
hssi_xcvr_rx_width_adapt rx_width_adp_dis
hssi_xcvr_rxfifo_ae_thld 1
hssi_xcvr_rxfifo_af_thld 2
hssi_xcvr_rxfifo_e_thld 0
hssi_xcvr_rxfifo_f_thld 31
hssi_xcvr_rxfifo_rd_empty allow_rd_rx_fifo_empty
hssi_xcvr_rxfifo_wr_full allow_wr_rx_fifo_full
hssi_xcvr_seq_en_bitwidth en_bitwidth_seq
hssi_xcvr_seq_en_crc dis_crc_seq
hssi_xcvr_seq_en_phaseopt dis_ph_opt_seq
hssi_xcvr_seq_en_reserved1 dis_reserved1_seq
hssi_xcvr_seq_en_reserved2 dis_reserved2_seq
hssi_xcvr_seq_en_reserved3 dis_reserved3_seq
hssi_xcvr_seq_en_reserved4 dis_reserved4_seq
hssi_xcvr_seq_en_reserved5 dis_reserved5_seq
hssi_xcvr_seq_en_reserved6 dis_reserved6_seq
hssi_xcvr_seq_en_reserved7 dis_reserved7_seq
hssi_xcvr_seq_en_rx_bitrate dis_rx_bitrate_seq
hssi_xcvr_seq_en_rx_phase_slip en_rx_phase_slip_seq
hssi_xcvr_seq_en_tx_amp dis_tx_amp_seq
hssi_xcvr_seq_en_tx_atten dis_tx_atten_seq
hssi_xcvr_seq_en_tx_bitrate en_tx_bitrate_seq
hssi_xcvr_seq_en_tx_broadcast dis_tx_broadcast_seq
hssi_xcvr_seq_en_tx_phase_slip dis_tx_phase_slip_seq
hssi_xcvr_seq_en_tx_post1 dis_tx_post1_seq
hssi_xcvr_seq_en_tx_pre1 dis_tx_pre1_seq
hssi_xcvr_seq_en_tx_slew dis_tx_slew_seq
hssi_xcvr_serdes_en_seq en_serdes_seq
hssi_xcvr_serdes_grp_id grp0
hssi_xcvr_serdes_rx_enc rx_nrz
hssi_xcvr_serdes_tx_enc tx_nrz
hssi_xcvr_set_int_seq0 set_int_seq0
hssi_xcvr_set_int_seq1 set_int_seq1
hssi_xcvr_set_int_seq10 set_int_seq10
hssi_xcvr_set_int_seq11 set_int_seq11
hssi_xcvr_set_int_seq12 set_int_seq12
hssi_xcvr_set_int_seq13 set_int_seq13
hssi_xcvr_set_int_seq14_code 0
hssi_xcvr_set_int_seq14_data 0
hssi_xcvr_set_int_seq15_code 0
hssi_xcvr_set_int_seq15_data 0
hssi_xcvr_set_int_seq16_code 0
hssi_xcvr_set_int_seq16_data 0
hssi_xcvr_set_int_seq17_code 0
hssi_xcvr_set_int_seq17_data 0
hssi_xcvr_set_int_seq18_code 0
hssi_xcvr_set_int_seq18_data 0
hssi_xcvr_set_int_seq19_code 0
hssi_xcvr_set_int_seq19_data 0
hssi_xcvr_set_int_seq2 set_int_seq2
hssi_xcvr_set_int_seq3 set_int_seq3
hssi_xcvr_set_int_seq4 set_int_seq4
hssi_xcvr_set_int_seq5 set_int_seq5
hssi_xcvr_set_int_seq6 set_int_seq6
hssi_xcvr_set_int_seq7 set_int_seq7
hssi_xcvr_set_int_seq8 set_int_seq8
hssi_xcvr_set_int_seq9 set_int_seq9
hssi_xcvr_set_int_seq_serd_en seq_en_tx_rx
hssi_xcvr_set_refclk_scratch0 i_refclk0
hssi_xcvr_set_refclk_scratch1 i_refclk1
hssi_xcvr_set_refclk_scratch2 i_refclk2
hssi_xcvr_set_refclk_scratch3 i_refclk3
hssi_xcvr_set_refclk_sel i_refclk0
hssi_xcvr_sh_location tx_sh_location_1_0
hssi_xcvr_soft_reset_rx dis_sft_rst_rx
hssi_xcvr_soft_reset_tx dis_sft_rst_tx
hssi_xcvr_sup_mode user_mode
hssi_xcvr_topology pmadir_pllch
hssi_xcvr_tx_adapt_order_sel tx_adapt_order_sel_0
hssi_xcvr_tx_bitslip dis_tx_user_bitslip
hssi_xcvr_tx_clk_dp_sel tx_clk_dp_sel_0
hssi_xcvr_tx_clk_out_sel tx_clk_out_sel_0
hssi_xcvr_tx_data_in_sel tx_data_in_sel_0
hssi_xcvr_tx_datarate_bps 25781250000
hssi_xcvr_tx_deskew tx_dsk_dis
hssi_xcvr_tx_det_latency_en tx_det_dis
hssi_xcvr_tx_dskew_ml_sel ml_dsk_sel_ckb_above_ckb_below
hssi_xcvr_tx_gb_idwidth tx_gb_idwidth_64b
hssi_xcvr_tx_gb_mode tx_gb_64_64
hssi_xcvr_tx_gb_odwidth tx_gb_odwidth_64b
hssi_xcvr_tx_if_slv_bonding_config dis_tx_if_slv_bonding_config
hssi_xcvr_tx_interleave_mode tx_il_disable
hssi_xcvr_tx_ml_sel tx_ml_sel_0
hssi_xcvr_tx_pma_width tx_width_32
hssi_xcvr_tx_pma_width_sd 32
hssi_xcvr_tx_refclk_freq 156250000
hssi_xcvr_tx_reset_val_31_0 0
hssi_xcvr_tx_reset_val_63_32 0
hssi_xcvr_tx_reset_val_66_64 0
hssi_xcvr_tx_width_adapt tx_width_adp_dis
hssi_xcvr_txfifo_ae_thld 1
hssi_xcvr_txfifo_af_thld 20
hssi_xcvr_txfifo_e_thld 0
hssi_xcvr_txfifo_f_thld 31
hssi_xcvr_txfifo_ph_comp dis_ph_comp
hssi_xcvr_txfifo_rd_empty allow_rd_tx_fifo_empty
hssi_xcvr_txfifo_wr_full allow_wr_tx_fifo_full
hssi_xcvr_xcvr_spare_ctrl0 0
hssi_xcvr_xcvr_spare_ctrl1 0
hssi_xcvr_silicon_rev 10nm6bcr3a
hssi_xcvr_set_refclk_scratch4 i_refclk4
hssi_xcvr_refclk_mux_powerdown_mode false
hssi_xcvr_refclk_mux_refclk0_sel i_refclk0
hssi_xcvr_refclk_mux_topology disabled_block
hssi_xcvr_refclk_mux_silicon_rev 10nm6bcr3a
message_level error
protocol_mode pll
user_preserve_unused_xcvr_channels 0
user_bti_channel_clock_select 0
user_bti_channel_ref_clock_freq_mhz 100
enable_manual_reset 0
reduced_sim_time 1
reduced_reset_sim_time 0
enable_ind_txrx 0
enable_ind_channel 0
enable_port_latency_measurement 0
pll_refclk_cnt 1
pll_select 0
pll_outclk_freq_mhz 805.6640625
pll_outclk2_freq_mhz 402.83203125
pll_refclk_freq_mhz 156.250000
pma_example_qsf_strings 0
user_set_int_seq_serd_en seq_en_tx_rx
user_set_serdes_en_seq en_serdes_seq
pma_tx_modulation NRZ
pma_tx_data_rate 25781.25
pma_tx_clkdiv66_enable 1
pma_tx_bonding_enable 0
pma_tx_pll_post_divider 1
pma_tx_pll_refclk_freq_mhz 156.250000
pldif_tx_fast_pipeln_reg_enable 0
pldif_tx_fifo_mode phase_comp
pldif_tx_fifo_pfull_thld 10
pldif_tx_fifo_pempty_thld 2
pldif_tx_double_width_transfer_enable 1
enable_port_tx_fifo_full 0
enable_port_tx_fifo_empty 0
enable_port_tx_fifo_pfull 0
enable_port_tx_fifo_pempty 0
enable_port_tx_dll_lock 0
pldif_tx_clkout_sel half-rate
enable_port_tx_clkout2 1
pldif_tx_clkout2_sel full-rate
pldif_tx_coreclkin_clock_network dedicated
pldif_tx_coreclkin2_external_clk_enable 0
enable_port_tx_clkin2 0
pldif_tx_coreclkin2_clock_network dedicated
pmaif_tx_width 32
enable_port_tx_enh_pmaif_fifo_almost_full 0
enable_port_tx_enh_pmaif_fifo_almost_empty 0
enable_port_tx_enh_pmaif_fifo_overflow 0
enable_port_tx_enh_pmaif_fifo_underflow 0
qsf_assignments_list
design_example_filename top
rcfg_shared 0
validation_rule_select
internal_derived_parameter_select l_is_loopback_mode_enabled
rcp_load_enable 0
adpt_recipe_cnt 1
adpt_recipe_select 0
rcfg_enable 0
rcfg_jtag_enable 0
set_capability_reg_enable 0
set_user_identifier 0
set_csr_soft_logic_enable 0
rcfg_file_prefix altera_xcvr_rcfg_10
rcfg_sv_file_enable 0
rcfg_h_file_enable 0
rcfg_mif_file_enable 0
rcfg_multi_enable 0
set_rcfg_emb_strm_enable 0
rcfg_reduced_files_enable 0
rcfg_profile_cnt 2
rcfg_profile_select 1
rcfg_profile_data0
rcfg_profile_data1
rcfg_profile_data2
rcfg_profile_data3
rcfg_profile_data4
rcfg_profile_data5
rcfg_profile_data6
rcfg_profile_data7
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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