agilex_hps

2022.04.29.17:28:34 Datasheet
Overview

Memory Map
intel_agilex_hps_inst_arm_a9_0 intel_agilex_hps_inst_arm_a9_1
 altera_axi_master  altera_axi_master

intel_agilex_hps_inst

intel_agilex_hps v22.0.0


Parameters

MPU_EVENTS_Enable false
GP_Enable false
DEBUG_APB_Enable false
STM_Enable true
CTI_Enable false
DDR_ATB_Enable false
IPXACT_Enable false
F2S_mode 0
F2S_Width 5
F2S_ADDRESS_WIDTH 32
F2S_Route_config 1
S2F_Width 3
S2F_ADDRESS_WIDTH 32
LWH2F_Enable 1
LWH2F_ADDRESS_WIDTH 21
EMIF_CONDUIT_Enable true
EMIF_DDR_WIDTH 64
SMMU_sid_config 0
SMMU_ssd_config 0
DMA_PeriphId_DERIVED 0,1,2,3,4,5,6,7
DMA_Enable No,No,No,No,No,No,No,No
F2SINTERRUPT_Enable true
S2FINTERRUPT_CLOCKPERIPHERAL_Enable false
S2FINTERRUPT_DMA_Enable false
S2FINTERRUPT_EMAC0_Enable false
S2FINTERRUPT_EMAC1_Enable false
S2FINTERRUPT_EMAC2_Enable false
S2FINTERRUPT_GPIO_Enable false
S2FINTERRUPT_I2CEMAC0_Enable false
S2FINTERRUPT_I2CEMAC1_Enable false
S2FINTERRUPT_I2CEMAC2_Enable false
S2FINTERRUPT_I2C0_Enable false
S2FINTERRUPT_I2C1_Enable false
S2FINTERRUPT_L4TIMER_Enable false
S2FINTERRUPT_NAND_Enable false
S2FINTERRUPT_SYSTIMER_Enable false
S2FINTERRUPT_SDMMC_Enable false
S2FINTERRUPT_SPIM0_Enable false
S2FINTERRUPT_SPIM1_Enable false
S2FINTERRUPT_SPIS0_Enable false
S2FINTERRUPT_SPIS1_Enable false
S2FINTERRUPT_SYSTEMMANAGER_Enable false
S2FINTERRUPT_UART0_Enable false
S2FINTERRUPT_UART1_Enable false
S2FINTERRUPT_USB0_Enable false
S2FINTERRUPT_USB1_Enable false
S2FINTERRUPT_WATCHDOG_Enable false
eosc1_clk_mhz 25.0
F2H_FREE_CLK_Enable false
F2H_FREE_CLK_FREQ 200
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK 2.5
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK 125
FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK 125
DEFAULT_MPU_CLK 1200
USE_DEFAULT_MPU_CLK false
CUSTOM_MPU_CLK 800.0
H2F_USER0_CLK_Enable false
H2F_USER0_CLK_FREQ 500
H2F_USER1_CLK_Enable false
H2F_USER1_CLK_FREQ 500
L3_MAIN_FREE_CLK 400
L4_SYS_FREE_CLK 2
L4_SYS_FREE_CLK_HZ 100
NOCDIV_L4MAINCLK 0
NOCDIV_L4MAINCLK_HZ 400
NOCDIV_L4MPCLK 1
NOCDIV_L4MPCLK_HZ 200
NOCDIV_L4SPCLK 2
NOCDIV_L4SPCLK_HZ 100
NOCDIV_CS_ATCLK 0
NOCDIV_CS_ATCLK_HZ 400
NOCDIV_CS_PDBGCLK 2
NOCDIV_CS_PDBGCLK_HZ 100
NOCDIV_CS_TRACECLK 0
NOCDIV_CS_TRACECLK_HZ 400
HPS_DIV_GPIO_FREQ2 100
CONFIG_HPS_DIV_GPIO 1
EMAC0_CLK 250
EMAC1_CLK 250
EMAC2_CLK 250
MANUAL_PERPLL_CFREQ_EN false
MANUAL_PERPLL_C0 1200.0
MANUAL_PERPLL_C2 480.0
MANUAL_PERPLL_C3 200.0
CLK_MAIN_PLL_SOURCE2 0
CLK_PERI_PLL_SOURCE2 0
MANUAL_CLK_SRC_EN false
CLK_MPU_SOURCE 1
CLK_NOC_SOURCE 1
CLK_S2F_USER0_SOURCE 0
CLK_S2F_USER1_SOURCE 0
CLK_PSI_SOURCE 0
CLK_EMAC_PTP_SOURCE 1
CLK_GPIO_SOURCE 1
CLK_SDMMC_SOURCE 1
CLK_EMACA_SOURCE 0
CLK_EMACB_SOURCE 1
H2F_PENDING_RST_Enable false
H2F_COLD_RST_Enable false
watchdog_reset true
W_RESET_ACTION 0
IO_INPUT_DELAY0 0
IO_OUTPUT_DELAY0 0
IO_INPUT_DELAY1 0
IO_OUTPUT_DELAY1 0
IO_INPUT_DELAY2 0
IO_OUTPUT_DELAY2 0
IO_INPUT_DELAY3 0
IO_OUTPUT_DELAY3 0
IO_INPUT_DELAY4 0
IO_OUTPUT_DELAY4 0
IO_INPUT_DELAY5 0
IO_OUTPUT_DELAY5 0
IO_INPUT_DELAY6 0
IO_OUTPUT_DELAY6 0
IO_INPUT_DELAY7 0
IO_OUTPUT_DELAY7 0
IO_INPUT_DELAY8 0
IO_OUTPUT_DELAY8 0
IO_INPUT_DELAY9 0
IO_OUTPUT_DELAY9 0
IO_INPUT_DELAY10 0
IO_OUTPUT_DELAY10 0
IO_INPUT_DELAY11 0
IO_OUTPUT_DELAY11 0
IO_INPUT_DELAY12 0
IO_OUTPUT_DELAY12 45
IO_INPUT_DELAY13 0
IO_OUTPUT_DELAY13 0
IO_INPUT_DELAY14 0
IO_OUTPUT_DELAY14 0
IO_INPUT_DELAY15 0
IO_OUTPUT_DELAY15 0
IO_INPUT_DELAY16 0
IO_OUTPUT_DELAY16 0
IO_INPUT_DELAY17 0
IO_OUTPUT_DELAY17 0
IO_INPUT_DELAY18 0
IO_OUTPUT_DELAY18 0
IO_INPUT_DELAY19 0
IO_OUTPUT_DELAY19 0
IO_INPUT_DELAY20 0
IO_OUTPUT_DELAY20 0
IO_INPUT_DELAY21 0
IO_OUTPUT_DELAY21 0
IO_INPUT_DELAY22 0
IO_OUTPUT_DELAY22 0
IO_INPUT_DELAY23 0
IO_OUTPUT_DELAY23 0
IO_INPUT_DELAY24 0
IO_OUTPUT_DELAY24 0
IO_INPUT_DELAY25 0
IO_OUTPUT_DELAY25 0
IO_INPUT_DELAY26 0
IO_OUTPUT_DELAY26 0
IO_INPUT_DELAY27 0
IO_OUTPUT_DELAY27 0
IO_INPUT_DELAY28 0
IO_OUTPUT_DELAY28 0
IO_INPUT_DELAY29 0
IO_OUTPUT_DELAY29 0
IO_INPUT_DELAY30 0
IO_OUTPUT_DELAY30 0
IO_INPUT_DELAY31 0
IO_OUTPUT_DELAY31 0
IO_INPUT_DELAY32 0
IO_OUTPUT_DELAY32 0
IO_INPUT_DELAY33 0
IO_OUTPUT_DELAY33 0
IO_INPUT_DELAY34 0
IO_OUTPUT_DELAY34 0
IO_INPUT_DELAY35 0
IO_OUTPUT_DELAY35 0
IO_INPUT_DELAY36 0
IO_OUTPUT_DELAY36 0
IO_INPUT_DELAY37 0
IO_OUTPUT_DELAY37 0
IO_INPUT_DELAY38 0
IO_OUTPUT_DELAY38 0
IO_INPUT_DELAY39 0
IO_OUTPUT_DELAY39 0
IO_INPUT_DELAY40 0
IO_OUTPUT_DELAY40 0
IO_INPUT_DELAY41 0
IO_OUTPUT_DELAY41 0
IO_INPUT_DELAY42 0
IO_OUTPUT_DELAY42 0
IO_INPUT_DELAY43 0
IO_OUTPUT_DELAY43 0
IO_INPUT_DELAY44 0
IO_OUTPUT_DELAY44 0
IO_INPUT_DELAY45 0
IO_OUTPUT_DELAY45 0
IO_INPUT_DELAY46 0
IO_OUTPUT_DELAY46 0
IO_INPUT_DELAY47 0
IO_OUTPUT_DELAY47 0
HPS_IOA_1_open_drain_en false
HPS_IOA_2_open_drain_en false
HPS_IOA_3_open_drain_en false
HPS_IOA_4_open_drain_en false
HPS_IOA_5_open_drain_en false
HPS_IOA_6_open_drain_en false
HPS_IOA_7_open_drain_en false
HPS_IOA_8_open_drain_en false
HPS_IOA_9_open_drain_en false
HPS_IOA_10_open_drain_en false
HPS_IOA_11_open_drain_en false
HPS_IOA_12_open_drain_en false
HPS_IOA_13_open_drain_en false
HPS_IOA_14_open_drain_en false
HPS_IOA_15_open_drain_en false
HPS_IOA_16_open_drain_en false
HPS_IOA_17_open_drain_en false
HPS_IOA_18_open_drain_en false
HPS_IOA_19_open_drain_en false
HPS_IOA_20_open_drain_en false
HPS_IOA_21_open_drain_en false
HPS_IOA_22_open_drain_en false
HPS_IOA_23_open_drain_en false
HPS_IOA_24_open_drain_en false
HPS_IOB_1_open_drain_en false
HPS_IOB_2_open_drain_en false
HPS_IOB_3_open_drain_en false
HPS_IOB_4_open_drain_en false
HPS_IOB_5_open_drain_en false
HPS_IOB_6_open_drain_en false
HPS_IOB_7_open_drain_en false
HPS_IOB_8_open_drain_en false
HPS_IOB_9_open_drain_en false
HPS_IOB_10_open_drain_en false
HPS_IOB_11_open_drain_en false
HPS_IOB_12_open_drain_en false
HPS_IOB_13_open_drain_en false
HPS_IOB_14_open_drain_en false
HPS_IOB_15_open_drain_en false
HPS_IOB_16_open_drain_en false
HPS_IOB_17_open_drain_en false
HPS_IOB_18_open_drain_en false
HPS_IOB_19_open_drain_en false
HPS_IOB_20_open_drain_en false
HPS_IOB_21_open_drain_en false
HPS_IOB_22_open_drain_en false
HPS_IOB_23_open_drain_en false
HPS_IOB_24_open_drain_en false
EMAC0_PTP false
EMAC1_PTP false
EMAC2_PTP false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_fpga_interfaces

intel_agilex_interface_generator v19.1


Parameters

interfaceDefinition constraints {if\ \{\[get_collection_size\ \[get_nodes\ \ -nowarn\ hps_inst|s2f_module~l4_mp_clk\ \]\]\ >\ 0\}\ \{ {create_clock -name hps_l4_mp_clk_src -period 5.0 [get_nodes hps_inst|s2f_module~l4_mp_clk]} {create_generated_clock -divide_by 1 -name hps_l4_mp_clk [get_registers hps_inst|s2f_module~l4_mp_clk.reg] -master_clock [get_clocks hps_l4_mp_clk_src] -source [get_nodes hps_inst|s2f_module~l4_mp_clk]} \}} instances {hps_inst {parameters {} signal_widths {dbgapbdisable 1 f2s_pending_rst_ack 1 f2s_free_clk 1 tpiu_trace_ctl 1 pclkendbg 1} entity_name tennm_hps_hps_wrapper location HPSHPS_X280_Y211_N1 signal_terminations {dbgapbdisable {0:0 0} f2s_pending_rst_ack {0:0 1} f2s_free_clk {0:0 0} tpiu_trace_ctl {0:0 1} pclkendbg {0:0 0}} signal_default_terminations {dbgapbdisable 0 f2s_pending_rst_ack 1 f2s_free_clk 1 tpiu_trace_ctl 1 pclkendbg 0}} emif_interface {signal_widths {} parameters {} location {} entity_name one_hps_interface_ddr signal_default_terminations {} signal_terminations {}} @orderednames {hps_inst emif_interface}} interfaces {@orderednames {h2f_reset h2f_watchdog_rst f2h_stm_hw_events h2f_cs hps_emif hps_io} h2f_reset {properties {associatedResetSinks none synchronousEdges none} direction Output type reset signals {@orderednames h2f_rst h2f_rst {width 1 properties {} instance_name hps_inst internal_name s2f_rst direction Output role reset fragments {}}}} h2f_watchdog_rst {properties {associatedResetSinks none synchronousEdges none} direction Output type reset signals {@orderednames h2f_watchdog_rst h2f_watchdog_rst {width 1 properties {} instance_name hps_inst internal_name s2f_watchdog_rst direction Output role reset_n fragments {}}}} f2h_stm_hw_events {properties {} direction Input type conduit signals {@orderednames f2h_stm_hwevents f2h_stm_hwevents {width 44 properties {} instance_name hps_inst internal_name cs_hwevents_fpga direction Input role stm_hwevents fragments {}}}} h2f_cs {properties {} direction Input type conduit signals {@orderednames {h2f_cs_ntrst h2f_cs_tck h2f_cs_tdi h2f_cs_tdo h2f_cs_tdoen h2f_cs_tms} h2f_cs_ntrst {width 1 properties {} instance_name hps_inst internal_name cs_ntrst_fpga direction Input role ntrst fragments {}} h2f_cs_tck {width 1 properties {} instance_name hps_inst internal_name cs_tck_fpga direction Input role tck fragments {}} h2f_cs_tdi {width 1 properties {} instance_name hps_inst internal_name cs_tdi_fpga direction Input role tdi fragments {}} h2f_cs_tdo {width 1 properties {} instance_name hps_inst internal_name cs_tdo_fpga direction Output role tdo fragments {}} h2f_cs_tdoen {width 1 properties {} instance_name hps_inst internal_name cs_tdoen_fpga direction Output role tdoen fragments {}} h2f_cs_tms {width 1 properties {} instance_name hps_inst internal_name cs_tms_fpga direction Input role tms fragments {}}}} hps_emif {properties {} direction Output type conduit signals {@orderednames {hps_emif_emif_to_hps hps_emif_hps_to_emif hps_emif_emif_to_gp hps_emif_gp_to_emif} hps_emif_emif_to_hps {width 4096 properties {} instance_name emif_interface internal_name io48_b_cdata_pb0_in direction Input role emif_to_hps fragments {}} hps_emif_hps_to_emif {width 4096 properties {} instance_name emif_interface internal_name io48_b_iod_pb0_out direction Output role hps_to_emif fragments {}} hps_emif_emif_to_gp {width 1 properties {} instance_name hps_emif internal_name hps_emif_emif_to_gp direction Input role emif_to_gp fragments {}} hps_emif_gp_to_emif {width 2 properties {} instance_name hps_emif internal_name hps_emif_gp_to_emif direction Output role gp_to_emif fragments {}}}} hps_io {properties {} direction bidir type conduit signals {@orderednames {EMAC0_TX_CLK EMAC0_TXD0 EMAC0_TXD1 EMAC0_TXD2 EMAC0_TXD3 EMAC0_RX_CTL EMAC0_TX_CTL EMAC0_RX_CLK EMAC0_RXD0 EMAC0_RXD1 EMAC0_RXD2 EMAC0_RXD3 EMAC0_MDIO EMAC0_MDC SDMMC_CMD SDMMC_D0 SDMMC_D1 SDMMC_D2 SDMMC_D3 SDMMC_CCLK USB0_DATA0 USB0_DATA1 USB0_DATA2 USB0_DATA3 USB0_DATA4 USB0_DATA5 USB0_DATA6 USB0_DATA7 USB0_CLK USB0_STP USB0_DIR USB0_NXT UART0_RX UART0_TX I2C1_SDA I2C1_SCL gpio1_io0 gpio1_io1 gpio1_io4 hps_osc_clk jtag_tck jtag_tms jtag_tdo jtag_tdi gpio1_io18 gpio1_io19 gpio1_io20 gpio1_io21} EMAC0_TX_CLK {width 1 properties {} instance_name hps_io internal_name EMAC0_TX_CLK direction output bidir {{} EMAC0_TX_CLK_out} role EMAC0_TX_CLK open_drain false fragments {}} EMAC0_TXD0 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD0 direction output bidir {{} EMAC0_TXD0_out} role EMAC0_TXD0 open_drain false fragments {}} EMAC0_TXD1 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD1 direction output bidir {{} EMAC0_TXD1_out} role EMAC0_TXD1 open_drain false fragments {}} EMAC0_TXD2 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD2 direction output bidir {{} EMAC0_TXD2_out} role EMAC0_TXD2 open_drain false fragments {}} EMAC0_TXD3 {width 1 properties {} instance_name hps_io internal_name EMAC0_TXD3 direction output bidir {{} EMAC0_TXD3_out} role EMAC0_TXD3 open_drain false fragments {}} EMAC0_RX_CTL {width 1 properties {} instance_name hps_io internal_name EMAC0_RX_CTL direction input bidir {EMAC0_RX_CTL_in {}} role EMAC0_RX_CTL open_drain false fragments {}} EMAC0_TX_CTL {width 1 properties {} instance_name hps_io internal_name EMAC0_TX_CTL direction output bidir {{} EMAC0_TX_CTL_out} role EMAC0_TX_CTL open_drain false fragments {}} EMAC0_RX_CLK {width 1 properties {} instance_name hps_io internal_name EMAC0_RX_CLK direction input bidir {EMAC0_RX_CLK_in {}} role EMAC0_RX_CLK open_drain false fragments {}} EMAC0_RXD0 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD0 direction input bidir {EMAC0_RXD0_in {}} role EMAC0_RXD0 open_drain false fragments {}} EMAC0_RXD1 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD1 direction input bidir {EMAC0_RXD1_in {}} role EMAC0_RXD1 open_drain false fragments {}} EMAC0_RXD2 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD2 direction input bidir {EMAC0_RXD2_in {}} role EMAC0_RXD2 open_drain false fragments {}} EMAC0_RXD3 {width 1 properties {} instance_name hps_io internal_name EMAC0_RXD3 direction input bidir {EMAC0_RXD3_in {}} role EMAC0_RXD3 open_drain false fragments {}} EMAC0_MDIO {width 1 properties {} instance_name hps_io internal_name EMAC0_MDIO direction bidir bidir {EMAC0_MDIO_in EMAC0_MDIO_out} role EMAC0_MDIO open_drain false fragments {}} EMAC0_MDC {width 1 properties {} instance_name hps_io internal_name EMAC0_MDC direction output bidir {{} EMAC0_MDC_out} role EMAC0_MDC open_drain false fragments {}} SDMMC_CMD {width 1 properties {} instance_name hps_io internal_name SDMMC_CMD direction bidir bidir {SDMMC_CMD_in SDMMC_CMD_out} role SDMMC_CMD open_drain false fragments {}} SDMMC_D0 {width 1 properties {} instance_name hps_io internal_name SDMMC_D0 direction bidir bidir {SDMMC_D0_in SDMMC_D0_out} role SDMMC_D0 open_drain false fragments {}} SDMMC_D1 {width 1 properties {} instance_name hps_io internal_name SDMMC_D1 direction bidir bidir {SDMMC_D1_in SDMMC_D1_out} role SDMMC_D1 open_drain false fragments {}} SDMMC_D2 {width 1 properties {} instance_name hps_io internal_name SDMMC_D2 direction bidir bidir {SDMMC_D2_in SDMMC_D2_out} role SDMMC_D2 open_drain false fragments {}} SDMMC_D3 {width 1 properties {} instance_name hps_io internal_name SDMMC_D3 direction bidir bidir {SDMMC_D3_in SDMMC_D3_out} role SDMMC_D3 open_drain false fragments {}} SDMMC_CCLK {width 1 properties {} instance_name hps_io internal_name SDMMC_CCLK direction output bidir {{} SDMMC_CCLK_out} role SDMMC_CCLK open_drain false fragments {}} USB0_DATA0 {width 1 properties {} instance_name hps_io internal_name USB0_DATA0 direction bidir bidir {USB0_DATA0_in USB0_DATA0_out} role USB0_DATA0 open_drain false fragments {}} USB0_DATA1 {width 1 properties {} instance_name hps_io internal_name USB0_DATA1 direction bidir bidir {USB0_DATA1_in USB0_DATA1_out} role USB0_DATA1 open_drain false fragments {}} USB0_DATA2 {width 1 properties {} instance_name hps_io internal_name USB0_DATA2 direction bidir bidir {USB0_DATA2_in USB0_DATA2_out} role USB0_DATA2 open_drain false fragments {}} USB0_DATA3 {width 1 properties {} instance_name hps_io internal_name USB0_DATA3 direction bidir bidir {USB0_DATA3_in USB0_DATA3_out} role USB0_DATA3 open_drain false fragments {}} USB0_DATA4 {width 1 properties {} instance_name hps_io internal_name USB0_DATA4 direction bidir bidir {USB0_DATA4_in USB0_DATA4_out} role USB0_DATA4 open_drain false fragments {}} USB0_DATA5 {width 1 properties {} instance_name hps_io internal_name USB0_DATA5 direction bidir bidir {USB0_DATA5_in USB0_DATA5_out} role USB0_DATA5 open_drain false fragments {}} USB0_DATA6 {width 1 properties {} instance_name hps_io internal_name USB0_DATA6 direction bidir bidir {USB0_DATA6_in USB0_DATA6_out} role USB0_DATA6 open_drain false fragments {}} USB0_DATA7 {width 1 properties {} instance_name hps_io internal_name USB0_DATA7 direction bidir bidir {USB0_DATA7_in USB0_DATA7_out} role USB0_DATA7 open_drain false fragments {}} USB0_CLK {width 1 properties {} instance_name hps_io internal_name USB0_CLK direction input bidir {USB0_CLK_in {}} role USB0_CLK open_drain false fragments {}} USB0_STP {width 1 properties {} instance_name hps_io internal_name USB0_STP direction output bidir {{} USB0_STP_out} role USB0_STP open_drain false fragments {}} USB0_DIR {width 1 properties {} instance_name hps_io internal_name USB0_DIR direction input bidir {USB0_DIR_in {}} role USB0_DIR open_drain false fragments {}} USB0_NXT {width 1 properties {} instance_name hps_io internal_name USB0_NXT direction input bidir {USB0_NXT_in {}} role USB0_NXT open_drain false fragments {}} UART0_RX {width 1 properties {} instance_name hps_io internal_name UART0_RX direction input bidir {UART0_RX_in {}} role UART0_RX open_drain false fragments {}} UART0_TX {width 1 properties {} instance_name hps_io internal_name UART0_TX direction output bidir {{} UART0_TX_out} role UART0_TX open_drain false fragments {}} I2C1_SDA {width 1 properties {} instance_name hps_io internal_name I2C1_SDA direction bidir bidir {I2C1_SDA_in I2C1_SDA_out} role I2C1_SDA open_drain false fragments {}} I2C1_SCL {width 1 properties {} instance_name hps_io internal_name I2C1_SCL direction bidir bidir {I2C1_SCL_in I2C1_SCL_out} role I2C1_SCL open_drain false fragments {}} gpio1_io0 {width 1 properties {} instance_name hps_io internal_name gpio1_io0 direction bidir bidir {gpio1_io0_in gpio1_io0_out} role gpio1_io0 open_drain false fragments {}} gpio1_io1 {width 1 properties {} instance_name hps_io internal_name gpio1_io1 direction bidir bidir {gpio1_io1_in gpio1_io1_out} role gpio1_io1 open_drain false fragments {}} gpio1_io4 {width 1 properties {} instance_name hps_io internal_name gpio1_io4 direction bidir bidir {gpio1_io4_in gpio1_io4_out} role gpio1_io4 open_drain false fragments {}} hps_osc_clk {width 1 properties {} instance_name hps_io internal_name hps_osc_clk direction input bidir {hps_osc_clk_in {}} role hps_osc_clk open_drain false fragments {}} jtag_tck {width 1 properties {} instance_name hps_io internal_name jtag_tck direction input bidir {jtag_tck_in {}} role jtag_tck open_drain false fragments {}} jtag_tms {width 1 properties {} instance_name hps_io internal_name jtag_tms direction input bidir {jtag_tms_in {}} role jtag_tms open_drain false fragments {}} jtag_tdo {width 1 properties {} instance_name hps_io internal_name jtag_tdo direction output bidir {{} jtag_tdo_out} role jtag_tdo open_drain false fragments {}} jtag_tdi {width 1 properties {} instance_name hps_io internal_name jtag_tdi direction input bidir {jtag_tdi_in {}} role jtag_tdi open_drain false fragments {}} gpio1_io18 {width 1 properties {} instance_name hps_io internal_name gpio1_io18 direction bidir bidir {gpio1_io18_in gpio1_io18_out} role gpio1_io18 open_drain false fragments {}} gpio1_io19 {width 1 properties {} instance_name hps_io internal_name gpio1_io19 direction bidir bidir {gpio1_io19_in gpio1_io19_out} role gpio1_io19 open_drain false fragments {}} gpio1_io20 {width 1 properties {} instance_name hps_io internal_name gpio1_io20 direction bidir bidir {gpio1_io20_in gpio1_io20_out} role gpio1_io20 open_drain false fragments {}} gpio1_io21 {width 1 properties {} instance_name hps_io internal_name gpio1_io21 direction bidir bidir {gpio1_io21_in gpio1_io21_out} role gpio1_io21 open_drain false fragments {}}}}} properties {} interface_sim_style {} raw_assigns {} intermediate_wire_count 0 raw_assign_sim_style {} wires_to_fragments {jtag_tdo_out {output hps_inst:HPS_IOB_11_O(0:0)} jtag_tdi_in {input hps_inst:HPS_IOB_12_I(0:0)} I2C1_SDA_out {output hps_inst:HPS_IOB_7_O(0:0)} SDMMC_D0_in {input hps_inst:HPS_IOB_13_I(0:0)} gpio1_io18_in {input hps_inst:HPS_IOB_19_I(0:0)} SDMMC_D0_out {output hps_inst:HPS_IOB_13_O(0:0)} USB0_DATA5_in {input hps_inst:HPS_IOA_10_I(0:0)} I2C1_SCL_out {output hps_inst:HPS_IOB_8_O(0:0)} SDMMC_D2_out {output hps_inst:HPS_IOB_17_O(0:0)} USB0_DATA0_in {input hps_inst:HPS_IOA_4_I(0:0)} EMAC0_RXD2_in {input hps_inst:HPS_IOA_23_I(0:0)} USB0_DATA1_out {output hps_inst:HPS_IOA_5_O(0:0)} I2C1_SDA_in {input hps_inst:HPS_IOB_7_I(0:0)} EMAC0_TXD1_out {output hps_inst:HPS_IOA_18_O(0:0)} USB0_DATA3_out {output hps_inst:HPS_IOA_8_O(0:0)} gpio1_io1_in {input hps_inst:HPS_IOB_2_I(0:0)} gpio1_io18_out {output hps_inst:HPS_IOB_19_O(0:0)} EMAC0_TXD3_out {output hps_inst:HPS_IOA_22_O(0:0)} USB0_DATA5_out {output hps_inst:HPS_IOA_10_O(0:0)} SDMMC_D3_in {input hps_inst:HPS_IOB_18_I(0:0)} gpio1_io21_out {output hps_inst:HPS_IOB_22_O(0:0)} USB0_DATA7_out {output hps_inst:HPS_IOA_12_O(0:0)} USB0_DATA3_in {input hps_inst:HPS_IOA_8_I(0:0)} jtag_tck_in {input hps_inst:HPS_IOB_9_I(0:0)} EMAC0_MDIO_out {output hps_inst:HPS_IOB_23_O(0:0)} gpio1_io1_out {output hps_inst:HPS_IOB_2_O(0:0)} USB0_STP_out {output hps_inst:HPS_IOA_2_O(0:0)} gpio1_io4_in {input hps_inst:HPS_IOB_5_I(0:0)} EMAC0_RXD0_in {input hps_inst:HPS_IOA_19_I(0:0)} EMAC0_MDIO_in {input hps_inst:HPS_IOB_23_I(0:0)} hps_osc_clk_in {input hps_inst:HPS_IOB_6_I(0:0)} EMAC0_RX_CLK_in {input hps_inst:HPS_IOA_15_I(0:0)} SDMMC_D1_in {input hps_inst:HPS_IOB_16_I(0:0)} gpio1_io20_in {input hps_inst:HPS_IOB_21_I(0:0)} gpio1_io19_in {input hps_inst:HPS_IOB_20_I(0:0)} USB0_DATA6_in {input hps_inst:HPS_IOA_11_I(0:0)} EMAC0_TX_CTL_out {output hps_inst:HPS_IOA_14_O(0:0)} USB0_DATA1_in {input hps_inst:HPS_IOA_5_I(0:0)} EMAC0_RXD3_in {input hps_inst:HPS_IOA_24_I(0:0)} jtag_tms_in {input hps_inst:HPS_IOB_10_I(0:0)} SDMMC_D1_out {output hps_inst:HPS_IOB_16_O(0:0)} EMAC0_MDC_out {output hps_inst:HPS_IOB_24_O(0:0)} SDMMC_D3_out {output hps_inst:HPS_IOB_18_O(0:0)} USB0_NXT_in {input hps_inst:HPS_IOA_6_I(0:0)} USB0_DATA0_out {output hps_inst:HPS_IOA_4_O(0:0)} EMAC0_TXD0_out {output hps_inst:HPS_IOA_17_O(0:0)} USB0_DATA2_out {output hps_inst:HPS_IOA_7_O(0:0)} USB0_DATA4_in {input hps_inst:HPS_IOA_9_I(0:0)} EMAC0_TXD2_out {output hps_inst:HPS_IOA_21_O(0:0)} USB0_DATA4_out {output hps_inst:HPS_IOA_9_O(0:0)} USB0_DIR_in {input hps_inst:HPS_IOA_3_I(0:0)} gpio1_io20_out {output hps_inst:HPS_IOB_21_O(0:0)} gpio1_io19_out {output hps_inst:HPS_IOB_20_O(0:0)} USB0_DATA6_out {output hps_inst:HPS_IOA_11_O(0:0)} EMAC0_RXD1_in {input hps_inst:HPS_IOA_20_I(0:0)} UART0_RX_in {input hps_inst:HPS_IOB_4_I(0:0)} gpio1_io0_in {input hps_inst:HPS_IOB_1_I(0:0)} SDMMC_CMD_in {input hps_inst:HPS_IOB_14_I(0:0)} gpio1_io0_out {output hps_inst:HPS_IOB_1_O(0:0)} SDMMC_CMD_out {output hps_inst:HPS_IOB_14_O(0:0)} UART0_TX_out {output hps_inst:HPS_IOB_3_O(0:0)} SDMMC_D2_in {input hps_inst:HPS_IOB_17_I(0:0)} SDMMC_CCLK_out {output hps_inst:HPS_IOB_15_O(0:0)} gpio1_io21_in {input hps_inst:HPS_IOB_22_I(0:0)} USB0_DATA7_in {input hps_inst:HPS_IOA_12_I(0:0)} EMAC0_TX_CLK_out {output hps_inst:HPS_IOA_13_O(0:0)} USB0_CLK_in {input hps_inst:HPS_IOA_1_I(0:0)} gpio1_io4_out {output hps_inst:HPS_IOB_5_O(0:0)} USB0_DATA2_in {input hps_inst:HPS_IOA_7_I(0:0)} I2C1_SCL_in {input hps_inst:HPS_IOB_8_I(0:0)} EMAC0_RX_CTL_in {input hps_inst:HPS_IOA_16_I(0:0)}} wire_sim_style {}
qipEntries
ignoreSimulation false
hps_parameter_map
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_clk_0

hps_clk_src v19.1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_bridges

falconmesa_hps_bridge_avalon v20.1.0
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_bridges
  clock_sink
clk_reset  
  reset_sink


Parameters

address_map
F2S_mode 0
F2S_Width 5
S2F_Width 3
LWH2F_Enable 1
F2S_ADDRESS_WIDTH 32
S2F_ADDRESS_WIDTH 32
F2S_Route_config 1
LWH2F_ADDRESS_WIDTH 21
IPXACT_Enable false
quartus_ini_hps_ip_enable_ace_interface false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_eosc1

hps_virt_clk v19.1


Parameters

clockFrequency 25000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_cb_intosc_hs_div2_clk

hps_virt_clk v19.1


Parameters

clockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_cb_intosc_ls_clk

hps_virt_clk v19.1


Parameters

clockFrequency 60000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_f2s_free_clk

hps_virt_clk v19.1


Parameters

clockFrequency 200000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_arm_a9_0

arm_a9 v19.1
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_arm_a9_0
  clock_sink
clk_reset  
  reset_sink
altera_axi_master   intel_agilex_hps_inst_arm_gic_0
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

address_map <address-map><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /></address-map>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_arm_a9_1

arm_a9 v19.1
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_arm_a9_1
  clock_sink
clk_reset  
  reset_sink
altera_axi_master   intel_agilex_hps_inst_arm_gic_0
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

address_map <address-map><slave name='arm_gic_0.axi_slave1' start='0xFFFFC100' end='0xFFFFC200' datawidth='32' /><slave name='arm_gic_0.axi_slave0' start='0xFFFFD000' end='0xFFFFE000' datawidth='32' /></address-map>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_agilex_hps_inst_arm_gic_0

falconmesa_arm_gic v19.1
intel_agilex_hps_inst_clk_0 clk   intel_agilex_hps_inst_arm_gic_0
  clock_sink
clk_reset  
  reset_sink
intel_agilex_hps_inst_arm_a9_0 altera_axi_master  
  axi_slave0
altera_axi_master  
  axi_slave1
intel_agilex_hps_inst_arm_a9_1 altera_axi_master  
  axi_slave0
altera_axi_master  
  axi_slave1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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