Qsys

2022.04.29.13:39:27 Datasheet
Overview
Processor
   nios2_gen2 Nios II 19.1.0
All Components
   fmc_refclk0 TERASIC_CLOCK_COUNT 1.0
   fmc_refclk1 TERASIC_CLOCK_COUNT 1.0
   info_board_version altera_avalon_pio 19.1.3
   info_core_cur altera_avalon_pio 19.1.3
   info_core_cur_2 altera_avalon_pio 19.1.3
   info_core_vol altera_avalon_pio 19.1.3
   info_core_vol_2 altera_avalon_pio 19.1.3
   info_fan_speed_1 altera_avalon_pio 19.1.3
   info_maxcode_version altera_avalon_pio 19.1.3
   info_power_in_cur altera_avalon_pio 19.1.3
   info_power_in_vol altera_avalon_pio 19.1.3
   info_temp_board altera_avalon_pio 19.1.3
   info_temp_board_2 altera_avalon_pio 19.1.3
   info_temp_etile altera_avalon_pio 19.1.3
   info_temp_fpga altera_avalon_pio 19.1.3
   info_temp_ptile altera_avalon_pio 19.1.3
   info_temp_sdm altera_avalon_pio 19.1.3
   intel_onchip_memory intel_onchip_memory 1.1.0
   jtag_uart altera_avalon_jtag_uart 19.1.0
   nios2_gen2 altera_nios2_gen2 19.1.0
   qsfp28_refclk TERASIC_CLOCK_COUNT 1.0
   qsfp28rsv_refclk TERASIC_CLOCK_COUNT 1.0
   si5340a_i2c i2c_opencores 12.0
   si5340a_oe_n altera_avalon_pio 19.1.3
   si5340a_rst_n altera_avalon_pio 19.1.3
   sysid_qsys altera_avalon_sysid_qsys 19.1.2
   timer altera_avalon_timer 19.2.0
Memory Map
nios2_gen2
 data_master  instruction_master
  fmc_refclk0
Slave  0x00101180
  fmc_refclk1
Slave  0x00101170
  info_board_version
s1  0x00101120
  info_core_cur
s1  0x001010d0
  info_core_cur_2
s1  0x001010b0
  info_core_vol
s1  0x001010e0
  info_core_vol_2
s1  0x001010c0
  info_fan_speed_1
s1  0x001010a0
  info_maxcode_version
s1  0x00101110
  info_power_in_cur
s1  0x001010f0
  info_power_in_vol
s1  0x00101100
  info_temp_board
s1  0x00101080
  info_temp_board_2
s1  0x00101070
  info_temp_etile
s1  0x00101050
  info_temp_fpga
s1  0x00101090
  info_temp_ptile
s1  0x00101040
  info_temp_sdm
s1  0x00101060
  intel_onchip_memory
s1  0x00080000 0x00080000
  jtag_uart
avalon_jtag_slave  0x00101198
  nios2_gen2
debug_mem_slave  0x00100800 0x00100800
  qsfp28_refclk
Slave  0x00101150
  qsfp28rsv_refclk
Slave  0x00101160
  si5340a_i2c
avalon_slave_0  0x00101020
  si5340a_oe_n
s1  0x00101140
  si5340a_rst_n
s1  0x00101130
  sysid_qsys
control_slave  0x00101190
  timer
s1  0x00101000

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_refclk0

TERASIC_CLOCK_COUNT v1.0
nios2_gen2 data_master   fmc_refclk0
  Slave
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

fmc_refclk1

TERASIC_CLOCK_COUNT v1.0
nios2_gen2 data_master   fmc_refclk1
  Slave
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

info_board_version

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_board_version
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_core_cur

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_core_cur
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_core_cur_2

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_core_cur_2
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_core_vol

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_core_vol
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_core_vol_2

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_core_vol_2
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_fan_speed_1

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_fan_speed_1
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_maxcode_version

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_maxcode_version
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_power_in_cur

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_power_in_cur
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_power_in_vol

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_power_in_vol
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_temp_board

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_temp_board
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_temp_board_2

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_temp_board_2
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_temp_etile

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_temp_etile
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_temp_fpga

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_temp_fpga
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_temp_ptile

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_temp_ptile
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

info_temp_sdm

altera_avalon_pio v19.1.3
nios2_gen2 data_master   info_temp_sdm
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 16
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

intel_onchip_memory

intel_onchip_memory v1.1.0
nios2_gen2 data_master   intel_onchip_memory
  s1
instruction_master  
  s1
clock_in out_clk  
  clk1
reset_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE Qsys_intel_onchip_memory_0_intel_onchip_memory_0
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 512000
WRITABLE 1

jtag_uart

altera_avalon_jtag_uart v19.1.0
nios2_gen2 data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

nios2_gen2

altera_nios2_gen2 v19.1.0
clock_in out_clk   nios2_gen2
  clk
reset_in out_reset  
  reset
data_master   fmc_refclk0
  Slave
data_master   fmc_refclk1
  Slave
data_master   qsfp28rsv_refclk
  Slave
data_master   qsfp28_refclk
  Slave
data_master   jtag_uart
  avalon_jtag_slave
irq  
  irq
data_master   si5340a_i2c
  avalon_slave_0
irq  
  interrupt_sender
data_master   sysid_qsys
  control_slave
data_master   intel_onchip_memory
  s1
instruction_master  
  s1
data_master   timer
  s1
irq  
  irq
data_master   si5340a_oe_n
  s1
data_master   si5340a_rst_n
  s1
data_master   info_board_version
  s1
data_master   info_maxcode_version
  s1
data_master   info_power_in_vol
  s1
data_master   info_power_in_cur
  s1
data_master   info_core_vol
  s1
data_master   info_core_cur
  s1
data_master   info_core_vol_2
  s1
data_master   info_core_cur_2
  s1
data_master   info_fan_speed_1
  s1
data_master   info_temp_fpga
  s1
data_master   info_temp_board
  s1
data_master   info_temp_board_2
  s1
data_master   info_temp_sdm
  s1
data_master   info_temp_etile
  s1
data_master   info_temp_ptile
  s1


Parameters

generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x00100820
CPU_ARCH_NIOS2_R1
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 21
DCACHE_BYPASS_MASK 0x80000000
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
EXCEPTION_ADDR 0x00080020
FLASH_ACCELERATOR_LINES 0
FLASH_ACCELERATOR_LINE_SIZE 0
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_EXTRA_EXCEPTION_INFO
HAS_ILLEGAL_INSTRUCTION_EXCEPTION
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 2048
INITDA_SUPPORTED
INST_ADDR_WIDTH 21
NUM_OF_SHADOW_REG_SETS 0
OCI_VERSION 1
RESET_ADDR 0x00080000

qsfp28_refclk

TERASIC_CLOCK_COUNT v1.0
nios2_gen2 data_master   qsfp28_refclk
  Slave
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

qsfp28rsv_refclk

TERASIC_CLOCK_COUNT v1.0
nios2_gen2 data_master   qsfp28rsv_refclk
  Slave
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   si5340a_i2c
  clock_reset
out_reset   nios2_gen2
  reset
out_reset   jtag_uart
  reset
out_reset   timer
  reset
out_reset   sysid_qsys
  reset
out_reset   fmc_refclk0
  reset
out_reset   fmc_refclk1
  reset
out_reset   qsfp28rsv_refclk
  reset
out_reset   qsfp28_refclk
  reset
out_reset   si5340a_oe_n
  reset
out_reset   si5340a_rst_n
  reset
out_reset   info_board_version
  reset
out_reset   info_maxcode_version
  reset
out_reset   info_power_in_vol
  reset
out_reset   info_power_in_cur
  reset
out_reset   info_core_vol
  reset
out_reset   info_core_cur
  reset
out_reset   info_core_vol_2
  reset
out_reset   info_core_cur_2
  reset
out_reset   info_fan_speed_1
  reset
out_reset   info_temp_fpga
  reset
out_reset   info_temp_board
  reset
out_reset   info_temp_board_2
  reset
out_reset   info_temp_sdm
  reset
out_reset   info_temp_etile
  reset
out_reset   info_temp_ptile
  reset
out_reset   intel_onchip_memory
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)

si5340a_i2c

i2c_opencores v12.0
nios2_gen2 data_master   si5340a_i2c
  avalon_slave_0
irq  
  interrupt_sender
clock_in out_clk  
  clock
reset_in out_reset  
  clock_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

si5340a_oe_n

altera_avalon_pio v19.1.3
nios2_gen2 data_master   si5340a_oe_n
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

si5340a_rst_n

altera_avalon_pio v19.1.3
nios2_gen2 data_master   si5340a_rst_n
  s1
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

sysid_qsys

altera_avalon_sysid_qsys v19.1.2
nios2_gen2 data_master   sysid_qsys
  control_slave
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

timer

altera_avalon_timer v19.2.0
nios2_gen2 data_master   timer
  s1
irq  
  irq
clock_in out_clk  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1
generation took 0.02 seconds rendering took 0.07 seconds