Generation Report - DDR2 SDRAM Controller with ALTMEMPHY v10.1

Entity Name	altmemddr2_controller_phy
Variation Name	altmemddr2
Variation HDL	Verilog HDL
Output Directory	D:\Work\AHA\Porting\C3H\720p\DVI_Demo_C3H_PortA

File Summary

The MegaWizard interface is creating the following files in the output directory:

File	Description
altmemddr2.v	A MegaCore^® function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
altmemddr2.qip	Contains Quartus II project information for your MegaCore function variation.
altmemddr2.html	The MegaCore function report file.
altmemddr2_example_driver.v	Example self-checking test generator that matches your variation.
altmemddr2_example_top.v	Example top level design file that you should set as your Quartus II project top level. Instantiates the example driver and the controller.
altmemddr2_example_top.sdc	Example Synopsys Design Constraints file for paths in the example top level.
altmemddr2_ex_lfsr8.v	Example linear feedback shift register that is used to generate the pseudo-random test data for the example driver.
testbench \| altmemddr2_example_top_tb.v	Example testbench that instantiates the example top level design file and the example memory model.
testbench \| altmemddr2_mem_model.v	A simple example memory model that matches your variation.
testbench \| altmemddr2_full_mem_model.v	Memory model that allocates memory for all available addresses.
altmemddr2_pin_assignments.tcl	TCL script
altmemddr2_advisor.ipa	IP Advisor file that matches your variation. Used by the IP Advisor feature in the Quartus II software.
altmemddr2_phy.qip	Generated ALTMEMPHY QIP file.