c5g_xcvr_qsys

2014.05.12.15:17:26 Datasheet
Overview
  HSMC_XCVR_0_clk_100  c5g_xcvr_qsys
  HSMC_XCVR_0_ref_clk 
  hsmc_xcvr_clk 
  HSMC_XCVR_1_clk_100 
  HSMC_XCVR_1_ref_clk 
  HSMC_XCVR_2_clk_100 
  HSMC_XCVR_2_ref_clk 
  HSMC_XCVR_3_clk_100 
  HSMC_XCVR_3_ref_clk 
  clk_100 
Processor
   cpu Nios II 13.1
All Components
   cpu altera_nios2_qsys 13.1
   onchip_memory altera_avalon_onchip_memory2 13.1
   jtag_uart altera_avalon_jtag_uart 13.1
   timer altera_avalon_timer 13.1
   HSMC_XCVR_0 C5_HSMC_XCVR 1.0
   HSMC_XCVR_0_xcvr_custom_phy_0 altera_xcvr_custom_phy 13.1
   HSMC_XCVR_0_data_pattern_generator_0 altera_avalon_data_pattern_generator 13.1
   HSMC_XCVR_0_data_pattern_checker_0 altera_avalon_data_pattern_checker 13.1
   alt_xcvr_reconfig alt_xcvr_reconfig 13.1
   HSMC_XCVR_1 C5_HSMC_XCVR 1.0
   HSMC_XCVR_1_xcvr_custom_phy_0 altera_xcvr_custom_phy 13.1
   HSMC_XCVR_1_data_pattern_generator_0 altera_avalon_data_pattern_generator 13.1
   HSMC_XCVR_1_data_pattern_checker_0 altera_avalon_data_pattern_checker 13.1
   HSMC_XCVR_2 C5_HSMC_XCVR 1.0
   HSMC_XCVR_2_xcvr_custom_phy_0 altera_xcvr_custom_phy 13.1
   HSMC_XCVR_2_data_pattern_generator_0 altera_avalon_data_pattern_generator 13.1
   HSMC_XCVR_2_data_pattern_checker_0 altera_avalon_data_pattern_checker 13.1
   HSMC_XCVR_3 C5_HSMC_XCVR 1.0
   HSMC_XCVR_3_xcvr_custom_phy_0 altera_xcvr_custom_phy 13.1
   HSMC_XCVR_3_data_pattern_generator_0 altera_avalon_data_pattern_generator 13.1
   HSMC_XCVR_3_data_pattern_checker_0 altera_avalon_data_pattern_checker 13.1
   reset_hsmc_xcvr_phy altera_avalon_pio 13.1
   reset_xcvr_config altera_avalon_pio 13.1
   button altera_avalon_pio 13.1
   ledg altera_avalon_pio 13.1
   sw altera_avalon_pio 13.1
Memory Map
cpu
 data_master  instruction_master
  cpu
jtag_debug_module  0x00042800 0x00042800
  onchip_memory
s1  0x00000000 0x00000000
  jtag_uart
avalon_jtag_slave  0x00043370
  timer
s1  0x00043300
  HSMC_XCVR_0
data_pattern_checker_0_csr_slave 
data_pattern_generator_0_csr_slave 
xcvr_custom_phy_0_phy_mgmt 
  HSMC_XCVR_0_xcvr_custom_phy_0
phy_mgmt  0x00041000
  HSMC_XCVR_0_data_pattern_generator_0
csr_slave  0x000432c0
  HSMC_XCVR_0_data_pattern_checker_0
csr_slave  0x000432e0
  alt_xcvr_reconfig
reconfig_mgmt  0x00043000
  HSMC_XCVR_1
data_pattern_checker_0_csr_slave 
data_pattern_generator_0_csr_slave 
xcvr_custom_phy_0_phy_mgmt 
  HSMC_XCVR_1_xcvr_custom_phy_0
phy_mgmt  0x00041800
  HSMC_XCVR_1_data_pattern_generator_0
csr_slave  0x00043280
  HSMC_XCVR_1_data_pattern_checker_0
csr_slave  0x000432a0
  HSMC_XCVR_2
data_pattern_checker_0_csr_slave 
data_pattern_generator_0_csr_slave 
xcvr_custom_phy_0_phy_mgmt 
  HSMC_XCVR_2_xcvr_custom_phy_0
phy_mgmt  0x00042000
  HSMC_XCVR_2_data_pattern_generator_0
csr_slave  0x00043240
  HSMC_XCVR_2_data_pattern_checker_0
csr_slave  0x00043260
  HSMC_XCVR_3
data_pattern_checker_0_csr_slave 
data_pattern_generator_0_csr_slave 
xcvr_custom_phy_0_phy_mgmt 
  HSMC_XCVR_3_xcvr_custom_phy_0
phy_mgmt  0x00040800
  HSMC_XCVR_3_data_pattern_generator_0
csr_slave  0x00043220
  HSMC_XCVR_3_data_pattern_checker_0
csr_slave  0x00043200
  reset_hsmc_xcvr_phy
s1  0x00043360
  reset_xcvr_config
s1  0x00043350
  button
s1  0x00043340
  ledg
s1  0x00043330
  sw
s1  0x00043320

cpu

altera_nios2_qsys v13.1
clk_100 clk   cpu
  clk
clk_reset  
  reset_n
data_master   onchip_memory
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset1
data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
jtag_debug_module_reset  
  reset
data_master   timer
  s1
d_irq  
  irq
data_master   reset_hsmc_xcvr_phy
  s1
data_master   reset_xcvr_config
  s1
data_master   HSMC_XCVR_2_xcvr_custom_phy_0
  phy_mgmt
data_master   HSMC_XCVR_1_xcvr_custom_phy_0
  phy_mgmt
data_master   HSMC_XCVR_0_xcvr_custom_phy_0
  phy_mgmt
data_master   HSMC_XCVR_3_xcvr_custom_phy_0
  phy_mgmt
data_master   HSMC_XCVR_0_data_pattern_checker_0
  csr_slave
data_master   HSMC_XCVR_0_data_pattern_generator_0
  csr_slave
data_master   HSMC_XCVR_1_data_pattern_checker_0
  csr_slave
data_master   HSMC_XCVR_1_data_pattern_generator_0
  csr_slave
data_master   HSMC_XCVR_2_data_pattern_checker_0
  csr_slave
data_master   HSMC_XCVR_2_data_pattern_generator_0
  csr_slave
data_master   HSMC_XCVR_3_data_pattern_generator_0
  csr_slave
data_master   HSMC_XCVR_3_data_pattern_checker_0
  csr_slave
data_master   button
  s1
d_irq  
  irq
data_master   alt_xcvr_reconfig
  reconfig_mgmt
data_master   ledg
  s1
data_master   sw
  s1


Parameters

setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_bit31BypassDCache true
setting_bigEndian false
setting_export_large_RAMs false
setting_asic_enabled false
setting_asic_synopsys_translate_on_off false
setting_oci_export_jtag_signals false
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTrace_user false
setting_activateTestEndChecker false
setting_ecc_sim_test_ports false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
setting_breakslaveoveride false
muldiv_divider false
mpu_useLimit false
mpu_enabled false
mmu_enabled false
mmu_autoAssignTlbPtrSz true
manuallyAssignCpuID true
debug_triggerArming true
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
dcache_omitDataMaster false
cpuReset false
is_hardcopy_compatible false
setting_shadowRegisterSets 0
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mmu_TLBMissExcOffset 0
debug_jtagInstanceID 0
resetOffset 0
exceptionOffset 32
cpuID 0
cpuID_stored 0
breakOffset 32
userDefinedSettings
resetSlave onchip_memory.s1
mmu_TLBMissExcSlave None
exceptionSlave onchip_memory.s1
breakSlave cpu.jtag_debug_module
setting_perfCounterWidth 32
setting_interruptControllerType Internal
setting_branchPredictionType Automatic
setting_bhtPtrSz 8
muldiv_multiplierType EmbeddedMulFast
mpu_minInstRegionSize 12
mpu_minDataRegionSize 12
mmu_uitlbNumEntries 4
mmu_udtlbNumEntries 6
mmu_tlbPtrSz 7
mmu_tlbNumWays 16
mmu_processIDNumBits 8
impl Fast
icache_size 4096
icache_tagramBlockType Automatic
icache_ramBlockType Automatic
icache_numTCIM 0
icache_burstType None
dcache_bursts false
dcache_victim_buf_impl ram
debug_level Level1
debug_OCIOnchipTrace _128
dcache_size 0
dcache_tagramBlockType Automatic
dcache_ramBlockType Automatic
dcache_numTCDM 0
dcache_lineSize 32
setting_exportvectors false
setting_ecc_present false
setting_ic_ecc_present true
setting_rf_ecc_present true
setting_mmu_ecc_present true
setting_dc_ecc_present false
setting_itcm_ecc_present false
setting_dtcm_ecc_present false
regfile_ramBlockType Automatic
ocimem_ramBlockType Automatic
mmu_ramBlockType Automatic
bht_ramBlockType Automatic
resetAbsoluteAddr 0
exceptionAbsoluteAddr 32
breakAbsoluteAddr 272416
mmu_TLBMissExcAbsAddr 0
dcache_bursts_derived false
dcache_size_derived 0
dcache_lineSize_derived 32
translate_on "synthesis translate_on"
translate_off "synthesis translate_off"
instAddrWidth 19
dataAddrWidth 19
tightlyCoupledDataMaster0AddrWidth 1
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster3AddrWidth 1
instSlaveMapParam <address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='cpu.jtag_debug_module' start='0x42800' end='0x43000' /></address-map>
dataSlaveMapParam <address-map><slave name='onchip_memory.s1' start='0x0' end='0x32000' /><slave name='HSMC_XCVR_3_xcvr_custom_phy_0.phy_mgmt' start='0x40800' end='0x41000' /><slave name='HSMC_XCVR_0_xcvr_custom_phy_0.phy_mgmt' start='0x41000' end='0x41800' /><slave name='HSMC_XCVR_1_xcvr_custom_phy_0.phy_mgmt' start='0x41800' end='0x42000' /><slave name='HSMC_XCVR_2_xcvr_custom_phy_0.phy_mgmt' start='0x42000' end='0x42800' /><slave name='cpu.jtag_debug_module' start='0x42800' end='0x43000' /><slave name='alt_xcvr_reconfig.reconfig_mgmt' start='0x43000' end='0x43200' /><slave name='HSMC_XCVR_3_data_pattern_checker_0.csr_slave' start='0x43200' end='0x43220' /><slave name='HSMC_XCVR_3_data_pattern_generator_0.csr_slave' start='0x43220' end='0x43240' /><slave name='HSMC_XCVR_2_data_pattern_generator_0.csr_slave' start='0x43240' end='0x43260' /><slave name='HSMC_XCVR_2_data_pattern_checker_0.csr_slave' start='0x43260' end='0x43280' /><slave name='HSMC_XCVR_1_data_pattern_generator_0.csr_slave' start='0x43280' end='0x432A0' /><slave name='HSMC_XCVR_1_data_pattern_checker_0.csr_slave' start='0x432A0' end='0x432C0' /><slave name='HSMC_XCVR_0_data_pattern_generator_0.csr_slave' start='0x432C0' end='0x432E0' /><slave name='HSMC_XCVR_0_data_pattern_checker_0.csr_slave' start='0x432E0' end='0x43300' /><slave name='timer.s1' start='0x43300' end='0x43320' /><slave name='sw.s1' start='0x43320' end='0x43330' /><slave name='ledg.s1' start='0x43330' end='0x43340' /><slave name='button.s1' start='0x43340' end='0x43350' /><slave name='reset_xcvr_config.s1' start='0x43350' end='0x43360' /><slave name='reset_hsmc_xcvr_phy.s1' start='0x43360' end='0x43370' /><slave name='jtag_uart.avalon_jtag_slave' start='0x43370' end='0x43378' /></address-map>
clockFrequency 100000000
deviceFamilyName CYCLONEV
internalIrqMaskSystemInfo 7
customInstSlavesSystemInfo <info/>
deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x00042820
CPU_FREQ 100000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 19
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
EXCEPTION_ADDR 0x00000020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INST_ADDR_WIDTH 19
NUM_OF_SHADOW_REG_SETS 0
RESET_ADDR 0x00000000

onchip_memory

altera_avalon_onchip_memory2 v13.1
cpu data_master   onchip_memory
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset1
clk_100 clk  
  clk1
clk_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
dualPort false
initMemContent true
initializationFileName onchip_mem.hex
instanceID NONE
memorySize 204800
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
ecc_enabled false
autoInitializationFileName c5g_xcvr_qsys_onchip_memory
deviceFamily CYCLONEV
deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 1 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width 16
derived_set_data_width 32
derived_gui_ram_block_type Automatic
derived_is_hardcopy false
derived_init_file_name c5g_xcvr_qsys_onchip_memory.hex
generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE c5g_xcvr_qsys_onchip_memory
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 204800
WRITABLE 1

jtag_uart

altera_avalon_jtag_uart v13.1
cpu data_master   jtag_uart
  avalon_jtag_slave
d_irq  
  irq
jtag_debug_module_reset  
  reset
clk_100 clk  
  clk
clk_reset  
  reset


Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions NO_INTERACTIVE_WINDOWS
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
avalonSpec 2.0
legacySignalAllow false
enableInteractiveInput false
enableInteractiveOutput false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

timer

altera_avalon_timer v13.1
cpu data_master   timer
  s1
d_irq  
  irq
clk_100 clk  
  clk
clk_reset  
  reset


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
timeoutPulseOutput false
systemFrequency 100000000
timerPreset FULL_FEATURED
periodUnitsString ms
valueInSecond 0
loadValue 99999
mult 0
ticksPerSec 1000
slave_address_width 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 100000000
LOAD_VALUE 99999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000.0
TIMEOUT_PULSE_OUTPUT 0

HSMC_XCVR_0

C5_HSMC_XCVR v1.0


Parameters

AUTO_GENERATION_ID 1399879044
AUTO_UNIQUE_ID c5g_xcvr_qsys_HSMC_XCVR_0
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
AUTO_CLK_100_CLOCK_RATE 100000000
AUTO_CLK_100_CLOCK_DOMAIN 1
AUTO_CLK_100_RESET_DOMAIN 1
AUTO_REFCLK_IN_CLOCK_RATE 100000000
AUTO_REFCLK_IN_CLOCK_DOMAIN 2
AUTO_REFCLK_IN_RESET_DOMAIN 2
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_clk_100

clock_source v13.1
clk_100 clk   HSMC_XCVR_0_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   HSMC_XCVR_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_0_xcvr_custom_phy_0
  phy_mgmt_clk
clk_reset   HSMC_XCVR_0_data_format_adapter
  reset
clk_reset   HSMC_XCVR_0_timing_adapter
  reset
clk_reset   HSMC_XCVR_0_data_format_adapter_1
  reset
clk_reset   HSMC_XCVR_0_timing_adapter_1
  reset


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_ref_clk

clock_source v13.1
hsmc_xcvr_clk clk   HSMC_XCVR_0_ref_clk
  clk_in
clk_100 clk_reset  
  clk_in_reset
clk   HSMC_XCVR_0_xcvr_custom_phy_0
  pll_ref_clk


Parameters

clockFrequency 644530000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_xcvr_custom_phy_0

altera_xcvr_custom_phy v13.1
HSMC_XCVR_0_clk_100 clk   HSMC_XCVR_0_xcvr_custom_phy_0
  phy_mgmt_clk
HSMC_XCVR_0_ref_clk clk  
  pll_ref_clk
HSMC_XCVR_0_timing_adapter out  
  tx_parallel_data0
reset_bridge_hsmc_phy out_reset  
  phy_mgmt_clk_reset
cpu data_master  
  phy_mgmt
rx_clkout0   HSMC_XCVR_0_data_pattern_checker_0
  pattern_in_clk
tx_clkout0   HSMC_XCVR_0_data_pattern_generator_0
  pattern_out_clk
tx_clkout0   HSMC_XCVR_0_data_format_adapter
  clk
rx_clkout0   HSMC_XCVR_0_data_format_adapter_1
  clk
tx_clkout0   HSMC_XCVR_0_timing_adapter
  clk
rx_parallel_data0   HSMC_XCVR_0_timing_adapter_1
  in
rx_clkout0  
  clk
reconfig_to_xcvr   alt_xcvr_reconfig
  ch2_3_to_xcvr
reconfig_from_xcvr  
  ch2_3_from_xcvr


Parameters

device_family CYCLONEV
gui_parameter_rules Custom
protocol_hint basic
operation_mode Duplex
lanes 1
gui_bonding_enable false
bonded_group_size 1
gui_bonded_mode xN
bonded_mode xN
gui_pma_bonding_mode xN
pma_bonding_mode xN
gui_deser_factor 20
gui_pcs_pma_width PARAM_DEFAULT
pcs_pma_width 10
ser_base_factor 10
ser_words 2
gui_pll_type CMU
data_rate 2000 Mbps
gui_base_data_rate 1250 Mbps
base_data_rate 2000 Mbps
gui_pll_refclk_freq 100.0 MHz
en_synce_support 0
gui_tx_bitslip_enable false
tx_bitslip_enable false
gui_rx_use_coreclk false
rx_use_coreclk false
gui_tx_use_coreclk false
tx_use_coreclk false
gui_rx_use_recovered_clk false
gui_use_status false
gui_use_8b10b false
use_8b10b false
gui_use_8b10b_manual_control false
use_8b10b_manual_control false
gui_use_8b10b_status false
std_tx_pcfifo_mode low_latency
std_rx_pcfifo_mode low_latency
word_aligner_mode manual
word_aligner_state_machine_datacnt 1
word_aligner_state_machine_errcnt 1
word_aligner_state_machine_patterncnt 10
gui_use_wa_status false
word_aligner_pattern_length 10
word_align_pattern 1111100111
gui_enable_run_length false
run_length_violation_checking 40
use_rate_match_fifo 0
rate_match_pattern1 11010000111010000011
rate_match_pattern2 00101111000101111100
gui_use_rmfifo_status false
byte_order_mode none
gui_use_byte_order_block false
gui_byte_order_pld_ctrl_enable false
byte_order_pattern 111111011
byte_order_pad_pattern 000000000
use_double_data_mode DEPRECATED
coreclk_0ppm_enable false
pll_refclk_cnt 1
pll_refclk_freq 100.0 MHz
pll_refclk_select 0
cdr_refclk_select 0
plls 1
pll_type CMU
pll_select 0
pll_reconfig 0
pll_external_enable 0
gxb_analog_power AUTO
pll_lock_speed AUTO
tx_analog_power AUTO
tx_slew_rate OFF
tx_termination OCT_100_OHMS
tx_use_external_termination false
tx_preemp_pretap 0
gui_tx_preemp_pretap_inv false
tx_preemp_pretap_inv false
tx_preemp_tap_1 0
tx_preemp_tap_2 0
gui_tx_preemp_tap_2_inv false
tx_preemp_tap_2_inv false
tx_vod_selection 2
tx_common_mode 0.65V
rx_pll_lock_speed AUTO
rx_common_mode 0.82V
rx_termination OCT_100_OHMS
rx_use_external_termination false
rx_eq_dc_gain 1
rx_eq_ctrl 16
gui_pll_reconfig_enable_pll_reconfig false
gui_pll_reconfig_pll_count 1
gui_pll_reconfig_refclk_count 1
gui_pll_reconfig_main_pll_index 0
gui_pll_reconfig_cdr_pll_refclk_sel 0
gui_pll_reconfig_pll0_pll_type CMU
gui_pll_reconfig_pll0_data_rate 0 Mbps
gui_pll_reconfig_pll0_data_rate_der 2000 Mbps
gui_pll_reconfig_pll0_refclk_freq 0 MHz
gui_pll_reconfig_pll0_refclk_sel 0
gui_pll_reconfig_pll0_clk_network x1
gui_pll_reconfig_pll1_pll_type CMU
gui_pll_reconfig_pll1_data_rate 0 Mbps
gui_pll_reconfig_pll1_data_rate_der 2000 Mbps
gui_pll_reconfig_pll1_refclk_freq 0 MHz
gui_pll_reconfig_pll1_refclk_sel 0
gui_pll_reconfig_pll1_clk_network x1
gui_pll_reconfig_pll2_pll_type CMU
gui_pll_reconfig_pll2_data_rate 0 Mbps
gui_pll_reconfig_pll2_data_rate_der 2000 Mbps
gui_pll_reconfig_pll2_refclk_freq 0 MHz
gui_pll_reconfig_pll2_refclk_sel 0
gui_pll_reconfig_pll2_clk_network x1
gui_pll_reconfig_pll3_pll_type CMU
gui_pll_reconfig_pll3_data_rate 0 Mbps
gui_pll_reconfig_pll3_data_rate_der 2000 Mbps
gui_pll_reconfig_pll3_refclk_freq 0 MHz
gui_pll_reconfig_pll3_refclk_sel 0
gui_pll_reconfig_pll3_clk_network x1
mgmt_clk_in_mhz 250
gui_mgmt_clk_in_hz 250000000
gui_split_interfaces 1
gui_embedded_reset 1
embedded_reset 1
channel_interface 0
manual_reset DEPRECATED
AUTO_PHY_MGMT_CLK_CLOCK_RATE 100000000
AUTO_PLL_REF_CLK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_data_pattern_generator_0

altera_avalon_data_pattern_generator v13.1
HSMC_XCVR_0_clk_100 clk   HSMC_XCVR_0_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_0_xcvr_custom_phy_0 tx_clkout0  
  pattern_out_clk
cpu data_master  
  csr_slave
pattern_out   HSMC_XCVR_0_data_format_adapter
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_data_pattern_checker_0

altera_avalon_data_pattern_checker v13.1
HSMC_XCVR_0_clk_100 clk   HSMC_XCVR_0_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_0_xcvr_custom_phy_0 rx_clkout0  
  pattern_in_clk
HSMC_XCVR_0_data_format_adapter_1 out  
  pattern_in
cpu data_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_data_format_adapter

data_format_adapter v13.1
HSMC_XCVR_0_data_pattern_generator_0 pattern_out   HSMC_XCVR_0_data_format_adapter
  in
HSMC_XCVR_0_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_0_clk_100 clk_reset  
  reset
out   HSMC_XCVR_0_timing_adapter
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 4
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 2
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_data_format_adapter_1

data_format_adapter v13.1
HSMC_XCVR_0_xcvr_custom_phy_0 rx_clkout0   HSMC_XCVR_0_data_format_adapter_1
  clk
HSMC_XCVR_0_timing_adapter_1 out  
  in
HSMC_XCVR_0_clk_100 clk_reset  
  reset
out   HSMC_XCVR_0_data_pattern_checker_0
  pattern_in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 4
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_timing_adapter

timing_adapter v13.1
HSMC_XCVR_0_data_format_adapter out   HSMC_XCVR_0_timing_adapter
  in
HSMC_XCVR_0_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_0_clk_100 clk_reset  
  reset
out   HSMC_XCVR_0_xcvr_custom_phy_0
  tx_parallel_data0


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
inUseValid true
moduleName
outReadyLatency 0
outUseReady false
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_0_timing_adapter_1

timing_adapter v13.1
HSMC_XCVR_0_xcvr_custom_phy_0 rx_parallel_data0   HSMC_XCVR_0_timing_adapter_1
  in
rx_clkout0  
  clk
HSMC_XCVR_0_clk_100 clk_reset  
  reset
out   HSMC_XCVR_0_data_format_adapter_1
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady false
inUseValid false
moduleName
outReadyLatency 0
outUseReady true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

hsmc_xcvr_clk

clock_source v13.1
clk_100 clk_reset   hsmc_xcvr_clk
  clk_in_reset
clk   HSMC_XCVR_1_ref_clk
  clk_in
clk   HSMC_XCVR_2_ref_clk
  clk_in
clk   HSMC_XCVR_3_ref_clk
  clk_in
clk   HSMC_XCVR_0_ref_clk
  clk_in


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_xcvr_reconfig

alt_xcvr_reconfig v13.1
reset_bridge_xcvr_reconfg out_reset   alt_xcvr_reconfig
  mgmt_rst_reset
clk_100 clk  
  mgmt_clk_clk
cpu data_master  
  reconfig_mgmt
HSMC_XCVR_0_xcvr_custom_phy_0 reconfig_to_xcvr  
  ch2_3_to_xcvr
reconfig_from_xcvr  
  ch2_3_from_xcvr
HSMC_XCVR_1_xcvr_custom_phy_0 reconfig_from_xcvr  
  ch4_5_from_xcvr
HSMC_XCVR_2_xcvr_custom_phy_0 reconfig_from_xcvr  
  ch6_7_from_xcvr
HSMC_XCVR_3_xcvr_custom_phy_0 reconfig_from_xcvr  
  ch8_9_from_xcvr
ch4_5_to_xcvr   HSMC_XCVR_1_xcvr_custom_phy_0
  reconfig_to_xcvr
ch6_7_to_xcvr   HSMC_XCVR_2_xcvr_custom_phy_0
  reconfig_to_xcvr
ch8_9_to_xcvr   HSMC_XCVR_3_xcvr_custom_phy_0
  reconfig_to_xcvr


Parameters

device_family CYCLONEV
number_of_reconfig_interfaces 10
gui_split_sizes 2,2,2,2,2
enable_offset 1
enable_lc 0
enable_dcd 1
enable_dcd_power_up 1
enable_analog 1
enable_eyemon 0
ber_en 0
enable_ber 0
enable_dfe 0
enable_adce 0
enable_mif 0
gui_enable_pll 0
enable_pll 0
gui_cal_status_port false
AUTO_MGMT_CLK_CLK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1

C5_HSMC_XCVR v1.0


Parameters

AUTO_GENERATION_ID 1399879044
AUTO_UNIQUE_ID c5g_xcvr_qsys_HSMC_XCVR_1
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
AUTO_CLK_100_CLOCK_RATE 100000000
AUTO_CLK_100_CLOCK_DOMAIN 1
AUTO_CLK_100_RESET_DOMAIN 1
AUTO_REFCLK_IN_CLOCK_RATE 100000000
AUTO_REFCLK_IN_CLOCK_DOMAIN 2
AUTO_REFCLK_IN_RESET_DOMAIN 2
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_clk_100

clock_source v13.1
clk_100 clk   HSMC_XCVR_1_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   HSMC_XCVR_1_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_1_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_1_xcvr_custom_phy_0
  phy_mgmt_clk
clk_reset   HSMC_XCVR_1_data_format_adapter
  reset
clk_reset   HSMC_XCVR_1_timing_adapter
  reset
clk_reset   HSMC_XCVR_1_data_format_adapter_1
  reset
clk_reset   HSMC_XCVR_1_timing_adapter_1
  reset


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_ref_clk

clock_source v13.1
hsmc_xcvr_clk clk   HSMC_XCVR_1_ref_clk
  clk_in
clk_100 clk_reset  
  clk_in_reset
clk   HSMC_XCVR_1_xcvr_custom_phy_0
  pll_ref_clk


Parameters

clockFrequency 644530000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_xcvr_custom_phy_0

altera_xcvr_custom_phy v13.1
HSMC_XCVR_1_clk_100 clk   HSMC_XCVR_1_xcvr_custom_phy_0
  phy_mgmt_clk
HSMC_XCVR_1_ref_clk clk  
  pll_ref_clk
HSMC_XCVR_1_timing_adapter out  
  tx_parallel_data0
reset_bridge_hsmc_phy out_reset  
  phy_mgmt_clk_reset
cpu data_master  
  phy_mgmt
alt_xcvr_reconfig ch4_5_to_xcvr  
  reconfig_to_xcvr
rx_clkout0   HSMC_XCVR_1_data_pattern_checker_0
  pattern_in_clk
tx_clkout0   HSMC_XCVR_1_data_pattern_generator_0
  pattern_out_clk
tx_clkout0   HSMC_XCVR_1_data_format_adapter
  clk
rx_clkout0   HSMC_XCVR_1_data_format_adapter_1
  clk
tx_clkout0   HSMC_XCVR_1_timing_adapter
  clk
rx_parallel_data0   HSMC_XCVR_1_timing_adapter_1
  in
rx_clkout0  
  clk
reconfig_from_xcvr   alt_xcvr_reconfig
  ch4_5_from_xcvr


Parameters

device_family CYCLONEV
gui_parameter_rules Custom
protocol_hint basic
operation_mode Duplex
lanes 1
gui_bonding_enable false
bonded_group_size 1
gui_bonded_mode xN
bonded_mode xN
gui_pma_bonding_mode xN
pma_bonding_mode xN
gui_deser_factor 20
gui_pcs_pma_width PARAM_DEFAULT
pcs_pma_width 10
ser_base_factor 10
ser_words 2
gui_pll_type CMU
data_rate 2000 Mbps
gui_base_data_rate 1250 Mbps
base_data_rate 2000 Mbps
gui_pll_refclk_freq 100.0 MHz
en_synce_support 0
gui_tx_bitslip_enable false
tx_bitslip_enable false
gui_rx_use_coreclk false
rx_use_coreclk false
gui_tx_use_coreclk false
tx_use_coreclk false
gui_rx_use_recovered_clk false
gui_use_status false
gui_use_8b10b false
use_8b10b false
gui_use_8b10b_manual_control false
use_8b10b_manual_control false
gui_use_8b10b_status false
std_tx_pcfifo_mode low_latency
std_rx_pcfifo_mode low_latency
word_aligner_mode manual
word_aligner_state_machine_datacnt 1
word_aligner_state_machine_errcnt 1
word_aligner_state_machine_patterncnt 10
gui_use_wa_status false
word_aligner_pattern_length 10
word_align_pattern 1111100111
gui_enable_run_length false
run_length_violation_checking 40
use_rate_match_fifo 0
rate_match_pattern1 11010000111010000011
rate_match_pattern2 00101111000101111100
gui_use_rmfifo_status false
byte_order_mode none
gui_use_byte_order_block false
gui_byte_order_pld_ctrl_enable false
byte_order_pattern 111111011
byte_order_pad_pattern 000000000
use_double_data_mode DEPRECATED
coreclk_0ppm_enable false
pll_refclk_cnt 1
pll_refclk_freq 100.0 MHz
pll_refclk_select 0
cdr_refclk_select 0
plls 1
pll_type CMU
pll_select 0
pll_reconfig 0
pll_external_enable 0
gxb_analog_power AUTO
pll_lock_speed AUTO
tx_analog_power AUTO
tx_slew_rate OFF
tx_termination OCT_100_OHMS
tx_use_external_termination false
tx_preemp_pretap 0
gui_tx_preemp_pretap_inv false
tx_preemp_pretap_inv false
tx_preemp_tap_1 0
tx_preemp_tap_2 0
gui_tx_preemp_tap_2_inv false
tx_preemp_tap_2_inv false
tx_vod_selection 2
tx_common_mode 0.65V
rx_pll_lock_speed AUTO
rx_common_mode 0.82V
rx_termination OCT_100_OHMS
rx_use_external_termination false
rx_eq_dc_gain 1
rx_eq_ctrl 16
gui_pll_reconfig_enable_pll_reconfig false
gui_pll_reconfig_pll_count 1
gui_pll_reconfig_refclk_count 1
gui_pll_reconfig_main_pll_index 0
gui_pll_reconfig_cdr_pll_refclk_sel 0
gui_pll_reconfig_pll0_pll_type CMU
gui_pll_reconfig_pll0_data_rate 0 Mbps
gui_pll_reconfig_pll0_data_rate_der 2000 Mbps
gui_pll_reconfig_pll0_refclk_freq 0 MHz
gui_pll_reconfig_pll0_refclk_sel 0
gui_pll_reconfig_pll0_clk_network x1
gui_pll_reconfig_pll1_pll_type CMU
gui_pll_reconfig_pll1_data_rate 0 Mbps
gui_pll_reconfig_pll1_data_rate_der 2000 Mbps
gui_pll_reconfig_pll1_refclk_freq 0 MHz
gui_pll_reconfig_pll1_refclk_sel 0
gui_pll_reconfig_pll1_clk_network x1
gui_pll_reconfig_pll2_pll_type CMU
gui_pll_reconfig_pll2_data_rate 0 Mbps
gui_pll_reconfig_pll2_data_rate_der 2000 Mbps
gui_pll_reconfig_pll2_refclk_freq 0 MHz
gui_pll_reconfig_pll2_refclk_sel 0
gui_pll_reconfig_pll2_clk_network x1
gui_pll_reconfig_pll3_pll_type CMU
gui_pll_reconfig_pll3_data_rate 0 Mbps
gui_pll_reconfig_pll3_data_rate_der 2000 Mbps
gui_pll_reconfig_pll3_refclk_freq 0 MHz
gui_pll_reconfig_pll3_refclk_sel 0
gui_pll_reconfig_pll3_clk_network x1
mgmt_clk_in_mhz 250
gui_mgmt_clk_in_hz 250000000
gui_split_interfaces 1
gui_embedded_reset 1
embedded_reset 1
channel_interface 0
manual_reset DEPRECATED
AUTO_PHY_MGMT_CLK_CLOCK_RATE 100000000
AUTO_PLL_REF_CLK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_data_pattern_generator_0

altera_avalon_data_pattern_generator v13.1
HSMC_XCVR_1_clk_100 clk   HSMC_XCVR_1_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_1_xcvr_custom_phy_0 tx_clkout0  
  pattern_out_clk
cpu data_master  
  csr_slave
pattern_out   HSMC_XCVR_1_data_format_adapter
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_data_pattern_checker_0

altera_avalon_data_pattern_checker v13.1
HSMC_XCVR_1_clk_100 clk   HSMC_XCVR_1_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_1_xcvr_custom_phy_0 rx_clkout0  
  pattern_in_clk
HSMC_XCVR_1_data_format_adapter_1 out  
  pattern_in
cpu data_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_data_format_adapter

data_format_adapter v13.1
HSMC_XCVR_1_data_pattern_generator_0 pattern_out   HSMC_XCVR_1_data_format_adapter
  in
HSMC_XCVR_1_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_1_clk_100 clk_reset  
  reset
out   HSMC_XCVR_1_timing_adapter
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 4
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 2
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_data_format_adapter_1

data_format_adapter v13.1
HSMC_XCVR_1_xcvr_custom_phy_0 rx_clkout0   HSMC_XCVR_1_data_format_adapter_1
  clk
HSMC_XCVR_1_timing_adapter_1 out  
  in
HSMC_XCVR_1_clk_100 clk_reset  
  reset
out   HSMC_XCVR_1_data_pattern_checker_0
  pattern_in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 4
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_timing_adapter

timing_adapter v13.1
HSMC_XCVR_1_data_format_adapter out   HSMC_XCVR_1_timing_adapter
  in
HSMC_XCVR_1_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_1_clk_100 clk_reset  
  reset
out   HSMC_XCVR_1_xcvr_custom_phy_0
  tx_parallel_data0


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
inUseValid true
moduleName
outReadyLatency 0
outUseReady false
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_1_timing_adapter_1

timing_adapter v13.1
HSMC_XCVR_1_xcvr_custom_phy_0 rx_parallel_data0   HSMC_XCVR_1_timing_adapter_1
  in
rx_clkout0  
  clk
HSMC_XCVR_1_clk_100 clk_reset  
  reset
out   HSMC_XCVR_1_data_format_adapter_1
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady false
inUseValid false
moduleName
outReadyLatency 0
outUseReady true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2

C5_HSMC_XCVR v1.0


Parameters

AUTO_GENERATION_ID 1399879044
AUTO_UNIQUE_ID c5g_xcvr_qsys_HSMC_XCVR_2
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
AUTO_CLK_100_CLOCK_RATE 100000000
AUTO_CLK_100_CLOCK_DOMAIN 1
AUTO_CLK_100_RESET_DOMAIN 1
AUTO_REFCLK_IN_CLOCK_RATE 100000000
AUTO_REFCLK_IN_CLOCK_DOMAIN 2
AUTO_REFCLK_IN_RESET_DOMAIN 2
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_clk_100

clock_source v13.1
clk_100 clk   HSMC_XCVR_2_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   HSMC_XCVR_2_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_2_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_2_xcvr_custom_phy_0
  phy_mgmt_clk
clk_reset   HSMC_XCVR_2_data_format_adapter
  reset
clk_reset   HSMC_XCVR_2_timing_adapter
  reset
clk_reset   HSMC_XCVR_2_data_format_adapter_1
  reset
clk_reset   HSMC_XCVR_2_timing_adapter_1
  reset


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_ref_clk

clock_source v13.1
hsmc_xcvr_clk clk   HSMC_XCVR_2_ref_clk
  clk_in
clk_100 clk_reset  
  clk_in_reset
clk   HSMC_XCVR_2_xcvr_custom_phy_0
  pll_ref_clk


Parameters

clockFrequency 644530000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_xcvr_custom_phy_0

altera_xcvr_custom_phy v13.1
HSMC_XCVR_2_clk_100 clk   HSMC_XCVR_2_xcvr_custom_phy_0
  phy_mgmt_clk
HSMC_XCVR_2_ref_clk clk  
  pll_ref_clk
HSMC_XCVR_2_timing_adapter out  
  tx_parallel_data0
reset_bridge_hsmc_phy out_reset  
  phy_mgmt_clk_reset
cpu data_master  
  phy_mgmt
alt_xcvr_reconfig ch6_7_to_xcvr  
  reconfig_to_xcvr
rx_clkout0   HSMC_XCVR_2_data_pattern_checker_0
  pattern_in_clk
tx_clkout0   HSMC_XCVR_2_data_pattern_generator_0
  pattern_out_clk
tx_clkout0   HSMC_XCVR_2_data_format_adapter
  clk
rx_clkout0   HSMC_XCVR_2_data_format_adapter_1
  clk
tx_clkout0   HSMC_XCVR_2_timing_adapter
  clk
rx_parallel_data0   HSMC_XCVR_2_timing_adapter_1
  in
rx_clkout0  
  clk
reconfig_from_xcvr   alt_xcvr_reconfig
  ch6_7_from_xcvr


Parameters

device_family CYCLONEV
gui_parameter_rules Custom
protocol_hint basic
operation_mode Duplex
lanes 1
gui_bonding_enable false
bonded_group_size 1
gui_bonded_mode xN
bonded_mode xN
gui_pma_bonding_mode xN
pma_bonding_mode xN
gui_deser_factor 20
gui_pcs_pma_width PARAM_DEFAULT
pcs_pma_width 10
ser_base_factor 10
ser_words 2
gui_pll_type CMU
data_rate 2000 Mbps
gui_base_data_rate 1250 Mbps
base_data_rate 2000 Mbps
gui_pll_refclk_freq 100.0 MHz
en_synce_support 0
gui_tx_bitslip_enable false
tx_bitslip_enable false
gui_rx_use_coreclk false
rx_use_coreclk false
gui_tx_use_coreclk false
tx_use_coreclk false
gui_rx_use_recovered_clk false
gui_use_status false
gui_use_8b10b false
use_8b10b false
gui_use_8b10b_manual_control false
use_8b10b_manual_control false
gui_use_8b10b_status false
std_tx_pcfifo_mode low_latency
std_rx_pcfifo_mode low_latency
word_aligner_mode manual
word_aligner_state_machine_datacnt 1
word_aligner_state_machine_errcnt 1
word_aligner_state_machine_patterncnt 10
gui_use_wa_status false
word_aligner_pattern_length 10
word_align_pattern 1111100111
gui_enable_run_length false
run_length_violation_checking 40
use_rate_match_fifo 0
rate_match_pattern1 11010000111010000011
rate_match_pattern2 00101111000101111100
gui_use_rmfifo_status false
byte_order_mode none
gui_use_byte_order_block false
gui_byte_order_pld_ctrl_enable false
byte_order_pattern 111111011
byte_order_pad_pattern 000000000
use_double_data_mode DEPRECATED
coreclk_0ppm_enable false
pll_refclk_cnt 1
pll_refclk_freq 100.0 MHz
pll_refclk_select 0
cdr_refclk_select 0
plls 1
pll_type CMU
pll_select 0
pll_reconfig 0
pll_external_enable 0
gxb_analog_power AUTO
pll_lock_speed AUTO
tx_analog_power AUTO
tx_slew_rate OFF
tx_termination OCT_100_OHMS
tx_use_external_termination false
tx_preemp_pretap 0
gui_tx_preemp_pretap_inv false
tx_preemp_pretap_inv false
tx_preemp_tap_1 0
tx_preemp_tap_2 0
gui_tx_preemp_tap_2_inv false
tx_preemp_tap_2_inv false
tx_vod_selection 2
tx_common_mode 0.65V
rx_pll_lock_speed AUTO
rx_common_mode 0.82V
rx_termination OCT_100_OHMS
rx_use_external_termination false
rx_eq_dc_gain 1
rx_eq_ctrl 16
gui_pll_reconfig_enable_pll_reconfig false
gui_pll_reconfig_pll_count 1
gui_pll_reconfig_refclk_count 1
gui_pll_reconfig_main_pll_index 0
gui_pll_reconfig_cdr_pll_refclk_sel 0
gui_pll_reconfig_pll0_pll_type CMU
gui_pll_reconfig_pll0_data_rate 0 Mbps
gui_pll_reconfig_pll0_data_rate_der 2000 Mbps
gui_pll_reconfig_pll0_refclk_freq 0 MHz
gui_pll_reconfig_pll0_refclk_sel 0
gui_pll_reconfig_pll0_clk_network x1
gui_pll_reconfig_pll1_pll_type CMU
gui_pll_reconfig_pll1_data_rate 0 Mbps
gui_pll_reconfig_pll1_data_rate_der 2000 Mbps
gui_pll_reconfig_pll1_refclk_freq 0 MHz
gui_pll_reconfig_pll1_refclk_sel 0
gui_pll_reconfig_pll1_clk_network x1
gui_pll_reconfig_pll2_pll_type CMU
gui_pll_reconfig_pll2_data_rate 0 Mbps
gui_pll_reconfig_pll2_data_rate_der 2000 Mbps
gui_pll_reconfig_pll2_refclk_freq 0 MHz
gui_pll_reconfig_pll2_refclk_sel 0
gui_pll_reconfig_pll2_clk_network x1
gui_pll_reconfig_pll3_pll_type CMU
gui_pll_reconfig_pll3_data_rate 0 Mbps
gui_pll_reconfig_pll3_data_rate_der 2000 Mbps
gui_pll_reconfig_pll3_refclk_freq 0 MHz
gui_pll_reconfig_pll3_refclk_sel 0
gui_pll_reconfig_pll3_clk_network x1
mgmt_clk_in_mhz 250
gui_mgmt_clk_in_hz 250000000
gui_split_interfaces 1
gui_embedded_reset 1
embedded_reset 1
channel_interface 0
manual_reset DEPRECATED
AUTO_PHY_MGMT_CLK_CLOCK_RATE 100000000
AUTO_PLL_REF_CLK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_data_pattern_generator_0

altera_avalon_data_pattern_generator v13.1
HSMC_XCVR_2_clk_100 clk   HSMC_XCVR_2_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_2_xcvr_custom_phy_0 tx_clkout0  
  pattern_out_clk
cpu data_master  
  csr_slave
pattern_out   HSMC_XCVR_2_data_format_adapter
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_data_pattern_checker_0

altera_avalon_data_pattern_checker v13.1
HSMC_XCVR_2_clk_100 clk   HSMC_XCVR_2_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_2_xcvr_custom_phy_0 rx_clkout0  
  pattern_in_clk
HSMC_XCVR_2_data_format_adapter_1 out  
  pattern_in
cpu data_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_data_format_adapter

data_format_adapter v13.1
HSMC_XCVR_2_data_pattern_generator_0 pattern_out   HSMC_XCVR_2_data_format_adapter
  in
HSMC_XCVR_2_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_2_clk_100 clk_reset  
  reset
out   HSMC_XCVR_2_timing_adapter
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 4
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 2
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_data_format_adapter_1

data_format_adapter v13.1
HSMC_XCVR_2_xcvr_custom_phy_0 rx_clkout0   HSMC_XCVR_2_data_format_adapter_1
  clk
HSMC_XCVR_2_timing_adapter_1 out  
  in
HSMC_XCVR_2_clk_100 clk_reset  
  reset
out   HSMC_XCVR_2_data_pattern_checker_0
  pattern_in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 4
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_timing_adapter

timing_adapter v13.1
HSMC_XCVR_2_data_format_adapter out   HSMC_XCVR_2_timing_adapter
  in
HSMC_XCVR_2_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_2_clk_100 clk_reset  
  reset
out   HSMC_XCVR_2_xcvr_custom_phy_0
  tx_parallel_data0


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
inUseValid true
moduleName
outReadyLatency 0
outUseReady false
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_2_timing_adapter_1

timing_adapter v13.1
HSMC_XCVR_2_xcvr_custom_phy_0 rx_parallel_data0   HSMC_XCVR_2_timing_adapter_1
  in
rx_clkout0  
  clk
HSMC_XCVR_2_clk_100 clk_reset  
  reset
out   HSMC_XCVR_2_data_format_adapter_1
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady false
inUseValid false
moduleName
outReadyLatency 0
outUseReady true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3

C5_HSMC_XCVR v1.0


Parameters

AUTO_GENERATION_ID 1399879044
AUTO_UNIQUE_ID c5g_xcvr_qsys_HSMC_XCVR_3
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
AUTO_CLK_100_CLOCK_RATE 100000000
AUTO_CLK_100_CLOCK_DOMAIN 1
AUTO_CLK_100_RESET_DOMAIN 1
AUTO_REFCLK_IN_CLOCK_RATE 100000000
AUTO_REFCLK_IN_CLOCK_DOMAIN 2
AUTO_REFCLK_IN_RESET_DOMAIN 2
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_clk_100

clock_source v13.1
clk_100 clk   HSMC_XCVR_3_clk_100
  clk_in
clk_reset  
  clk_in_reset
clk   HSMC_XCVR_3_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_3_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
clk   HSMC_XCVR_3_xcvr_custom_phy_0
  phy_mgmt_clk
clk_reset   HSMC_XCVR_3_data_format_adapter
  reset
clk_reset   HSMC_XCVR_3_timing_adapter
  reset
clk_reset   HSMC_XCVR_3_data_format_adapter_1
  reset
clk_reset   HSMC_XCVR_3_timing_adapter_1
  reset


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_ref_clk

clock_source v13.1
hsmc_xcvr_clk clk   HSMC_XCVR_3_ref_clk
  clk_in
clk_100 clk_reset  
  clk_in_reset
clk   HSMC_XCVR_3_xcvr_custom_phy_0
  pll_ref_clk


Parameters

clockFrequency 644530000
clockFrequencyKnown true
inputClockFrequency 100000000
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_xcvr_custom_phy_0

altera_xcvr_custom_phy v13.1
HSMC_XCVR_3_clk_100 clk   HSMC_XCVR_3_xcvr_custom_phy_0
  phy_mgmt_clk
HSMC_XCVR_3_ref_clk clk  
  pll_ref_clk
HSMC_XCVR_3_timing_adapter out  
  tx_parallel_data0
reset_bridge_hsmc_phy out_reset  
  phy_mgmt_clk_reset
cpu data_master  
  phy_mgmt
alt_xcvr_reconfig ch8_9_to_xcvr  
  reconfig_to_xcvr
rx_clkout0   HSMC_XCVR_3_data_pattern_checker_0
  pattern_in_clk
tx_clkout0   HSMC_XCVR_3_data_pattern_generator_0
  pattern_out_clk
tx_clkout0   HSMC_XCVR_3_data_format_adapter
  clk
rx_clkout0   HSMC_XCVR_3_data_format_adapter_1
  clk
tx_clkout0   HSMC_XCVR_3_timing_adapter
  clk
rx_parallel_data0   HSMC_XCVR_3_timing_adapter_1
  in
rx_clkout0  
  clk
reconfig_from_xcvr   alt_xcvr_reconfig
  ch8_9_from_xcvr


Parameters

device_family CYCLONEV
gui_parameter_rules Custom
protocol_hint basic
operation_mode Duplex
lanes 1
gui_bonding_enable false
bonded_group_size 1
gui_bonded_mode xN
bonded_mode xN
gui_pma_bonding_mode xN
pma_bonding_mode xN
gui_deser_factor 20
gui_pcs_pma_width PARAM_DEFAULT
pcs_pma_width 10
ser_base_factor 10
ser_words 2
gui_pll_type CMU
data_rate 2000 Mbps
gui_base_data_rate 1250 Mbps
base_data_rate 2000 Mbps
gui_pll_refclk_freq 100.0 MHz
en_synce_support 0
gui_tx_bitslip_enable false
tx_bitslip_enable false
gui_rx_use_coreclk false
rx_use_coreclk false
gui_tx_use_coreclk false
tx_use_coreclk false
gui_rx_use_recovered_clk false
gui_use_status false
gui_use_8b10b false
use_8b10b false
gui_use_8b10b_manual_control false
use_8b10b_manual_control false
gui_use_8b10b_status false
std_tx_pcfifo_mode low_latency
std_rx_pcfifo_mode low_latency
word_aligner_mode manual
word_aligner_state_machine_datacnt 1
word_aligner_state_machine_errcnt 1
word_aligner_state_machine_patterncnt 10
gui_use_wa_status false
word_aligner_pattern_length 10
word_align_pattern 1111100111
gui_enable_run_length false
run_length_violation_checking 40
use_rate_match_fifo 0
rate_match_pattern1 11010000111010000011
rate_match_pattern2 00101111000101111100
gui_use_rmfifo_status false
byte_order_mode none
gui_use_byte_order_block false
gui_byte_order_pld_ctrl_enable false
byte_order_pattern 111111011
byte_order_pad_pattern 000000000
use_double_data_mode DEPRECATED
coreclk_0ppm_enable false
pll_refclk_cnt 1
pll_refclk_freq 100.0 MHz
pll_refclk_select 0
cdr_refclk_select 0
plls 1
pll_type CMU
pll_select 0
pll_reconfig 0
pll_external_enable 0
gxb_analog_power AUTO
pll_lock_speed AUTO
tx_analog_power AUTO
tx_slew_rate OFF
tx_termination OCT_100_OHMS
tx_use_external_termination false
tx_preemp_pretap 0
gui_tx_preemp_pretap_inv false
tx_preemp_pretap_inv false
tx_preemp_tap_1 0
tx_preemp_tap_2 0
gui_tx_preemp_tap_2_inv false
tx_preemp_tap_2_inv false
tx_vod_selection 2
tx_common_mode 0.65V
rx_pll_lock_speed AUTO
rx_common_mode 0.82V
rx_termination OCT_100_OHMS
rx_use_external_termination false
rx_eq_dc_gain 1
rx_eq_ctrl 16
gui_pll_reconfig_enable_pll_reconfig false
gui_pll_reconfig_pll_count 1
gui_pll_reconfig_refclk_count 1
gui_pll_reconfig_main_pll_index 0
gui_pll_reconfig_cdr_pll_refclk_sel 0
gui_pll_reconfig_pll0_pll_type CMU
gui_pll_reconfig_pll0_data_rate 0 Mbps
gui_pll_reconfig_pll0_data_rate_der 2000 Mbps
gui_pll_reconfig_pll0_refclk_freq 0 MHz
gui_pll_reconfig_pll0_refclk_sel 0
gui_pll_reconfig_pll0_clk_network x1
gui_pll_reconfig_pll1_pll_type CMU
gui_pll_reconfig_pll1_data_rate 0 Mbps
gui_pll_reconfig_pll1_data_rate_der 2000 Mbps
gui_pll_reconfig_pll1_refclk_freq 0 MHz
gui_pll_reconfig_pll1_refclk_sel 0
gui_pll_reconfig_pll1_clk_network x1
gui_pll_reconfig_pll2_pll_type CMU
gui_pll_reconfig_pll2_data_rate 0 Mbps
gui_pll_reconfig_pll2_data_rate_der 2000 Mbps
gui_pll_reconfig_pll2_refclk_freq 0 MHz
gui_pll_reconfig_pll2_refclk_sel 0
gui_pll_reconfig_pll2_clk_network x1
gui_pll_reconfig_pll3_pll_type CMU
gui_pll_reconfig_pll3_data_rate 0 Mbps
gui_pll_reconfig_pll3_data_rate_der 2000 Mbps
gui_pll_reconfig_pll3_refclk_freq 0 MHz
gui_pll_reconfig_pll3_refclk_sel 0
gui_pll_reconfig_pll3_clk_network x1
mgmt_clk_in_mhz 250
gui_mgmt_clk_in_hz 250000000
gui_split_interfaces 1
gui_embedded_reset 1
embedded_reset 1
channel_interface 0
manual_reset DEPRECATED
AUTO_PHY_MGMT_CLK_CLOCK_RATE 100000000
AUTO_PLL_REF_CLK_CLOCK_RATE 100000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_data_pattern_generator_0

altera_avalon_data_pattern_generator v13.1
HSMC_XCVR_3_clk_100 clk   HSMC_XCVR_3_data_pattern_generator_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_3_xcvr_custom_phy_0 tx_clkout0  
  pattern_out_clk
cpu data_master  
  csr_slave
pattern_out   HSMC_XCVR_3_data_format_adapter
  in


Parameters

ST_DATA_W 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_data_pattern_checker_0

altera_avalon_data_pattern_checker v13.1
HSMC_XCVR_3_clk_100 clk   HSMC_XCVR_3_data_pattern_checker_0
  csr_clk
clk_reset  
  reset
HSMC_XCVR_3_xcvr_custom_phy_0 rx_clkout0  
  pattern_in_clk
HSMC_XCVR_3_data_format_adapter_1 out  
  pattern_in
cpu data_master  
  csr_slave


Parameters

ST_DATA_W 40
NUM_CYCLES_FOR_LOCK 40
BYPASS_ENABLED false
AVALON_ENABLED true
FREQ_CNTER_ENABLED false
CROSS_CLK_SYNC_DEPTH 2
AUTO_CSR_CLK_CLOCK_RATE 100000000
AUTO_CSR_CLK_CLOCK_DOMAIN 7
AUTO_CSR_CLK_RESET_DOMAIN 7
AUTO_DEVICE_FAMILY CYCLONEV
AUTO_DEVICE 5CGXFC5C6F27C7
deviceFamily Cyclone V
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_data_format_adapter

data_format_adapter v13.1
HSMC_XCVR_3_data_pattern_generator_0 pattern_out   HSMC_XCVR_3_data_format_adapter
  in
HSMC_XCVR_3_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_3_clk_100 clk_reset  
  reset
out   HSMC_XCVR_3_timing_adapter
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 4
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 2
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_data_format_adapter_1

data_format_adapter v13.1
HSMC_XCVR_3_xcvr_custom_phy_0 rx_clkout0   HSMC_XCVR_3_data_format_adapter_1
  clk
HSMC_XCVR_3_timing_adapter_1 out  
  in
HSMC_XCVR_3_clk_100 clk_reset  
  reset
out   HSMC_XCVR_3_data_pattern_checker_0
  pattern_in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
moduleName
outSymbolsPerBeat 4
outUseEmpty false
outUseEmptyPort NO
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_timing_adapter

timing_adapter v13.1
HSMC_XCVR_3_data_format_adapter out   HSMC_XCVR_3_timing_adapter
  in
HSMC_XCVR_3_xcvr_custom_phy_0 tx_clkout0  
  clk
HSMC_XCVR_3_clk_100 clk_reset  
  reset
out   HSMC_XCVR_3_xcvr_custom_phy_0
  tx_parallel_data0


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady true
inUseValid true
moduleName
outReadyLatency 0
outUseReady false
outUseValid false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

HSMC_XCVR_3_timing_adapter_1

timing_adapter v13.1
HSMC_XCVR_3_xcvr_custom_phy_0 rx_parallel_data0   HSMC_XCVR_3_timing_adapter_1
  in
rx_clkout0  
  clk
HSMC_XCVR_3_clk_100 clk_reset  
  reset
out   HSMC_XCVR_3_data_format_adapter_1
  in


Parameters

generationLanguage VERILOG
inBitsPerSymbol 10
inChannelWidth 0
inErrorDescriptor
inErrorWidth 0
inMaxChannel 0
inReadyLatency 0
inSymbolsPerBeat 2
inUseEmpty false
inUseEmptyPort NO
inUsePackets false
inUseReady false
inUseValid false
moduleName
outReadyLatency 0
outUseReady true
outUseValid true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

reset_bridge_hsmc_phy

altera_reset_bridge v13.1


Parameters

ACTIVE_LOW_RESET 0
SYNCHRONOUS_EDGES none
NUM_RESET_OUTPUTS 1
AUTO_CLK_CLOCK_RATE -1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

reset_bridge_xcvr_reconfg

altera_reset_bridge v13.1


Parameters

ACTIVE_LOW_RESET 0
SYNCHRONOUS_EDGES none
NUM_RESET_OUTPUTS 1
AUTO_CLK_CLOCK_RATE -1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

reset_hsmc_xcvr_phy

altera_avalon_pio v13.1
cpu data_master   reset_hsmc_xcvr_phy
  s1
clk_100 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 100000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

reset_xcvr_config

altera_avalon_pio v13.1
cpu data_master   reset_xcvr_config
  s1
clk_100 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
clockRate 100000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

button

altera_avalon_pio v13.1
cpu data_master   button
  s1
d_irq  
  irq
clk_100 clk  
  clk
clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
clockRate 100000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture true
derived_edge_type FALLING
derived_irq_type EDGE
derived_has_irq true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

clk_100

clock_source v13.1


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ledg

altera_avalon_pio v13.1
clk_100 clk   ledg
  clk
clk_reset  
  reset
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 10
clockRate 100000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 10
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

sw

altera_avalon_pio v13.1
clk_100 clk   sw
  clk
clk_reset  
  reset
cpu data_master  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
clockRate 100000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture true
derived_edge_type FALLING
derived_irq_type EDGE
derived_has_irq true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
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IRQ_TYPE EDGE
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