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TimeQuest Timing Analyzer Summary
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Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -2.789
TNS   : -1066.480

Type  : Slow 900mV 85C Model Setup 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.434
TNS   : -66.622

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDQSS'
Slack : 0.349
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDQSS'
Slack : 0.353
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDQSS'
Slack : 0.359
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDQSS'
Slack : 0.373
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDSS'
Slack : 0.475
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDSS'
Slack : 0.479
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.485
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDSS'
Slack : 0.485
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDSS'
Slack : 0.499
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_fall'
Slack : 0.566
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_fall'
Slack : 0.570
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_fall'
Slack : 0.576
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_rise'
Slack : 0.580
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_rise'
Slack : 0.584
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_fall'
Slack : 0.590
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_rise'
Slack : 0.590
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_rise'
Slack : 0.604
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.658
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.796
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.028
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.028
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.028
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.028
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.028
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.028
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 1.029
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.029
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.029
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.029
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.029
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.029
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.030
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.030
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.030
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.030
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 1.384
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.749
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 3.335
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 8.326
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'OSC_50_BANK2'
Slack : 13.383
TNS   : 0.000

Type  : Slow 900mV 85C Model Setup 'altera_reserved_tck'
Slack : 46.735
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.108
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.115
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.116
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.117
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 0.123
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.125
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.132
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.150
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.185
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.240
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.247
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.256
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'OSC_50_BANK2'
Slack : 0.289
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDQSS'
Slack : 0.294
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.303
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDQSS'
Slack : 0.308
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 0.309
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDQSS'
Slack : 0.342
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDQSS'
Slack : 0.346
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDSS'
Slack : 0.429
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDSS'
Slack : 0.443
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDSS'
Slack : 0.477
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDSS'
Slack : 0.481
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_rise'
Slack : 0.550
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_fall'
Slack : 0.553
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_rise'
Slack : 0.564
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_fall'
Slack : 0.567
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'altera_reserved_tck'
Slack : 0.576
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.583
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_rise'
Slack : 0.598
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_fall'
Slack : 0.601
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_rise'
Slack : 0.602
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_fall'
Slack : 0.605
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.047
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.047
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.048
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.048
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.048
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.048
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.049
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.050
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.232
TNS   : 0.000

Type  : Slow 900mV 85C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 1.676
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.677
TNS   : -99.783

Type  : Slow 900mV 85C Model Recovery 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.950
TNS   : -24.812

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.877
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.149
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.284
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 1.354
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.381
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 2.603
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 3.076
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 3.119
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 3.788
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 3.839
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 18.428
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'OSC_50_BANK2'
Slack : 18.843
TNS   : 0.000

Type  : Slow 900mV 85C Model Recovery 'altera_reserved_tck'
Slack : 48.615
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.351
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.511
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 0.543
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.545
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.583
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.589
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.599
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.604
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.604
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.610
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.637
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.739
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'OSC_50_BANK2'
Slack : 0.777
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 1.136
TNS   : 0.000

Type  : Slow 900mV 85C Model Removal 'altera_reserved_tck'
Slack : 1.188
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.000
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.466
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.626
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.682
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.710
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.757
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 1.760
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.762
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.764
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.764
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.764
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.766
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.766
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 1.882
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 1.961
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.341
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.341
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.341
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.341
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.342
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.342
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.342
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.342
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.342
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 8.973
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'OSC_50_BANK2'
Slack : 9.410
TNS   : 0.000

Type  : Slow 900mV 85C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.213
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -2.450
TNS   : -876.973

Type  : Slow 900mV 0C Model Setup 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.401
TNS   : -64.768

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDQSS'
Slack : 0.383
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDQSS'
Slack : 0.387
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDQSS'
Slack : 0.388
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDQSS'
Slack : 0.402
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDSS'
Slack : 0.495
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDSS'
Slack : 0.499
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDSS'
Slack : 0.500
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.505
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDSS'
Slack : 0.514
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_fall'
Slack : 0.621
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_fall'
Slack : 0.625
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_fall'
Slack : 0.626
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_fall'
Slack : 0.640
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_rise'
Slack : 0.646
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_rise'
Slack : 0.650
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_rise'
Slack : 0.651
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_rise'
Slack : 0.665
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.774
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.836
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.052
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.052
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.052
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.052
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.053
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.055
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.055
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.055
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.055
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 1.425
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.861
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 3.400
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 8.365
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'OSC_50_BANK2'
Slack : 13.679
TNS   : 0.000

Type  : Slow 900mV 0C Model Setup 'altera_reserved_tck'
Slack : 46.792
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.079
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.080
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.083
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.095
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 0.109
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.112
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.114
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.119
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.172
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.233
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.242
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.257
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'OSC_50_BANK2'
Slack : 0.284
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.298
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 0.305
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDQSS'
Slack : 0.328
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDQSS'
Slack : 0.343
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDQSS'
Slack : 0.374
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDQSS'
Slack : 0.379
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDSS'
Slack : 0.470
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDSS'
Slack : 0.485
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDSS'
Slack : 0.516
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDSS'
Slack : 0.521
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_rise'
Slack : 0.548
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.563
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_rise'
Slack : 0.563
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_fall'
Slack : 0.564
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.568
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_fall'
Slack : 0.579
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_rise'
Slack : 0.594
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_rise'
Slack : 0.599
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_fall'
Slack : 0.610
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_fall'
Slack : 0.615
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.063
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.063
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.064
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.064
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.064
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.064
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.064
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.065
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.217
TNS   : 0.000

Type  : Slow 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 1.696
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -1.622
TNS   : -96.251

Type  : Slow 900mV 0C Model Recovery 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.924
TNS   : -24.137

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.065
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.331
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.429
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.536
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 1.545
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 2.708
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 3.163
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 3.201
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 3.826
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 3.883
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 18.485
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'OSC_50_BANK2'
Slack : 18.881
TNS   : 0.000

Type  : Slow 900mV 0C Model Recovery 'altera_reserved_tck'
Slack : 48.649
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.358
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.491
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 0.527
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.532
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.556
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.566
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.579
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.582
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.584
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.586
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.608
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.720
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'OSC_50_BANK2'
Slack : 0.761
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 1.093
TNS   : 0.000

Type  : Slow 900mV 0C Model Removal 'altera_reserved_tck'
Slack : 1.136
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.000
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.473
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.644
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.701
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.727
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.728
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.732
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.735
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.735
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.735
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 1.736
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.737
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.741
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 1.897
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 1.942
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.358
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.358
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.358
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.358
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.358
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.359
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.359
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.359
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.362
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 8.989
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'OSC_50_BANK2'
Slack : 9.413
TNS   : 0.000

Type  : Slow 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.196
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.706
TNS   : -31.294

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDQSS'
Slack : 0.433
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDQSS'
Slack : 0.436
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDQSS'
Slack : 0.438
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDQSS'
Slack : 0.445
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.496
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDSS'
Slack : 0.560
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDSS'
Slack : 0.563
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDSS'
Slack : 0.565
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDSS'
Slack : 0.572
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.782
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_rise'
Slack : 0.823
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_fall'
Slack : 0.824
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_rise'
Slack : 0.826
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_fall'
Slack : 0.827
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_rise'
Slack : 0.828
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_fall'
Slack : 0.829
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_rise'
Slack : 0.835
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_fall'
Slack : 0.836
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.060
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.112
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.113
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.113
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.113
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.113
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 1.648
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 1.668
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 3.550
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.044
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 8.695
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'OSC_50_BANK2'
Slack : 16.051
TNS   : 0.000

Type  : Fast 900mV 0C Model Setup 'altera_reserved_tck'
Slack : 47.896
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.077
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.098
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.104
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 0.105
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.105
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.105
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.108
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.109
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.114
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.119
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.119
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.133
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.141
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'OSC_50_BANK2'
Slack : 0.150
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 0.156
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.289
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDQSS'
Slack : 0.397
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDQSS'
Slack : 0.409
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDQSS'
Slack : 0.424
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDQSS'
Slack : 0.426
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.481
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_fall'
Slack : 0.499
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_ac_rise'
Slack : 0.506
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_fall'
Slack : 0.511
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[0]_tDSS'
Slack : 0.515
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_ac_rise'
Slack : 0.518
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_fall'
Slack : 0.526
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_n_M1_DDR2_clk_n[1]_tDSS'
Slack : 0.527
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_fall'
Slack : 0.528
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_ac_rise'
Slack : 0.533
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_ac_rise'
Slack : 0.535
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[0]_tDSS'
Slack : 0.542
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_ck_p_M1_DDR2_clk[1]_tDSS'
Slack : 0.544
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.129
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.129
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.129
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.129
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.130
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.130
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.130
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 1.130
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 1.132
TNS   : 0.000

Type  : Fast 900mV 0C Model Hold 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 1.498
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.860
TNS   : -50.668

Type  : Fast 900mV 0C Model Recovery 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.420
TNS   : -10.826

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 2.495
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 2.661
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 2.752
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 2.815
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 2.947
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 3.591
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 3.893
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 3.924
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 4.323
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 4.388
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 19.106
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'OSC_50_BANK2'
Slack : 19.356
TNS   : 0.000

Type  : Fast 900mV 0C Model Recovery 'altera_reserved_tck'
Slack : 49.586
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.148
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.258
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 0.293
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.301
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.317
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.323
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.324
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 0.325
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.326
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.340
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 0.342
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 0.362
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'OSC_50_BANK2'
Slack : 0.411
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 0.649
TNS   : 0.000

Type  : Fast 900mV 0C Model Removal 'altera_reserved_tck'
Slack : 0.744
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'sys_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.000
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1]'
Slack : 0.505
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[4]'
Slack : 0.705
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[3]'
Slack : 0.833
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 1.715
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.744
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.744
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.746
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.746
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.747
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.clk_div_master|clkout'
Slack : 1.748
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.748
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[0].clk_div_slave|clkout'
Slack : 1.751
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[6]'
Slack : 2.085
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[5]'
Slack : 2.155
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'vpg_inst|gen_pll_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.332
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[6].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.400
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[7].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.400
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[0].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.401
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[1].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.401
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[2].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.401
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[3].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.401
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[4].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.401
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|dpio|ddr_clkdiv_gen.grp_gen[5].slaves_gen[1].clk_div_slave|clkout'
Slack : 2.401
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst|ddr2_phy_alt_mem_phy_inst|clk|scan_clk|q_clock'
Slack : 8.944
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'OSC_50_BANK2'
Slack : 9.347
TNS   : 0.000

Type  : Fast 900mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.175
TNS   : 0.000

------------------------------------------------------------
