module VGA_TIMING_CTRL (

				
			iVGA_CLK,
			iRST_n,
			
			oVGA_CLK,
			oVGA_DE,
			oVGA_HS,
			oVGA_VS

				);


input		iVGA_CLK;
input		iRST_n;

output	oVGA_CLK;
output	oVGA_DE;
output	oVGA_HS;
output	oVGA_VS;

			
	//////////////////////////
	//	Output VGA Timing	//  1920*1080 @60Hz
	//////////////////////////
	reg	[10:0]oPixelCounter;
	wire	pixel_en;
	wire	read_empty;
	
//	always@(posedge DVI_CLK)
//		begin
//			if (!BUTTON[0])
//				pixel_en <= 0;
//			else if (start_rd)
//				pixel_en <= 1;
//		end
	assign	pixel_en = 1;
	
	always@(posedge iVGA_CLK)							
		begin
			if (!iRST_n)
				oPixelCounter <= 0;
			else if (oPixelCounter == 2048)
				oPixelCounter <= 1;
			else if (pixel_en)
				oPixelCounter <= oPixelCounter + 1;
		end
		
	wire wVGA_HS;
	wire wVGA_VS;	
	wire wVGA_BLANK; 
	assign	wVGA_HS = (oPixelCounter < 33)? 0 : 1;
	
	
	reg	[10:0]oHS_cnt;
	
	reg	wVGA_HS_pre;
	reg	wVGA_HS_crt;
	wire	wVGA_HS_fall;
	
	// HS falling edge
	assign	wVGA_HS_fall = ((wVGA_HS_crt) && (!wVGA_HS_pre))? 1 : 0;
	always@(posedge iVGA_CLK)
		begin
			wVGA_HS_crt <= wVGA_HS;
			wVGA_HS_pre <= wVGA_HS_crt;
		end
		
	
	always@(posedge iVGA_CLK)
		begin
			if (!iRST_n)
				oHS_cnt <= 0;
			else if ( (oHS_cnt == 1111)&&(wVGA_HS_fall) )
				oHS_cnt <= 1;
			else if (wVGA_HS_fall)
				oHS_cnt <= oHS_cnt + 1;
		end
	assign	wVGA_VS = (oHS_cnt < 4)? 0 : 1;						
	assign	wVGA_BLANK = (   ( (oPixelCounter > 96 ) && (oPixelCounter < 2017) ) && 
							 ( (oHS_cnt  > 30       ) && (oHS_cnt  < 1111     ) )     ) ? 1 : 0;	
							 
	//	DVI signal assignment
	assign	oVGA_DE 	=	wVGA_BLANK;	
	assign	oVGA_VS 	= wVGA_VS;			 
	assign	oVGA_HS 	= wVGA_HS;
	assign	oVGA_CLK 	= 	iVGA_CLK;				
				
				
				
//		`FHD_1920x1080p60: begin
//			{h_disp, h_fporch, h_sync, h_bporch} <= {12'd1920, 12'd88, 12'd44, 12'd148};
//			{v_disp, v_fporch, v_sync, v_bporch} <= {12'd1080,  12'd4, 12'd5,  12'd36};
//			{frame_interlaced, vs_polarity, hs_polarity} <= 3'b000;				
				
				
				
				
				
				
				
				
endmodule 