#Core: ddr2_phy - Instance: u7|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst
#Path, Setup Margin, Hold Margin
"Address Command (Slow 1100mV 85C Model)",1.507,1.453
"DQS vs CK (Slow 1100mV 85C Model)",0.768,0.777
"Half Rate Address/Command (Slow 1100mV 85C Model)",6.211,1.703
"Phy (Slow 1100mV 85C Model)",1.806,-0.541
"Phy Reset (Slow 1100mV 85C Model)",4.843,0.619
"Read Capture (All Conditions)",0.729,0.344
"Read Resync (All Conditions)",1.546,1.546
"Write (All Conditions)",0.521,0.504
 
"Address Command (Slow 1100mV 0C Model)",1.638,1.427
"DQS vs CK (Slow 1100mV 0C Model)",0.809,0.813
"Half Rate Address/Command (Slow 1100mV 0C Model)",6.364,1.659
"Phy (Slow 1100mV 0C Model)",1.997,-0.494
"Phy Reset (Slow 1100mV 0C Model)",5.149,0.564
"Read Capture (All Conditions)",0.729,0.344
"Read Resync (All Conditions)",1.549,1.549
"Write (All Conditions)",0.521,0.504
 
"Address Command (Fast 1100mV 0C Model)",1.953,1.221
"DQS vs CK (Fast 1100mV 0C Model)",0.874,0.869
"Half Rate Address/Command (Fast 1100mV 0C Model)",6.758,1.379
"Phy (Fast 1100mV 0C Model)",2.112,-0.335
"Phy Reset (Fast 1100mV 0C Model)",6.602,0.335
"Read Capture (All Conditions)",0.729,0.344
"Read Resync (All Conditions)",1.549,1.549
"Write (All Conditions)",0.521,0.504
