#AFI afi generate sequencer: hdl/sequencer/seq/alt_mem_phy_seq alt_mem_phy_seq
#AFI generate sequencer wrapper: hdl/datapath/common/alt_mem_phy_seq_wrapper ddr2_phy alt_mem_phy_seq_wrapper
ALTMEMPHY 10.0
Date Stamp: Wed Nov 17 17:08:34 CST 2010
Entity Name: ddr2_phy_alt_mem_phy	Vendor: Altera Corporation
Variation Name: ddr2_phy	Variation Language: Verilog HDL
Working Directory: E:\clr\cd\Demonstration\DE3_340_CLR
ALTMEMPHY Returning list of Ports to IPTB
[pll_ref_clk, global_reset_n, soft_reset_n, reset_request_n, ctl_clk, ctl_reset_n, ctl_dqs_burst[15..0], ctl_wdata_valid[15..0], ctl_wdata[255..0], ctl_dm[31..0], ctl_wlat[4..0], ctl_addr[27..0], ctl_ba[3..0], ctl_cas_n[1..0], ctl_cke[1..0], ctl_cs_n[1..0], ctl_odt[1..0], ctl_ras_n[1..0], ctl_we_n[1..0], ctl_rst_n[1..0], ctl_doing_rd[15..0], ctl_rdata[255..0], ctl_rdata_valid[1..0], ctl_rlat[4..0], ctl_cal_req, ctl_mem_clk_disable[1..0], ctl_cal_success, ctl_cal_fail, ctl_cal_warning, mem_ac_parity, mem_err_out_n, parity_error_n, ctl_cal_byte_lane_sel_n[7..0], mem_addr[13..0], mem_ba[1..0], mem_cas_n, mem_cke[0..0], mem_cs_n[0..0], mem_dm[7..0], mem_odt[0..0], mem_ras_n, mem_we_n, mem_reset_n, mem_clk[1..0], mem_clk_n[1..0], mem_dq[63..0], mem_dqs[7..0], mem_dqs_n[7..0], oct_ctl_rs_value[13..0], oct_ctl_rt_value[13..0], dqs_offset_delay_ctrl[5..0], dqs_delay_ctrl_import[5..0], dqs_delay_ctrl_export[5..0], dll_reference_clk, aux_half_rate_clk, aux_full_rate_clk, aux_scan_clk, aux_scan_clk_reset_n, dbg_clk, dbg_reset_n, dbg_addr[12..0], dbg_wr, dbg_rd, dbg_cs, dbg_wr_data[31..0], dbg_rd_data[31..0], dbg_waitrequest, pll_reconfig_enable, pll_phasecounterselect[3..0], pll_phaseupdown, pll_phasestep, pll_phase_done, hc_scan_enable_access, hc_scan_enable_dq[63..0], hc_scan_enable_dm[7..0], hc_scan_enable_dqs[7..0], hc_scan_enable_dqs_config[7..0], hc_scan_din[7..0], hc_scan_update[7..0], hc_scan_dout[63..0], hc_scan_ck]
Generating MegaCore function top-level...
MSG NF-1 Added project file "ddr2_phy.v" Location = 2
Generating QIP file ...
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy_seq_wrapper.v" Location = 2
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy_seq.vhd" Location = 2
MSG NF-1 Added project file "ddr2_phy.v" Location = 2
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy.v" Location = 2
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy_pll.v" Location = 2
MSG APF-6: Processing ddr2_phy_alt_mem_phy_seq_wrapper.v
MSG QIP-2: Adding Verilog file ddr2_phy_alt_mem_phy_seq_wrapper.v
MSG APF-6: Processing ddr2_phy_alt_mem_phy_seq.vhd
MSG QIP-1: Adding VHDL file ddr2_phy_alt_mem_phy_seq.vhd
MSG APF-6: Processing ddr2_phy.v
MSG QIP-2: Adding Verilog file ddr2_phy.v
MSG APF-6: Processing ddr2_phy_alt_mem_phy.v
MSG QIP-2: Adding Verilog file ddr2_phy_alt_mem_phy.v
MSG APF-6: Processing ddr2_phy_alt_mem_phy_pll.v
MSG QIP-2: Adding Verilog file ddr2_phy_alt_mem_phy_pll.v
Adding design files to Quartus II project ...
MSG BRT-7: Copying quartus.ini to quartus.ini
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy_seq_wrapper.v" Location = 2
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy_seq.vhd" Location = 2
MSG NF-1 Added project file "ddr2_phy.v" Location = 2
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy.v" Location = 2
MSG NF-1 Added project file "ddr2_phy_alt_mem_phy_pll.v" Location = 2
MSG APF-8: Processing ddr2_phy_alt_mem_phy_seq_wrapper.v
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy_seq_wrapper.v
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy_seq_wrapper.v
MSG APF-8: Processing ddr2_phy_alt_mem_phy_seq.vhd
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy_seq.vhd
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy_seq.vhd
MSG APF-8: Processing ddr2_phy.v
MSG APF-1: Adding Tcl file ddr2_phy.v
MSG APF-1: Adding Tcl file ddr2_phy.v
MSG APF-8: Processing ddr2_phy_alt_mem_phy.v
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy.v
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy.v
MSG APF-8: Processing ddr2_phy_alt_mem_phy_pll.v
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy_pll.v
MSG APF-1: Adding Tcl file ddr2_phy_alt_mem_phy_pll.v
ALTMEMPHY Returning list of Ports to IPTB
[pll_ref_clk, global_reset_n, soft_reset_n, reset_request_n, ctl_clk, ctl_reset_n, ctl_dqs_burst[15..0], ctl_wdata_valid[15..0], ctl_wdata[255..0], ctl_dm[31..0], ctl_wlat[4..0], ctl_addr[27..0], ctl_ba[3..0], ctl_cas_n[1..0], ctl_cke[1..0], ctl_cs_n[1..0], ctl_odt[1..0], ctl_ras_n[1..0], ctl_we_n[1..0], ctl_rst_n[1..0], ctl_doing_rd[15..0], ctl_rdata[255..0], ctl_rdata_valid[1..0], ctl_rlat[4..0], ctl_cal_req, ctl_mem_clk_disable[1..0], ctl_cal_success, ctl_cal_fail, ctl_cal_warning, mem_ac_parity, mem_err_out_n, parity_error_n, ctl_cal_byte_lane_sel_n[7..0], mem_addr[13..0], mem_ba[1..0], mem_cas_n, mem_cke[0..0], mem_cs_n[0..0], mem_dm[7..0], mem_odt[0..0], mem_ras_n, mem_we_n, mem_reset_n, mem_clk[1..0], mem_clk_n[1..0], mem_dq[63..0], mem_dqs[7..0], mem_dqs_n[7..0], oct_ctl_rs_value[13..0], oct_ctl_rt_value[13..0], dqs_offset_delay_ctrl[5..0], dqs_delay_ctrl_import[5..0], dqs_delay_ctrl_export[5..0], dll_reference_clk, aux_half_rate_clk, aux_full_rate_clk, aux_scan_clk, aux_scan_clk_reset_n, dbg_clk, dbg_reset_n, dbg_addr[12..0], dbg_wr, dbg_rd, dbg_cs, dbg_wr_data[31..0], dbg_rd_data[31..0], dbg_waitrequest, pll_reconfig_enable, pll_phasecounterselect[3..0], pll_phaseupdown, pll_phasestep, pll_phase_done, hc_scan_enable_access, hc_scan_enable_dq[63..0], hc_scan_enable_dm[7..0], hc_scan_enable_dqs[7..0], hc_scan_enable_dqs_config[7..0], hc_scan_din[7..0], hc_scan_update[7..0], hc_scan_dout[63..0], hc_scan_ck]
MegaCore Function Generation successful.
MSG FMP-1: Posting close event for IP Toolbench. Application will exit now with code 4
MSG FMP-2: Calling windowClosing. Application will exit now with the code 4
