# DE4 FPGA Board Configuration

## Pin Assignments:

- CLOCK
- External PLL
- LED x 8
- BUTTON x 4, EXT_IO and CPU_RESET_n
- DIP SWITCH x 8
- SLIDE SWITCH x 4
- SEG7
- Temperature
- Current
- Fan
- EEPROM
- SDCARD
- RS232
- Ethernet x 4
- Flash and SRAM Address/Data Share Bus
- Flash Control
- SSRAM Control
- 3-Ports High-Speed USB OTG
- DDR2 SODIMM
- HSMC-A
- HSMC-B
- HSMC I2C

## Pin Assignment Table:

##

CLOCK
Name | Location | Direction | Standard
--- | --- | --- | ---
OSC_50_BANK2 | AC35 | input | 2.5 V
OSC_50_BANK3 | AV22 | input | 1.8 V
OSC_50_BANK4 | AV19 | input | 1.8 V
OSC_50_BANK5 | AC6 | input | 3.0-V PCI-X
OSC_50_BANK6 | AB6 | input | 2.5 V
OSC_50_BANK7 | A19 | input | 1.8 V
GCLKOUT_FPGA | AH19 | output | 1.8 V
GCLKIN | A21 | input | 1.8 V
PLL_CLKIN_p | B22 | input | LVDS

##

External PLL
Name | Location | Direction | Standard
--- | --- | --- | ---
MAX_I2C_SCLK | AP24 | output | 1.8 V
MAX_I2C_SDAT | AN22 | inout | 1.8 V

##

LED x 8
Name | Location | Direction | Standard
--- | --- | --- | ---
LED[0] | V28 | output | 2.5 V
LED[1] | W28 | output | 2.5 V
LED[2] | R29 | output | 2.5 V
LED[3] | P29 | output | 2.5 V
LED[4] | N29 | output | 2.5 V
LED[5] | M29 | output | 2.5 V
LED[6] | M30 | output | 2.5 V
LED[7] | N30 | output | 2.5 V

##

BUTTON x 4, EXT_IO and CPU_RESET_n
Name | Location | Direction | Standard
--- | --- | --- | ---
BUTTON[0] | AH5 | input | 3.0-V PCI-X
BUTTON[1] | AG5 | input | 3.0-V PCI-X
BUTTON[2] | AG7 | input | 3.0-V PCI-X
BUTTON[3] | AG8 | input | 3.0-V PCI-X
EXT_IO | AC11 | inout | 3.0-V PCI-X
CPU_RESET_n | V34 | input | 2.5 V

##

DIP SWITCH x 8
Name | Location | Direction | Standard
--- | --- | --- | ---
SW[0] | AB13 | input | 3.0-V PCI-X
SW[1] | AB12 | input | 3.0-V PCI-X
SW[2] | AB11 | input | 3.0-V PCI-X
SW[3] | AB10 | input | 3.0-V PCI-X
SW[4] | AB9 | input | 3.0-V PCI-X
SW[5] | AC8 | input | 3.0-V PCI-X
SW[6] | AH6 | input | 3.0-V PCI-X
SW[7] | AG6 | input | 3.0-V PCI-X

##

SLIDE SWITCH x 4
Name | Location | Direction | Standard
--- | --- | --- | ---
SLIDE_SW[0] | J7 | input | 2.5 V
SLIDE_SW[1] | K7 | input | 2.5 V
SLIDE_SW[2] | AK6 | input | 3.0-V PCI-X
SLIDE_SW[3] | L7 | input | 2.5 V

##

SEG7
Name | Location | Direction | Standard
--- | --- | --- | ---
SEG0_D[0] | L34 | output | 2.5 V
SEG0_D[1] | M34 | output | 2.5 V
SEG0_D[2] | M33 | output | 2.5 V
SEG0_D[3] | H31 | output | 2.5 V
SEG0_D[4] | J33 | output | 2.5 V
SEG0_D[5] | L35 | output | 2.5 V
SEG0_D[6] | K32 | output | 2.5 V
SEG0_DP | AL34 | output | 2.5 V
SEG1_D[0] | E31 | output | 2.5 V
SEG1_D[1] | F31 | output | 2.5 V
SEG1_D[2] | G31 | output | 2.5 V
SEG1_D[3] | C34 | output | 2.5 V
SEG1_D[4] | C33 | output | 2.5 V
SEG1_D[5] | D33 | output | 2.5 V
SEG1_D[6] | D34 | output | 2.5 V
SEG1_DP | AL35 | output | 2.5 V

##

Temperature
Name | Location | Direction | Standard
--- | --- | --- | ---
TEMP_SMCLK | AN18 | output | 1.8 V
TEMP_SMDAT | AP18 | inout | 1.8 V
TEMP_INT_n | AP19 | input | 1.8 V

##

Current
Name | Location | Direction | Standard
--- | --- | --- | ---
CSENSE_SCK | AH13 | output | 1.8 V
CSENSE_SDI | AJ13 | output | 1.8 V
CSENSE_SDO | AK14 | input | 1.8 V
CSENSE_ADC_FO | AK13 | output | 1.8 V
CSENSE_CS_n[0] | AG14 | output | 1.8 V
CSENSE_CS_n[1] | AG15 | output | 1.8 V

##

Fan
Name | Location | Direction | Standard
--- | --- | --- | ---
FAN_CTRL | AP20 | output | 1.8 V

##

EEPROM
Name | Location | Direction | Standard
--- | --- | --- | ---
EEP_SCL | G33 | output | 2.5 V
EEP_SDA | F33 | inout | 2.5 V

##

SDCARD
Name | Location | Direction | Standard
--- | --- | --- | ---
SD_CMD | AV20 | inout | 1.8 V
SD_CLK | AT19 | output | 1.8 V
SD_WP_n | AH18 | input | 1.8 V
SD_DAT[0] | AR20 | inout | 1.8 V
SD_DAT[1] | AT20 | inout | 1.8 V
SD_DAT[2] | AU19 | inout | 1.8 V
SD_DAT[3] | AU20 | inout | 1.8 V

##

RS232
Name | Location | Direction | Standard
--- | --- | --- | ---
UART_RXD | AH32 | input | 2.5 V
UART_RTS | AH33 | input | 2.5 V
UART_TXD | AN34 | output | 2.5 V
UART_CTS | AN35 | output | 2.5 V

##

Ethernet x 4
Name | Location | Direction | Standard
--- | --- | --- | ---
ETH_RX_p[0] | U31 | input | LVDS
ETH_TX_p[0] | T30 | output | LVDS
ETH_MDIO[0] | W32 | inout | 2.5 V
ETH_MDC[0] | R30 | output | 2.5 V
ETH_INT_n[0] | B20 | input | 1.8 V
ETH_RX_p[1] | N33 | input | LVDS
ETH_TX_p[1] | R32 | output | LVDS
ETH_MDIO[1] | J5 | inout | 2.5 V
ETH_MDC[1] | J6 | output | 2.5 V
ETH_INT_n[1] | AG30 | input | 2.5 V
ETH_RX_p[2] | K34 | input | LVDS
ETH_TX_p[2] | M32 | output | LVDS
ETH_MDIO[2] | K5 | inout | 2.5 V
ETH_MDC[2] | K6 | output | 2.5 V
ETH_INT_n[2] | AE30 | input | 2.5 V
ETH_RX_p[3] | J34 | input | LVDS
ETH_TX_p[3] | P31 | output | LVDS
ETH_MDIO[3] | N8 | inout | 2.5 V
ETH_MDC[3] | N7 | output | 2.5 V
ETH_INT_n[3] | AE31 | input | 2.5 V
ETH_RST_n | V29 | output | 2.5 V

##

Flash and SRAM Address/Data Share Bus
Name | Location | Direction | Standard
--- | --- | --- | ---
FSM_D[0] | K29 | inout | 2.5 V
FSM_D[1] | J30 | inout | 2.5 V
FSM_D[2] | K30 | inout | 2.5 V
FSM_D[3] | L29 | inout | 2.5 V
FSM_D[4] | K31 | inout | 2.5 V
FSM_D[5] | E32 | inout | 2.5 V
FSM_D[6] | F32 | inout | 2.5 V
FSM_D[7] | H32 | inout | 2.5 V
FSM_D[8] | B32 | inout | 2.5 V
FSM_D[9] | C32 | inout | 2.5 V
FSM_D[10] | C35 | inout | 2.5 V
FSM_D[11] | D35 | inout | 2.5 V
FSM_D[12] | M22 | inout | 2.5 V
FSM_D[13] | M28 | inout | 2.5 V
FSM_D[14] | C31 | inout | 2.5 V
FSM_D[15] | D31 | inout | 2.5 V
FSM_A[1] | G22 | output | 2.5 V
FSM_A[2] | G23 | output | 2.5 V
FSM_A[3] | A25 | output | 2.5 V
FSM_A[4] | H22 | output | 2.5 V
FSM_A[5] | H23 | output | 2.5 V
FSM_A[6] | J22 | output | 2.5 V
FSM_A[7] | K22 | output | 2.5 V
FSM_A[8] | M21 | output | 2.5 V
FSM_A[9] | J23 | output | 2.5 V
FSM_A[10] | F34 | output | 2.5 V
FSM_A[11] | G35 | output | 2.5 V
FSM_A[12] | E34 | output | 2.5 V
FSM_A[13] | J32 | output | 2.5 V
FSM_A[14] | F35 | output | 2.5 V
FSM_A[15] | C24 | output | 2.5 V
FSM_A[16] | A24 | output | 2.5 V
FSM_A[17] | D23 | output | 2.5 V
FSM_A[18] | D24 | output | 2.5 V
FSM_A[19] | T27 | output | 2.5 V
FSM_A[20] | T28 | output | 2.5 V
FSM_A[21] | D22 | output | 2.5 V
FSM_A[22] | E23 | output | 2.5 V
FSM_A[23] | N20 | output | 2.5 V
FSM_A[24] | P20 | output | 2.5 V
FSM_A[25] | C22 | output | 2.5 V

##

Flash Control
Name | Location | Direction | Standard
--- | --- | --- | ---
FLASH_RYBY_n | G21 | input | 2.5 V
FLASH_CLK | E22 | output | 2.5 V
FLASH_RESET_n | D21 | output | 2.5 V
FLASH_OE_n | N21 | output | 2.5 V
FLASH_WE_n | R20 | output | 2.5 V
FLASH_ADV_n | F21 | output | 2.5 V
FLASH_CE_n | F23 | output | 2.5 V

##

SSRAM Control
Name | Location | Direction | Standard
--- | --- | --- | ---
SSRAM_BWA_n | R27 | output | 2.5 V
SSRAM_BWB_n | N31 | output | 2.5 V
SSRAM_CLK | M31 | output | 2.5 V
SSRAM_OE_n | H34 | output | 2.5 V
SSRAM_WE_n | L31 | output | 2.5 V
SSRAM_CKE_n | N28 | output | 2.5 V
SSRAM_CE_n | R28 | output | 2.5 V
SSRAM_ADV | H35 | output | 2.5 V

##

3-Ports High-Speed USB OTG
Name | Location | Direction | Standard
--- | --- | --- | ---
OTG_D[0] | AF16 | inout | 1.8 V
OTG_D[1] | AJ14 | inout | 1.8 V
OTG_D[2] | AD15 | inout | 1.8 V
OTG_D[3] | AE15 | inout | 1.8 V
OTG_D[4] | AE16 | inout | 1.8 V
OTG_D[5] | AH14 | inout | 1.8 V
OTG_D[6] | AM13 | inout | 1.8 V
OTG_D[7] | AN15 | inout | 1.8 V
OTG_D[8] | AP15 | inout | 1.8 V
OTG_D[9] | AG18 | inout | 1.8 V
OTG_D[10] | AG19 | inout | 1.8 V
OTG_D[11] | AM19 | inout | 1.8 V
OTG_D[12] | AN19 | inout | 1.8 V
OTG_D[13] | AV16 | inout | 1.8 V
OTG_D[14] | AT17 | inout | 1.8 V
OTG_D[15] | AV17 | inout | 1.8 V
OTG_D[16] | AU17 | inout | 1.8 V
OTG_D[17] | AW18 | inout | 1.8 V
OTG_D[18] | AT18 | inout | 1.8 V
OTG_D[19] | AU18 | inout | 1.8 V
OTG_D[20] | AR19 | inout | 1.8 V
OTG_D[21] | AW20 | inout | 1.8 V
OTG_D[22] | AW21 | inout | 1.8 V
OTG_D[23] | AF19 | inout | 1.8 V
OTG_D[24] | AE19 | inout | 1.8 V
OTG_D[25] | AE18 | inout | 1.8 V
OTG_D[26] | AD19 | inout | 1.8 V
OTG_D[27] | G13 | inout | 1.8 V
OTG_D[28] | M16 | inout | 1.8 V
OTG_D[29] | M27 | inout | 1.8 V
OTG_D[30] | K27 | inout | 1.8 V
OTG_D[31] | L26 | inout | 1.8 V
OTG_A[1] | K26 | output | 1.8 V
OTG_A[2] | P25 | output | 1.8 V
OTG_A[3] | N25 | output | 1.8 V
OTG_A[4] | R24 | output | 1.8 V
OTG_A[5] | P24 | output | 1.8 V
OTG_A[6] | M25 | output | 1.8 V
OTG_A[7] | L25 | output | 1.8 V
OTG_A[8] | N23 | output | 1.8 V
OTG_A[9] | K28 | output | 1.8 V
OTG_A[10] | A29 | output | 1.8 V
OTG_A[11] | J27 | output | 1.8 V
OTG_A[12] | G26 | output | 1.8 V
OTG_A[13] | F26 | output | 1.8 V
OTG_A[14] | G28 | output | 1.8 V
OTG_A[15] | B26 | output | 1.8 V
OTG_A[16] | D17 | output | 1.8 V
OTG_A[17] | F16 | output | 1.8 V
OTG_CS_n | P19 | output | 1.8 V
OTG_DC_DACK | AH20 | output | 1.8 V
OTG_DC_DREQ | AP21 | input | 1.8 V
OTG_DC_IRQ | AT22 | input | 1.8 V
OTG_HC_DACK | AT21 | output | 1.8 V
OTG_HC_DREQ | AN21 | input | 1.8 V
OTG_HC_IRQ | AJ20 | input | 1.8 V
OTG_OE_n | N19 | output | 1.8 V
OTG_RESET_n | AU22 | output | 1.8 V
OTG_WE_n | AR22 | output | 1.8 V

##

DDR2 SODIMM_0
Name | Location | Direction | Standard | DDR2 SODIMM Pin Index
--- | --- | --- | --- | ---
M1_DDR2_dq[4] | AW34 | inout | SSTL-18 Class I | 4
M1_DDR2_dq[0] | AV32 | inout | SSTL-18 Class I | 5
M1_DDR2_dq[5] | AW33 | inout | SSTL-18 Class I | 6
M1_DDR2_dq[1] | AV31 | inout | SSTL-18 Class I | 7
M1_DDR2_dm[0] | AW31 | output | SSTL-18 Class I | 10
M1_DDR2_dqsn[0] | AW30 | inout | Differential 1.8-V SSTL Class I | 11
M1_DDR2_dqs[0] | AV29 | inout | Differential 1.8-V SSTL Class I | 13
M1_DDR2_dq[6] | AW28 | inout | SSTL-18 Class I | 14
M1_DDR2_dq[7] | AW27 | inout | SSTL-18 Class I | 16
M1_DDR2_dq[2] | AW29 | inout | SSTL-18 Class I | 17
M1_DDR2_dq[3] | AV28 | inout | SSTL-18 Class I | 19
M1_DDR2_dq[12] | AM25 | inout | SSTL-18 Class I | 20
M1_DDR2_dq[13] | AN25 | inout | SSTL-18 Class I | 22
M1_DDR2_dq[8] | AP25 | inout | SSTL-18 Class I | 23
M1_DDR2_dq[9] | AV26 | inout | SSTL-18 Class I | 25
M1_DDR2_dm[1] | AW26 | output | SSTL-18 Class I | 26
M1_DDR2_dqsn[1] | AU26 | inout | Differential 1.8-V SSTL Class I | 29
M1_DDR2_clk[0] | AP28 | inout | Differential 1.8-V SSTL Class I | 30
M1_DDR2_dqs[1] | AT26 | inout | Differential 1.8-V SSTL Class I | 31
M1_DDR2_clk_n[0] | AR28 | inout | Differential 1.8-V SSTL Class I | 32
M1_DDR2_dq[10] | AU25 | inout | SSTL-18 Class I | 35
M1_DDR2_dq[14] | AR25 | inout | SSTL-18 Class I | 36
M1_DDR2_dq[11] | AT25 | inout | SSTL-18 Class I | 37
M1_DDR2_dq[15] | AN24 | inout | SSTL-18 Class I | 38
M1_DDR2_dq[16] | AN23 | inout | SSTL-18 Class I | 43
M1_DDR2_dq[20] | AM23 | inout | SSTL-18 Class I | 44
M1_DDR2_dq[17] | AP23 | inout | SSTL-18 Class I | 45
M1_DDR2_dq[21] | AR23 | inout | SSTL-18 Class I | 46
M1_DDR2_dqsn[2] | AU24 | inout | Differential 1.8-V SSTL Class I | 49
M1_DDR2_dqs[2] | AT24 | inout | Differential 1.8-V SSTL Class I | 51
M1_DDR2_dm[2] | AU23 | output | SSTL-18 Class I | 52
M1_DDR2_dq[18] | AL22 | inout | SSTL-18 Class I | 55
M1_DDR2_dq[22] | AT23 | inout | SSTL-18 Class I | 56
M1_DDR2_dq[19] | AM22 | inout | SSTL-18 Class I | 57
M1_DDR2_dq[23] | AL21 | inout | SSTL-18 Class I | 58
M1_DDR2_dq[24] | AJ22 | inout | SSTL-18 Class I | 61
M1_DDR2_dq[28] | AK24 | inout | SSTL-18 Class I | 62
M1_DDR2_dq[25] | AH23 | inout | SSTL-18 Class I | 63
M1_DDR2_dq[29] | AJ23 | inout | SSTL-18 Class I | 64
M1_DDR2_dm[3] | AH22 | output | SSTL-18 Class I | 67
M1_DDR2_dqsn[3] | AL23 | inout | Differential 1.8-V SSTL Class I | 68
M1_DDR2_dqs[3] | AK23 | inout | Differential 1.8-V SSTL Class I | 70
M1_DDR2_dq[26] | AF22 | inout | SSTL-18 Class I | 73
M1_DDR2_dq[30] | AF23 | inout | SSTL-18 Class I | 74
M1_DDR2_dq[27] | AE23 | inout | SSTL-18 Class I | 75
M1_DDR2_dq[31] | AE22 | inout | SSTL-18 Class I | 76
M1_DDR2_cke[0] | AT28 | output | SSTL-18 Class I | 79
M1_DDR2_cke[1] | AK27 | output | SSTL-18 Class I | 80
M1_DDR2_addr[15] | AT29 | output | SSTL-18 Class I | 84
M1_DDR2_ba[2] | AP27 | output | SSTL-18 Class I | 85
M1_DDR2_addr[14] | AU29 | output | SSTL-18 Class I | 86
M1_DDR2_addr[12] | AP26 | output | SSTL-18 Class I | 89
M1_DDR2_addr[11] | AU28 | output | SSTL-18 Class I | 90
M1_DDR2_addr[9] | AN27 | output | SSTL-18 Class I | 91
M1_DDR2_addr[7] | AT27 | output | SSTL-18 Class I | 92
M1_DDR2_addr[8] | AL27 | output | SSTL-18 Class I | 93
M1_DDR2_addr[6] | AU27 | output | SSTL-18 Class I | 94
M1_DDR2_addr[5] | AK26 | output | SSTL-18 Class I | 97
M1_DDR2_addr[4] | AN26 | output | SSTL-18 Class I | 98
M1_DDR2_addr[3] | AM26 | output | SSTL-18 Class I | 99
M1_DDR2_addr[2] | AW23 | output | SSTL-18 Class I | 100
M1_DDR2_addr[1] | AL25 | output | SSTL-18 Class I | 101
M1_DDR2_addr[0] | AV23 | output | SSTL-18 Class I | 102
M1_DDR2_addr[10] | AJ26 | output | SSTL-18 Class I | 105
M1_DDR2_ba[1] | AD25 | output | SSTL-18 Class I | 106
M1_DDR2_ba[0] | AH26 | output | SSTL-18 Class I | 107
M1_DDR2_ras_n | AE21 | output | SSTL-18 Class I | 108
M1_DDR2_we_n | AK25 | output | SSTL-18 Class I | 109
M1_DDR2_cs_n[0] | AG21 | output | SSTL-18 Class I | 110
M1_DDR2_cas_n | AJ25 | output | SSTL-18 Class I | 113
M1_DDR2_odt[0] | AG20 | output | SSTL-18 Class I | 114
M1_DDR2_cs_n[1] | AE25 | output | SSTL-18 Class I | 115
M1_DDR2_addr[13] | AD21 | output | SSTL-18 Class I | 116
M1_DDR2_odt[1] | AE24 | output | SSTL-18 Class I | 119
M1_DDR2_dq[32] | AK17 | inout | SSTL-18 Class I | 123
M1_DDR2_dq[36] | AG16 | inout | SSTL-18 Class I | 124
M1_DDR2_dq[33] | AM17 | inout | SSTL-18 Class I | 125
M1_DDR2_dq[37] | AH17 | inout | SSTL-18 Class I | 126
M1_DDR2_dqsn[4] | AL16 | inout | Differential 1.8-V SSTL Class I | 129
M1_DDR2_dm[4] | AL17 | output | SSTL-18 Class I | 130
M1_DDR2_dqs[4] | AK16 | inout | Differential 1.8-V SSTL Class I | 131
M1_DDR2_dq[38] | AF17 | inout | SSTL-18 Class I | 134
M1_DDR2_dq[34] | AH16 | inout | SSTL-18 Class I | 135
M1_DDR2_dq[39] | AE17 | inout | SSTL-18 Class I | 136
M1_DDR2_dq[35] | AJ16 | inout | SSTL-18 Class I | 137
M1_DDR2_dq[44] | AN17 | inout | SSTL-18 Class I | 140
M1_DDR2_dq[40] | AR17 | inout | SSTL-18 Class I | 141
M1_DDR2_dq[45] | AP17 | inout | SSTL-18 Class I | 142
M1_DDR2_dq[41] | AN16 | inout | SSTL-18 Class I | 143
M1_DDR2_dqsn[5] | AR16 | inout | Differential 1.8-V SSTL Class I | 146
M1_DDR2_dm[5] | AT16 | output | SSTL-18 Class I | 147
M1_DDR2_dqs[5] | AP16 | inout | Differential 1.8-V SSTL Class I | 148
M1_DDR2_dq[42] | AU16 | inout | SSTL-18 Class I | 151
M1_DDR2_dq[46] | AU15 | inout | SSTL-18 Class I | 152
M1_DDR2_dq[43] | AW16 | inout | SSTL-18 Class I | 153
M1_DDR2_dq[47] | AT15 | inout | SSTL-18 Class I | 154
M1_DDR2_dq[48] | AW11 | inout | SSTL-18 Class I | 157
M1_DDR2_dq[52] | AW14 | inout | SSTL-18 Class I | 158
M1_DDR2_dq[49] | AW12 | inout | SSTL-18 Class I | 159
M1_DDR2_dq[53] | AV14 | inout | SSTL-18 Class I | 160
M1_DDR2_clk[1] | AE20 | inout | Differential 1.8-V SSTL Class I | 164
M1_DDR2_clk_n[1] | AF20 | inout | Differential 1.8-V SSTL Class I | 166
M1_DDR2_dqsn[6] | AW13 | inout | Differential 1.8-V SSTL Class I | 167
M1_DDR2_dqs[6] | AV13 | inout | Differential 1.8-V SSTL Class I | 169
M1_DDR2_dm[6] | AU14 | output | SSTL-18 Class I | 170
M1_DDR2_dq[50] | AT14 | inout | SSTL-18 Class I | 173
M1_DDR2_dq[54] | AU11 | inout | SSTL-18 Class I | 174
M1_DDR2_dq[51] | AU12 | inout | SSTL-18 Class I | 175
M1_DDR2_dq[55] | AT12 | inout | SSTL-18 Class I | 176
M1_DDR2_dq[56] | AP13 | inout | SSTL-18 Class I | 179
M1_DDR2_dq[60] | AR14 | inout | SSTL-18 Class I | 180
M1_DDR2_dq[57] | AN14 | inout | SSTL-18 Class I | 181
M1_DDR2_dq[61] | AP14 | inout | SSTL-18 Class I | 182
M1_DDR2_dm[7] | AN13 | output | SSTL-18 Class I | 185
M1_DDR2_dqsn[7] | AT13 | inout | Differential 1.8-V SSTL Class I | 186
M1_DDR2_dqs[7] | AR13 | inout | Differential 1.8-V SSTL Class I | 188
M1_DDR2_dq[58] | AL15 | inout | SSTL-18 Class I | 189
M1_DDR2_dq[59] | AM14 | inout | SSTL-18 Class I | 191
M1_DDR2_dq[62] | AL14 | inout | SSTL-18 Class I | 192
M1_DDR2_dq[63] | AL13 | inout | SSTL-18 Class I | 194
M1_DDR2_SDA | AG24 | inout | 1.8 V | 195
M1_DDR2_SCL | AH24 | output | 1.8 V | 197
M1_DDR2_SA[0] | AV25 | output | 1.8 V | 198
M1_DDR2_SA[1] | AW25 | output | 1.8 V | 200

##

HSMC-A connect to DVI - FullHD TX/RX
Name | Location | Direction | Standard | HSMC Pin Index
--- | --- | --- | --- | ---
DVI_RX_D[0] | AC26 | input | 2.5 V | 41
DVI_RX_D[14] | AC31 | input | 2.5 V | 42
DVI_RX_D[1] | AD26 | input | 2.5 V | 43
DVI_RX_D[15] | AC32 | input | 2.5 V | 44
DVI_RX_D[2] | AB27 | input | 2.5 V | 47
DVI_RX_D[13] | AJ32 | input | 2.5 V | 48
DVI_RX_D[3] | AB28 | input | 2.5 V | 49
DVI_RX_D[12] | AK33 | input | 2.5 V | 50
DVI_RX_D[4] | AB30 | input | 2.5 V | 53
DVI_RX_D[11] | AH34 | input | 2.5 V | 54
DVI_RX_D[5] | AB31 | input | 2.5 V | 55
DVI_RX_D[10] | AH35 | input | 2.5 V | 56
DVI_RX_D[6] | AD27 | input | 2.5 V | 59
DVI_RX_D[9] | AJ34 | input | 2.5 V | 60
DVI_RX_D[7] | AE27 | input | 2.5 V | 61
DVI_RX_D[8] | AJ35 | input | 2.5 V | 62
DVI_RX_CTL[1] | AD28 | input | 2.5 V | 65
DVI_RX_D[23] | AK34 | input | 2.5 V | 66
DVI_RX_HS | AD29 | input | 2.5 V | 67
DVI_RX_D[22] | AK35 | input | 2.5 V | 68
DVI_RX_VS | AE28 | input | 2.5 V | 71
DVI_RX_D[21] | AN30 | input | 2.5 V | 72
DVI_RX_DE | AE29 | input | 2.5 V | 73
DVI_RX_D[20] | AP30 | input | 2.5 V | 74
DVI_RX_CTL[3] | AE26 | input | 2.5 V | 77
DVI_RX_D[19] | AM34 | input | 2.5 V | 78
DVI_RX_CTL[2] | AF26 | input | 2.5 V | 79
DVI_RX_D[18] | AM35 | input | 2.5 V | 80
DVI_RX_DDCSDA | AG31 | inout | 2.5 V | 83
DVI_RX_D[17] | AM31 | input | 2.5 V | 84
DVI_RX_DDCSCL | AG32 | inout | 2.5 V | 85
DVI_RX_D[16] | AN31 | input | 2.5 V | 86
DVI_EDID_WP | AG29 | output | 2.5 V | 89
DVI_RX_SCDT | AN33 | input | 2.5 V | 90
DVI_TX_D[17] | AP34 | output | 2.5 V | 92
DVI_TX_D[16] | AG28 | output | 2.5 V | 95
DVI_RX_CLK | AB34 | input | 2.5 V | 96
DVI_TX_D[12] | AC28 | output | 2.5 V | 101
DVI_TX_D[18] | AP32 | output | 2.5 V | 102
DVI_TX_D[13] | AC29 | output | 2.5 V | 103
DVI_TX_D[19] | AR32 | output | 2.5 V | 104
DVI_TX_D[14] | AJ29 | output | 2.5 V | 107
DVI_TX_D[20] | AR31 | output | 2.5 V | 108
DVI_TX_D[15] | AK29 | output | 2.5 V | 109
DVI_TX_D[21] | AT30 | output | 2.5 V | 110
DVI_TX_D[11] | AD30 | output | 2.5 V | 113
DVI_TX_D[22] | AT33 | output | 2.5 V | 114
DVI_TX_D[10] | AD31 | output | 2.5 V | 115
DVI_TX_D[23] | AU33 | output | 2.5 V | 116
DVI_TX_D[9] | AK32 | output | 2.5 V | 119
DVI_TX_DKEN | AU34 | output | 2.5 V | 120
DVI_TX_D[8] | AL32 | output | 2.5 V | 121
DVI_TX_HS | AV34 | output | 2.5 V | 122
DVI_TX_D[7] | AG27 | output | 2.5 V | 125
DVI_TX_VS | AT32 | output | 2.5 V | 126
DVI_TX_D[6] | AH27 | output | 2.5 V | 127
DVI_TX_CTL[3] | AU32 | output | 2.5 V | 128
DVI_TX_D[5] | AK31 | output | 2.5 V | 131
DVI_TX_CTL[2] | AT31 | output | 2.5 V | 132
DVI_TX_D[4] | AL31 | output | 2.5 V | 133
DVI_TX_CTL[1] | AU31 | output | 2.5 V | 134
DVI_TX_D[3] | AJ31 | output | 2.5 V | 137
DVI_TX_HTPLG | AP35 | output | 2.5 V | 138
DVI_TX_D[2] | AH30 | output | 2.5 V | 139
DVI_TX_PD_N | AR35 | output | 2.5 V | 140
DVI_TX_D[1] | AL29 | output | 2.5 V | 143
DVI_TX_MSEN | AN32 | output | 2.5 V | 144
DVI_TX_D[0] | AM29 | output | 2.5 V | 145
DVI_TX_ISEL | AP33 | output | 2.5 V | 146
DVI_TX_DE | AK30 | output | 2.5 V | 149
DVI_TX_SDA | AT34 | inout | 2.5 V | 150
DVI_TX_DDCSDA | AL30 | inout | 2.5 V | 151
DVI_TX_SCL | AR34 | output | 2.5 V | 152
DVI_TX_CLK | AG34 | output | 2.5 V | 155
DVI_TX_DDCSCL | AG35 | inout | 2.5 V | 157

##

HSMC-B connect to DVI - FullHD TX/RX
Name | Location | Direction | Standard | HSMC Pin Index
--- | --- | --- | --- | ---
CLR_GXB_TX_p[7] | B4 | output | 1.4-V PCML | 1
CLR_GXB_RX_p[7] | C2 | input | 1.4-V PCML | 2
CLR_GXB_TX_p[6] | D4 | output | 1.4-V PCML | 5
CLR_GXB_RX_p[6] | E2 | input | 1.4-V PCML | 6
CLR_GXB_TX_p[5] | K4 | output | 1.4-V PCML | 9
CLR_GXB_RX_p[5] | L2 | input | 1.4-V PCML | 10
CLR_GXB_TX_p[4] | M4 | output | 1.4-V PCML | 13
CLR_GXB_RX_p[4] | N2 | input | 1.4-V PCML | 14
CLR_GXB_TX_p[3] | P4 | output | 1.4-V PCML | 17
CLR_GXB_RX_p[3] | R2 | input | 1.4-V PCML | 18
CLR_GXB_TX_p[2] | T4 | output | 1.4-V PCML | 21
CLR_GXB_RX_p[2] | U2 | input | 1.4-V PCML | 22
CLR_GXB_TX_p[1] | AB4 | output | 1.4-V PCML | 25
CLR_GXB_RX_p[1] | AC2 | input | 1.4-V PCML | 26
CLR_GXB_TX_p[0] | AD4 | output | 1.4-V PCML | 29
CLR_GXB_RX_p[0] | AE2 | input | 1.4-V PCML | 30
CLR_OUT0 | L8 | output | 2.5 V | 39
CLR_CLKIN0 | AA5 | input | 2.5 V | 40
CLR_D[0] | H10 | inout | 2.5 V | 41
CLR_D[1] | D6 | inout | 2.5 V | 42
CLR_D[2] | G10 | inout | 2.5 V | 43
CLR_D[3] | C6 | inout | 2.5 V | 44
CLR_TX_p[0] | K9 | inout | 2.5 V | 47
CLR_RX_p[0] | D5 | inout | 2.5 V | 48
CLR_TX_n[0] | J9 | inout | 2.5 V | 49
CLR_RX_n[0] | C5 | inout | 2.5 V | 50
CLR_TX_p[1] | K10 | inout | 2.5 V | 53
CLR_RX_p[1] | D10 | inout | 2.5 V | 54
CLR_TX_n[1] | J10 | inout | 2.5 V | 55
CLR_RX_n[1] | C10 | inout | 2.5 V | 56
CLR_TX_p[2] | N11 | inout | 2.5 V | 59
CLR_RX_p[2] | D9 | inout | 2.5 V | 60
CLR_TX_n[2] | N10 | inout | 2.5 V | 61
CLR_RX_n[2] | C9 | inout | 2.5 V | 62
CLR_TX_p[3] | N12 | inout | 2.5 V | 65
CLR_RX_p[3] | D8 | inout | 2.5 V | 66
CLR_TX_n[3] | M12 | inout | 2.5 V | 67
CLR_RX_n[3] | C8 | inout | 2.5 V | 68
CLR_TX_p[4] | R12 | inout | 2.5 V | 71
CLR_RX_p[4] | D7 | inout | 2.5 V | 72
CLR_TX_n[4] | R11 | inout | 2.5 V | 73
CLR_RX_n[4] | C7 | inout | 2.5 V | 74
CLR_TX_p[5] | T13 | inout | 2.5 V | 77
CLR_RX_p[5] | F10 | inout | 2.5 V | 78
CLR_TX_n[5] | T12 | inout | 2.5 V | 79
CLR_RX_n[5] | E10 | inout | 2.5 V | 80
CLR_TX_p[6] | R13 | inout | 2.5 V | 83
CLR_RX_p[6] | G5 | inout | 2.5 V | 84
CLR_TX_n[6] | P13 | inout | 2.5 V | 85
CLR_RX_n[6] | F5 | inout | 2.5 V | 86
CLR_TX_p[7] | H7 | inout | 2.5 V | 89
CLR_RX_p[7] | G6 | inout | 2.5 V | 90
CLR_TX_n[7] | G7 | inout | 2.5 V | 91
CLR_RX_n[7] | F6 | inout | 2.5 V | 92
CLR_OUT_p1 | K8 | output | 2.5 V | 95
CLR_CLKIN_p1 | W34 | input | 2.5 V | 96
CLR_OUT_n1 | J8 | output | 2.5 V | 97
CLR_CLKIN_n1 | W35 | input | 2.5 V | 98
CLR_TX_p[8] | M10 | inout | 2.5 V | 101
CLR_RX_p[8] | F7 | inout | 2.5 V | 102
CLR_TX_n[8] | L10 | inout | 2.5 V | 103
CLR_RX_n[8] | E7 | inout | 2.5 V | 104
CLR_TX_p[9] | M8 | inout | 2.5 V | 107
CLR_RX_p[9] | G8 | inout | 2.5 V | 108
CLR_TX_n[9] | M7 | inout | 2.5 V | 109
CLR_RX_n[9] | F8 | inout | 2.5 V | 110
CLR_TX_p[10] | M11 | inout | 2.5 V | 113
CLR_RX_p[10] | G9 | inout | 2.5 V | 114
CLR_TX_n[10] | L11 | inout | 2.5 V | 115
CLR_RX_n[10] | F9 | inout | 2.5 V | 116
CLR_TX_p[11] | N9 | inout | 2.5 V | 119
CLR_RX_p[11] | N6 | inout | 2.5 V | 120
CLR_TX_n[11] | P8 | inout | 2.5 V | 121
CLR_RX_n[11] | N5 | inout | 2.5 V | 122
CLR_TX_p[12] | R9 | inout | 2.5 V | 125
CLR_RX_p[12] | M6 | inout | 2.5 V | 126
CLR_TX_n[12] | R8 | inout | 2.5 V | 127
CLR_RX_n[12] | L5 | inout | 2.5 V | 128
CLR_TX_p[13] | U10 | inout | 2.5 V | 131
CLR_RX_p[13] | R6 | inout | 2.5 V | 132
CLR_TX_n[13] | T9 | inout | 2.5 V | 133
CLR_RX_n[13] | R5 | inout | 2.5 V | 134
CLR_TX_p[14] | V10 | inout | 2.5 V | 137
CLR_RX_p[14] | R7 | inout | 2.5 V | 138
CLR_TX_n[14] | V9 | inout | 2.5 V | 139
CLR_RX_n[14] | P6 | inout | 2.5 V | 140
CLR_TX_p[15] | T10 | inout | 2.5 V | 143
CLR_RX_p[15] | V6 | inout | 2.5 V | 144
CLR_TX_n[15] | R10 | inout | 2.5 V | 145
CLR_RX_n[15] | U5 | inout | 2.5 V | 146
CLR_TX_p[16] | V12 | inout | 2.5 V | 149
CLR_RX_p[16] | W8 | inout | 2.5 V | 150
CLR_TX_n[16] | V11 | inout | 2.5 V | 151
CLR_RX_n[16] | W7 | inout | 2.5 V | 152
CLR_CLKOUT_p2 | W12 | output | 2.5 V | 155
CLR_CLKIN_p2 | W6 | input | 2.5 V | 156
CLR_CLKOUT_n2 | W11 | output | 2.5 V | 157
CLR_CLKIN_n2 | W5 | input | 2.5 V | 158

##

HSMC I2C
Name | Location | Direction | Standard
--- | --- | --- | ---
HSMC_SCL | L19 | output | 1.8 V
HSMC_SDA | M19 | inout | 1.8 V