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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

///** This Verilog HDL file is used for synthesis in chaining DMA design example
//*
//* This file provides the top level for synthesis
//*/
module LEDTEST_TOP (
                                  // inputs:
                                   local_rstn_ext,
                                   pcie_rstn,
//                                   refclk,
//                                   rx_in0,
//                                   rx_in1,
//                                   rx_in2,
//                                   rx_in3,
//                                   rx_in4,
//                                   rx_in5,
//                                   rx_in6,
//                                   rx_in7,
                                   usr_sw,

                                  // outputs:
                                   L0_led,
                                   alive_led,
                                   comp_led,
                                   gen2_led,
                                   lane_active_led,
//                                   tx_out0,
//                                   tx_out1,
//                                   tx_out2,
//                                   tx_out3,
//                                   tx_out4,
//                                   tx_out5,
//                                   tx_out6,
//                                   tx_out7
                                )
;

  output           L0_led;
  output           alive_led;
  output           comp_led;
  output           gen2_led;
  output  [  3: 0] lane_active_led;
//  output           tx_out0;
//  output           tx_out1;
//  output           tx_out2;
//  output           tx_out3;
//  output           tx_out4;
//  output           tx_out5;
//  output           tx_out6;
//  output           tx_out7;
  input            local_rstn_ext;
  input            pcie_rstn;
//  input            refclk;
//  input            rx_in0;
//  input            rx_in1;
//  input            rx_in2;
//  input            rx_in3;
//  input            rx_in4;
//  input            rx_in5;
//  input            rx_in6;
//  input            rx_in7;
  input   [  7: 0] usr_sw;

assign	lane_active_led = 4'b1010;    
endmodule

