BANDWIDTH_TYPE=AUTO
CLK0_DIVIDE_BY=1
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=2
CLK0_PHASE_SHIFT=833
CLK1_DIVIDE_BY=1
CLK1_DUTY_CYCLE=50
CLK1_MULTIPLY_BY=4
CLK1_PHASE_SHIFT=0
CLK2_DIVIDE_BY=1
CLK2_DUTY_CYCLE=50
CLK2_MULTIPLY_BY=4
CLK2_PHASE_SHIFT=833
CLK3_DIVIDE_BY=1
CLK3_DUTY_CYCLE=50
CLK3_MULTIPLY_BY=4
CLK3_PHASE_SHIFT=-1250
CLK4_DIVIDE_BY=1
CLK4_DUTY_CYCLE=50
CLK4_MULTIPLY_BY=4
CLK4_PHASE_SHIFT=0
CLK5_DIVIDE_BY=1
CLK5_DUTY_CYCLE=50
CLK5_MULTIPLY_BY=2
CLK5_PHASE_SHIFT=0
CLK6_DIVIDE_BY=1
CLK6_DUTY_CYCLE=50
CLK6_MULTIPLY_BY=2
CLK6_PHASE_SHIFT=6667
INCLK0_INPUT_FREQUENCY=20000
INTENDED_DEVICE_FAMILY="Stratix III"
LPM_TYPE=altpll
OPERATION_MODE=NO_COMPENSATION
PLL_TYPE=AUTO
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_USED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_FBOUT=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_USED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_USED
PORT_PHASEDONE=PORT_USED
PORT_PHASESTEP=PORT_USED
PORT_PHASEUPDOWN=PORT_USED
PORT_PLLENA=PORT_UNUSED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_USED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_USED
PORT_clk2=PORT_USED
PORT_clk3=PORT_USED
PORT_clk4=PORT_USED
PORT_clk5=PORT_USED
PORT_clk6=PORT_USED
PORT_clk7=PORT_UNUSED
PORT_clk8=PORT_UNUSED
PORT_clk9=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
SELF_RESET_ON_LOSS_LOCK=OFF
USING_FBMIMICBIDIR_PORT=OFF
VCO_FREQUENCY_CONTROL=MANUAL_PHASE
VCO_PHASE_SHIFT_STEP=104
WIDTH_CLOCK=10
DEVICE_FAMILY="Stratix III"
CBX_AUTO_BLACKBOX=ALL
areset
inclk
inclk
phasecounterselect
phasestep
phaseupdown
scanclk
clk
clk
clk
clk
clk
clk
clk
locked
phasedone
