<optimization_record_list>

<optimization_record>
<recommendation_key>
PCI_INST_top
</recommendation_key>
<recommendation>
top
</recommendation>
<recommendation_description>
Follow the recommendations to configure your core.
</recommendation_description>
<description>
megacore variation
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	NA
	</action_description>
	<action_link>
	NA
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="100">
	PCIE
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="Edit Megafunction" quartus_exe="">
dummy.tcl
</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
DEE_top
</recommendation_key>
<recommendation>
Chaining DMA Design Example
</recommendation>
<recommendation_description>
This optional step shows you how to use your PCI Express variation with a high performance chaining DMA back-end application design example.
</recommendation_description>
<description>
In addition to generating a top-level instantiation wrapper for the PCI Express MegaCore function that you can use in your design, the PCI Express Compiler also generates a project for the Quartus II software, containing an application example design with your custom variation of the PCI Express MegaCore function connected to a high performance chaining DMA. For illustrative purposes, the PCI Express IP Advisor walks you through the optional step of using the project generated by the Quartus II software that contains the high performance chaining DMA example design.&lt;p&gt;You can compile this example project in the Quartus II software to get resource utilization and performance estimates. You can also simulate this project using the generated VHDL or Verilog HDL testbench in conjunction with the root port bus functional model (BFM) provided. This project is called top_example_chaining_top.qpf which is located at D:\My_Work\PCIe_Demo\alt_pcie_qar_90\hip_gen2_x8_128_sig_reva\top_examples\chaining_dma&lt;p&gt;If you enabled generation of the IP functional simulation model on the MegaWizard's EDA page, the Verilog HDL(.vo) or VHDL (.vho) file is generated to your project directory D:\My_Work\PCIe_Demo\alt_pcie_qar_90\hip_gen2_x8_128_sig_reva.
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	If you choose to try the example design project provided with this MegaCore function, click Open Example below. You can then compile, simulate, and study this example.&lt;p&gt;If you do not choose to try the example project, proceed to the next step in the IP Advisor.
	</action_description>
	<action_link>
	OPEN_PROJECT
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="90">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="Open Example Project" quartus_exe="">
top_examples/chaining_dma/top_example_chaining_top.qpf
</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
INFOIC_top
</recommendation_key>
<recommendation>
Information about using Quartus II incremental compilation
</recommendation>
<recommendation_description>
You can use the incremental compilation feature in the Quartus II software to help meet your performance goals while reducing compilation time.
</recommendation_description>
<description>

Please see the description of the incremental compilation flow in Quartus II Help. For PCI Express, Altera recommends that you use a MegaCore variant with an Avalon-ST application interface. You can use either the top-down or bottom up incremental compilation methodology. You should set the partition boundary at the clear text ICM module located under the D:\My_Work\PCIe_Demo\alt_pcie_qar_90\hip_gen2_x8_128_sig_reva\top_examples\common\incremental_compile_module subdirectory.
</description>
<more_info_link>
comp.chm::/increment/comp_view_qid.htm
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	NA
	</action_description>
	<acf_variable_list>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="100">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="" quartus_exe="">

</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
INSTVAR_top
</recommendation_key>
<recommendation>
Instantiate your PCI Express variation
</recommendation>
<recommendation_description>
You can instantiate your customized PCI Express MegaCore variation into your design.
</recommendation_description>
<description>
Please make sure that your formal and actual port lists match. Altera recommends that you do not leave any input ports unconnected.
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	Instantiate the Verilog module or VHDL entity contained in the following file into your design: top.v&lt;p&gt;To ensure that the timing constraints provided with the MegaCore function work, please make sure that the signal names in your formal and actual port lists match. If you are using more than one instance of the PCI Express MegaCore variation, you need to edit the signal names in the provided timing constraints.&lt;p&gt;Altera recommends that you do not leave any input ports unconnected. See the PCI Express Compiler MegaCore function user guide for more information. 
	</action_description>
	<action_link>
	NA
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="120">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="" quartus_exe="">

</tcl_script>
</optimization_record>


<optimization_record>
<recommendation_key>
SETINST_top
</recommendation_key>
<recommendation>
Modify your Quartus II Settings File (.qsf)
</recommendation>
<recommendation_description>
A tcl script is generated to your project directory for each PCI Express MegaCore variation in your design. These tcl scripts set the appropriate Quartus II Settings File (.qsf) settings for your design. The name of each tcl script is top.tcl.
</recommendation_description>
<description>
Set the Quartus II Settings File (.qsf) settings to meet PCI Express requirements.
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	If you have more than one instance of the PCI Express MegaCore in your design, you need to modify the tcl scripts to specify the correct signal names for each instance before you source each tcl script. For more information please see the PCI Express Compiler user guide.
	</action_description>
	<action_link>
	NA
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="140">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="Modify QSF Settings" quartus_exe="">
D:\My_Work\PCIe_Demo\alt_pcie_qar_90\hip_gen2_x8_128_sig_reva/top.tcl;
</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
VERDEV_top
</recommendation_key>
<recommendation>
Verify that you have chosen a recommended device
</recommendation>
<recommendation_description>
Altera recommends devices and speed-grades depending on the variation you specify.
</recommendation_description>
<description>
Produce a warning or error message based upon variation settings and device selection.
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	NA
	</action_description>
	<action_link>
	NA
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
		<acf_variable name="HIDE">
		
		</acf_variable>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="150">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="Verify Valid Device" quartus_exe="">
dummy.tcl
</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
CHECKSETTING_top
</recommendation_key>
<recommendation>
Check Quartus II Settings File (.qsf) settings
</recommendation>
<recommendation_description>
Check Quartus II Settings File (.qsf) settings made in step 8.  
</recommendation_description>
<description>
Produce a warning describing potential negative impact if the current settings are not recommended.
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	Click Modify QSF Settings below to let the IP Advisor verify the contents of the Quartus II settings file.
	</action_description>
	<action_link>
	NA
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
		<acf_variable name=" HIDE">
		
		</acf_variable>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="170">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="Check Settings" quartus_exe="">
pcie_check_qsf_settings.tcl
</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
CHECKLIC_top
</recommendation_key>
<recommendation>
Check license
</recommendation>
<recommendation_description>
NA
</recommendation_description>
<description>
The PCI Express hard IP mode does not require a license.
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>NA</action_description>
	<action_link>
	NA
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="175">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="" quartus_exe="">
</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
COMPILE_top
</recommendation_key>
<recommendation>
Compile design
</recommendation>
<recommendation_description>
Compile your design
</recommendation_description>
<description>
Compile your design
</description>
<more_info_link>
NA
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
	<action_description>
	Click Start Compilation below to compile your design.
	</action_description>
	<action_link>
	NA
	</action_link>
	<acf_variable_list>
		<acf_variable name="NA">
		
		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="180">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="Start Compilation" quartus_exe="">
dummy.tcl
</tcl_script>
</optimization_record>

<optimization_record>
<recommendation_key>
RUNDSE_top
</recommendation_key>
<recommendation>
Was your timing requirement met?
</recommendation>
<recommendation_description>
Analyze your result to see if you met your timing requirement.</recommendation_description>
<description>
If your timing requirement was not met, run the Quartus II Design Space Explorer. You may need to use the Quartus II Design Space Explorer or Quartus II seed sweeping methodology. See the Quartus II Development Software Handbook for more information.
</description>
<more_info_link>
http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf
</more_info_link>
<effect_list>
	<fmax_effect>
	NA
	</fmax_effect>
	<resource_effect>
	NA
	</resource_effect>
	<compilation_effect>
	NA
	</compilation_effect>
</effect_list>
<action>
   <!-- NEED to run the script qt_seed.tcl
   package require ::quartus::project
   package require ::quartus::flow

   set project_name  "top_chaining_dma.qpf"
   set QT_SEED 0

   if { [ project_exists $project_name ]  } {
   project_open $project_name
   set_global_assignment -name SEED $QT_SEED
   if { [ catch { execute_flow -$COMPILE_OPTION } result ] } {
         puts " TCL:ERROR : Compiling project $project_name revision $project_rev"
      }
   puts " Closing project $project_name revision $project_rev"
   project_close
   # TODO Add timequest analysis
   }
-->

	<action_description>
	Click Run seed sweep to let the IP Advisor run the seed sweep script. This can take a very long time because the script iterates until Fmax is met. The seed sweeping script will generate report file top.pcie_sweep.rpt which summarizes actual compilation Fmax for each seed.
	</action_description>
	<acf_variable_list>
		<acf_variable name="NA">

		</acf_variable>
	</acf_variable_list>
</action>
<device_family_list>
	<device_family exclude="">
	ALL
	</device_family>
</device_family_list>
<conditions>
</conditions>
<image_path>

</image_path>
<parent_list>
	<parent priority="190">
	PCI_INST_top
	</parent>
</parent_list>
<logic_algorithm>
NA
</logic_algorithm>
<tcl_script button_name="Run seed sweep" quartus_exe="">
        D:\My_Work\PCIe_Demo\alt_pcie_qar_90\hip_gen2_x8_128_sig_reva\top_examples\common\incremental_compile_module/../pcie_seed_sweep.tcl
 </tcl_script>
</optimization_record>
</optimization_record_list>
