#Core: ddr2_phy - Instance: u8|the_ddr2|ddr2_controller_phy_inst|ddr2_phy_inst
#Path, Setup Margin, Hold Margin
"Address Command (Slow 900mV 85C Model)",0.571,0.551
"DQS vs CK (Slow 900mV 85C Model)",0.322,0.333
"Half Rate Address/Command (Slow 900mV 85C Model)",2.398,1.089
"Phy (Slow 900mV 85C Model)",-0.542,0.087
"Phy Reset (Slow 900mV 85C Model)",1.537,0.425
"Read Capture (Slow 900mV 85C Model)",0.056,0.279
"Read Resync (All Conditions)",0.526,0.555
"Write (Slow 900mV 85C Model)",0.050,0.108
 
"Address Command (Slow 900mV 0C Model)",0.627,0.548
"DQS vs CK (Slow 900mV 0C Model)",0.355,0.361
"Half Rate Address/Command (Slow 900mV 0C Model)",2.494,1.051
"Phy (Slow 900mV 0C Model)",-0.269,0.050
"Phy Reset (Slow 900mV 0C Model)",1.724,0.412
"Read Capture (Slow 900mV 0C Model)",0.059,0.270
"Read Resync (All Conditions)",0.526,0.555
"Write (Slow 900mV 0C Model)",0.067,0.109
 
"Address Command (Fast 900mV 0C Model)",0.802,0.501
"DQS vs CK (Fast 900mV 0C Model)",0.409,0.417
"Half Rate Address/Command (Fast 900mV 0C Model)",2.845,0.865
"Phy (Fast 900mV 0C Model)",0.783,0.076
"Phy Reset (Fast 900mV 0C Model)",2.877,0.239
"Read Capture (Fast 900mV 0C Model)",0.102,0.290
"Read Resync (All Conditions)",0.526,0.555
"Write (Fast 900mV 0C Model)",0.107,0.162
