
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================


module DE4_DDR2(

	//////// CLOCK //////////
	GCLKIN,
	GCLKOUT_FPGA,
	MAX_CONF_D,
	MAX_PLL_D,
	OSC_50_Bank2,
	OSC_50_Bank3,
	OSC_50_Bank4,
	OSC_50_Bank5,
	OSC_50_Bank6,
	OSC_50_Bank7,
	PLL_CLKIN_p,

	//////// LED x 8 //////////
	LED,

	//////// BUTTON x 4 //////////
	BUTTON,
	CPU_RESET_n,
	EXT_IO,


	//////// DDR2 SODIMM //////////
	M1_DDR2_addr,
	M1_DDR2_ba,
	M1_DDR2_cas_n,
	M1_DDR2_cke,
	M1_DDR2_clk,
	M1_DDR2_clk_n,
	M1_DDR2_cs_n,
	M1_DDR2_dm,
	M1_DDR2_dq,
	M1_DDR2_dqs,
	M1_DDR2_dqsn,
	M1_DDR2_odt,
	M1_DDR2_ras_n,
	M1_DDR2_SA,
	M1_DDR2_SCL,
	M1_DDR2_SDA,
	M1_DDR2_we_n


	//////// DDR2 SODIMM //////////

//	M2_DDR2_addr,
//	M2_DDR2_ba,
//	M2_DDR2_cas_n,
//	M2_DDR2_cke,
//	M2_DDR2_clk,
//	M2_DDR2_clk_n,
//	M2_DDR2_cs_n,
//	M2_DDR2_dm,
//	M2_DDR2_dq,
//	M2_DDR2_dqs,
//	M2_DDR2_dqsn,
//	M2_DDR2_odt,
//	M2_DDR2_ras_n,
//	M2_DDR2_SA,
//	M2_DDR2_SCL,
//	M2_DDR2_SDA,
//	M2_DDR2_we_n 

);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input		          		GCLKIN;
output		          		GCLKOUT_FPGA;
inout		     [2:0]		MAX_CONF_D;
output		     [2:0]		MAX_PLL_D;
input		          		OSC_50_Bank2;
input		          		OSC_50_Bank3;
input		          		OSC_50_Bank4;
input		          		OSC_50_Bank5;
input		          		OSC_50_Bank6;
input		          		OSC_50_Bank7;
input		          		PLL_CLKIN_p;

//////////// LED x 8 //////////
output		     [7:0]		LED;

//////////// BUTTON x 4 //////////
input		     [3:0]		BUTTON;
input		          		CPU_RESET_n;
inout		          		EXT_IO;


//////////// DDR2 SODIMM //////////
output		    [15:0]		M1_DDR2_addr;
output		     [2:0]		M1_DDR2_ba;
output		          		M1_DDR2_cas_n;
output		     [1:0]		M1_DDR2_cke;
inout		     [1:0]		M1_DDR2_clk;
inout		     [1:0]		M1_DDR2_clk_n;
output		     [1:0]		M1_DDR2_cs_n;
output		     [7:0]		M1_DDR2_dm;
inout		    [63:0]		M1_DDR2_dq;
inout		     [7:0]		M1_DDR2_dqs;
inout		     [7:0]		M1_DDR2_dqsn;
output		     [1:0]		M1_DDR2_odt;
output		          		M1_DDR2_ras_n;
output		     [1:0]		M1_DDR2_SA;
output		          		M1_DDR2_SCL;
inout		          		M1_DDR2_SDA;
output		          		M1_DDR2_we_n;


//////////// DDR2 SODIMM //////////
//output		    [15:0]		M2_DDR2_addr;
//output		     [2:0]		M2_DDR2_ba;
//output		          		M2_DDR2_cas_n;
//output		     [1:0]		M2_DDR2_cke;
//inout		     [1:0]		M2_DDR2_clk;
//inout		     [1:0]		M2_DDR2_clk_n;
//output		     [1:0]		M2_DDR2_cs_n;
//output		     [7:0]		M2_DDR2_dm;
//inout		    [63:0]		M2_DDR2_dq;
//inout		     [7:0]		M2_DDR2_dqs;
//inout		     [7:0]		M2_DDR2_dqsn;
//output		     [1:0]		M2_DDR2_odt;
//output		          		M2_DDR2_ras_n;
//output		     [1:0]		M2_DDR2_SA;
//output		          		M2_DDR2_SCL;
//inout		          		M2_DDR2_SDA;
//output		          		M2_DDR2_we_n;



//=======================================================
//  REG/WIRE declarations
//=======================================================




//=======================================================
//  Structural coding
//=======================================================

wire reset_n;
assign reset_n = CPU_RESET_n;

wire	ip_init_done;
wire	wrt_full;


DE4_SOPC SOPC0(
                  // 1) global signals:
                   .clk_50(OSC_50_Bank3),
                   .reset_n(reset_n),

                 // the_Read_Port0   
                   .iCLK_F_to_the_Read_Port0(OSC_50_Bank3),
                   .iIP_INIT_DONE_to_the_Read_Port0(ip_init_done),
                   .iREAD_ACK_F_to_the_Read_Port0(mp_read),
                   .iRST_n_F_to_the_Read_Port0(read_rstn),
                   .oEMPTY_F_from_the_Read_Port0(),
                   .oPORT_READY_F_from_the_Read_Port0(),
                   .oREAD_DATA_F_from_the_Read_Port0(),

                  // the_Write_Port0     
                   .iCLK_F_to_the_Write_Port0(OSC_50_Bank3),
                   .iFLUSH_REQ_F_to_the_Write_Port0(),
                   .iIP_INIT_DONE_to_the_Write_Port0(ip_init_done),
                   .iRST_n_F_to_the_Write_Port0(CPU_RESET_n),
                   .iWRITE_DATA_F_to_the_Write_Port0(write_cnt),
                   .iWRITE_F_to_the_Write_Port0(mp_write),
                   .oBURST_COUNT_from_the_Write_Port0(),
                   .oFLUSH_BUSY_F_from_the_Write_Port0(),
                   .oFULL_F_from_the_Write_Port0(wrt_full),
                  
                  // the_ddr2   
                   .global_reset_n_to_the_ddr2(reset_n),
                   .local_init_done_from_the_ddr2(ip_init_done),
                   .mem_addr_from_the_ddr2(M1_DDR2_addr),
                   .mem_ba_from_the_ddr2(M1_DDR2_ba),
                   .mem_cas_n_from_the_ddr2(M1_DDR2_cas_n),
                   .mem_cke_from_the_ddr2(M1_DDR2_cke),
                   .mem_clk_n_to_and_from_the_ddr2(M1_DDR2_clk_n),
                   .mem_clk_to_and_from_the_ddr2(M1_DDR2_clk),
                   .mem_cs_n_from_the_ddr2(M1_DDR2_cs_n),
                   .mem_dm_from_the_ddr2(M1_DDR2_dm),
                   .mem_dq_to_and_from_the_ddr2(M1_DDR2_dq),
                   .mem_dqs_to_and_from_the_ddr2(M1_DDR2_dqs),
                   .mem_dqsn_to_and_from_the_ddr2(M1_DDR2_dqsn),
                   .mem_odt_from_the_ddr2(M1_DDR2_odt),
                   .mem_ras_n_from_the_ddr2(M1_DDR2_ras_n),
                   .mem_we_n_from_the_ddr2(M1_DDR2_we_n),
                )
;

	reg	mp_write;
	always@(posedge OSC_50_Bank3)
		begin
			if (~CPU_RESET_n)
				mp_write <= 0;
			else if (ip_init_done & ~wrt_full & st_write)
				begin
					if (write_cnt !== 67108863)
						mp_write <= 1;
					else
						mp_write <= 0;
				end
			else
				mp_write <= 0;
		end

	reg	[63:0]write_cnt;
	always@(posedge OSC_50_Bank3)
		if (~CPU_RESET_n)
			write_cnt <= 0;
		else if ( (mp_write) & (write_cnt !== 67108863) )
			write_cnt <= write_cnt + 1;

	reg	mp_read;
	always@(posedge OSC_50_Bank3)
		begin
			if (~CPU_RESET_n)
				mp_read <= 0;
			else if (~BUTTON[1])
				mp_read <= 1;
		end

	reg	read_rstn;
	always@(posedge OSC_50_Bank3)
		begin
			if (~CPU_RESET_n)
				read_rstn <= 0;
			else if (write_cnt == 256)
				read_rstn <= 1;
		end

	reg	st_write;
	always@(posedge OSC_50_Bank3)
		begin
			if (~CPU_RESET_n)
				st_write <= 0;
			else if (~BUTTON[2])
				st_write <= 1;
		end


endmodule
