# TCL File Generated by Component Editor 10.0sp1
# Mon Feb 14 16:51:55 CST 2011
# DO NOT MODIFY


# +-----------------------------------
# | 
# | DDR2_SODIMM_Read_Port "DDR2_SODIMM_Read_Port" v1.0
# | Jeff Chou 2011.02.14.16:51:55
# | Avalon-MM FIFO Port
# | 
# | D:/SVN/Camera_Link_Card/trunk/cd/Demonstration/DE4_530_CLR/DDR2_SODIMM_Read_Port.v
# | 
# |    ./DDR2_SODIMM_Read_Port.v syn
# | 
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.0
# | 
package require -exact sopc 10.0
# | 
# +-----------------------------------

# +-----------------------------------
# | module DDR2_SODIMM_Read_Port
# | 
set_module_property DESCRIPTION "Avalon-MM FIFO Port"
set_module_property NAME DDR2_SODIMM_Read_Port
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property GROUP Terasic
set_module_property AUTHOR "Jeff Chou"
set_module_property DISPLAY_NAME DDR2_SODIMM_Read_Port
set_module_property TOP_LEVEL_HDL_FILE DDR2_SODIMM_Read_Port.v
set_module_property TOP_LEVEL_HDL_MODULE DDR2_SODIMM_Read_Port
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file DDR2_SODIMM_Read_Port.v SYNTHESIS
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
add_parameter DATA_WIDTH_BITS INTEGER 128 "Width of Read DATA"
set_parameter_property DATA_WIDTH_BITS DEFAULT_VALUE 128
set_parameter_property DATA_WIDTH_BITS DISPLAY_NAME DATA_WIDTH_BITS
set_parameter_property DATA_WIDTH_BITS TYPE INTEGER
set_parameter_property DATA_WIDTH_BITS UNITS None
set_parameter_property DATA_WIDTH_BITS ALLOWED_RANGES -2147483648:2147483647
set_parameter_property DATA_WIDTH_BITS DESCRIPTION "Width of Read DATA"
set_parameter_property DATA_WIDTH_BITS AFFECTS_GENERATION false
set_parameter_property DATA_WIDTH_BITS HDL_PARAMETER true
add_parameter STARTING_ADDRESS INTEGER 0 "Starting Address of Avalon Bus(Byte Address)"
set_parameter_property STARTING_ADDRESS DEFAULT_VALUE 0
set_parameter_property STARTING_ADDRESS DISPLAY_NAME STARTING_ADDRESS
set_parameter_property STARTING_ADDRESS TYPE INTEGER
set_parameter_property STARTING_ADDRESS UNITS None
set_parameter_property STARTING_ADDRESS ALLOWED_RANGES -2147483648:2147483647
set_parameter_property STARTING_ADDRESS DESCRIPTION "Starting Address of Avalon Bus(Byte Address)"
set_parameter_property STARTING_ADDRESS AFFECTS_GENERATION false
set_parameter_property STARTING_ADDRESS HDL_PARAMETER true
add_parameter PORT_SIZE_BYTES INTEGER 1104000 "Total Size of the Accessed Memory"
set_parameter_property PORT_SIZE_BYTES DEFAULT_VALUE 1104000
set_parameter_property PORT_SIZE_BYTES DISPLAY_NAME PORT_SIZE_BYTES
set_parameter_property PORT_SIZE_BYTES TYPE INTEGER
set_parameter_property PORT_SIZE_BYTES UNITS None
set_parameter_property PORT_SIZE_BYTES ALLOWED_RANGES -2147483648:2147483647
set_parameter_property PORT_SIZE_BYTES DESCRIPTION "Total Size of the Accessed Memory"
set_parameter_property PORT_SIZE_BYTES AFFECTS_GENERATION false
set_parameter_property PORT_SIZE_BYTES HDL_PARAMETER true
add_parameter BURST_COUNT INTEGER 8
set_parameter_property BURST_COUNT DEFAULT_VALUE 8
set_parameter_property BURST_COUNT DISPLAY_NAME BURST_COUNT
set_parameter_property BURST_COUNT TYPE INTEGER
set_parameter_property BURST_COUNT ENABLED false
set_parameter_property BURST_COUNT UNITS None
set_parameter_property BURST_COUNT ALLOWED_RANGES -2147483648:2147483647
set_parameter_property BURST_COUNT AFFECTS_GENERATION false
set_parameter_property BURST_COUNT HDL_PARAMETER true
# | 
# +-----------------------------------

# +-----------------------------------
# | display items
# | 
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_master
# | 
add_interface avalon_master avalon start
set_interface_property avalon_master associatedClock clock_sink
set_interface_property avalon_master burstOnBurstBoundariesOnly false
set_interface_property avalon_master doStreamReads false
set_interface_property avalon_master doStreamWrites false
set_interface_property avalon_master linewrapBursts false

set_interface_property avalon_master ASSOCIATED_CLOCK clock_sink
set_interface_property avalon_master ENABLED true

add_interface_port avalon_master oADDRESS address Output 32
add_interface_port avalon_master oCS chipselect Output 1
add_interface_port avalon_master oREAD read Output 1
add_interface_port avalon_master iREAD_DATA readdata Input 256
add_interface_port avalon_master iREAD_VALID readdatavalid Input 1
add_interface_port avalon_master oBURST_COUNT burstcount Output 8
add_interface_port avalon_master iWAIT_REQ waitrequest Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock_sink
# | 
add_interface clock_sink clock end

set_interface_property clock_sink ENABLED true

add_interface_port clock_sink iCLK clk Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock_sink_reset
# | 
add_interface clock_sink_reset reset end
set_interface_property clock_sink_reset associatedClock clock_sink
set_interface_property clock_sink_reset synchronousEdges DEASSERT

set_interface_property clock_sink_reset ASSOCIATED_CLOCK clock_sink
set_interface_property clock_sink_reset ENABLED true

add_interface_port clock_sink_reset iRST_n reset_n Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point conduit_end
# | 
add_interface conduit_end conduit end

set_interface_property conduit_end ENABLED true

add_interface_port conduit_end iRST_n_F export Input 1
add_interface_port conduit_end iCLK_F export Input 1
add_interface_port conduit_end iREAD_ACK_F export Input 1
add_interface_port conduit_end oREAD_DATA_F export Output DATA_WIDTH_BITS
add_interface_port conduit_end oEMPTY_F export Output 1
add_interface_port conduit_end oPORT_READY_F export Output 1
add_interface_port conduit_end iIP_INIT_DONE export Input 1
add_interface_port conduit_end c_state export Output 4
add_interface_port conduit_end error export Output 1
# | 
# +-----------------------------------
