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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

///** This Verilog HDL file is used for synthesis in chaining DMA design example
//*
//* This file provides the top level for synthesis
//*/
module top_example_chaining_top (
                                  // inputs:
                                   local_rstn_ext,
                                   pcie_rstn,
                                   refclk,
                                   rx_in0,
                                   rx_in1,
                                   rx_in2,
                                   rx_in3,
                                    rx_in4,
                                   rx_in5,
                                   rx_in6,
                                   rx_in7,
                                   usr_sw,

                                  // outputs:
//                                   L0_led,
//                                   alive_led,
//                                   comp_led,
                                   gen2_led,
                                   lane_active_led,
                                   tx_out0,
                                   tx_out1,
                                   tx_out2,
                                   tx_out3,
                                   tx_out4,
                                   tx_out5,
                                   tx_out6,
                                   tx_out7,
                                   
                                   user_led,
                                   user_pb
                                )
;

  output reg	[7:0]user_led;
  output           gen2_led;
  output  [  3: 0] lane_active_led;
  output           tx_out0;
  output           tx_out1;
  output           tx_out2;
  output           tx_out3;
  output           tx_out4;
  output           tx_out5;
  output           tx_out6;
  output           tx_out7;
  input            local_rstn_ext;
  input            pcie_rstn;
  input            refclk;
  input            rx_in0;
  input            rx_in1;
  input            rx_in2;
  input            rx_in3;
  input            rx_in4;
  input            rx_in5;
  input            rx_in6;
  input            rx_in7;
  input   [  7: 0] usr_sw;
  input	[2:1]user_pb;

  reg              L0_led;
  reg     [ 25: 0] alive_cnt;
  reg              alive_led;
  wire             any_rstn;
  reg              any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102"  */;
  reg              any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102"  */;
  wire             clk_out_buf;
  reg              comp_led;
  reg              gen2_led;
  wire             gen2_speed;
  reg     [  3: 0] lane_active_led;
  wire             local_rstn;
  wire    [  3: 0] open_lane_width_code;
  wire    [  3: 0] open_phy_sel_code;
  wire    [  3: 0] open_ref_clk_sel_code;

  wire             safe_mode;

  wire             tx_out0;
  wire             tx_out1;
  wire             tx_out2;
  wire             tx_out3;
  wire             tx_out4;
  wire             tx_out5;
  wire             tx_out6;
  wire             tx_out7;

  assign safe_mode = 1;
  assign local_rstn = safe_mode | local_rstn_ext;
  assign any_rstn = pcie_rstn & local_rstn;

  //reset Synchronizer
  always @(posedge clk_out_buf or negedge any_rstn)
    begin
      if (any_rstn == 0)
        begin
          any_rstn_r <= 0;
          any_rstn_rr <= 0;
        end
      else 
        begin
          any_rstn_r <= 1;
          any_rstn_rr <= any_rstn_r;
        end
    end


  //LED logic
//  always @(posedge clk_out_buf or negedge any_rstn_rr)
//    begin
//      if (any_rstn_rr == 0)
//        begin
//          alive_cnt <= 0;
//          alive_led <= 0;
//          comp_led <= 0;
//          L0_led <= 0;
//          lane_active_led <= 0;
//        end
//      else 
//        begin
//          alive_cnt <= alive_cnt +1;
//          alive_led <= alive_cnt[25];
//          comp_led <= ~(test_out_icm[4 : 0] == 5'b00011);
//          L0_led <= ~(test_out_icm[4 : 0] == 5'b01111);
//          lane_active_led[3 : 0] <= ~(test_out_icm[8 : 5]);
//        end
//    end


  //Gen2 LED logic
  always @(posedge clk_out_buf or negedge any_rstn_rr)
    begin
      if (any_rstn_rr == 0)
          gen2_led <= 0;
      else 
        gen2_led <= ~gen2_speed;
    end


  top_example_chaining_pipen1b core
    (
      .core_clk_out (clk_out_buf),
      .gen2_speed (gen2_speed),
      .local_rstn (local_rstn),
      .pcie_rstn (pcie_rstn),
      .phy_sel_code (open_phy_sel_code),
      .pipe_mode (1'b0),
      .pld_clk (clk_out_buf),
      .refclk (refclk),
      .rx_in0 (rx_in0),
      .rx_in1 (rx_in1),
      .rx_in2 (rx_in2),
      .rx_in3 (rx_in3),
      .rx_in4 (rx_in4),
      .rx_in5 (rx_in5),
      .rx_in6 (rx_in6),
      .rx_in7 (rx_in7),

      .tx_out0 (tx_out0),
      .tx_out1 (tx_out1),
      .tx_out2 (tx_out2),
      .tx_out3 (tx_out3),
      .tx_out4 (tx_out4),
      .tx_out5 (tx_out5),
      .tx_out6 (tx_out6),
      .tx_out7 (tx_out7),

      
      //Single Cycle Memory or Register R/W Local Interface
      .sc_rd_addr       (sc_rd_addr),
      .sc_rd_data       (sc_rd_data),
      .sc_rd_read       (sc_rd_read),
      .sc_rd_dval (sc_rd_dval),
      .sc_wr_addr       (sc_wr_addr),
      .sc_wr_data       (sc_wr_data),
      .sc_wr_be         (sc_wr_be),
      .sc_wr_write		(sc_wr_write),
	
      //PCIe DMA Write data to PC
      .read_address  (read_address    ),
		.read_wait     (read_wait),
		.read          (read       ),
		.read_data     (read_data   ), 
		.real_read(real_read),
      
		.rd_wrreq_d		(rd_wrreq_d),
		.rd_read_int	(rd_read_int),
		.rd_wr_fifo_wrreq (rd_wr_fifo_wrreq),
		
		//PCIe DMA Read data from PC
		.write_data(write_data),
      .write_address(write_address),
      .write(write),
      .write_byteena(write_byteena)
      
      
    );
		reg    				sc_rd_dval;
		wire 	[11:0]      sc_rd_addr;
		reg 	[127:0]     sc_rd_data;
		wire          		sc_rd_read;
		wire 	[11:0]      sc_wr_addr;
		wire 	[127:0]     sc_wr_data;
		wire					sc_wr_write;
		wire 	[15:0] 		sc_wr_be;
		
	
		wire  [127:0] 		read_data;
		wire  [11:0] 		read_address;
		wire            	read;
		wire           	read_wait;

		wire	[5:0] 		rd_wrreq_d;
		wire					rd_read_int;
		wire					rd_wr_fifo_wrreq;
		
		wire	[127:0]		write_data;
		wire	[11:0]		write_address;
		wire	[15:0]		write_byteena;
		wire					write;

		reg	[11:0]		rd_addr_delay1;
		reg	[11:0]		rd_addr_delay2;
		
		//	Address Decode for Controlling LED
		always@(posedge clk_out_buf)
			begin
				if ( (sc_wr_write) & ( sc_wr_addr == 12'h34 ) )
					user_led <= sc_wr_data[7:0];
			end
		
		//	Address Decode for Button Status Monitor
		always@(posedge clk_out_buf)
			begin
				if ( ( sc_rd_read ) & ( sc_rd_addr == 12'h34 ) )
					begin
						sc_rd_dval <= 1;
						sc_rd_data <= { 126'h0, user_pb[2:1]};
					end
				else
					begin
						sc_rd_data <= 0;
						sc_rd_dval <= 0;
					end
			end
		
		
		
		
		always@(posedge clk_out_buf)
			begin
				rd_addr_delay1 <= read_address;			
			end
		
		internal_ram i_ram(
			
			
			.clock(clk_out_buf),	
			.rdaddress(rd_addr_delay1),
			.rden(real_read),
			.q(read_data),
			.wraddress(write_address[7:0]),
			.byteena_a(16'hffff),
			.wren(write),
			.data(write_data)
			
			);
                                       
		
		
		

endmodule

