ddr2_multi_port



2010.07.19.09:52:03 Datasheet
Overview
  clk_50  ddr2_multi_port


Peripheral

   ddr2 altmemddr2 9.1
Memory Map
Read_Port0 Write_Port0
 avalon_master  avalon_master
  ddr2
s1  0x00000000 0x00000000

clk_50

clock_source v9.1





Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr2

altmemddr2 v9.1

clk_50 clk   ddr2
  refclk
Read_Port0 avalon_master  
  s1
Write_Port0 avalon_master  
  s1
sysclk   Read_Port0
  clock_sink
sysclk   Write_Port0
  clock_sink




Parameters

pipeline_commands false
debug_en false
export_debug_port false
use_generated_memory_model true
dedicated_memory_clk_phase_label Dedicated memory clock phase:
mem_if_clk_mhz 400.0
quartus_project_exists false
local_if_drate HALF
enable_v72_rsu false
local_if_clk_mhz_label 200.0
new_variant true
mem_if_memtype DDR2 SDRAM
pll_ref_clk_mhz 50.0
mem_if_clk_ps_label (2500 ps)
family Stratix IV
project_family Stratix IV
speed_grade 2
dedicated_memory_clk_phase 0
pll_ref_clk_ps_label (20000 ps)
avalon_burst_length 1
mem_if_clk_pair_count 2
mem_if_cs_per_dimm 1
pre_latency_label Fix read latency at:
dedicated_memory_clk_en false
mirror_addressing 0
mem_if_bankaddr_width 3
register_control_word_9 0000
mem_if_rowaddr_width 14
mem_dyn_deskew_en false
post_latency_label cycles (0 cycles=minimum latency, non-deterministic)
mem_if_dm_pins_en Yes
local_if_dwidth_label 256
register_control_word_7 0000
register_control_word_8 0000
mem_if_preset Custom (DE4_DDR2_800_1GB)
mem_if_pchaddr_bit 10
WIDTH_RATIO 4
vendor Micron
register_control_word_3 0000
register_control_word_4 0000
chip_or_dimm Unbuffered DIMM
register_control_word_5 0000
register_control_word_6 0000
mem_fmax 400.0
register_control_word_0 0000
register_control_word_size 4
register_control_word_1 0000
register_control_word_2 0000
register_control_word_11 0000
register_control_word_10 0000
mem_if_cs_width 1
mem_if_preset_rlat 0
mem_if_cs_per_rank 1
fast_simulation_en FAST
register_control_word_15 0000
register_control_word_14 0000
mem_if_dwidth 64
mem_if_dq_per_dqs 8
mem_if_coladdr_width 10
register_control_word_13 0000
register_control_word_12 0000
mem_tiha_ps 375
mem_tdsh_ck 0.2
mem_if_trfc_ns 127.5
mem_tqh_ck 0.36
mem_tisa_ps 375
mem_tdss_ck 0.2
mem_trtp_ns 7.5
mem_if_tinit_us 200.0
mem_if_trcd_ns 15.0
mem_if_twtr_ck 3
mem_trrd_ns 7.5
mem_tdqss_ck 0.25
mem_tqhs_ps 300
mem_tdsa_ps 250
mem_tac_ps 400
mem_tdha_ps 250
mem_if_tras_ns 40.0
mem_if_twr_ns 15.0
mem_tdqsck_ps 350
mem_if_trp_ns 15.0
mem_tdqsq_ps 200
mem_if_tmrd_ns 5.0
mem_tfaw_ns 37.5
mem_if_trefi_us 7.8
mem_tcl_40_fmax 267.0
mem_odt 50
mp_WLH_percent 0.6
mem_drv_str Normal
mp_DH_percent 0.5
input_period 0
mp_QH_percent 0.5
mp_QHS_percent 0.5
mem_tcl_30_fmax 267.0
ac_clk_select dedicated
mp_DQSQ_percent 0.65
mp_DS_percent 0.6
pll_reconfig_ports_en false
mem_btype Sequential
mp_IS_percent 0.7
mem_tcl 6.0
mp_DQSS_percent 0.5
export_bank_info false
mp_DSS_percent 0.6
mem_dll_en Yes
ac_phase 240
mem_if_oct_en true
mem_tcl_60_fmax 400.0
mp_DSH_percent 0.6
mem_if_dqsn_en true
enable_mp_calibration true
mp_IH_percent 0.6
mem_tcl_15_fmax 533.0
dll_external false
mem_bl 8
mp_WLS_percent 0.7
mem_tcl_50_fmax 334.0
mp_DQSCK_percent 0.5
mem_tcl_25_fmax 533.0
mem_tcl_20_fmax 533.0
mem_addr_mapping CHIP_ROW_BANK_COL
ctl_ecc_en false
user_refresh_en false
ctl_hrb_en false
clk_source_sharing_en false
ctl_lookahead_depth 4
ref_clk_source clk_50
ctl_autopch_en false
multicast_wr_en false
ctl_powerdn_en false
auto_powerdn_cycles 0
csr_en false
local_if_type_avalon true
auto_powerdn_en false
ctl_auto_correct_en false
ctl_self_refresh_en false
phy_if_type_afi true
shared_sys_clk_source
controller_type ddrx_ctl
max_local_size 4
tool_context SOPC_BUILDER
mem_srtr Normal
mem_mpr_loc Predefined Pattern
dss_tinit_rst_us 200.0
mem_tcl_90_fmax 400.0
mem_rtt_wr Dynamic ODT off
mem_tcl_100_fmax 400.0
mem_pasr Full Array
mem_asrm Manual SR Reference (SRT)
mem_mpr_oper Predefined Pattern
mem_tcl_80_fmax 400.0
mem_drv_impedance RZQ/7
mem_rtt_nom ODT Disabled
mem_tcl_70_fmax 400.0
mem_wtcl 5.0
mem_dll_pch Fast Exit
mem_atcl Disabled
board_settings_valid true
t_IH 0.375
board_intra_DQS_group_skew 0.02
isi_DQS 0.0
addr_cmd_slew_rate 1.0
board_tpd_inter_DIMM 0.05
board_addresscmd_CK_skew 0.0
t_DS_calculated 0.246
isi_addresscmd_hold 0.0
t_IS 0.375
restore_default_toggle false
dqs_dqsn_slew_rate 4.35
dq_slew_rate 1.39
board_inter_DQS_group_skew 0.02
isi_addresscmd_setup 0.0
board_minCK_DQS_skew -0.01
t_IS_calculated 0.375
num_slots_or_devices 1
board_maxCK_DQS_skew 0.01
board_skew_ps 20
t_DH 0.231
ck_ckn_slew_rate 2.0
isi_DQ 0.0
t_IH_calculated 0.375
t_DH_calculated 0.231
t_DS 0.246
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

Read_Port0

DDR2_SODIMM_Read_Port v1.0

ddr2 sysclk   Read_Port0
  clock_sink
avalon_master   ddr2
  s1




Parameters

DATA_WIDTH_BITS 32
STARTING_ADDRESS 0
PORT_SIZE_BYTES 5242880
BURST_COUNT 8
AUTO_CLOCK_SINK_CLOCK_RATE 200000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

Write_Port0

DDR2_SODIMM_Write_Port v1.0

ddr2 sysclk   Write_Port0
  clock_sink
avalon_master   ddr2
  s1




Parameters

DATA_WIDTH_BITS 32
STARTING_ADDRESS 0
PORT_SIZE_BYTES 5242880
BURST_CNT 8
AUTO_CLOCK_SINK_CLOCK_RATE 200000000
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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