pcie_example_design_DUT

2019.07.25.15:58:04 Datasheet
Overview

Memory Map
DUT
 wrdm_master  rddm_master  bam_master

DUT

avmm_bridge_512 v19.1


Parameters

interface_type_hwtcl Avalon-MM
wrala_hwtcl Gen3x16, Interface - 512 bit, 250 MHz
select_design_example_hwtcl DMA
virtual_rp_ep_mode_hwtcl Native Endpoint
user_total_pf_count_hwtcl 1
pf0_bar0_type_hwtcl 64-bit prefetchable memory
pf0_bar0_address_width_hwtcl 16
pf0_bar1_type_hwtcl Disabled
pf0_bar2_type_hwtcl 64-bit prefetchable memory
pf0_bar2_address_width_hwtcl 16
pf0_bar3_type_hwtcl Disabled
pf0_bar4_type_hwtcl Disabled
pf0_bar5_type_hwtcl Disabled
pf0_expansion_base_address_register_hwtcl 0
enable_read_mover_hwtcl 1
read_mover_address_width_hwtcl 64
enable_write_mover_hwtcl 1
write_mover_address_width_hwtcl 64
enable_advanced_interrupt_hwtcl 0
enable_bursting_slave_hwtcl 0
enable_bursting_master_hwtcl 1
bursting_master_address_width_hwtcl 16
virtual_maxpayload_size_hwtcl 512
pf0_pcie_cap_flr_cap_user_hwtcl 1
pf0_pcie_cap_port_num_hwtcl 1
pf0_pcie_cap_slot_clk_config_hwtcl 1
virtual_pf0_msi_enable_user_hwtcl 0
virtual_pf0_msix_enable_hwtcl 0
pf0_pci_msix_table_size_hwtcl 0
pf0_pci_msix_table_offset_hwtcl 0
pf0_pci_msix_bir_hwtcl 0
pf0_pci_msix_pba_offset_hwtcl 0
pf0_pci_msix_pba_hwtcl 0
virtual_pf1_msix_enable_hwtcl 0
pf1_pci_msix_table_size_hwtcl 0
pf1_pci_msix_table_offset_hwtcl 0
pf1_pci_msix_bir_hwtcl 0
pf1_pci_msix_pba_offset_hwtcl 0
pf1_pci_msix_pba_hwtcl 0
virtual_pf2_msix_enable_hwtcl 0
pf2_pci_msix_table_size_hwtcl 0
pf2_pci_msix_table_offset_hwtcl 0
pf2_pci_msix_bir_hwtcl 0
pf2_pci_msix_pba_offset_hwtcl 0
pf2_pci_msix_pba_hwtcl 0
virtual_pf3_msix_enable_hwtcl 0
pf3_pci_msix_table_size_hwtcl 0
pf3_pci_msix_table_offset_hwtcl 0
pf3_pci_msix_bir_hwtcl 0
pf3_pci_msix_pba_offset_hwtcl 0
pf3_pci_msix_pba_hwtcl 0
pf0_pcie_slot_imp_hwtcl 0
pf0_pcie_cap_slot_power_limit_value_hwtcl 0
pf0_pcie_cap_slot_power_limit_scale_hwtcl 0
pf0_pcie_cap_phy_slot_num_hwtcl 0
pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl 0
pf0_pcie_cap_ep_l1_accpt_latency_hwtcl 0
cvp_user_id_hwtcl 0
hip_reconfig_hwtcl 0
xcvr_reconfig_hwtcl 0
xcvr_adme_hwtcl 0
pcie_link_inspector_hwtcl 0
pf0_pcie_cap_sel_deemphasis_hwtcl 6dB
anlg_voltage 1_0V
enable_hip_status_for_avmm_hwtcl 0
pf0_pci_type0_vendor_id_hwtcl 4466
pf0_pci_type0_device_id_hwtcl 0
pf0_revision_id_hwtcl 1
pf0_class_code_hwtcl 0
pf0_subsys_vendor_id_hwtcl 0
pf0_subsys_dev_id_hwtcl 0
pf1_pci_type0_vendor_id_hwtcl 0
pf1_pci_type0_device_id_hwtcl 0
pf1_revision_id_hwtcl 0
pf1_class_code_hwtcl 0
pf1_subsys_vendor_id_hwtcl 0
pf1_subsys_dev_id_hwtcl 0
pf2_pci_type0_vendor_id_hwtcl 0
pf2_pci_type0_device_id_hwtcl 0
pf2_revision_id_hwtcl 0
pf2_class_code_hwtcl 0
pf2_subsys_vendor_id_hwtcl 0
pf2_subsys_dev_id_hwtcl 0
pf3_pci_type0_vendor_id_hwtcl 0
pf3_pci_type0_device_id_hwtcl 0
pf3_revision_id_hwtcl 0
pf3_class_code_hwtcl 0
pf3_subsys_vendor_id_hwtcl 0
pf3_subsys_dev_id_hwtcl 0
enable_completion_checking_hwtcl 0
enable_dma_msix_table_hwtcl 0
enable_example_design_sim_hwtcl 1
select_example_design_sim_BFM_hwtcl Intel FPGA BFM
enable_example_design_synth_hwtcl 1
select_design_example_rtl_lang_hwtcl Verilog
chosen_devkit_hwtcl NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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