Altera® OpenCL™ Design Example
Channelizer

This readme file for the Channelizer OpenCL Design Example contains information about the design example package. For more examples, please visit the Altera OpenCL Design Examples page.

Description

This benchmark demonstrates an OpenCL implementation of a channelizer design on Altera FPGAs. The channelizer combines a polyphase filter bank (PFB) with a fast Fourier transform to reduce the effects of spectral leakage on the resulting frequency spectrum. The benchmark processes a stream containing multiple sets of 4k real-valued samples. The benchmark outputs the results of the last stage's 4k-point FFT.

The core kernels of this benchmark (fft1d, filter, reorder) are designed to operate in a streaming manner, using Altera's channels extension to the OpenCL standard. The channelizer accepts 8 real samples streaming into the PFB stage and produces 8 complex FFT bins per clock cycle. The channelizer is connected to a test harness that transfers data bewteen global memory and the input and output streams. This eliminates the need for additional external hardware to produce and consume streaming data. The data_in and data_out kernels implement this test harness.

A brief description of the kernels making up this example design follows:

Kernel Description
data_in Read sample data from global memory and push data onto the channelizer's input channel at a rate of 8 real 32-bit samples per cycle.
filter Implements an 8-stage polyphase filter bank which applies a Hanning-windowed sinc filter to the samples.
reorder Reorders the stream of data to convert in-order samples to strided samples for the FFT engine. See the 1D FFT design example for more information on the expected input format of the fft1d kernel.
fft1d A 4k complex single-precision floating point FFT engine.
data_out Transfers data from the output channel to a buffer in global memory. In order to reduce the memory bandwidth demands, this kernel converts the complex frequency bin data into magnitude-squared data for consumption by the host.

More information about individual kernels can be found in the kernel source code.

The host application generates sample data by sampling a linear superposition of three sine waves, writes these samples to DDR, and enqueues the 5 kernels and tasks with enough work to precisely measure the system's bandwidth and runtime. The frequency data is read back from the FPGA and compared against a software implementation of the same algorithm.

Software & Hardware Requirements

Requirement Version OpenCL KernelHost Program
Hardware
Compile
Emulation
Compile
HardwareEmulation
CompileRunCompileRun
Altera Complete Design Suite (Quartus II)16.0 or later
Altera SDK for OpenCL16.0 or later
(either)
(either)
(either)
(either)
Altera Runtime Environment for OpenCL16.0 or later
Board Support Package16.0-compatible
Board Hardware-
gcc4.4.7 or later
GNU Make3.8.1 or later

Package Contents

Path Description
channelizer/
channelizer.pdf A walkthrough of tools, concepts, and results of an FPGA channelizer design written in OpenCL.
Makefile Makefile for host program
bin/ Host program, AOCX files
device/ OpenCL kernel files
channelizer.cl Top-level OpenCL kernel file
host/
inc/ Host include files
src/ Host source files

Additional Documentation

This presentation contains detailed information about this design:

  • Overview of the application
  • Using Altera's channels vendor extension to efficiently pass data between kernels
  • Deep dive of implementation architecture
  • Performance and resource usage results

Compiling the OpenCL Kernel

The top-level OpenCL kernel file is device/channelizer.cl.

To compile the OpenCL kernel, run:

aoc device/channelizer.cl -o bin/channelizer.aocx --fp-relaxed --fpc --board <board>

where <board> matches the board you want to target. The -o bin/channelizer.aocx argument is used to place the compiled binary in the location that the host program expects.

If you are unsure of the boards available, use the following command to list available boards:

aoc --list-boards

Compiling for Emulator

To use the emulation flow, the compilation command just needs to be modified slightly:

aoc -march=emulator device/channelizer.cl -o bin/channelizer.aocx --fp-relaxed --fpc --board <board>

Compiling the Host Program

To compile the host program, run:

make

The compiled host program will be located at bin/host.

Running the Host Program

Before running the host program, you should have compiled the OpenCL kernel and the host program. Refer to the above sections if you have not completed those steps.

To run the host program on hardware, execute:

bin/host

Example output of running this benchmark is shown below:

Using AOCX: channelizer.aocx

Init complete!
Launching FFT transform
        Processing time = 933.5220ms
        Throughput = 2.0847 Gpoints / sec
        L2-Norm check: PASSED
Output

Running with the Emulator

Prior to running the emulation flow, ensure that you have compiled the kernel for emulation. Refer to the above sections if you have not done so. Also, please set up your environment for emulation. Please see the Altera SDK for OpenCL Programming Guide for more information.

For this example design, the suggested emulation command is:

CL_CONTEXT_EMULATOR_DEVICE_ALTERA=1 bin/host -i=200

Host Parameters

The general command-line for the host program is:

bin/host [-i=<#>]

where the one parameter is:

Parameter Type Default Description
-i=<#> Optional 85 × 58 × 1024 Number of iterations; must be a multiple of 8

OpenCL Binary Selection

The host program requires a OpenCL binary (AOCX) file to run. For this example design, OpenCL binary files should be placed in the bin directory.

By default, the host program will look for a binary file in the following order (earlier pattern matches take priority):

  1. A file named channelizer.aocx.
  2. A file named channelizer_<board>_160.aocx, where <board> is the name of the board (as passed as the --board argument to aoc).

Release History

Example Version SDK Version Date Changes
1.4 16.0 June 2016
  • Fixed makefile.
1.3 14.1 December 2014
  • New readme documentation.
  • Provide suggested emulation-specific arguments.
  • Remove __attribute((task))__ from kernels (no longer necessary).
  • Updated PDF to fix animations in the source presentation.
1.2 14.0 July 2014
  • Update documentation for 14.0 release.
  • Add optional host argument to control number of iterations.
1.1 13.1 January 2014
  • Fix small errors in presentation.
1.0 13.1 December 2013
  • First release of example.

Legal

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Trademarks

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.

Contacting Altera

Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact Altera support (myAltera).