module dvi_out_driver(
	// control
	reset_n,
	clk,
	clk90,
	
	// signal from signal generaotr
	gen_data,
	gen_de,
	gen_hsync,
	gen_vsync,
	
	// dvi output
	dvi_clk,
	dvi_data,
	dvi_de,
	dvi_hsync,
	dvi_vsync
);


input			reset_n;
input			clk;
input			clk90;

input	[23:0]	gen_data;
input			gen_de;
input			gen_hsync;
input			gen_vsync;

output				dvi_clk;
output		[11:0]	dvi_data;
output	reg			dvi_de;
output	reg			dvi_hsync;
output	reg			dvi_vsync;

always @(posedge clk or negedge reset_n)
begin
	if (~reset_n)
		dvi_de <= 1'b0;
	else
		dvi_de <= gen_de;
end				

always @(posedge clk or negedge reset_n)
begin
	if (~reset_n)
		begin
			dvi_hsync <= 1'b0;
			dvi_vsync <= 1'b0;
		end
	else
		begin
			dvi_hsync <= gen_hsync;
			dvi_vsync <= gen_vsync;
		end
end		

wire aclr;
assign aclr = ~reset_n;



// data out
	// split data into upper and lower parts
	wire [11:0] data_h = gen_data[23:12];
	wire [11:0] data_l = gen_data[11:0];

ddio_out ddio_out_inst(
	.aclr(aclr),
	.datain_h(data_l),
	.datain_l(data_h),
	.outclock(clk),
	.dataout(dvi_data)
	);	
	
// clock out	
ddio_clk_out ddio_clk_out_inst(
	.aclr(aclr),
	.datain_h(1'b1),
	.datain_l(1'b0), 
	.outclock(clk90),
	.dataout(dvi_clk)
	);		




endmodule
