// --------------------------------------------------------------------
// Copyright (c) 2010 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/   
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
// --------------------------------------------------------------------
//
// Major Functions:	DVI Demo
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
//   V1.0 :| BEN               :| 15/12/11  :| Initial Revision
// --------------------------------------------------------------------

module Tr4_DVI(

	//////////// CLOCK //////////
	OSC_50_BANK1,
	OSC_50_BANK3,
	OSC_50_BANK4,
	OSC_50_BANK7,
	OSC_50_BANK8,

	//////////// Loop //////////
	LOOP_CLKIN0,
	LOOP_CLKIN1,
	LOOP_CLKOUT0,
	LOOP_CLKOUT1,

	//////////// LED x 4 //////////
	LED,

	//////////// BUTTON x 4 //////////
	BUTTON,

	//////////// SWITCH x 4 //////////
	SW,

	//////////// HSMC-D, HSMC-D connect to DVI - FullHD TX/RX //////////
	DVI_EDID_WP,
	DVI_RX_CLK,
	DVI_RX_CTL,
	DVI_RX_D,
	DVI_RX_DDCSCL,
	DVI_RX_DDCSDA,
	DVI_RX_DE,
	DVI_RX_HS,
	DVI_RX_SCDT,
	DVI_RX_VS,
	DVI_TX_CLK,
	DVI_TX_CTL,
	DVI_TX_D,
	DVI_TX_DDCSCL,
	DVI_TX_DDCSDA,
	DVI_TX_DE,
	DVI_TX_DKEN,
	DVI_TX_HS,
	DVI_TX_HTPLG,
	DVI_TX_ISEL,
	DVI_TX_MSEN,
	DVI_TX_PD_N,
	DVI_TX_SCL,
	DVI_TX_SDA,
	DVI_TX_VS,

	//////////// HSMC D/E/F I2C //////////
	HSMC_DEF_SCL,
	HSMC_DEF_SDA 
);

//=======================================================
//  PARAMETER declarations
//=======================================================


//=======================================================
//  PORT declarations
//=======================================================

//////////// CLOCK //////////
input 		          		OSC_50_BANK1;
input 		          		OSC_50_BANK3;
input 		          		OSC_50_BANK4;
input 		          		OSC_50_BANK7;
input 		          		OSC_50_BANK8;

//////////// Loop //////////
input 		          		LOOP_CLKIN0;
input 		          		LOOP_CLKIN1;
output		          		LOOP_CLKOUT0;
output		          		LOOP_CLKOUT1;

//////////// LED x 4 //////////
output		     [3:0]		LED;

//////////// BUTTON x 4 //////////
input 		     [3:0]		BUTTON;

//////////// SWITCH x 4 //////////
input 		     [3:0]		SW;

//////////// HSMC-D, HSMC-D connect to DVI - FullHD TX/RX //////////
output		          		DVI_EDID_WP;
input 		          		DVI_RX_CLK;
input 		     [3:1]		DVI_RX_CTL;
input 		    [23:0]		DVI_RX_D;
inout 		          		DVI_RX_DDCSCL;
inout 		          		DVI_RX_DDCSDA;
input 		          		DVI_RX_DE;
input 		          		DVI_RX_HS;
input 		          		DVI_RX_SCDT;
input 		          		DVI_RX_VS;
output		          		DVI_TX_CLK;
output		     [3:1]		DVI_TX_CTL;
output		    [23:0]		DVI_TX_D;
inout 		          		DVI_TX_DDCSCL;
inout 		          		DVI_TX_DDCSDA;
output		          		DVI_TX_DE;
output		          		DVI_TX_DKEN;
output		          		DVI_TX_HS;
output		          		DVI_TX_HTPLG;
output		          		DVI_TX_ISEL;
output		          		DVI_TX_MSEN;
output		          		DVI_TX_PD_N;
output		          		DVI_TX_SCL;
inout 		          		DVI_TX_SDA;
output		          		DVI_TX_VS;

//////////// HSMC D/E/F I2C //////////
output		          		HSMC_DEF_SCL;
inout 		          		HSMC_DEF_SDA;


//=======================================================
//  REG/WIRE declarations
//=======================================================
Tr4_DVI_TOP Tr4_DVI_TOP_inst(
  .CLK_50(OSC_50_BANK1),
  .BUTTON(BUTTON),
  .HSMC_DVI_RX_CLK(DVI_RX_CLK),
  .HSMC_DVI_RX_D(DVI_RX_D),
  .HSMC_DVI_RX_DE(DVI_RX_DE),
  .HSMC_DVI_RX_HS(DVI_RX_HS),
  .HSMC_DVI_RX_VS(DVI_RX_VS),
  
  .HSMC_DVI_TX_CLK(DVI_TX_CLK),
  .HSMC_DVI_TX_ISEL(DVI_TX_ISEL),
  .HSMC_DVI_TX_SCL(DVI_TX_SCL),
  .HSMC_DVI_TX_HTPLG(DVI_TX_HTPLG),
  .HSMC_DVI_TX_SDA(DVI_TX_SDA),
  .HSMC_TX_PD_N(DVI_TX_PD_N),
  .HSMC_DVI_TX_DE(DVI_TX_DE),
  .HSMC_DVI_TX_VS(DVI_TX_VS), 
  .HSMC_DVI_TX_HS(DVI_TX_HS), 
  .HSMC_DVI_TX_D(DVI_TX_D),
  .HSMC_DVI_RX_DDCSCL(DVI_TX_DDCSCL),
  .HSMC_DVI_RX_DDCSDA(DVI_TX_DDCSDA),
  .HSMC_EDID_WP(DVI_EDID_WP),
  .LED(LED));



//=======================================================
//  Structural coding
//=======================================================



endmodule
