The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design rom_pll_108.v. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 1, 0, 1, 0, ...). The design rom_pll_108.v has one read port. The read port has 180 words of 1 bits each. The output of the read port is registered by clock.
The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. Read enable port should be enabled for read The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.