Flik top Board Configuration

Flik top Board Configuration

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Copyright © 2003-2018 Terasic Inc. All Rights Reserved.

Pin Assignments:

CLOCK
Name Location Direction IO Standard
OSC_100_CLKUSR AP20 input 1.8 V
SYS_REFCLK1_p AP18 input LVDS
SYS_REFCLK2_p C11 input LVDS

KEY
Name Location Direction IO Standard
CPU_RESET_n AV21 input 1.8 V

LED
Name Location Direction IO Standard
LED[1] D23 output 1.8 V
LED[2] D24 output 1.8 V
LED[3] D25 output 1.8 V
LED[4] E23 output 1.8 V

DDR4A
Name Location Direction IO Standard
DDR4A_REFCLK_p AG5 input LVDS
DDR4A_A[0] AN3 output SSTL-12
DDR4A_A[1] AM4 output SSTL-12
DDR4A_A[2] AL3 output SSTL-12
DDR4A_A[3] AL4 output SSTL-12
DDR4A_A[4] AL5 output SSTL-12
DDR4A_A[5] AK5 output SSTL-12
DDR4A_A[6] AK6 output SSTL-12
DDR4A_A[7] AJ6 output SSTL-12
DDR4A_A[8] AK3 output SSTL-12
DDR4A_A[9] AJ4 output SSTL-12
DDR4A_A[10] AJ5 output SSTL-12
DDR4A_A[11] AH6 output SSTL-12
DDR4A_A[12] AG7 output SSTL-12
DDR4A_A[13] AJ3 output SSTL-12
DDR4A_A[14] AH3 output SSTL-12
DDR4A_A[15] AF7 output SSTL-12
DDR4A_A[16] AE7 output SSTL-12
DDR4A_BA[0] AF5 output SSTL-12
DDR4A_BA[1] AH4 output SSTL-12
DDR4A_CK AK1 output DIFFERENTIAL 1.2-V SSTL
DDR4A_CK_n AK2 output DIFFERENTIAL 1.2-V SSTL
DDR4A_CKE AM1 output SSTL-12
DDR4A_DQS[0] AW6 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[1] AR5 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[2] AN7 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[3] AG9 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[4] AA7 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[5] AE5 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[6] AA2 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[7] AH1 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[0] AV6 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[1] AP6 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[2] AM7 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[3] AG10 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[4] AA8 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[5] AE6 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[6] AA3 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[7] AG1 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQ[0] AU4 inout 1.2-V POD
DDR4A_DQ[1] AT5 inout 1.2-V POD
DDR4A_DQ[2] AT4 inout 1.2-V POD
DDR4A_DQ[3] AV4 inout 1.2-V POD
DDR4A_DQ[4] AR6 inout 1.2-V POD
DDR4A_DQ[5] AW4 inout 1.2-V POD
DDR4A_DQ[6] AU5 inout 1.2-V POD
DDR4A_DQ[7] AW5 inout 1.2-V POD
DDR4A_DQ[8] AR3 inout 1.2-V POD
DDR4A_DQ[9] AP3 inout 1.2-V POD
DDR4A_DQ[10] AT2 inout 1.2-V POD
DDR4A_DQ[11] AT3 inout 1.2-V POD
DDR4A_DQ[12] AP4 inout 1.2-V POD
DDR4A_DQ[13] AN4 inout 1.2-V POD
DDR4A_DQ[14] AU2 inout 1.2-V POD
DDR4A_DQ[15] AU1 inout 1.2-V POD
DDR4A_DQ[16] AN6 inout 1.2-V POD
DDR4A_DQ[17] AN8 inout 1.2-V POD
DDR4A_DQ[18] AM6 inout 1.2-V POD
DDR4A_DQ[19] AL7 inout 1.2-V POD
DDR4A_DQ[20] AL8 inout 1.2-V POD
DDR4A_DQ[21] AK7 inout 1.2-V POD
DDR4A_DQ[22] AM9 inout 1.2-V POD
DDR4A_DQ[23] AL9 inout 1.2-V POD
DDR4A_DQ[24] AH9 inout 1.2-V POD
DDR4A_DQ[25] AJ10 inout 1.2-V POD
DDR4A_DQ[26] AJ8 inout 1.2-V POD
DDR4A_DQ[27] AF12 inout 1.2-V POD
DDR4A_DQ[28] AH8 inout 1.2-V POD
DDR4A_DQ[29] AG12 inout 1.2-V POD
DDR4A_DQ[30] AH11 inout 1.2-V POD
DDR4A_DQ[31] AG11 inout 1.2-V POD
DDR4A_DQ[32] Y10 inout 1.2-V POD
DDR4A_DQ[33] AC7 inout 1.2-V POD
DDR4A_DQ[34] AA10 inout 1.2-V POD
DDR4A_DQ[35] AB10 inout 1.2-V POD
DDR4A_DQ[36] AB11 inout 1.2-V POD
DDR4A_DQ[37] AB9 inout 1.2-V POD
DDR4A_DQ[38] W8 inout 1.2-V POD
DDR4A_DQ[39] Y8 inout 1.2-V POD
DDR4A_DQ[40] AA5 inout 1.2-V POD
DDR4A_DQ[41] AD6 inout 1.2-V POD
DDR4A_DQ[42] Y5 inout 1.2-V POD
DDR4A_DQ[43] AD5 inout 1.2-V POD
DDR4A_DQ[44] Y6 inout 1.2-V POD
DDR4A_DQ[45] Y7 inout 1.2-V POD
DDR4A_DQ[46] AB5 inout 1.2-V POD
DDR4A_DQ[47] AD4 inout 1.2-V POD
DDR4A_DQ[48] Y1 inout 1.2-V POD
DDR4A_DQ[49] W1 inout 1.2-V POD
DDR4A_DQ[50] AB4 inout 1.2-V POD
DDR4A_DQ[51] Y2 inout 1.2-V POD
DDR4A_DQ[52] AC3 inout 1.2-V POD
DDR4A_DQ[53] AC4 inout 1.2-V POD
DDR4A_DQ[54] AB1 inout 1.2-V POD
DDR4A_DQ[55] AB2 inout 1.2-V POD
DDR4A_DQ[56] AC2 inout 1.2-V POD
DDR4A_DQ[57] AD1 inout 1.2-V POD
DDR4A_DQ[58] AF2 inout 1.2-V POD
DDR4A_DQ[59] AG2 inout 1.2-V POD
DDR4A_DQ[60] AF3 inout 1.2-V POD
DDR4A_DQ[61] AE2 inout 1.2-V POD
DDR4A_DQ[62] AE1 inout 1.2-V POD
DDR4A_DQ[63] AE3 inout 1.2-V POD
DDR4A_CS_n AM2 output SSTL-12
DDR4A_RESET_n AN2 output SSTL-12
DDR4A_ODT AR1 output SSTL-12
DDR4A_ACT_n AL2 output SSTL-12
DDR4A_ALERT_n AP1 input SSTL-12
DDR4A_BG AG4 output SSTL-12
DDR4A_DBI_n[0] AR7 inout 1.2-V POD
DDR4A_DBI_n[1] AM5 inout 1.2-V POD
DDR4A_DBI_n[2] AK10 inout 1.2-V POD
DDR4A_DBI_n[3] AJ11 inout 1.2-V POD
DDR4A_DBI_n[4] AB7 inout 1.2-V POD
DDR4A_DBI_n[5] AB6 inout 1.2-V POD
DDR4A_DBI_n[6] Y3 inout 1.2-V POD
DDR4A_DBI_n[7] AD3 inout 1.2-V POD
DDR4A_PAR AH2 output SSTL-12
DDR4A_RZQ AH7 input 1.2 V

DDR4B
Name Location Direction IO Standard
DDR4B_REFCLK_p J3 input LVDS
DDR4B_A[0] L5 output SSTL-12
DDR4B_A[1] M5 output SSTL-12
DDR4B_A[2] L4 output SSTL-12
DDR4B_A[3] M4 output SSTL-12
DDR4B_A[4] M6 output SSTL-12
DDR4B_A[5] M7 output SSTL-12
DDR4B_A[6] K7 output SSTL-12
DDR4B_A[7] L7 output SSTL-12
DDR4B_A[8] K5 output SSTL-12
DDR4B_A[9] K6 output SSTL-12
DDR4B_A[10] N6 output SSTL-12
DDR4B_A[11] N7 output SSTL-12
DDR4B_A[12] L3 output SSTL-12
DDR4B_A[13] K1 output SSTL-12
DDR4B_A[14] K2 output SSTL-12
DDR4B_A[15] H3 output SSTL-12
DDR4B_A[16] H4 output SSTL-12
DDR4B_BA[0] J1 output SSTL-12
DDR4B_BA[1] J4 output SSTL-12
DDR4B_CK N8 output DIFFERENTIAL 1.2-V SSTL
DDR4B_CK_n M9 output DIFFERENTIAL 1.2-V SSTL
DDR4B_CKE P9 output SSTL-12
DDR4B_DQS[0] W9 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[1] V1 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[2] U5 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[3] N1 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[4] B6 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[5] D4 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[6] G5 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[7] M10 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[0] W10 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[1] V2 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[2] U6 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[3] N2 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[4] C6 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[5] D5 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[6] G6 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[7] N11 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQ[0] U9 inout 1.2-V POD
DDR4B_DQ[1] T9 inout 1.2-V POD
DDR4B_DQ[2] U10 inout 1.2-V POD
DDR4B_DQ[3] T8 inout 1.2-V POD
DDR4B_DQ[4] V11 inout 1.2-V POD
DDR4B_DQ[5] R6 inout 1.2-V POD
DDR4B_DQ[6] V8 inout 1.2-V POD
DDR4B_DQ[7] R7 inout 1.2-V POD
DDR4B_DQ[8] T2 inout 1.2-V POD
DDR4B_DQ[9] T4 inout 1.2-V POD
DDR4B_DQ[10] U2 inout 1.2-V POD
DDR4B_DQ[11] V4 inout 1.2-V POD
DDR4B_DQ[12] U1 inout 1.2-V POD
DDR4B_DQ[13] V3 inout 1.2-V POD
DDR4B_DQ[14] W3 inout 1.2-V POD
DDR4B_DQ[15] W4 inout 1.2-V POD
DDR4B_DQ[16] R5 inout 1.2-V POD
DDR4B_DQ[17] V6 inout 1.2-V POD
DDR4B_DQ[18] T5 inout 1.2-V POD
DDR4B_DQ[19] U7 inout 1.2-V POD
DDR4B_DQ[20] P6 inout 1.2-V POD
DDR4B_DQ[21] W5 inout 1.2-V POD
DDR4B_DQ[22] P5 inout 1.2-V POD
DDR4B_DQ[23] T7 inout 1.2-V POD
DDR4B_DQ[24] P3 inout 1.2-V POD
DDR4B_DQ[25] N3 inout 1.2-V POD
DDR4B_DQ[26] R2 inout 1.2-V POD
DDR4B_DQ[27] P1 inout 1.2-V POD
DDR4B_DQ[28] R1 inout 1.2-V POD
DDR4B_DQ[29] M1 inout 1.2-V POD
DDR4B_DQ[30] R3 inout 1.2-V POD
DDR4B_DQ[31] M2 inout 1.2-V POD
DDR4B_DQ[32] C7 inout 1.2-V POD
DDR4B_DQ[33] A4 inout 1.2-V POD
DDR4B_DQ[34] C8 inout 1.2-V POD
DDR4B_DQ[35] F8 inout 1.2-V POD
DDR4B_DQ[36] E8 inout 1.2-V POD
DDR4B_DQ[37] A5 inout 1.2-V POD
DDR4B_DQ[38] B5 inout 1.2-V POD
DDR4B_DQ[39] D8 inout 1.2-V POD
DDR4B_DQ[40] C2 inout 1.2-V POD
DDR4B_DQ[41] D6 inout 1.2-V POD
DDR4B_DQ[42] D3 inout 1.2-V POD
DDR4B_DQ[43] C3 inout 1.2-V POD
DDR4B_DQ[44] C4 inout 1.2-V POD
DDR4B_DQ[45] E5 inout 1.2-V POD
DDR4B_DQ[46] E7 inout 1.2-V POD
DDR4B_DQ[47] E6 inout 1.2-V POD
DDR4B_DQ[48] F9 inout 1.2-V POD
DDR4B_DQ[49] G9 inout 1.2-V POD
DDR4B_DQ[50] H8 inout 1.2-V POD
DDR4B_DQ[51] H6 inout 1.2-V POD
DDR4B_DQ[52] J8 inout 1.2-V POD
DDR4B_DQ[53] J6 inout 1.2-V POD
DDR4B_DQ[54] H7 inout 1.2-V POD
DDR4B_DQ[55] G7 inout 1.2-V POD
DDR4B_DQ[56] L10 inout 1.2-V POD
DDR4B_DQ[57] M12 inout 1.2-V POD
DDR4B_DQ[58] K10 inout 1.2-V POD
DDR4B_DQ[59] N13 inout 1.2-V POD
DDR4B_DQ[60] J9 inout 1.2-V POD
DDR4B_DQ[61] J11 inout 1.2-V POD
DDR4B_DQ[62] M11 inout 1.2-V POD
DDR4B_DQ[63] N12 inout 1.2-V POD
DDR4B_CS_n P11 output SSTL-12
DDR4B_RESET_n L9 output SSTL-12
DDR4B_ODT P8 output SSTL-12
DDR4B_ACT_n R11 output SSTL-12
DDR4B_ALERT_n L8 input SSTL-12
DDR4B_BG J5 output SSTL-12
DDR4B_DBI_n[0] V9 inout 1.2-V POD
DDR4B_DBI_n[1] U4 inout 1.2-V POD
DDR4B_DBI_n[2] W6 inout 1.2-V POD
DDR4B_DBI_n[3] N4 inout 1.2-V POD
DDR4B_DBI_n[4] B4 inout 1.2-V POD
DDR4B_DBI_n[5] F5 inout 1.2-V POD
DDR4B_DBI_n[6] H9 inout 1.2-V POD
DDR4B_DBI_n[7] K11 inout 1.2-V POD
DDR4B_PAR P10 output SSTL-12
DDR4B_RZQ L2 input 1.2 V

SI5340B
Name Location Direction IO Standard
SI5340B_I2C_SCL M21 inout 1.8 V
SI5340B_I2C_SDA M22 inout 1.8 V
SI5340B_INTR N23 input 1.8 V
SI5340B_OE_n K23 output 1.8 V
SI5340B_RST_n L22 output 1.8 V

PCIE
Name Location Direction IO Standard
PCIE_REFCLK_p AN29 input HCSL
PCIE_TX_p[0] AU37 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[1] AT35 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[2] AT39 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[3] AR37 output HSSI DIFFERENTIAL I/O
PCIE_RX_p[0] AN33 input HSSI DIFFERENTIAL I/O
PCIE_RX_p[1] AM31 input HSSI DIFFERENTIAL I/O
PCIE_RX_p[2] AM35 input HSSI DIFFERENTIAL I/O
PCIE_RX_p[3] AL33 input HSSI DIFFERENTIAL I/O
PCIE_PERST_n AW16 input 1.8 V
PCIE_WAKE_n AW18 output 1.8 V

Clock RSV for XCVR
Name Location Direction IO Standard
RSV_REFCLK_p AG29 input LVDS

DEBUG
Name Location Direction IO Standard
DEBUG[1] A19 inout 1.8 V
DEBUG[2] A20 inout 1.8 V
DEBUG[3] A23 inout 1.8 V
DEBUG[4] A24 inout 1.8 V
DEBUG[5] A25 inout 1.8 V
DEBUG[6] A26 inout 1.8 V
DEBUG[7] B22 inout 1.8 V
DEBUG[8] B24 inout 1.8 V
DEBUG[9] B26 inout 1.8 V
DEBUG[10] C21 inout 1.8 V
DEBUG[11] C22 inout 1.8 V
DEBUG[12] C23 inout 1.8 V
DEBUG[13] C24 inout 1.8 V
DEBUG[14] C25 inout 1.8 V
DEBUG[15] C26 inout 1.8 V

M10A10
Name Location Direction IO Standard
M10A10_R_IO[0] K21 inout 1.8 V
M10A10_R_IO[1] K20 inout 1.8 V
M10A10_R_IO[2] H23 inout 1.8 V
M10A10_R_IO[3] J23 inout 1.8 V
M10A10_R_IO[4] N20 inout 1.8 V
M10A10_R_IO[5] P20 inout 1.8 V
M10A10_R_IO[6] L20 inout 1.8 V
M10A10_R_IO[7] M20 inout 1.8 V