ep_g3x8_avmm256_integrated

2019.09.17.11:59:43 Datasheet
Overview

All Components
   DUT altera_pcie_a10_hip 19.1
   ddr4_a_status altera_avalon_pio 19.1
   ddr4_b_status altera_avalon_pio 19.1
   emif_ddr4_a altera_emif 19.1.0
   emif_ddr4_b altera_emif 19.1.0
   mm_clock_crossing_bridge_ddr4_a altera_avalon_mm_clock_crossing_bridge 19.1
   mm_clock_crossing_bridge_ddr4_b altera_avalon_mm_clock_crossing_bridge 19.1
   onchip_memory2_0 altera_avalon_onchip_memory2 19.1
   pio_led altera_avalon_pio 19.1
   pipe_stage_ddr4a_dimm altera_avalon_mm_bridge 19.1
   pipe_stage_ddr4b_dimm altera_avalon_mm_bridge 19.1
Memory Map
DUT
 rxm_bar4  dma_rd_master  dma_wr_master  rd_dcm_master  wr_dcm_master
  DUT
txs  0x00000000 0x00000000
rd_dts_slave  0x80000000
wr_dts_slave  0x80002000
  ddr4_a_status
s1  0x00080000
  ddr4_b_status
s1  0x00080010
  emif_ddr4_a
ctrl_amm_0  0x0000000200000000 0x0000000200000000
  emif_ddr4_b
ctrl_amm_0  0x0000000400000000 0x0000000400000000
  onchip_memory2_0
s1  0x00000000 0x00000000
s2  0x00000000
  pio_led
s1  0x04000010

DUT

altera_pcie_a10_hip v19.1
DUT dma_rd_master   mm_clock_crossing_bridge_ddr4_a
  s0
dma_wr_master  
  s0
coreclkout_hip  
  s0_clk
app_nreset_status  
  m0_reset
app_nreset_status  
  s0_reset
dma_rd_master   mm_clock_crossing_bridge_ddr4_b
  s0
dma_wr_master  
  s0
coreclkout_hip  
  s0_clk
app_nreset_status  
  m0_reset
app_nreset_status  
  s0_reset
dma_rd_master   onchip_memory2_0
  s1
dma_wr_master  
  s2
rxm_bar4  
  s1
coreclkout_hip  
  clk1
coreclkout_hip  
  clk2
app_nreset_status  
  reset1
app_nreset_status  
  reset2
rxm_bar4   pio_led
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset
rxm_bar4   ddr4_a_status
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset
rxm_bar4   ddr4_b_status
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

ddr4_a_status

altera_avalon_pio v19.1
DUT rxm_bar4   ddr4_a_status
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 125000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

ddr4_b_status

altera_avalon_pio v19.1
DUT rxm_bar4   ddr4_b_status
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 125000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

emif_ddr4_a

altera_emif v19.1.0
pipe_stage_ddr4a_dimm m0   emif_ddr4_a
  ctrl_amm_0
reset_bridge_0 out_reset  
  global_reset_n
emif_usr_clk   pipe_stage_ddr4a_dimm
  clk
emif_usr_clk   reset_controller_ddr4a_0
  clk
emif_usr_reset_n  
  reset_in0
emif_usr_clk   reset_controller_ddr4a_1
  clk
emif_usr_reset_n  
  reset_in0
emif_usr_clk   mm_clock_crossing_bridge_ddr4_a
  m0_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_ddr4_b

altera_emif v19.1.0
pipe_stage_ddr4b_dimm m0   emif_ddr4_b
  ctrl_amm_0
reset_bridge_0 out_reset  
  global_reset_n
emif_usr_clk   pipe_stage_ddr4b_dimm
  clk
emif_usr_clk   reset_controller_ddr4b_0
  clk
emif_usr_reset_n  
  reset_in0
emif_usr_clk   reset_controller_ddr4b_1
  clk
emif_usr_reset_n  
  reset_in0
emif_usr_clk   mm_clock_crossing_bridge_ddr4_b
  m0_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_clock_crossing_bridge_ddr4_a

altera_avalon_mm_clock_crossing_bridge v19.1
DUT dma_rd_master   mm_clock_crossing_bridge_ddr4_a
  s0
dma_wr_master  
  s0
coreclkout_hip  
  s0_clk
app_nreset_status  
  m0_reset
app_nreset_status  
  s0_reset
emif_ddr4_a emif_usr_clk  
  m0_clk
m0   pipe_stage_ddr4a_dimm
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_clock_crossing_bridge_ddr4_b

altera_avalon_mm_clock_crossing_bridge v19.1
DUT dma_rd_master   mm_clock_crossing_bridge_ddr4_b
  s0
dma_wr_master  
  s0
coreclkout_hip  
  s0_clk
app_nreset_status  
  m0_reset
app_nreset_status  
  s0_reset
emif_ddr4_b emif_usr_clk  
  m0_clk
m0   pipe_stage_ddr4b_dimm
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

onchip_memory2_0

altera_avalon_onchip_memory2 v19.1
DUT dma_rd_master   onchip_memory2_0
  s1
dma_wr_master  
  s2
rxm_bar4  
  s1
coreclkout_hip  
  clk1
coreclkout_hip  
  clk2
app_nreset_status  
  reset1
app_nreset_status  
  reset2


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 1
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE ep_g3x8_avmm256_integrated_onchip_memory2_0_onchip_memory2_0
INIT_MEM_CONTENT 0
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

pio_led

altera_avalon_pio v19.1
DUT rxm_bar4   pio_led
  s1
coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 125000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pipe_stage_ddr4a_dimm

altera_avalon_mm_bridge v19.1
mm_clock_crossing_bridge_ddr4_a m0   pipe_stage_ddr4a_dimm
  s0
emif_ddr4_a emif_usr_clk  
  clk
reset_controller_ddr4a_1 reset_out  
  reset
m0   emif_ddr4_a
  ctrl_amm_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pipe_stage_ddr4b_dimm

altera_avalon_mm_bridge v19.1
mm_clock_crossing_bridge_ddr4_b m0   pipe_stage_ddr4b_dimm
  s0
emif_ddr4_b emif_usr_clk  
  clk
reset_controller_ddr4b_1 reset_out  
  reset
m0   emif_ddr4_b
  ctrl_amm_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_bridge_0

altera_reset_bridge v19.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_controller_ddr4a_0

altera_reset_controller v19.1
emif_ddr4_a emif_usr_clk   reset_controller_ddr4a_0
  clk
emif_usr_reset_n  
  reset_in0


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_controller_ddr4a_1

altera_reset_controller v19.1
emif_ddr4_a emif_usr_clk   reset_controller_ddr4a_1
  clk
emif_usr_reset_n  
  reset_in0
reset_out   pipe_stage_ddr4a_dimm
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_controller_ddr4b_0

altera_reset_controller v19.1
emif_ddr4_b emif_usr_clk   reset_controller_ddr4b_0
  clk
emif_usr_reset_n  
  reset_in0


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_controller_ddr4b_1

altera_reset_controller v19.1
emif_ddr4_b emif_usr_clk   reset_controller_ddr4b_1
  clk
emif_usr_reset_n  
  reset_in0
reset_out   pipe_stage_ddr4b_dimm
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)
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