ep_g3x8_avmm256_integrated_DUT

2019.09.17.11:47:20 Datasheet
Overview

All Components
   DUT altera_pcie_a10_hip 19.1
Memory Map
DUT
 rxm_bar4  dma_rd_master  dma_wr_master  rd_dcm_master  wr_dcm_master
  DUT
txs 
rd_dts_slave 
wr_dts_slave 

DUT

altera_pcie_a10_hip v19.1


Parameters

interface_type_hwtcl Avalon-MM with DMA
wrala_hwtcl 1
avmm_addr_width_hwtcl 64
cg_impl_cra_av_slave_port_hwtcl 0
cg_enable_advanced_interrupt_hwtcl 0
enable_hip_status_for_avmm_hwtcl 0
internal_controller_hwtcl 1
enable_rxm_burst_hwtcl 0
extended_tag_support_hwtcl 0
user_txs_addr_width_hwtcl 64
port_type_hwtcl Native endpoint
rx_buffer_credit_alloc_hwtcl Low
rx_buffer_credit_alloc_display Header:195 Data:773
enable_avst_reset_hwtcl 0
use_ast_parity_hwtcl 0
multiple_packets_per_cycle_hwtcl 0
cvp_enable_hwtcl 0
use_tx_cons_cred_sel_hwtcl 0
hip_reconfig_hwtcl 0
xcvr_reconfig_hwtcl 0
adme_enable_hwtcl 0
enable_devkit_conduit_hwtcl 0
select_design_example_hwtcl DMA
enable_example_design_sim_hwtcl 1
enable_example_design_synth_hwtcl 1
select_design_example_rtl_lang_hwtcl Verilog
targeted_devkit_hwtcl Arria 10 GX FPGA Development Kit
bar0_type_hwtcl 64-bit prefetchable memory
bar1_type_hwtcl Disabled
bar2_type_hwtcl Disabled
bar3_type_hwtcl Disabled
bar4_type_hwtcl 64-bit prefetchable memory
bar5_type_hwtcl Disabled
bar0_address_width_avmm_hwtcl 0
bar1_address_width_avmm_hwtcl 0
bar2_address_width_avmm_hwtcl 0
bar3_address_width_avmm_hwtcl 0
bar4_address_width_avmm_hwtcl 27
bar5_address_width_avmm_hwtcl 0
io_window_addr_width_hwtcl 0
prefetchable_mem_window_addr_width_hwtcl 0
vendor_id_hwtcl 4466
device_id_hwtcl 57347
revision_id_hwtcl 0
class_code_hwtcl 0
subsystem_vendor_id_hwtcl 0
subsystem_device_id_hwtcl 0
pf0_vf_subsystem_device_id_hwtcl 0
maximum_payload_size_hwtcl 256
completion_timeout_hwtcl NONE
completion_timeout_disable_hwtcl 1
advance_error_reporting_hwtcl 0
ecrc_check_capable_hwtcl 0
ecrc_gen_capable_hwtcl 0
use_crc_forwarding_hwtcl 0
track_rxfc_cplbuf_ovf_hwtcl 0
port_link_number_hwtcl 1
dll_active_report_support_hwtcl 0
surprise_down_error_support_hwtcl 0
slot_clock_cfg_hwtcl 1
msi_multi_message_capable_hwtcl 4
vsec_id_hwtcl 4466
vsec_cap_hwtcl 0
user_id_hwtcl 0
enable_function_msix_support_hwtcl 0
msix_table_size_hwtcl 0
msix_table_offset_hwtcl 0
msix_table_bir_hwtcl 0
msix_pba_offset_hwtcl 0
msix_pba_bir_hwtcl 0
enable_slot_register_hwtcl 0
slot_power_scale_hwtcl 0
slot_power_limit_hwtcl 0
slot_number_hwtcl 0
endpoint_l0_latency_hwtcl 0
endpoint_l1_latency_hwtcl 0
deemphasis_enable_hwtcl 0
gen3_coeff_1_hwtcl 8
pf0_virtio_capability_present_hwtcl 0
pf0_virtio_device_specific_cap_present_hwtcl 0
pf0_virtio_cmn_config_bar_indicator_hwtcl 0
pf0_virtio_cmn_config_bar_offset_hwtcl 0
pf0_virtio_cmn_config_structure_length_hwtcl 0
pf0_virtio_notification_bar_indicator_hwtcl 0
pf0_virtio_notification_bar_offset_hwtcl 0
pf0_virtio_notification_structure_length_hwtcl 0
pf0_virtio_notify_off_multiplier_hwtcl 0
pf0_virtio_isrstatus_bar_indicator_hwtcl 0
pf0_virtio_isrstatus_bar_offset_hwtcl 0
pf0_virtio_isrstatus_structure_length_hwtcl 0
pf0_virtio_devspecific_bar_indicator_hwtcl 0
pf0_virtio_devspecific_bar_offset_hwtcl 0
pf0_virtio_devspecific_structure_length_hwtcl 0
pf0_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf0_virtio_pciconfig_access_bar_offset_hwtcl 0
pf0_virtio_pciconfig_access_structure_length_hwtcl 0
pf1_virtio_capability_present_hwtcl 0
pf1_virtio_device_specific_cap_present_hwtcl 0
pf1_virtio_cmn_config_bar_indicator_hwtcl 0
pf1_virtio_cmn_config_bar_offset_hwtcl 0
pf1_virtio_cmn_config_structure_length_hwtcl 0
pf1_virtio_notification_bar_indicator_hwtcl 0
pf1_virtio_notification_bar_offset_hwtcl 0
pf1_virtio_notification_structure_length_hwtcl 0
pf1_virtio_notify_off_multiplier_hwtcl 0
pf1_virtio_isrstatus_bar_indicator_hwtcl 0
pf1_virtio_isrstatus_bar_offset_hwtcl 0
pf1_virtio_isrstatus_structure_length_hwtcl 0
pf1_virtio_devspecific_bar_indicator_hwtcl 0
pf1_virtio_devspecific_bar_offset_hwtcl 0
pf1_virtio_devspecific_structure_length_hwtcl 0
pf1_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf1_virtio_pciconfig_access_bar_offset_hwtcl 0
pf1_virtio_pciconfig_access_structure_length_hwtcl 0
pf2_virtio_capability_present_hwtcl 0
pf2_virtio_device_specific_cap_present_hwtcl 0
pf2_virtio_cmn_config_bar_indicator_hwtcl 0
pf2_virtio_cmn_config_bar_offset_hwtcl 0
pf2_virtio_cmn_config_structure_length_hwtcl 0
pf2_virtio_notification_bar_indicator_hwtcl 0
pf2_virtio_notification_bar_offset_hwtcl 0
pf2_virtio_notification_structure_length_hwtcl 0
pf2_virtio_notify_off_multiplier_hwtcl 0
pf2_virtio_isrstatus_bar_indicator_hwtcl 0
pf2_virtio_isrstatus_bar_offset_hwtcl 0
pf2_virtio_isrstatus_structure_length_hwtcl 0
pf2_virtio_devspecific_bar_indicator_hwtcl 0
pf2_virtio_devspecific_bar_offset_hwtcl 0
pf2_virtio_devspecific_structure_length_hwtcl 0
pf2_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf2_virtio_pciconfig_access_bar_offset_hwtcl 0
pf2_virtio_pciconfig_access_structure_length_hwtcl 0
pf3_virtio_capability_present_hwtcl 0
pf3_virtio_device_specific_cap_present_hwtcl 0
pf3_virtio_cmn_config_bar_indicator_hwtcl 0
pf3_virtio_cmn_config_bar_offset_hwtcl 0
pf3_virtio_cmn_config_structure_length_hwtcl 0
pf3_virtio_notification_bar_indicator_hwtcl 0
pf3_virtio_notification_bar_offset_hwtcl 0
pf3_virtio_notification_structure_length_hwtcl 0
pf3_virtio_notify_off_multiplier_hwtcl 0
pf3_virtio_isrstatus_bar_indicator_hwtcl 0
pf3_virtio_isrstatus_bar_offset_hwtcl 0
pf3_virtio_isrstatus_structure_length_hwtcl 0
pf3_virtio_devspecific_bar_indicator_hwtcl 0
pf3_virtio_devspecific_bar_offset_hwtcl 0
pf3_virtio_devspecific_structure_length_hwtcl 0
pf3_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf3_virtio_pciconfig_access_bar_offset_hwtcl 0
pf3_virtio_pciconfig_access_structure_length_hwtcl 0
pf4_virtio_capability_present_hwtcl 0
pf4_virtio_device_specific_cap_present_hwtcl 0
pf4_virtio_cmn_config_bar_indicator_hwtcl 0
pf4_virtio_cmn_config_bar_offset_hwtcl 0
pf4_virtio_cmn_config_structure_length_hwtcl 0
pf4_virtio_notification_bar_indicator_hwtcl 0
pf4_virtio_notification_bar_offset_hwtcl 0
pf4_virtio_notification_structure_length_hwtcl 0
pf4_virtio_notify_off_multiplier_hwtcl 0
pf4_virtio_isrstatus_bar_indicator_hwtcl 0
pf4_virtio_isrstatus_bar_offset_hwtcl 0
pf4_virtio_isrstatus_structure_length_hwtcl 0
pf4_virtio_devspecific_bar_indicator_hwtcl 0
pf4_virtio_devspecific_bar_offset_hwtcl 0
pf4_virtio_devspecific_structure_length_hwtcl 0
pf4_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf4_virtio_pciconfig_access_bar_offset_hwtcl 0
pf4_virtio_pciconfig_access_structure_length_hwtcl 0
pf5_virtio_capability_present_hwtcl 0
pf5_virtio_device_specific_cap_present_hwtcl 0
pf5_virtio_cmn_config_bar_indicator_hwtcl 0
pf5_virtio_cmn_config_bar_offset_hwtcl 0
pf5_virtio_cmn_config_structure_length_hwtcl 0
pf5_virtio_notification_bar_indicator_hwtcl 0
pf5_virtio_notification_bar_offset_hwtcl 0
pf5_virtio_notification_structure_length_hwtcl 0
pf5_virtio_notify_off_multiplier_hwtcl 0
pf5_virtio_isrstatus_bar_indicator_hwtcl 0
pf5_virtio_isrstatus_bar_offset_hwtcl 0
pf5_virtio_isrstatus_structure_length_hwtcl 0
pf5_virtio_devspecific_bar_indicator_hwtcl 0
pf5_virtio_devspecific_bar_offset_hwtcl 0
pf5_virtio_devspecific_structure_length_hwtcl 0
pf5_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf5_virtio_pciconfig_access_bar_offset_hwtcl 0
pf5_virtio_pciconfig_access_structure_length_hwtcl 0
pf6_virtio_capability_present_hwtcl 0
pf6_virtio_device_specific_cap_present_hwtcl 0
pf6_virtio_cmn_config_bar_indicator_hwtcl 0
pf6_virtio_cmn_config_bar_offset_hwtcl 0
pf6_virtio_cmn_config_structure_length_hwtcl 0
pf6_virtio_notification_bar_indicator_hwtcl 0
pf6_virtio_notification_bar_offset_hwtcl 0
pf6_virtio_notification_structure_length_hwtcl 0
pf6_virtio_notify_off_multiplier_hwtcl 0
pf6_virtio_isrstatus_bar_indicator_hwtcl 0
pf6_virtio_isrstatus_bar_offset_hwtcl 0
pf6_virtio_isrstatus_structure_length_hwtcl 0
pf6_virtio_devspecific_bar_indicator_hwtcl 0
pf6_virtio_devspecific_bar_offset_hwtcl 0
pf6_virtio_devspecific_structure_length_hwtcl 0
pf6_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf6_virtio_pciconfig_access_bar_offset_hwtcl 0
pf6_virtio_pciconfig_access_structure_length_hwtcl 0
pf7_virtio_capability_present_hwtcl 0
pf7_virtio_device_specific_cap_present_hwtcl 0
pf7_virtio_cmn_config_bar_indicator_hwtcl 0
pf7_virtio_cmn_config_bar_offset_hwtcl 0
pf7_virtio_cmn_config_structure_length_hwtcl 0
pf7_virtio_notification_bar_indicator_hwtcl 0
pf7_virtio_notification_bar_offset_hwtcl 0
pf7_virtio_notification_structure_length_hwtcl 0
pf7_virtio_notify_off_multiplier_hwtcl 0
pf7_virtio_isrstatus_bar_indicator_hwtcl 0
pf7_virtio_isrstatus_bar_offset_hwtcl 0
pf7_virtio_isrstatus_structure_length_hwtcl 0
pf7_virtio_devspecific_bar_indicator_hwtcl 0
pf7_virtio_devspecific_bar_offset_hwtcl 0
pf7_virtio_devspecific_structure_length_hwtcl 0
pf7_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf7_virtio_pciconfig_access_bar_offset_hwtcl 0
pf7_virtio_pciconfig_access_structure_length_hwtcl 0
pf0vf_virtio_capability_present_hwtcl 0
pf0vf_virtio_device_specific_cap_present_hwtcl 0
pf0vf_virtio_cmn_config_bar_indicator_hwtcl 0
pf0vf_virtio_cmn_config_bar_offset_hwtcl 0
pf0vf_virtio_cmn_config_structure_length_hwtcl 0
pf0vf_virtio_notification_bar_indicator_hwtcl 0
pf0vf_virtio_notification_bar_offset_hwtcl 0
pf0vf_virtio_notification_structure_length_hwtcl 0
pf0vf_virtio_notify_off_multiplier_hwtcl 0
pf0vf_virtio_isrstatus_bar_indicator_hwtcl 0
pf0vf_virtio_isrstatus_bar_offset_hwtcl 0
pf0vf_virtio_isrstatus_structure_length_hwtcl 0
pf0vf_virtio_devspecific_bar_indicator_hwtcl 0
pf0vf_virtio_devspecific_bar_offset_hwtcl 0
pf0vf_virtio_devspecific_structure_length_hwtcl 0
pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf0vf_virtio_pciconfig_access_bar_offset_hwtcl 0
pf0vf_virtio_pciconfig_access_structure_length_hwtcl 0
pf1vf_virtio_capability_present_hwtcl 0
pf1vf_virtio_device_specific_cap_present_hwtcl 0
pf1vf_virtio_cmn_config_bar_indicator_hwtcl 0
pf1vf_virtio_cmn_config_bar_offset_hwtcl 0
pf1vf_virtio_cmn_config_structure_length_hwtcl 0
pf1vf_virtio_notification_bar_indicator_hwtcl 0
pf1vf_virtio_notification_bar_offset_hwtcl 0
pf1vf_virtio_notification_structure_length_hwtcl 0
pf1vf_virtio_notify_off_multiplier_hwtcl 0
pf1vf_virtio_isrstatus_bar_indicator_hwtcl 0
pf1vf_virtio_isrstatus_bar_offset_hwtcl 0
pf1vf_virtio_isrstatus_structure_length_hwtcl 0
pf1vf_virtio_devspecific_bar_indicator_hwtcl 0
pf1vf_virtio_devspecific_bar_offset_hwtcl 0
pf1vf_virtio_devspecific_structure_length_hwtcl 0
pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf1vf_virtio_pciconfig_access_bar_offset_hwtcl 0
pf1vf_virtio_pciconfig_access_structure_length_hwtcl 0
pf2vf_virtio_capability_present_hwtcl 0
pf2vf_virtio_device_specific_cap_present_hwtcl 0
pf2vf_virtio_cmn_config_bar_indicator_hwtcl 0
pf2vf_virtio_cmn_config_bar_offset_hwtcl 0
pf2vf_virtio_cmn_config_structure_length_hwtcl 0
pf2vf_virtio_notification_bar_indicator_hwtcl 0
pf2vf_virtio_notification_bar_offset_hwtcl 0
pf2vf_virtio_notification_structure_length_hwtcl 0
pf2vf_virtio_notify_off_multiplier_hwtcl 0
pf2vf_virtio_isrstatus_bar_indicator_hwtcl 0
pf2vf_virtio_isrstatus_bar_offset_hwtcl 0
pf2vf_virtio_isrstatus_structure_length_hwtcl 0
pf2vf_virtio_devspecific_bar_indicator_hwtcl 0
pf2vf_virtio_devspecific_bar_offset_hwtcl 0
pf2vf_virtio_devspecific_structure_length_hwtcl 0
pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf2vf_virtio_pciconfig_access_bar_offset_hwtcl 0
pf2vf_virtio_pciconfig_access_structure_length_hwtcl 0
pf3vf_virtio_capability_present_hwtcl 0
pf3vf_virtio_device_specific_cap_present_hwtcl 0
pf3vf_virtio_cmn_config_bar_indicator_hwtcl 0
pf3vf_virtio_cmn_config_bar_offset_hwtcl 0
pf3vf_virtio_cmn_config_structure_length_hwtcl 0
pf3vf_virtio_notification_bar_indicator_hwtcl 0
pf3vf_virtio_notification_bar_offset_hwtcl 0
pf3vf_virtio_notification_structure_length_hwtcl 0
pf3vf_virtio_notify_off_multiplier_hwtcl 0
pf3vf_virtio_isrstatus_bar_indicator_hwtcl 0
pf3vf_virtio_isrstatus_bar_offset_hwtcl 0
pf3vf_virtio_isrstatus_structure_length_hwtcl 0
pf3vf_virtio_devspecific_bar_indicator_hwtcl 0
pf3vf_virtio_devspecific_bar_offset_hwtcl 0
pf3vf_virtio_devspecific_structure_length_hwtcl 0
pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl 0
pf3vf_virtio_pciconfig_access_bar_offset_hwtcl 0
pf3vf_virtio_pciconfig_access_structure_length_hwtcl 0
pf0_msix_table_size_hwtcl 0
pf0_msix_table_offset_hwtcl 0
pf0_msix_table_bir_hwtcl 0
pf0_msix_pba_offset_hwtcl 0
pf0_msix_pba_bir_hwtcl 0
pf1_msix_table_size_hwtcl 0
pf1_msix_table_offset_hwtcl 0
pf1_msix_table_bir_hwtcl 0
pf1_msix_pba_offset_hwtcl 0
pf1_msix_pba_bir_hwtcl 0
pf2_msix_table_size_hwtcl 0
pf2_msix_table_offset_hwtcl 0
pf2_msix_table_bir_hwtcl 0
pf2_msix_pba_offset_hwtcl 0
pf2_msix_pba_bir_hwtcl 0
pf3_msix_table_size_hwtcl 0
pf3_msix_table_offset_hwtcl 0
pf3_msix_table_bir_hwtcl 0
pf3_msix_pba_offset_hwtcl 0
pf3_msix_pba_bir_hwtcl 0
pf4_msix_table_size_hwtcl 0
pf4_msix_table_offset_hwtcl 0
pf4_msix_table_bir_hwtcl 0
pf4_msix_pba_offset_hwtcl 0
pf4_msix_pba_bir_hwtcl 0
pf5_msix_table_size_hwtcl 0
pf5_msix_table_offset_hwtcl 0
pf5_msix_table_bir_hwtcl 0
pf5_msix_pba_offset_hwtcl 0
pf5_msix_pba_bir_hwtcl 0
pf6_msix_table_size_hwtcl 0
pf6_msix_table_offset_hwtcl 0
pf6_msix_table_bir_hwtcl 0
pf6_msix_pba_offset_hwtcl 0
pf6_msix_pba_bir_hwtcl 0
pf7_msix_table_size_hwtcl 0
pf7_msix_table_offset_hwtcl 0
pf7_msix_table_bir_hwtcl 0
pf7_msix_pba_offset_hwtcl 0
pf7_msix_pba_bir_hwtcl 0
pf0_vf_msix_tbl_size_hwtcl 0
pf0_vf_msix_tbl_offset_hwtcl 0
pf0_vf_msix_tbl_bir_hwtcl 0
pf0_vf_msix_pba_offset_hwtcl 0
pf0_vf_msix_pba_bir_hwtcl 0
pf1_vf_msix_tbl_size_hwtcl 0
pf1_vf_msix_tbl_offset_hwtcl 0
pf1_vf_msix_tbl_bir_hwtcl 0
pf1_vf_msix_pba_offset_hwtcl 0
pf1_vf_msix_pba_bir_hwtcl 0
pf2_vf_msix_tbl_size_hwtcl 0
pf2_vf_msix_tbl_offset_hwtcl 0
pf2_vf_msix_tbl_bir_hwtcl 0
pf2_vf_msix_pba_offset_hwtcl 0
pf2_vf_msix_pba_bir_hwtcl 0
pf3_vf_msix_tbl_size_hwtcl 0
pf3_vf_msix_tbl_offset_hwtcl 0
pf3_vf_msix_tbl_bir_hwtcl 0
pf3_vf_msix_pba_offset_hwtcl 0
pf3_vf_msix_pba_bir_hwtcl 0
rx_polinv_soft_logic_enable 0
enable_soft_dfe 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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