This Board Update Portal web page is being served by a design running in the FPGA on your development board. This page, in coordination with the FPGA design serving it, allows you to write new FPGA images to the flash on your board and provides links to useful information on the Terasic website. The FPGA design contains a Nios® II processor and the Triple Speed Ethernet media access control (MAC) MegaCore® function.. This design is one example of how to remotely update an FPGA system over Ethernet. Remote update can be accomplished without a web server, and it can also be used to update just the firmware of an embedded FPGA system.
Instructions on preparing your own .sof/.elf files for uploading to flash via the Board Update Portal are available in the NET-FMC user manual.
Mouse over the board photo to view features.