Just a Board Image

This page is being served from a web server running on a configurable Nios II processor.

The TR5 is based on Stratix IV GX FPGA (EP4SX230 or EP4SGX530) with integrated transceivers that operate up to 8.5 Gbps allowing engineers to prototype and test their high-speed interfaces quickly and easily.

The TR5 Development Board is complete and easy-to-use, enabling designs with industry-standard high-speed serial protocols including PCI Express (version 2.0) with up to x8-lane configurations, four Serial ATA ports (Revision 3.0), four Gigabit Ethernet ports, two DDR2 SDRAM, nine clock sources to drive the clock circuitry of the TR5. Similarly, the TR5 includes 16-Mb SSRAM memory, 64-Mb flash memory for storing FPGA images and embedded USB-Blaster for FPGA configuration


The contents of this website are contained in a read only zip filing system. Want to replace this with your own custom web content? Follow these steps to do so:

  1. Open the file "ro_zipfs.zip" in your Nios II IDE system library project that this web server was built with.
  2. Add & remove your custom web content. For best results, always include "index.html" and "not_found.html" files in the root. Other files may follow a directory structure.
  3. Save the .zip file with the additional files. Make sure that compression is OFF.
  4. Re-compile your system library & re-program flash as described in the web-server example design readme.txt file.
  5. Keep content sensible in size -- your Nios development board has a limited amount of flash memory.
Note: Content you add must be of a known "type" to be served properly. HTML, GIF, and JPEG images are a few supported by this example application. For more advanced file types you'll need to modify the web-server example application.

Board Status/Control

LEDs
Seven Seg.
sweep

Fan Control

Just a Fan Image