TR4 FPGA Board Configuration



Pin Assignments:




Pin Assignment Table:



CLOCK
Name Location Direction Standard
OSC_50_BANK1 AB34 input 2.5 V
OSC_50_BANK3 AW22 input 2.5 V
OSC_50_BANK4 AV19 input 2.5 V
OSC_50_BANK7 A21 input 1.5V
OSC_50_BANK8 B23 input 1.5V



Loop
Name Location Direction Standard
LOOP_CLKIN0 B22 input 1.5V
LOOP_CLKIN1 B20 input 1.5V
LOOP_CLKOUT0 M20 output 1.5V
LOOP_CLKOUT1 L20 output 1.5V



LED x 4
Name Location Direction Standard
LED[0] B19 output 1.5V
LED[1] A18 output 1.5V
LED[2] D19 output 1.5V
LED[3] C19 output 1.5V



BUTTON x 4
Name Location Direction Standard
BUTTON[0] L19 input 1.5V
BUTTON[1] M19 input 1.5V
BUTTON[2] A19 input 1.5V
BUTTON[3] P20 input 1.5V



SWITCH x 4
Name Location Direction Standard
SW[0] AH18 input 2.5 V
SW[1] AH19 input 2.5 V
SW[2] D6 input 2.5 V
SW[3] C6 input 2.5 V



Temperature
Name Location Direction Standard
TEMP_SMCLK AR14 output 2.5 V
TEMP_SMDAT AP14 inout 2.5 V
TEMP_INT_n AH13 input 2.5 V
TEMP_OVERT_n AK14 input 2.5 V



Fan
Name Location Direction Standard
FAN_CTRL B17 output 1.5V



PCIe0 4-Lane Downstream
Name Location Direction Standard
PCIE0_REFCLK_p AN38 input HCSL
PCIE0_PERST_n F8 input 2.5 V
PCIE0_WAKE_n AE10 output 2.5 V
PCIE0_TX_p[0] AT36 output 1.4-V PCML
PCIE0_RX_p[0] AU38 input 1.4-V PCML
PCIE0_TX_p[1] AP36 output 1.4-V PCML
PCIE0_RX_p[1] AR38 input 1.4-V PCML
PCIE0_TX_p[2] AH36 output 1.4-V PCML
PCIE0_RX_p[2] AJ38 input 1.4-V PCML
PCIE0_TX_p[3] AF36 output 1.4-V PCML
PCIE0_RX_p[3] AG38 input 1.4-V PCML



Flash and SRAM Address/Data/OE/WM Share Bus
Name Location Direction Standard
FSM_D[0] B32 inout 3.0-V PCI-X
FSM_D[1] C32 inout 3.0-V PCI-X
FSM_D[2] C31 inout 3.0-V PCI-X
FSM_D[3] F32 inout 3.0-V PCI-X
FSM_D[4] J30 inout 3.0-V PCI-X
FSM_D[5] K29 inout 3.0-V PCI-X
FSM_D[6] K30 inout 3.0-V PCI-X
FSM_D[7] L29 inout 3.0-V PCI-X
FSM_D[8] M29 inout 3.0-V PCI-X
FSM_D[9] N29 inout 3.0-V PCI-X
FSM_D[10] P29 inout 3.0-V PCI-X
FSM_D[11] T27 inout 3.0-V PCI-X
FSM_D[12] AM17 inout 3.0-V PCI-X
FSM_D[13] AL17 inout 3.0-V PCI-X
FSM_D[14] AK16 inout 3.0-V PCI-X
FSM_D[15] AJ16 inout 3.0-V PCI-X
FSM_D[16] AK17 inout 3.0-V PCI-X
FSM_D[17] T28 inout 3.0-V PCI-X
FSM_D[18] R27 inout 3.0-V PCI-X
FSM_D[19] R28 inout 3.0-V PCI-X
FSM_D[20] R29 inout 3.0-V PCI-X
FSM_D[21] N30 inout 3.0-V PCI-X
FSM_D[22] N28 inout 3.0-V PCI-X
FSM_D[23] M28 inout 3.0-V PCI-X
FSM_D[24] H31 inout 3.0-V PCI-X
FSM_D[25] G31 inout 3.0-V PCI-X
FSM_D[26] D31 inout 3.0-V PCI-X
FSM_D[27] E31 inout 3.0-V PCI-X
FSM_D[28] F31 inout 3.0-V PCI-X
FSM_D[29] E32 inout 3.0-V PCI-X
FSM_D[30] C33 inout 3.0-V PCI-X
FSM_D[31] D33 inout 3.0-V PCI-X
FSM_A[1] L31 output 3.0-V PCI-X
FSM_A[2] F34 output 3.0-V PCI-X
FSM_A[3] D35 output 3.0-V PCI-X
FSM_A[4] D34 output 3.0-V PCI-X
FSM_A[5] E34 output 3.0-V PCI-X
FSM_A[6] C35 output 3.0-V PCI-X
FSM_A[7] C34 output 3.0-V PCI-X
FSM_A[8] F33 output 3.0-V PCI-X
FSM_A[9] G35 output 3.0-V PCI-X
FSM_A[10] H35 output 3.0-V PCI-X
FSM_A[11] J32 output 3.0-V PCI-X
FSM_A[12] J33 output 3.0-V PCI-X
FSM_A[13] K32 output 3.0-V PCI-X
FSM_A[14] K31 output 3.0-V PCI-X
FSM_A[15] AH17 output 3.0-V PCI-X
FSM_A[16] AH16 output 3.0-V PCI-X
FSM_A[17] AE17 output 3.0-V PCI-X
FSM_A[18] AG16 output 3.0-V PCI-X
FSM_A[19] H32 output 3.0-V PCI-X
FSM_A[20] H34 output 3.0-V PCI-X
FSM_A[21] G33 output 3.0-V PCI-X
FSM_A[22] F35 output 3.0-V PCI-X
FSM_A[23] N31 output 3.0-V PCI-X
FSM_A[24] M31 output 3.0-V PCI-X
FSM_A[25] M30 output 3.0-V PCI-X
FSM_OE_n AT16 output 3.0-V PCI-X
FSM_WE_n AL16 output 3.0-V PCI-X



Flash Control
Name Location Direction Standard
FLASH_RDY_BSY_n A23 input 1.5V
FLASH_CLK AU15 output 3.0-V PCI-X
FLASH_RESET_n AV16 output 3.0-V PCI-X
FLASH_ADV_n AT15 output 3.0-V PCI-X
FLASH_CE_n AP16 output 3.0-V PCI-X
FLASH_WP_n A20 output 1.5V



SSRAM Control
Name Location Direction Standard
SSRAM_CLK AG17 output 3.0-V PCI-X
SSRAM_ADSC_n AP17 output 3.0-V PCI-X
SSRAM_ADSP_n AR17 output 3.0-V PCI-X
SSRAM_ADV_n AW16 output 3.0-V PCI-X
SSRAM_CE1_n AF17 output 3.0-V PCI-X
SSRAM_BE_n[0] AN16 output 3.0-V PCI-X
SSRAM_BE_n[1] AN17 output 3.0-V PCI-X
SSRAM_BE_n[2] AR16 output 3.0-V PCI-X
SSRAM_BE_n[3] AU16 output 3.0-V PCI-X



MAX2
Name Location Direction Standard
MAX2_I2C_SCL C20 output 1.5V
MAX2_I2C_SDA A17 inout 1.5V



Programming PLL
Name Location Direction Standard
HSMA_REFCLK_p AA2 input 1.4-V PCML
HSME_REFCLK_p AA38 input 1.4-V PCML
PGM_GXB_CLK_p1 J2 input 1.4-V PCML



Name Location Direction Standard DDR3 SODIMM Pin Index
mem_dq[4] G17 inout SSTL-15 Class I 4
mem_dq[0] G15 inout SSTL-15 Class I 5
mem_dq[5] A16 inout SSTL-15 Class I 6
mem_dq[1] F15 inout SSTL-15 Class I 7
mem_dqs_n[0] C15 inout Differential 1.5-V SSTL Class I 10
mem_dm[0] G16 output SSTL-15 Class I 11
mem_dqs[0] D15 inout Differential 1.5-V SSTL Class I 12
mem_dq[2] C16 inout SSTL-15 Class I 15
mem_dq[6] D16 inout SSTL-15 Class I 16
mem_dq[3] B16 inout SSTL-15 Class I 17
mem_dq[7] E16 inout SSTL-15 Class I 18
mem_dq[8] N17 inout SSTL-15 Class I 21
mem_dq[12] P16 inout SSTL-15 Class I 22
mem_dq[9] M17 inout SSTL-15 Class I 23
mem_dq[13] P17 inout SSTL-15 Class I 24
mem_dqs_n[1] J16 inout Differential 1.5-V SSTL Class I 27
mem_dm[1] N16 output SSTL-15 Class I 28
mem_dqs[1] K16 inout Differential 1.5-V SSTL Class I 29
mem_reset_n J18 output 1.5V 30
mem_dq[10] K17 inout SSTL-15 Class I 33
mem_dq[14] J17 inout SSTL-15 Class I 34
mem_dq[11] L16 inout SSTL-15 Class I 35
mem_dq[15] H17 inout SSTL-15 Class I 36
mem_dq[16] N22 inout SSTL-15 Class I 39
mem_dq[20] R22 inout SSTL-15 Class I 40
mem_dq[17] M23 inout SSTL-15 Class I 41
mem_dq[21] P22 inout SSTL-15 Class I 42
mem_dqs_n[2] K23 inout Differential 1.5-V SSTL Class I 45
mem_dm[2] P23 output SSTL-15 Class I 46
mem_dqs[2] L23 inout Differential 1.5-V SSTL Class I 47
mem_dq[22] K24 inout SSTL-15 Class I 50
mem_dq[18] J25 inout SSTL-15 Class I 51
mem_dq[23] J24 inout SSTL-15 Class I 52
mem_dq[19] M24 inout SSTL-15 Class I 53
mem_dq[28] C27 inout SSTL-15 Class I 56
mem_dq[24] A27 inout SSTL-15 Class I 57
mem_dq[29] D27 inout SSTL-15 Class I 58
mem_dq[25] A28 inout SSTL-15 Class I 59
mem_dqs_n[3] B28 inout Differential 1.5-V SSTL Class I 62
mem_dm[3] B29 output SSTL-15 Class I 63
mem_dqs[3] C28 inout Differential 1.5-V SSTL Class I 64
mem_dq[26] C29 inout SSTL-15 Class I 67
mem_dq[30] A31 inout SSTL-15 Class I 68
mem_dq[27] C30 inout SSTL-15 Class I 69
mem_dq[31] B31 inout SSTL-15 Class I 70
mem_cke[0] P25 output SSTL-15 Class I 73
mem_cke[1] M16 output SSTL-15 Class I 74
mem_a[15] R20 output SSTL-15 Class I 78
mem_ba[2] R24 output SSTL-15 Class I 79
mem_a[14] F16 output SSTL-15 Class I 80
mem_a[12] M25 output SSTL-15 Class I 83
mem_a[11] N21 output SSTL-15 Class I 84
mem_a[9] N25 output SSTL-15 Class I 85
mem_a[7] D17 output SSTL-15 Class I 86
mem_a[8] A25 output SSTL-15 Class I 89
mem_a[6] M21 output SSTL-15 Class I 90
mem_a[5] A24 output SSTL-15 Class I 91
mem_a[4] P24 output SSTL-15 Class I 92
mem_a[3] D21 output SSTL-15 Class I 95
mem_a[2] M22 output SSTL-15 Class I 96
mem_a[1] C22 output SSTL-15 Class I 97
mem_a[0] N23 output SSTL-15 Class I 98
mem_ck[0] K27 output Differential 1.5-V SSTL Class I 101
mem_ck[1] L25 output Differential 1.5-V SSTL Class I 102
mem_ck_n[0] J27 output Differential 1.5-V SSTL Class I 103
mem_ck_n[1] K28 output Differential 1.5-V SSTL Class I 104
mem_a[10] C24 output SSTL-15 Class I 107
mem_ba[1] A29 output SSTL-15 Class I 108
mem_ba[0] B26 output SSTL-15 Class I 109
mem_ras_n D24 output SSTL-15 Class I 110
mem_we_n M27 output SSTL-15 Class I 113
mem_cs_n[0] D23 output SSTL-15 Class I 114
mem_cas_n L26 output SSTL-15 Class I 115
mem_odt[0] F26 output SSTL-15 Class I 116
mem_a[13] K26 output SSTL-15 Class I 119
mem_odt[1] G26 output SSTL-15 Class I 120
mem_cs_n[1] G28 output SSTL-15 Class I 121
mem_dq[32] G27 inout SSTL-15 Class I 129
mem_dq[36] E28 inout SSTL-15 Class I 130
mem_dq[33] G29 inout SSTL-15 Class I 131
mem_dq[37] D28 inout SSTL-15 Class I 132
mem_dqs_n[4] D29 inout Differential 1.5-V SSTL Class I 135
mem_dm[4] H28 output SSTL-15 Class I 136
mem_dqs[4] E29 inout Differential 1.5-V SSTL Class I 137
mem_dq[38] H26 inout SSTL-15 Class I 140
mem_dq[34] F28 inout SSTL-15 Class I 141
mem_dq[39] J26 inout SSTL-15 Class I 142
mem_dq[35] F27 inout SSTL-15 Class I 143
mem_dq[44] C17 inout SSTL-15 Class I 146
mem_dq[40] F19 inout SSTL-15 Class I 147
mem_dq[45] F17 inout SSTL-15 Class I 148
mem_dq[41] G19 inout SSTL-15 Class I 149
mem_dqs_n[5] F18 inout Differential 1.5-V SSTL Class I 152
mem_dm[5] E17 output SSTL-15 Class I 153
mem_dqs[5] G18 inout Differential 1.5-V SSTL Class I 154
mem_dq[42] F20 inout SSTL-15 Class I 157
mem_dq[46] C18 inout SSTL-15 Class I 158
mem_dq[43] G20 inout SSTL-15 Class I 159
mem_dq[47] D18 inout SSTL-15 Class I 160
mem_dq[48] D25 inout SSTL-15 Class I 163
mem_dq[52] B25 inout SSTL-15 Class I 164
mem_dq[49] C25 inout SSTL-15 Class I 165
mem_dq[53] A26 inout SSTL-15 Class I 166
mem_dqs_n[6] E25 inout Differential 1.5-V SSTL Class I 169
mem_dm[6] C26 output SSTL-15 Class I 170
mem_dqs[6] F25 inout Differential 1.5-V SSTL Class I 171
mem_dq[54] D26 inout SSTL-15 Class I 174
mem_dq[50] G24 inout SSTL-15 Class I 175
mem_dq[55] F24 inout SSTL-15 Class I 176
mem_dq[51] G25 inout SSTL-15 Class I 177
mem_dq[60] K22 inout SSTL-15 Class I 180
mem_dq[56] F23 inout SSTL-15 Class I 181
mem_dq[61] D22 inout SSTL-15 Class I 182
mem_dq[57] G23 inout SSTL-15 Class I 183
mem_dqs_n[7] H23 inout Differential 1.5-V SSTL Class I 186
mem_dm[7] E23 output SSTL-15 Class I 187
mem_dqs[7] J23 inout Differential 1.5-V SSTL Class I 188
mem_dq[58] J22 inout SSTL-15 Class I 191
mem_dq[62] G22 inout SSTL-15 Class I 192
mem_dq[59] H22 inout SSTL-15 Class I 193
mem_dq[63] E22 inout SSTL-15 Class I 194
mem_EVENT_n R18 input 1.5V 198
mem_SDA P18 inout 1.5V 200
mem_SCL H19 output 1.5V 202



OCT RUP/RDN for Altera DDR3 UniPHY Controller
Name Location Direction Standard
mem_oct_rdn N26 input 1.5V
mem_oct_rup P26 input 1.5V