q_sys

2017.10.20.15:56:43 Datasheet
Overview
  clkin_100  q_sys

All Components
   ddr3_status altera_avalon_pio 17.0
   mem_if_ddr3_emif_0 altera_mem_if_ddr3_emif 17.0
   mm_clock_crossing_bridge_0 altera_avalon_mm_clock_crossing_bridge 17.0
   modular_sgdma_dispatcher_0 modular_sgdma_dispatcher 17.0
   onchip_memory2_0 altera_avalon_onchip_memory2 17.0
   pcie_hard_ip_0 altera_pcie_hard_ip 17.0
   pio_key altera_avalon_pio 17.0
   pio_led altera_avalon_pio 17.0
Memory Map
dma_read_master_0 dma_write_master_0 pcie_hard_ip_0
 Data_Read_Master  Data_Write_Master  bar1_0  bar3_2  bar5_4
  ddr3_status
s1  0x00080000
  mem_if_ddr3_emif_0
avl  0x40000000 0x40000000
  modular_sgdma_dispatcher_0
CSR  0x06000000
Descriptor_Slave  0x06000020
  onchip_memory2_0
s1  0x07000000 0x07000000 0x07000000
  pcie_hard_ip_0
txs  0x00000000 0x00000000
cra  0x00000000
  pio_key
s1  0x04000020
  pio_led
s1  0x04000010

clkin_100

clock_source v17.0


Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr3_status

altera_avalon_pio v17.0
pcie_hard_ip_0 bar5_4   ddr3_status
  s1
pcie_core_clk  
  clk
clkin_100 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 3
clockRate 250000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 3
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 250000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

dma_read_master_0

dma_read_master v17.0
modular_sgdma_dispatcher_0 Read_Command_Source   dma_read_master_0
  Command_Sink
pcie_hard_ip_0 pcie_core_clk  
  Clock
clkin_100 clk_reset  
  Clock_reset
Data_Read_Master   mm_clock_crossing_bridge_0
  s0
Data_Read_Master   onchip_memory2_0
  s1
Data_Read_Master   pcie_hard_ip_0
  txs
Data_Source   dma_write_master_0
  Data_Sink
Response_Source   modular_sgdma_dispatcher_0
  Read_Response_Sink


Parameters

DATA_WIDTH 256
LENGTH_WIDTH 19
FIFO_DEPTH 256
USE_FIX_ADDRESS_WIDTH 0
FIX_ADDRESS_WIDTH 32
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
CHANNEL_ENABLE 0
CHANNEL_WIDTH 8
BYTE_ENABLE_WIDTH 32
BYTE_ENABLE_WIDTH_LOG2 5
AUTO_ADDRESS_WIDTH 31
ADDRESS_WIDTH 31
FIFO_DEPTH_LOG2 8
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 32
NUMBER_OF_SYMBOLS_LOG2 5
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

dma_write_master_0

dma_write_master v17.0
dma_read_master_0 Data_Source   dma_write_master_0
  Data_Sink
modular_sgdma_dispatcher_0 Write_Command_Source  
  Command_Sink
pcie_hard_ip_0 pcie_core_clk  
  Clock
clkin_100 clk_reset  
  Clock_reset
Data_Write_Master   mm_clock_crossing_bridge_0
  s0
Data_Write_Master   onchip_memory2_0
  s1
Data_Write_Master   pcie_hard_ip_0
  txs
Response_Source   modular_sgdma_dispatcher_0
  Write_Response_Sink


Parameters

DATA_WIDTH 256
LENGTH_WIDTH 19
FIFO_DEPTH 256
USE_FIX_ADDRESS_WIDTH 0
FIX_ADDRESS_WIDTH 32
STRIDE_ENABLE 0
GUI_STRIDE_WIDTH 1
BURST_ENABLE 1
GUI_MAX_BURST_COUNT 32
GUI_PROGRAMMABLE_BURST_ENABLE 0
GUI_BURST_WRAPPING_SUPPORT 0
TRANSFER_TYPE Full Word Accesses Only
PACKET_ENABLE 0
ERROR_ENABLE 0
ERROR_WIDTH 8
BYTE_ENABLE_WIDTH 32
BYTE_ENABLE_WIDTH_LOG2 5
AUTO_ADDRESS_WIDTH 31
ADDRESS_WIDTH 31
FIFO_DEPTH_LOG2 8
SYMBOL_WIDTH 8
NUMBER_OF_SYMBOLS 32
NUMBER_OF_SYMBOLS_LOG2 5
MAX_BURST_COUNT_WIDTH 6
UNALIGNED_ACCESSES_ENABLE 0
ONLY_FULL_ACCESS_ENABLE 1
BURST_WRAPPING_SUPPORT 0
PROGRAMMABLE_BURST_ENABLE 0
MAX_BURST_COUNT 32
FIFO_SPEED_OPTIMIZATION 1
STRIDE_WIDTH 1
ACTUAL_BYTES_TRANSFERRED_WIDTH 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mem_if_ddr3_emif_0

altera_mem_if_ddr3_emif v17.0
mm_clock_crossing_bridge_0 m0   mem_if_ddr3_emif_0
  avl
clkin_100 clk_reset  
  global_reset
clk_reset  
  soft_reset
afi_clk   mm_clock_crossing_bridge_0
  m0_clk
afi_reset  
  m0_reset


Parameters

AC_ROM_MR0 0100000110001
AC_ROM_MR0_MIRR 0100001001001
AC_ROM_MR0_CALIB
AC_ROM_MR0_DLL_RESET 0100100110000
AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
AC_ROM_MR1 0000001001110
AC_ROM_MR1_MIRR 0000000110110
AC_ROM_MR1_CALIB
AC_ROM_MR1_OCD_ENABLE
AC_ROM_MR2 0001001001000
AC_ROM_MR2_MIRR 0001000110000
AC_ROM_MR3 0000000000000
AC_ROM_MR3_MIRR 0000000000000
USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY false
MR0_BL 1
MR0_BT 0
MR0_CAS_LATENCY 3
MR0_DLL 1
MR0_WR 4
MR0_PD 0
MR1_DLL 0
MR1_ODS 1
MR1_RTT 3
MR1_AL 1
MR1_WL 0
MR1_TDQS 0
MR1_QOFF 0
MR1_DQS 0
MR1_RDQS 0
MR2_CWL 1
MR2_ASR 1
MR2_SRT 0
MR2_SRF 0
MR2_RTT_WR 1
MR3_MPR_RF 0
MR3_MPR 0
MR3_MPR_AA 0
MEM_IF_READ_DQS_WIDTH 8
MEM_IF_WRITE_DQS_WIDTH 8
SCC_DATA_WIDTH 1
MEM_IF_ADDR_WIDTH 14
MEM_IF_ADDR_WIDTH_MIN 13
MEM_IF_ROW_ADDR_WIDTH 14
MEM_IF_COL_ADDR_WIDTH 10
MEM_IF_DM_WIDTH 8
MEM_IF_CS_PER_RANK 1
MEM_IF_NUMBER_OF_RANKS 1
MEM_IF_CS_PER_DIMM 1
MEM_IF_CONTROL_WIDTH 1
MEM_BURST_LENGTH 8
MEM_LEVELING true
MEM_IF_DQS_WIDTH 8
MEM_IF_CS_WIDTH 1
MEM_IF_CHIP_BITS 1
MEM_IF_BANKADDR_WIDTH 3
MEM_IF_DQ_WIDTH 64
MEM_IF_CK_WIDTH 1
MEM_IF_CLK_EN_WIDTH 1
MEM_IF_CLK_PAIR_COUNT 1
DEVICE_WIDTH 1
MEM_CLK_MAX_NS 1.875
MEM_CLK_MAX_PS 1875.0
MEM_TRC 27
MEM_TRAS 20
MEM_TRCD 7
MEM_TRP 7
MEM_TREFI 4160
MEM_TRFC 59
CFG_TCCD 2
MEM_TWR 8
MEM_TFAW 20
MEM_TRRD 8
MEM_TRTP 8
MEM_DQS_TO_CLK_CAPTURE_DELAY 100
MEM_CLK_TO_DQS_CAPTURE_DELAY 100000
MEM_IF_ODT_WIDTH 1
MEM_WTCL_INT 6
FLY_BY true
RDIMM false
LRDIMM false
RDIMM_INT 0
LRDIMM_INT 0
MEM_IF_LRDIMM_RM 0
MEM_IF_RD_TO_WR_TURNAROUND_OCT 2
MEM_IF_WR_TO_RD_TURNAROUND_OCT 3
CTL_RD_TO_PCH_EXTRA_CLK 0
CTL_RD_TO_RD_EXTRA_CLK 0
CTL_WR_TO_WR_EXTRA_CLK 0
CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1
CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 1
MEM_TYPE DDR3
MEM_MIRROR_ADDRESSING_DEC 0
MEM_ATCL_INT 6
MEM_REGDIMM_ENABLED false
MEM_LRDIMM_ENABLED false
MEM_VENDOR Hynix
MEM_FORMAT UNBUFFERED
AC_PARITY false
RDIMM_CONFIG 0000000000000000
LRDIMM_EXTENDED_CONFIG 0x000000000000000000
DISCRETE_FLY_BY true
DEVICE_DEPTH 1
MEM_MIRROR_ADDRESSING 0
MEM_CLK_FREQ_MAX 533.333
MEM_ROW_ADDR_WIDTH 14
MEM_COL_ADDR_WIDTH 10
MEM_DQ_WIDTH 64
MEM_DQ_PER_DQS 8
MEM_BANKADDR_WIDTH 3
MEM_IF_DM_PINS_EN true
MEM_IF_DQSN_EN true
MEM_NUMBER_OF_DIMMS 1
MEM_NUMBER_OF_RANKS_PER_DIMM 1
MEM_NUMBER_OF_RANKS_PER_DEVICE 1
MEM_RANK_MULTIPLICATION_FACTOR 1
MEM_CK_WIDTH 1
MEM_CS_WIDTH 1
MEM_CLK_EN_WIDTH 1
ALTMEMPHY_COMPATIBLE_MODE false
NEXTGEN true
MEM_IF_BOARD_BASE_DELAY 10
MEM_IF_SIM_VALID_WINDOW 0
MEM_GUARANTEED_WRITE_INIT false
MEM_VERBOSE true
PINGPONGPHY_EN false
DUPLICATE_AC false
REFRESH_BURST_VALIDATION false
AP_MODE_EN 0
AP_MODE false
MEM_BL OTF
MEM_BT Sequential
MEM_ASR Automatic
MEM_SRT Normal
MEM_PD DLL off
MEM_DRV_STR RZQ/7
MEM_DLL_EN true
MEM_RTT_NOM RZQ/6
MEM_RTT_WR RZQ/4
MEM_WTCL 6
MEM_ATCL CL-1
MEM_TCL 7
MEM_AUTO_LEVELING_MODE true
MEM_USER_LEVELING_MODE Leveling
MEM_INIT_EN false
MEM_INIT_FILE
DAT_DATA_WIDTH 32
TIMING_TIS 125
TIMING_TIH 200
TIMING_TDS 25
TIMING_TDH 100
TIMING_TDQSQ 150
TIMING_TQH 0.38
TIMING_TDQSCK 400
TIMING_TDQSCKDS 450
TIMING_TDQSCKDM 900
TIMING_TDQSCKDL 1200
TIMING_TDQSS 0.25
TIMING_TQSH 0.38
TIMING_TDSH 0.2
TIMING_TDSS 0.2
MEM_TINIT_US 500
MEM_TINIT_CK 266665
MEM_TDQSCK 1
MEM_TMRD_CK 4
MEM_TRAS_NS 37.5
MEM_TRCD_NS 13.125
MEM_TRP_NS 13.125
MEM_TREFI_US 7.8
MEM_TRFC_NS 110.0
CFG_TCCD_NS 2.5
MEM_TWR_NS 15.0
MEM_TWTR 4
MEM_TFAW_NS 37.5
MEM_TRRD_NS 13.2
MEM_TRTP_NS 13.2
RATE Half
MEM_CLK_FREQ 533.33
USE_MEM_CLK_FREQ false
USE_DQS_TRACKING false
FORCE_DQS_TRACKING AUTO
USE_HPS_DQS_TRACKING false
TRK_PARALLEL_SCC_LOAD false
USE_SHADOW_REGS false
FORCE_SHADOW_REGS AUTO
DQ_DDR 1
ADDR_CMD_DDR 0
AFI_RATE_RATIO 2
DATA_RATE_RATIO 2
ADDR_RATE_RATIO 1
AFI_ADDR_WIDTH 28
AFI_BANKADDR_WIDTH 6
AFI_CONTROL_WIDTH 2
AFI_CS_WIDTH 2
AFI_CLK_EN_WIDTH 2
AFI_DM_WIDTH 32
AFI_DQ_WIDTH 256
AFI_ODT_WIDTH 2
AFI_WRITE_DQS_WIDTH 16
AFI_RLAT_WIDTH 6
AFI_WLAT_WIDTH 6
AFI_RRANK_WIDTH 16
AFI_WRANK_WIDTH 16
AFI_CLK_PAIR_COUNT 1
MRS_MIRROR_PING_PONG_ATSO false
SYS_INFO_DEVICE_FAMILY STRATIXIV
PARSE_FRIENDLY_DEVICE_FAMILY STRATIXIV
DEVICE_FAMILY Stratix IV
PRE_V_SERIES_FAMILY true
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false
PARSE_FRIENDLY_DEVICE_FAMILY_PARAM
DEVICE_FAMILY_PARAM
SPEED_GRADE 2
IS_ES_DEVICE false
DISABLE_CHILD_MESSAGING false
HARD_PHY false
HARD_EMIF false
HHP_HPS false
HHP_HPS_VERIFICATION false
HHP_HPS_SIMULATION false
HPS_PROTOCOL DEFAULT
CUT_NEW_FAMILY_TIMING true
EXPORT_CSR_PORT false
CSR_ADDR_WIDTH 8
CSR_DATA_WIDTH 32
CSR_BE_WIDTH 4
CTL_CS_WIDTH 1
AVL_ADDR_WIDTH 25
AVL_BE_WIDTH 32
AVL_DATA_WIDTH 256
AVL_SYMBOL_WIDTH 8
AVL_NUM_SYMBOLS 32
AVL_SIZE_WIDTH 4
HR_DDIO_OUT_HAS_THREE_REGS true
CTL_ECC_CSR_ENABLED false
DWIDTH_RATIO 4
CTL_ODT_ENABLED true
CTL_OUTPUT_REGD false
CTL_ECC_MULTIPLES_40_72 1
CTL_ECC_MULTIPLES_16_24_40_72 1
CTL_REGDIMM_ENABLED false
LOW_LATENCY false
CONTROLLER_TYPE nextgen_v110
CTL_TBP_NUM 4
CTL_USR_REFRESH 0
CTL_SELF_REFRESH 0
CFG_TYPE 2
CFG_INTERFACE_WIDTH 64
CFG_BURST_LENGTH 8
CFG_ADDR_ORDER 0
CFG_PDN_EXIT_CYCLES 10
CFG_POWER_SAVING_EXIT_CYCLES 5
CFG_MEM_CLK_ENTRY_CYCLES 20
CFG_SELF_RFSH_EXIT_CYCLES 512
CFG_PORT_WIDTH_WRITE_ODT_CHIP 1
CFG_PORT_WIDTH_READ_ODT_CHIP 1
CFG_WRITE_ODT_CHIP 1
CFG_READ_ODT_CHIP 0
LOCAL_CS_WIDTH 0
CFG_CLR_INTR 0
CFG_ENABLE_NO_DM 0
MEM_ADD_LAT 6
CTL_ENABLE_BURST_INTERRUPT_INT false
CTL_ENABLE_BURST_TERMINATE_INT false
CFG_ERRCMD_FIFO_REG 0
CFG_ECC_DECODER_REG 0
CTL_ENABLE_WDATA_PATH_LATENCY false
CFG_STARVE_LIMIT 10
MEM_AUTO_PD_CYCLES 0
AVL_PORT
AVL_DATA_WIDTH_PORT_0 0
AVL_ADDR_WIDTH_PORT_0 0
PRIORITY_PORT_0 0
WEIGHT_PORT_0 0
CPORT_TYPE_PORT_0 0
AVL_NUM_SYMBOLS_PORT_0 2
LSB_WFIFO_PORT_0 5
MSB_WFIFO_PORT_0 5
LSB_RFIFO_PORT_0 5
MSB_RFIFO_PORT_0 5
AVL_DATA_WIDTH_PORT_1 0
AVL_ADDR_WIDTH_PORT_1 0
PRIORITY_PORT_1 0
WEIGHT_PORT_1 0
CPORT_TYPE_PORT_1 0
AVL_NUM_SYMBOLS_PORT_1 2
LSB_WFIFO_PORT_1 5
MSB_WFIFO_PORT_1 5
LSB_RFIFO_PORT_1 5
MSB_RFIFO_PORT_1 5
AVL_DATA_WIDTH_PORT_2 0
AVL_ADDR_WIDTH_PORT_2 0
PRIORITY_PORT_2 0
WEIGHT_PORT_2 0
CPORT_TYPE_PORT_2 0
AVL_NUM_SYMBOLS_PORT_2 2
LSB_WFIFO_PORT_2 5
MSB_WFIFO_PORT_2 5
LSB_RFIFO_PORT_2 5
MSB_RFIFO_PORT_2 5
AVL_DATA_WIDTH_PORT_3 0
AVL_ADDR_WIDTH_PORT_3 0
PRIORITY_PORT_3 0
WEIGHT_PORT_3 0
CPORT_TYPE_PORT_3 0
AVL_NUM_SYMBOLS_PORT_3 2
LSB_WFIFO_PORT_3 5
MSB_WFIFO_PORT_3 5
LSB_RFIFO_PORT_3 5
MSB_RFIFO_PORT_3 5
AVL_DATA_WIDTH_PORT_4 0
AVL_ADDR_WIDTH_PORT_4 0
PRIORITY_PORT_4 0
WEIGHT_PORT_4 0
CPORT_TYPE_PORT_4 0
AVL_NUM_SYMBOLS_PORT_4 2
LSB_WFIFO_PORT_4 5
MSB_WFIFO_PORT_4 5
LSB_RFIFO_PORT_4 5
MSB_RFIFO_PORT_4 5
AVL_DATA_WIDTH_PORT_5 0
AVL_ADDR_WIDTH_PORT_5 0
PRIORITY_PORT_5 0
WEIGHT_PORT_5 0
CPORT_TYPE_PORT_5 0
AVL_NUM_SYMBOLS_PORT_5 2
LSB_WFIFO_PORT_5 5
MSB_WFIFO_PORT_5 5
LSB_RFIFO_PORT_5 5
MSB_RFIFO_PORT_5 5
ALLOCATED_RFIFO_PORT 0,None,None,None,None,None
ALLOCATED_WFIFO_PORT 0,None,None,None,None,None
ENUM_ATTR_COUNTER_ONE_RESET DISABLED
ENUM_ATTR_COUNTER_ZERO_RESET DISABLED
ENUM_ATTR_STATIC_CONFIG_VALID DISABLED
ENUM_AUTO_PCH_ENABLE_0 DISABLED
ENUM_AUTO_PCH_ENABLE_1 DISABLED
ENUM_AUTO_PCH_ENABLE_2 DISABLED
ENUM_AUTO_PCH_ENABLE_3 DISABLED
ENUM_AUTO_PCH_ENABLE_4 DISABLED
ENUM_AUTO_PCH_ENABLE_5 DISABLED
ENUM_CAL_REQ DISABLED
ENUM_CFG_BURST_LENGTH BL_8
ENUM_CFG_INTERFACE_WIDTH DWIDTH_32
ENUM_CFG_SELF_RFSH_EXIT_CYCLES
ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_32
ENUM_CFG_TYPE DDR3
ENUM_CLOCK_OFF_0 DISABLED
ENUM_CLOCK_OFF_1 DISABLED
ENUM_CLOCK_OFF_2 DISABLED
ENUM_CLOCK_OFF_3 DISABLED
ENUM_CLOCK_OFF_4 DISABLED
ENUM_CLOCK_OFF_5 DISABLED
ENUM_CLR_INTR NO_CLR_INTR
ENUM_CMD_PORT_IN_USE_0 FALSE
ENUM_CMD_PORT_IN_USE_1 FALSE
ENUM_CMD_PORT_IN_USE_2 FALSE
ENUM_CMD_PORT_IN_USE_3 FALSE
ENUM_CMD_PORT_IN_USE_4 FALSE
ENUM_CMD_PORT_IN_USE_5 FALSE
ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT0_RFIFO_MAP FIFO_0
ENUM_CPORT0_TYPE DISABLE
ENUM_CPORT0_WFIFO_MAP FIFO_0
ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT1_RFIFO_MAP FIFO_0
ENUM_CPORT1_TYPE DISABLE
ENUM_CPORT1_WFIFO_MAP FIFO_0
ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT2_RFIFO_MAP FIFO_0
ENUM_CPORT2_TYPE DISABLE
ENUM_CPORT2_WFIFO_MAP FIFO_0
ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT3_RFIFO_MAP FIFO_0
ENUM_CPORT3_TYPE DISABLE
ENUM_CPORT3_WFIFO_MAP FIFO_0
ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT4_RFIFO_MAP FIFO_0
ENUM_CPORT4_TYPE DISABLE
ENUM_CPORT4_WFIFO_MAP FIFO_0
ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL
ENUM_CPORT5_RFIFO_MAP FIFO_0
ENUM_CPORT5_TYPE DISABLE
ENUM_CPORT5_WFIFO_MAP FIFO_0
ENUM_CTL_ADDR_ORDER CHIP_BANK_ROW_COL
ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED
ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED
ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED
ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_DISABLED
ENUM_CTRL_WIDTH DATA_WIDTH_64_BIT
ENUM_DELAY_BONDING BONDING_LATENCY_0
ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED
ENUM_DISABLE_MERGING MERGING_ENABLED
ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0
ENUM_ENABLE_ATPG DISABLED
ENUM_ENABLE_BONDING_0 DISABLED
ENUM_ENABLE_BONDING_1 DISABLED
ENUM_ENABLE_BONDING_2 DISABLED
ENUM_ENABLE_BONDING_3 DISABLED
ENUM_ENABLE_BONDING_4 DISABLED
ENUM_ENABLE_BONDING_5 DISABLED
ENUM_ENABLE_BONDING_WRAPBACK DISABLED
ENUM_ENABLE_DQS_TRACKING DISABLED
ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED
ENUM_ENABLE_FAST_EXIT_PPD DISABLED
ENUM_ENABLE_INTR DISABLED
ENUM_ENABLE_NO_DM DISABLED
ENUM_ENABLE_PIPELINEGLOBAL DISABLED
ENUM_GANGED_ARF DISABLED
ENUM_GEN_DBE GEN_DBE_DISABLED
ENUM_GEN_SBE GEN_SBE_DISABLED
ENUM_INC_SYNC FIFO_SET_2
ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_2
ENUM_MASK_CORR_DROPPED_INTR DISABLED
ENUM_MASK_DBE_INTR DISABLED
ENUM_MASK_SBE_INTR DISABLED
ENUM_MEM_IF_AL AL_0
ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3
ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8
ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_12
ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1
ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1
ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8
ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_4
ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_32
ENUM_MEM_IF_MEMTYPE DDR3_SDRAM
ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_16
ENUM_MEM_IF_SPEEDBIN DDR3_1066_6_6_6
ENUM_MEM_IF_TCCD TCCD_4
ENUM_MEM_IF_TCL TCL_6
ENUM_MEM_IF_TCWL TCWL_5
ENUM_MEM_IF_TFAW TFAW_16
ENUM_MEM_IF_TMRD
ENUM_MEM_IF_TRAS TRAS_16
ENUM_MEM_IF_TRC TRC_22
ENUM_MEM_IF_TRCD TRCD_6
ENUM_MEM_IF_TRP TRP_6
ENUM_MEM_IF_TRRD TRRD_4
ENUM_MEM_IF_TRTP TRTP_4
ENUM_MEM_IF_TWR TWR_6
ENUM_MEM_IF_TWTR TWTR_4
ENUM_MMR_CFG_MEM_BL MP_BL_8
ENUM_OUTPUT_REGD DISABLED
ENUM_PDN_EXIT_CYCLES SLOW_EXIT
ENUM_PORT0_WIDTH PORT_64_BIT
ENUM_PORT1_WIDTH PORT_64_BIT
ENUM_PORT2_WIDTH PORT_64_BIT
ENUM_PORT3_WIDTH PORT_64_BIT
ENUM_PORT4_WIDTH PORT_64_BIT
ENUM_PORT5_WIDTH PORT_64_BIT
ENUM_PRIORITY_0_0 WEIGHT_0
ENUM_PRIORITY_0_1 WEIGHT_0
ENUM_PRIORITY_0_2 WEIGHT_0
ENUM_PRIORITY_0_3 WEIGHT_0
ENUM_PRIORITY_0_4 WEIGHT_0
ENUM_PRIORITY_0_5 WEIGHT_0
ENUM_PRIORITY_1_0 WEIGHT_0
ENUM_PRIORITY_1_1 WEIGHT_0
ENUM_PRIORITY_1_2 WEIGHT_0
ENUM_PRIORITY_1_3 WEIGHT_0
ENUM_PRIORITY_1_4 WEIGHT_0
ENUM_PRIORITY_1_5 WEIGHT_0
ENUM_PRIORITY_2_0 WEIGHT_0
ENUM_PRIORITY_2_1 WEIGHT_0
ENUM_PRIORITY_2_2 WEIGHT_0
ENUM_PRIORITY_2_3 WEIGHT_0
ENUM_PRIORITY_2_4 WEIGHT_0
ENUM_PRIORITY_2_5 WEIGHT_0
ENUM_PRIORITY_3_0 WEIGHT_0
ENUM_PRIORITY_3_1 WEIGHT_0
ENUM_PRIORITY_3_2 WEIGHT_0
ENUM_PRIORITY_3_3 WEIGHT_0
ENUM_PRIORITY_3_4 WEIGHT_0
ENUM_PRIORITY_3_5 WEIGHT_0
ENUM_PRIORITY_4_0 WEIGHT_0
ENUM_PRIORITY_4_1 WEIGHT_0
ENUM_PRIORITY_4_2 WEIGHT_0
ENUM_PRIORITY_4_3 WEIGHT_0
ENUM_PRIORITY_4_4 WEIGHT_0
ENUM_PRIORITY_4_5 WEIGHT_0
ENUM_PRIORITY_5_0 WEIGHT_0
ENUM_PRIORITY_5_1 WEIGHT_0
ENUM_PRIORITY_5_2 WEIGHT_0
ENUM_PRIORITY_5_3 WEIGHT_0
ENUM_PRIORITY_5_4 WEIGHT_0
ENUM_PRIORITY_5_5 WEIGHT_0
ENUM_PRIORITY_6_0 WEIGHT_0
ENUM_PRIORITY_6_1 WEIGHT_0
ENUM_PRIORITY_6_2 WEIGHT_0
ENUM_PRIORITY_6_3 WEIGHT_0
ENUM_PRIORITY_6_4 WEIGHT_0
ENUM_PRIORITY_6_5 WEIGHT_0
ENUM_PRIORITY_7_0 WEIGHT_0
ENUM_PRIORITY_7_1 WEIGHT_0
ENUM_PRIORITY_7_2 WEIGHT_0
ENUM_PRIORITY_7_3 WEIGHT_0
ENUM_PRIORITY_7_4 WEIGHT_0
ENUM_PRIORITY_7_5 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
ENUM_RCFG_USER_PRIORITY_0 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_1 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_2 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_3 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_4 PRIORITY_0
ENUM_RCFG_USER_PRIORITY_5 PRIORITY_0
ENUM_RD_DWIDTH_0 DWIDTH_0
ENUM_RD_DWIDTH_1 DWIDTH_0
ENUM_RD_DWIDTH_2 DWIDTH_0
ENUM_RD_DWIDTH_3 DWIDTH_0
ENUM_RD_DWIDTH_4 DWIDTH_0
ENUM_RD_DWIDTH_5 DWIDTH_0
ENUM_RD_FIFO_IN_USE_0 FALSE
ENUM_RD_FIFO_IN_USE_1 FALSE
ENUM_RD_FIFO_IN_USE_2 FALSE
ENUM_RD_FIFO_IN_USE_3 FALSE
ENUM_RD_PORT_INFO_0 USE_NO
ENUM_RD_PORT_INFO_1 USE_NO
ENUM_RD_PORT_INFO_2 USE_NO
ENUM_RD_PORT_INFO_3 USE_NO
ENUM_RD_PORT_INFO_4 USE_NO
ENUM_RD_PORT_INFO_5 USE_NO
ENUM_READ_ODT_CHIP ODT_DISABLED
ENUM_REORDER_DATA DATA_REORDERING
ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
ENUM_SINGLE_READY_0 CONCATENATE_RDY
ENUM_SINGLE_READY_1 CONCATENATE_RDY
ENUM_SINGLE_READY_2 CONCATENATE_RDY
ENUM_SINGLE_READY_3 CONCATENATE_RDY
ENUM_STATIC_WEIGHT_0 WEIGHT_0
ENUM_STATIC_WEIGHT_1 WEIGHT_0
ENUM_STATIC_WEIGHT_2 WEIGHT_0
ENUM_STATIC_WEIGHT_3 WEIGHT_0
ENUM_STATIC_WEIGHT_4 WEIGHT_0
ENUM_STATIC_WEIGHT_5 WEIGHT_0
ENUM_SYNC_MODE_0 ASYNCHRONOUS
ENUM_SYNC_MODE_1 ASYNCHRONOUS
ENUM_SYNC_MODE_2 ASYNCHRONOUS
ENUM_SYNC_MODE_3 ASYNCHRONOUS
ENUM_SYNC_MODE_4 ASYNCHRONOUS
ENUM_SYNC_MODE_5 ASYNCHRONOUS
ENUM_TEST_MODE NORMAL_MODE
ENUM_THLD_JAR1_0 THRESHOLD_32
ENUM_THLD_JAR1_1 THRESHOLD_32
ENUM_THLD_JAR1_2 THRESHOLD_32
ENUM_THLD_JAR1_3 THRESHOLD_32
ENUM_THLD_JAR1_4 THRESHOLD_32
ENUM_THLD_JAR1_5 THRESHOLD_32
ENUM_THLD_JAR2_0 THRESHOLD_16
ENUM_THLD_JAR2_1 THRESHOLD_16
ENUM_THLD_JAR2_2 THRESHOLD_16
ENUM_THLD_JAR2_3 THRESHOLD_16
ENUM_THLD_JAR2_4 THRESHOLD_16
ENUM_THLD_JAR2_5 THRESHOLD_16
ENUM_USE_ALMOST_EMPTY_0 EMPTY
ENUM_USE_ALMOST_EMPTY_1 EMPTY
ENUM_USE_ALMOST_EMPTY_2 EMPTY
ENUM_USE_ALMOST_EMPTY_3 EMPTY
ENUM_USER_ECC_EN DISABLE
ENUM_USER_PRIORITY_0 PRIORITY_0
ENUM_USER_PRIORITY_1 PRIORITY_0
ENUM_USER_PRIORITY_2 PRIORITY_0
ENUM_USER_PRIORITY_3 PRIORITY_0
ENUM_USER_PRIORITY_4 PRIORITY_0
ENUM_USER_PRIORITY_5 PRIORITY_0
ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL
ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL
ENUM_WR_DWIDTH_0 DWIDTH_0
ENUM_WR_DWIDTH_1 DWIDTH_0
ENUM_WR_DWIDTH_2 DWIDTH_0
ENUM_WR_DWIDTH_3 DWIDTH_0
ENUM_WR_DWIDTH_4 DWIDTH_0
ENUM_WR_DWIDTH_5 DWIDTH_0
ENUM_WR_FIFO_IN_USE_0 FALSE
ENUM_WR_FIFO_IN_USE_1 FALSE
ENUM_WR_FIFO_IN_USE_2 FALSE
ENUM_WR_FIFO_IN_USE_3 FALSE
ENUM_WR_PORT_INFO_0 USE_NO
ENUM_WR_PORT_INFO_1 USE_NO
ENUM_WR_PORT_INFO_2 USE_NO
ENUM_WR_PORT_INFO_3 USE_NO
ENUM_WR_PORT_INFO_4 USE_NO
ENUM_WR_PORT_INFO_5 USE_NO
ENUM_WRITE_ODT_CHIP ODT_DISABLED
INTG_MEM_AUTO_PD_CYCLES 0
INTG_CYC_TO_RLD_JARS_0 1
INTG_CYC_TO_RLD_JARS_1 1
INTG_CYC_TO_RLD_JARS_2 1
INTG_CYC_TO_RLD_JARS_3 1
INTG_CYC_TO_RLD_JARS_4 1
INTG_CYC_TO_RLD_JARS_5 1
INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0
INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0
INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0
INTG_EXTRA_CTL_CLK_ARF_PERIOD 0
INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0
INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0
INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0
INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0
INTG_EXTRA_CTL_CLK_PDN_PERIOD 0
INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_RD_TO_PCH 0
INTG_EXTRA_CTL_CLK_RD_TO_RD 0
INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_RD_TO_WR 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0
INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0
INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0
INTG_EXTRA_CTL_CLK_WR_TO_PCH 0
INTG_EXTRA_CTL_CLK_WR_TO_RD 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 0
INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 0
INTG_EXTRA_CTL_CLK_WR_TO_WR 0
INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0
INTG_MEM_IF_TREFI 3120
INTG_MEM_IF_TRFC 34
INTG_RCFG_SUM_WT_PRIORITY_0 0
INTG_RCFG_SUM_WT_PRIORITY_1 0
INTG_RCFG_SUM_WT_PRIORITY_2 0
INTG_RCFG_SUM_WT_PRIORITY_3 0
INTG_RCFG_SUM_WT_PRIORITY_4 0
INTG_RCFG_SUM_WT_PRIORITY_5 0
INTG_RCFG_SUM_WT_PRIORITY_6 0
INTG_RCFG_SUM_WT_PRIORITY_7 0
INTG_SUM_WT_PRIORITY_0 0
INTG_SUM_WT_PRIORITY_1 0
INTG_SUM_WT_PRIORITY_2 0
INTG_SUM_WT_PRIORITY_3 0
INTG_SUM_WT_PRIORITY_4 0
INTG_SUM_WT_PRIORITY_5 0
INTG_SUM_WT_PRIORITY_6 0
INTG_SUM_WT_PRIORITY_7 0
VECT_ATTR_COUNTER_ONE_MASK 0
VECT_ATTR_COUNTER_ONE_MATCH 0
VECT_ATTR_COUNTER_ZERO_MASK 0
VECT_ATTR_COUNTER_ZERO_MATCH 0
VECT_ATTR_DEBUG_SELECT_BYTE 0
INTG_POWER_SAVING_EXIT_CYCLES 5
INTG_MEM_CLK_ENTRY_CYCLES 10
ENUM_ENABLE_BURST_INTERRUPT DISABLED
ENUM_ENABLE_BURST_TERMINATE DISABLED
AV_PORT_0_CONNECT_TO_CV_PORT 0
CV_PORT_0_CONNECT_TO_AV_PORT 0
CV_AVL_DATA_WIDTH_PORT_0 0
CV_AVL_ADDR_WIDTH_PORT_0 0
CV_CPORT_TYPE_PORT_0 0
CV_AVL_NUM_SYMBOLS_PORT_0 2
CV_LSB_WFIFO_PORT_0 5
CV_MSB_WFIFO_PORT_0 5
CV_LSB_RFIFO_PORT_0 5
CV_MSB_RFIFO_PORT_0 5
CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED
CV_ENUM_CMD_PORT_IN_USE_0 FALSE
CV_ENUM_CPORT0_RFIFO_MAP FIFO_0
CV_ENUM_CPORT0_TYPE DISABLE
CV_ENUM_CPORT0_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_0 DISABLED
CV_ENUM_PORT0_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_0 WEIGHT_0
CV_ENUM_PRIORITY_1_0 WEIGHT_0
CV_ENUM_PRIORITY_2_0 WEIGHT_0
CV_ENUM_PRIORITY_3_0 WEIGHT_0
CV_ENUM_PRIORITY_4_0 WEIGHT_0
CV_ENUM_PRIORITY_5_0 WEIGHT_0
CV_ENUM_PRIORITY_6_0 WEIGHT_0
CV_ENUM_PRIORITY_7_0 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_0
CV_ENUM_RD_DWIDTH_0 DWIDTH_0
CV_ENUM_RD_PORT_INFO_0 USE_NO
CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0
CV_ENUM_USER_PRIORITY_0 PRIORITY_0
CV_ENUM_WR_DWIDTH_0 DWIDTH_0
CV_ENUM_WR_PORT_INFO_0 USE_NO
TG_TEMP_PORT_0 0
AV_PORT_1_CONNECT_TO_CV_PORT 1
CV_PORT_1_CONNECT_TO_AV_PORT 1
CV_AVL_DATA_WIDTH_PORT_1 0
CV_AVL_ADDR_WIDTH_PORT_1 0
CV_CPORT_TYPE_PORT_1 0
CV_AVL_NUM_SYMBOLS_PORT_1 2
CV_LSB_WFIFO_PORT_1 5
CV_MSB_WFIFO_PORT_1 5
CV_LSB_RFIFO_PORT_1 5
CV_MSB_RFIFO_PORT_1 5
CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED
CV_ENUM_CMD_PORT_IN_USE_1 FALSE
CV_ENUM_CPORT1_RFIFO_MAP FIFO_0
CV_ENUM_CPORT1_TYPE DISABLE
CV_ENUM_CPORT1_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_1 DISABLED
CV_ENUM_PORT1_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_1 WEIGHT_0
CV_ENUM_PRIORITY_1_1 WEIGHT_0
CV_ENUM_PRIORITY_2_1 WEIGHT_0
CV_ENUM_PRIORITY_3_1 WEIGHT_0
CV_ENUM_PRIORITY_4_1 WEIGHT_0
CV_ENUM_PRIORITY_5_1 WEIGHT_0
CV_ENUM_PRIORITY_6_1 WEIGHT_0
CV_ENUM_PRIORITY_7_1 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_0
CV_ENUM_RD_DWIDTH_1 DWIDTH_0
CV_ENUM_RD_PORT_INFO_1 USE_NO
CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0
CV_ENUM_USER_PRIORITY_1 PRIORITY_0
CV_ENUM_WR_DWIDTH_1 DWIDTH_0
CV_ENUM_WR_PORT_INFO_1 USE_NO
TG_TEMP_PORT_1 0
AV_PORT_2_CONNECT_TO_CV_PORT 2
CV_PORT_2_CONNECT_TO_AV_PORT 2
CV_AVL_DATA_WIDTH_PORT_2 0
CV_AVL_ADDR_WIDTH_PORT_2 0
CV_CPORT_TYPE_PORT_2 0
CV_AVL_NUM_SYMBOLS_PORT_2 2
CV_LSB_WFIFO_PORT_2 5
CV_MSB_WFIFO_PORT_2 5
CV_LSB_RFIFO_PORT_2 5
CV_MSB_RFIFO_PORT_2 5
CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED
CV_ENUM_CMD_PORT_IN_USE_2 FALSE
CV_ENUM_CPORT2_RFIFO_MAP FIFO_0
CV_ENUM_CPORT2_TYPE DISABLE
CV_ENUM_CPORT2_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_2 DISABLED
CV_ENUM_PORT2_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_2 WEIGHT_0
CV_ENUM_PRIORITY_1_2 WEIGHT_0
CV_ENUM_PRIORITY_2_2 WEIGHT_0
CV_ENUM_PRIORITY_3_2 WEIGHT_0
CV_ENUM_PRIORITY_4_2 WEIGHT_0
CV_ENUM_PRIORITY_5_2 WEIGHT_0
CV_ENUM_PRIORITY_6_2 WEIGHT_0
CV_ENUM_PRIORITY_7_2 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_0
CV_ENUM_RD_DWIDTH_2 DWIDTH_0
CV_ENUM_RD_PORT_INFO_2 USE_NO
CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0
CV_ENUM_USER_PRIORITY_2 PRIORITY_0
CV_ENUM_WR_DWIDTH_2 DWIDTH_0
CV_ENUM_WR_PORT_INFO_2 USE_NO
TG_TEMP_PORT_2 0
AV_PORT_3_CONNECT_TO_CV_PORT 3
CV_PORT_3_CONNECT_TO_AV_PORT 3
CV_AVL_DATA_WIDTH_PORT_3 0
CV_AVL_ADDR_WIDTH_PORT_3 0
CV_CPORT_TYPE_PORT_3 0
CV_AVL_NUM_SYMBOLS_PORT_3 2
CV_LSB_WFIFO_PORT_3 5
CV_MSB_WFIFO_PORT_3 5
CV_LSB_RFIFO_PORT_3 5
CV_MSB_RFIFO_PORT_3 5
CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED
CV_ENUM_CMD_PORT_IN_USE_3 FALSE
CV_ENUM_CPORT3_RFIFO_MAP FIFO_0
CV_ENUM_CPORT3_TYPE DISABLE
CV_ENUM_CPORT3_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_3 DISABLED
CV_ENUM_PORT3_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_3 WEIGHT_0
CV_ENUM_PRIORITY_1_3 WEIGHT_0
CV_ENUM_PRIORITY_2_3 WEIGHT_0
CV_ENUM_PRIORITY_3_3 WEIGHT_0
CV_ENUM_PRIORITY_4_3 WEIGHT_0
CV_ENUM_PRIORITY_5_3 WEIGHT_0
CV_ENUM_PRIORITY_6_3 WEIGHT_0
CV_ENUM_PRIORITY_7_3 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_0
CV_ENUM_RD_DWIDTH_3 DWIDTH_0
CV_ENUM_RD_PORT_INFO_3 USE_NO
CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0
CV_ENUM_USER_PRIORITY_3 PRIORITY_0
CV_ENUM_WR_DWIDTH_3 DWIDTH_0
CV_ENUM_WR_PORT_INFO_3 USE_NO
TG_TEMP_PORT_3 0
AV_PORT_4_CONNECT_TO_CV_PORT 4
CV_PORT_4_CONNECT_TO_AV_PORT 4
CV_AVL_DATA_WIDTH_PORT_4 0
CV_AVL_ADDR_WIDTH_PORT_4 0
CV_CPORT_TYPE_PORT_4 0
CV_AVL_NUM_SYMBOLS_PORT_4 2
CV_LSB_WFIFO_PORT_4 5
CV_MSB_WFIFO_PORT_4 5
CV_LSB_RFIFO_PORT_4 5
CV_MSB_RFIFO_PORT_4 5
CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED
CV_ENUM_CMD_PORT_IN_USE_4 FALSE
CV_ENUM_CPORT4_RFIFO_MAP FIFO_0
CV_ENUM_CPORT4_TYPE DISABLE
CV_ENUM_CPORT4_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_4 DISABLED
CV_ENUM_PORT4_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_4 WEIGHT_0
CV_ENUM_PRIORITY_1_4 WEIGHT_0
CV_ENUM_PRIORITY_2_4 WEIGHT_0
CV_ENUM_PRIORITY_3_4 WEIGHT_0
CV_ENUM_PRIORITY_4_4 WEIGHT_0
CV_ENUM_PRIORITY_5_4 WEIGHT_0
CV_ENUM_PRIORITY_6_4 WEIGHT_0
CV_ENUM_PRIORITY_7_4 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_0
CV_ENUM_RD_DWIDTH_4 DWIDTH_0
CV_ENUM_RD_PORT_INFO_4 USE_NO
CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0
CV_ENUM_USER_PRIORITY_4 PRIORITY_0
CV_ENUM_WR_DWIDTH_4 DWIDTH_0
CV_ENUM_WR_PORT_INFO_4 USE_NO
TG_TEMP_PORT_4 0
AV_PORT_5_CONNECT_TO_CV_PORT 5
CV_PORT_5_CONNECT_TO_AV_PORT 5
CV_AVL_DATA_WIDTH_PORT_5 0
CV_AVL_ADDR_WIDTH_PORT_5 0
CV_CPORT_TYPE_PORT_5 0
CV_AVL_NUM_SYMBOLS_PORT_5 2
CV_LSB_WFIFO_PORT_5 5
CV_MSB_WFIFO_PORT_5 5
CV_LSB_RFIFO_PORT_5 5
CV_MSB_RFIFO_PORT_5 5
CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED
CV_ENUM_CMD_PORT_IN_USE_5 FALSE
CV_ENUM_CPORT5_RFIFO_MAP FIFO_0
CV_ENUM_CPORT5_TYPE DISABLE
CV_ENUM_CPORT5_WFIFO_MAP FIFO_0
CV_ENUM_ENABLE_BONDING_5 DISABLED
CV_ENUM_PORT5_WIDTH PORT_64_BIT
CV_ENUM_PRIORITY_0_5 WEIGHT_0
CV_ENUM_PRIORITY_1_5 WEIGHT_0
CV_ENUM_PRIORITY_2_5 WEIGHT_0
CV_ENUM_PRIORITY_3_5 WEIGHT_0
CV_ENUM_PRIORITY_4_5 WEIGHT_0
CV_ENUM_PRIORITY_5_5 WEIGHT_0
CV_ENUM_PRIORITY_6_5 WEIGHT_0
CV_ENUM_PRIORITY_7_5 WEIGHT_0
CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_0
CV_ENUM_RD_DWIDTH_5 DWIDTH_0
CV_ENUM_RD_PORT_INFO_5 USE_NO
CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0
CV_ENUM_USER_PRIORITY_5 PRIORITY_0
CV_ENUM_WR_DWIDTH_5 DWIDTH_0
CV_ENUM_WR_PORT_INFO_5 USE_NO
TG_TEMP_PORT_5 0
CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0
CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0
CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0
CV_INTG_RCFG_SUM_WT_PRIORITY_0 0
CV_INTG_SUM_WT_PRIORITY_0 0
CV_INTG_RCFG_SUM_WT_PRIORITY_1 0
CV_INTG_SUM_WT_PRIORITY_1 0
CV_INTG_RCFG_SUM_WT_PRIORITY_2 0
CV_INTG_SUM_WT_PRIORITY_2 0
CV_INTG_RCFG_SUM_WT_PRIORITY_3 0
CV_INTG_SUM_WT_PRIORITY_3 0
CV_INTG_RCFG_SUM_WT_PRIORITY_4 0
CV_INTG_SUM_WT_PRIORITY_4 0
CV_INTG_RCFG_SUM_WT_PRIORITY_5 0
CV_INTG_SUM_WT_PRIORITY_5 0
CV_INTG_RCFG_SUM_WT_PRIORITY_6 0
CV_INTG_SUM_WT_PRIORITY_6 0
CV_INTG_RCFG_SUM_WT_PRIORITY_7 0
CV_INTG_SUM_WT_PRIORITY_7 0
CONTINUE_AFTER_CAL_FAIL false
MAX10_CFG false
POWER_OF_TWO_BUS false
SOPC_COMPAT_RESET false
AVL_MAX_SIZE 8
BYTE_ENABLE true
ENABLE_CTRL_AVALON_INTERFACE true
CTL_DEEP_POWERDN_EN false
CTL_SELF_REFRESH_EN false
AUTO_POWERDN_EN false
AUTO_PD_CYCLES 0
CTL_USR_REFRESH_EN false
CTL_AUTOPCH_EN false
CTL_ZQCAL_EN false
ADDR_ORDER 0
CTL_LOOK_AHEAD_DEPTH 4
CONTROLLER_LATENCY 5
CFG_REORDER_DATA true
STARVE_LIMIT 10
CTL_CSR_ENABLED false
CTL_CSR_CONNECTION INTERNAL_JTAG
CTL_ECC_ENABLED false
CTL_HRB_ENABLED false
CTL_ECC_AUTO_CORRECTION_ENABLED false
MULTICAST_EN false
CTL_DYNAMIC_BANK_ALLOCATION false
CTL_DYNAMIC_BANK_NUM 4
DEBUG_MODE false
ENABLE_BURST_MERGE false
CTL_ENABLE_BURST_INTERRUPT false
CTL_ENABLE_BURST_TERMINATE false
LOCAL_ID_WIDTH 8
RDBUFFER_ADDR_WIDTH 7
WRBUFFER_ADDR_WIDTH 6
MAX_PENDING_WR_CMD 16
MAX_PENDING_RD_CMD 32
USE_MM_ADAPTOR true
USE_AXI_ADAPTOR false
HCX_COMPAT_MODE false
CTL_CMD_QUEUE_DEPTH 8
CTL_CSR_READ_ONLY 1
CFG_DATA_REORDERING_TYPE INTER_BANK
NUM_OF_PORTS 1
ENABLE_BONDING false
ENABLE_USER_ECC false
AVL_DATA_WIDTH_PORT 32,32,32,32,32,32
PRIORITY_PORT 1,1,1,1,1,1
WEIGHT_PORT 0,0,0,0,0,0
CPORT_TYPE_PORT Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
CORE_PERIPHERY_DUAL_CLOCK false
USE_DR_CLK false
DLL_USE_DR_CLK false
USE_2X_FF false
DUAL_WRITE_CLOCK false
GENERIC_PLL false
USE_HARD_READ_FIFO false
READ_FIFO_HALF_RATE true
PLL_MASTER true
DLL_MASTER true
PHY_VERSION_NUMBER 170
ENABLE_NIOS_OCI false
ENABLE_EMIT_JTAG_MASTER true
ENABLE_NIOS_JTAG_UART false
ENABLE_NIOS_PRINTF_OUTPUT false
ENABLE_LARGE_RW_MGR_DI_BUFFER false
ENABLE_EMIT_BFM_MASTER false
FORCE_SEQUENCER_TCL_DEBUG_MODE false
ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false
ENABLE_MAX_SIZE_SEQ_MEM false
MAKE_INTERNAL_NIOS_VISIBLE false
DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false
ENABLE_CSR_SOFT_RESET_REQ true
DUPLICATE_PLL_FOR_PHY_CLK false
MAX_LATENCY_COUNT_WIDTH 4
READ_VALID_FIFO_SIZE 16
EXTRA_VFIFO_SHIFT 0
TB_MEM_CLK_FREQ 533.33
TB_RATE HALF
TB_MEM_IF_DQ_WIDTH 64
TB_MEM_IF_READ_DQS_WIDTH 8
TB_PLL_DLL_MASTER true
FAST_SIM_CALIBRATION false
REF_CLK_FREQ 50.0
REF_CLK_FREQ_STR 50.0 MHz
REF_CLK_NS 20.0
REF_CLK_PS 20000.0
PLL_DR_CLK_FREQ 0.0
PLL_DR_CLK_FREQ_STR
PLL_DR_CLK_FREQ_SIM_STR 0 ps
PLL_DR_CLK_PHASE_PS 0
PLL_DR_CLK_PHASE_PS_STR
PLL_DR_CLK_PHASE_DEG 0.0
PLL_DR_CLK_PHASE_PS_SIM 0
PLL_DR_CLK_PHASE_PS_SIM_STR
PLL_DR_CLK_PHASE_DEG_SIM 0.0
PLL_DR_CLK_MULT 0
PLL_DR_CLK_DIV 0
PLL_MEM_CLK_FREQ 533.3333
PLL_MEM_CLK_FREQ_STR 533.3333 MHz
PLL_MEM_CLK_FREQ_SIM_STR 1876 ps
PLL_MEM_CLK_PHASE_PS 0
PLL_MEM_CLK_PHASE_PS_STR 0 ps
PLL_MEM_CLK_PHASE_DEG 0.0
PLL_MEM_CLK_PHASE_PS_SIM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR 0 ps
PLL_MEM_CLK_PHASE_DEG_SIM 0.0
PLL_MEM_CLK_MULT 32
PLL_MEM_CLK_DIV 3
PLL_AFI_CLK_FREQ 266.6667
PLL_AFI_CLK_FREQ_STR 266.6667 MHz
PLL_AFI_CLK_FREQ_SIM_STR 3752 ps
PLL_AFI_CLK_PHASE_PS 0
PLL_AFI_CLK_PHASE_PS_STR 0 ps
PLL_AFI_CLK_PHASE_DEG 0.0
PLL_AFI_CLK_PHASE_PS_SIM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR 0 ps
PLL_AFI_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_CLK_MULT 16
PLL_AFI_CLK_DIV 3
PLL_WRITE_CLK_FREQ 533.3333
PLL_WRITE_CLK_FREQ_STR 533.3333 MHz
PLL_WRITE_CLK_FREQ_SIM_STR 1876 ps
PLL_WRITE_CLK_PHASE_PS 234
PLL_WRITE_CLK_PHASE_PS_STR 234 ps
PLL_WRITE_CLK_PHASE_DEG 45.0
PLL_WRITE_CLK_PHASE_PS_SIM 234
PLL_WRITE_CLK_PHASE_PS_SIM_STR 234 ps
PLL_WRITE_CLK_PHASE_DEG_SIM 45.0
PLL_WRITE_CLK_MULT 32
PLL_WRITE_CLK_DIV 3
PLL_ADDR_CMD_CLK_FREQ 266.6667
PLL_ADDR_CMD_CLK_FREQ_STR 266.6667 MHz
PLL_ADDR_CMD_CLK_FREQ_SIM_STR 3752 ps
PLL_ADDR_CMD_CLK_PHASE_PS 2812
PLL_ADDR_CMD_CLK_PHASE_PS_STR 2812 ps
PLL_ADDR_CMD_CLK_PHASE_DEG 270.0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM 2813
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR 2813 ps
PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0
PLL_ADDR_CMD_CLK_MULT 16
PLL_ADDR_CMD_CLK_DIV 3
PLL_AFI_HALF_CLK_FREQ 133.3333
PLL_AFI_HALF_CLK_FREQ_STR 133.3333 MHz
PLL_AFI_HALF_CLK_FREQ_SIM_STR 7504 ps
PLL_AFI_HALF_CLK_PHASE_PS 0
PLL_AFI_HALF_CLK_PHASE_PS_STR 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG 0.0
PLL_AFI_HALF_CLK_PHASE_PS_SIM 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR 0 ps
PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_HALF_CLK_MULT 8
PLL_AFI_HALF_CLK_DIV 3
PLL_NIOS_CLK_FREQ 88.8889
PLL_NIOS_CLK_FREQ_STR 88.8889 MHz
PLL_NIOS_CLK_FREQ_SIM_STR 11256 ps
PLL_NIOS_CLK_PHASE_PS 0
PLL_NIOS_CLK_PHASE_PS_STR 0 ps
PLL_NIOS_CLK_PHASE_DEG 0.0
PLL_NIOS_CLK_PHASE_PS_SIM 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR 0 ps
PLL_NIOS_CLK_PHASE_DEG_SIM 0.0
PLL_NIOS_CLK_MULT 16
PLL_NIOS_CLK_DIV 9
PLL_CONFIG_CLK_FREQ 22.2222
PLL_CONFIG_CLK_FREQ_STR 22.2222 MHz
PLL_CONFIG_CLK_FREQ_SIM_STR 45024 ps
PLL_CONFIG_CLK_PHASE_PS 0
PLL_CONFIG_CLK_PHASE_PS_STR 0 ps
PLL_CONFIG_CLK_PHASE_DEG 0.0
PLL_CONFIG_CLK_PHASE_PS_SIM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR 0 ps
PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0
PLL_CONFIG_CLK_MULT 4
PLL_CONFIG_CLK_DIV 9
PLL_P2C_READ_CLK_FREQ 0.0
PLL_P2C_READ_CLK_FREQ_STR
PLL_P2C_READ_CLK_FREQ_SIM_STR 0 ps
PLL_P2C_READ_CLK_PHASE_PS 0
PLL_P2C_READ_CLK_PHASE_PS_STR
PLL_P2C_READ_CLK_PHASE_DEG 0.0
PLL_P2C_READ_CLK_PHASE_PS_SIM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR
PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0
PLL_P2C_READ_CLK_MULT 0
PLL_P2C_READ_CLK_DIV 0
PLL_C2P_WRITE_CLK_FREQ 0.0
PLL_C2P_WRITE_CLK_FREQ_STR
PLL_C2P_WRITE_CLK_FREQ_SIM_STR 0 ps
PLL_C2P_WRITE_CLK_PHASE_PS 0
PLL_C2P_WRITE_CLK_PHASE_PS_STR
PLL_C2P_WRITE_CLK_PHASE_DEG 0.0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR
PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0
PLL_C2P_WRITE_CLK_MULT 0
PLL_C2P_WRITE_CLK_DIV 0
PLL_HR_CLK_FREQ 0.0
PLL_HR_CLK_FREQ_STR
PLL_HR_CLK_FREQ_SIM_STR 0 ps
PLL_HR_CLK_PHASE_PS 0
PLL_HR_CLK_PHASE_PS_STR
PLL_HR_CLK_PHASE_DEG 0.0
PLL_HR_CLK_PHASE_PS_SIM 0
PLL_HR_CLK_PHASE_PS_SIM_STR
PLL_HR_CLK_PHASE_DEG_SIM 0.0
PLL_HR_CLK_MULT 0
PLL_HR_CLK_DIV 0
PLL_AFI_PHY_CLK_FREQ 0.0
PLL_AFI_PHY_CLK_FREQ_STR
PLL_AFI_PHY_CLK_FREQ_SIM_STR 0 ps
PLL_AFI_PHY_CLK_PHASE_PS 0
PLL_AFI_PHY_CLK_PHASE_PS_STR
PLL_AFI_PHY_CLK_PHASE_DEG 0.0
PLL_AFI_PHY_CLK_PHASE_PS_SIM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR
PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0
PLL_AFI_PHY_CLK_MULT 0
PLL_AFI_PHY_CLK_DIV 0
REF_CLK_FREQ_CACHE_VALID true
REF_CLK_FREQ_PARAM_VALID false
REF_CLK_FREQ_MIN_PARAM 0.0
REF_CLK_FREQ_MAX_PARAM 0.0
REF_CLK_FREQ_MIN_CACHE 10.0
REF_CLK_FREQ_MAX_CACHE 500.0
PLL_DR_CLK_FREQ_PARAM 0.0
PLL_DR_CLK_FREQ_SIM_STR_PARAM
PLL_DR_CLK_PHASE_PS_PARAM 0
PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_DR_CLK_MULT_PARAM 0
PLL_DR_CLK_DIV_PARAM 0
PLL_DR_CLK_FREQ_CACHE 0.0
PLL_DR_CLK_FREQ_SIM_STR_CACHE
PLL_DR_CLK_PHASE_PS_CACHE 0
PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE
PLL_DR_CLK_MULT_CACHE 0
PLL_DR_CLK_DIV_CACHE 0
PLL_MEM_CLK_FREQ_PARAM 0.0
PLL_MEM_CLK_FREQ_SIM_STR_PARAM
PLL_MEM_CLK_PHASE_PS_PARAM 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM
PLL_MEM_CLK_MULT_PARAM 0
PLL_MEM_CLK_DIV_PARAM 0
PLL_MEM_CLK_FREQ_CACHE 533.3333
PLL_MEM_CLK_FREQ_SIM_STR_CACHE 1876 ps
PLL_MEM_CLK_PHASE_PS_CACHE 0
PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_MEM_CLK_MULT_CACHE 32
PLL_MEM_CLK_DIV_CACHE 3
PLL_AFI_CLK_FREQ_PARAM 0.0
PLL_AFI_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_CLK_PHASE_PS_PARAM 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_CLK_MULT_PARAM 0
PLL_AFI_CLK_DIV_PARAM 0
PLL_AFI_CLK_FREQ_CACHE 266.6667
PLL_AFI_CLK_FREQ_SIM_STR_CACHE 3752 ps
PLL_AFI_CLK_PHASE_PS_CACHE 0
PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_AFI_CLK_MULT_CACHE 16
PLL_AFI_CLK_DIV_CACHE 3
PLL_WRITE_CLK_FREQ_PARAM 0.0
PLL_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_WRITE_CLK_PHASE_PS_PARAM 0
PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_WRITE_CLK_MULT_PARAM 0
PLL_WRITE_CLK_DIV_PARAM 0
PLL_WRITE_CLK_FREQ_CACHE 533.3333
PLL_WRITE_CLK_FREQ_SIM_STR_CACHE 1876 ps
PLL_WRITE_CLK_PHASE_PS_CACHE 234
PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE 234 ps
PLL_WRITE_CLK_MULT_CACHE 32
PLL_WRITE_CLK_DIV_CACHE 3
PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM
PLL_ADDR_CMD_CLK_MULT_PARAM 0
PLL_ADDR_CMD_CLK_DIV_PARAM 0
PLL_ADDR_CMD_CLK_FREQ_CACHE 266.6667
PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE 3752 ps
PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 2812
PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE 2813 ps
PLL_ADDR_CMD_CLK_MULT_CACHE 16
PLL_ADDR_CMD_CLK_DIV_CACHE 3
PLL_AFI_HALF_CLK_FREQ_PARAM 0.0
PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_HALF_CLK_MULT_PARAM 0
PLL_AFI_HALF_CLK_DIV_PARAM 0
PLL_AFI_HALF_CLK_FREQ_CACHE 133.3333
PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE 7504 ps
PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0
PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_AFI_HALF_CLK_MULT_CACHE 8
PLL_AFI_HALF_CLK_DIV_CACHE 3
PLL_NIOS_CLK_FREQ_PARAM 0.0
PLL_NIOS_CLK_FREQ_SIM_STR_PARAM
PLL_NIOS_CLK_PHASE_PS_PARAM 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM
PLL_NIOS_CLK_MULT_PARAM 0
PLL_NIOS_CLK_DIV_PARAM 0
PLL_NIOS_CLK_FREQ_CACHE 88.8889
PLL_NIOS_CLK_FREQ_SIM_STR_CACHE 11256 ps
PLL_NIOS_CLK_PHASE_PS_CACHE 0
PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_NIOS_CLK_MULT_CACHE 16
PLL_NIOS_CLK_DIV_CACHE 9
PLL_CONFIG_CLK_FREQ_PARAM 0.0
PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM
PLL_CONFIG_CLK_PHASE_PS_PARAM 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM
PLL_CONFIG_CLK_MULT_PARAM 0
PLL_CONFIG_CLK_DIV_PARAM 0
PLL_CONFIG_CLK_FREQ_CACHE 22.2222
PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE 45024 ps
PLL_CONFIG_CLK_PHASE_PS_CACHE 0
PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE 0 ps
PLL_CONFIG_CLK_MULT_CACHE 4
PLL_CONFIG_CLK_DIV_CACHE 9
PLL_P2C_READ_CLK_FREQ_PARAM 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM
PLL_P2C_READ_CLK_PHASE_PS_PARAM 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM
PLL_P2C_READ_CLK_MULT_PARAM 0
PLL_P2C_READ_CLK_DIV_PARAM 0
PLL_P2C_READ_CLK_FREQ_CACHE 0.0
PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE
PLL_P2C_READ_CLK_PHASE_PS_CACHE 0
PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE
PLL_P2C_READ_CLK_MULT_CACHE 0
PLL_P2C_READ_CLK_DIV_CACHE 0
PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM
PLL_C2P_WRITE_CLK_MULT_PARAM 0
PLL_C2P_WRITE_CLK_DIV_PARAM 0
PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0
PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0
PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE
PLL_C2P_WRITE_CLK_MULT_CACHE 0
PLL_C2P_WRITE_CLK_DIV_CACHE 0
PLL_HR_CLK_FREQ_PARAM 0.0
PLL_HR_CLK_FREQ_SIM_STR_PARAM
PLL_HR_CLK_PHASE_PS_PARAM 0
PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM
PLL_HR_CLK_MULT_PARAM 0
PLL_HR_CLK_DIV_PARAM 0
PLL_HR_CLK_FREQ_CACHE 0.0
PLL_HR_CLK_FREQ_SIM_STR_CACHE
PLL_HR_CLK_PHASE_PS_CACHE 0
PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE
PLL_HR_CLK_MULT_CACHE 0
PLL_HR_CLK_DIV_CACHE 0
PLL_AFI_PHY_CLK_FREQ_PARAM 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM
PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM
PLL_AFI_PHY_CLK_MULT_PARAM 0
PLL_AFI_PHY_CLK_DIV_PARAM 0
PLL_AFI_PHY_CLK_FREQ_CACHE 0.0
PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE
PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0
PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE
PLL_AFI_PHY_CLK_MULT_CACHE 0
PLL_AFI_PHY_CLK_DIV_CACHE 0
SPEED_GRADE_CACHE 2
IS_ES_DEVICE_CACHE false
MEM_CLK_FREQ_CACHE 533.33
REF_CLK_FREQ_CACHE 50.0
RATE_CACHE Half
HCX_COMPAT_MODE_CACHE false
PARSE_FRIENDLY_DEVICE_FAMILY_CACHE STRATIXIV
COMMAND_PHASE_CACHE 0.0
MEM_CK_PHASE_CACHE 0.0
P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0
C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0
ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0
SEQUENCER_TYPE_CACHE NIOS
USE_MEM_CLK_FREQ_CACHE false
PLL_CLK_CACHE_VALID true
PLL_CLK_PARAM_VALID false
ENABLE_EXTRA_REPORTING false
NUM_EXTRA_REPORT_PATH 10
ENABLE_ISS_PROBES false
CALIB_REG_WIDTH 8
USE_SEQUENCER_BFM false
PLL_SHARING_MODE None
NUM_PLL_SHARING_INTERFACES 1
EXPORT_AFI_HALF_CLK false
ABSTRACT_REAL_COMPARE_TEST false
INCLUDE_BOARD_DELAY_MODEL false
INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false
USE_FAKE_PHY_INTERNAL false
USE_FAKE_PHY false
FORCE_MAX_LATENCY_COUNT_WIDTH 0
USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false
ENABLE_NON_DESTRUCTIVE_CALIB false
FIX_READ_LATENCY 8
USE_USER_RDIMM_VALUE false
ENABLE_DELAY_CHAIN_WRITE false
TRACKING_ERROR_TEST false
TRACKING_WATCH_TEST false
MARGIN_VARIATION_TEST false
AC_ROM_USER_ADD_0 0_0000_0000_0000
AC_ROM_USER_ADD_1 0_0000_0000_1000
TREFI 35100
REFRESH_INTERVAL 15000
ENABLE_NON_DES_CAL_TEST false
TRFC 350
ENABLE_NON_DES_CAL false
EXTRA_SETTINGS
MEM_DEVICE MISSING_MODEL
FORCE_SYNTHESIS_LANGUAGE
NUM_SUBGROUP_PER_READ_DQS 1
QVLD_EXTRA_FLOP_STAGES 2
QVLD_WR_ADDRESS_OFFSET 8
MAX_WRITE_LATENCY_COUNT_WIDTH 4
NUM_WRITE_PATH_FLOP_STAGES 0
NUM_AC_FR_CYCLE_SHIFTS 1
FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0
NUM_WRITE_FR_CYCLE_SHIFTS 0
PERFORM_READ_AFTER_WRITE_CALIBRATION false
SEQ_BURST_COUNT_WIDTH 1
VCALIB_COUNT_WIDTH 2
PLL_PHASE_COUNTER_WIDTH 4
DQS_DELAY_CHAIN_PHASE_SETTING 2
DQS_PHASE_SHIFT 9000
DELAYED_CLOCK_PHASE_SETTING 2
IO_DQS_IN_RESERVE 3
IO_DQS_OUT_RESERVE 3
IO_DQ_OUT_RESERVE 0
IO_DM_OUT_RESERVE 0
IO_DQS_EN_DELAY_OFFSET 0
IO_DQS_EN_PHASE_MAX 7
IO_DQDQS_OUT_PHASE_MAX 14
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS true
MEM_CLK_NS 1.875
MEM_CLK_PS 1875.0
CALIB_LFIFO_OFFSET 9
CALIB_VFIFO_OFFSET 21
DELAY_PER_OPA_TAP 234
DELAY_PER_DCHAIN_TAP 50
DELAY_PER_DQS_EN_DCHAIN_TAP 50
DQS_EN_DELAY_MAX 7
DQS_IN_DELAY_MAX 15
IO_IN_DELAY_MAX 15
IO_OUT1_DELAY_MAX 15
IO_OUT2_DELAY_MAX 7
IO_STANDARD SSTL-15
VFIFO_AS_SHIFT_REG true
SEQUENCER_TYPE NIOS
NIOS_HEX_FILE_LOCATION ../
ADVERTIZE_SEQUENCER_SW_BUILD_FILES false
NEGATIVE_WRITE_CK_PHASE false
MEM_T_WL 10
MEM_T_RL 13
PHY_CLKBUF false
USE_LDC_AS_LOW_SKEW_CLOCK false
USE_LDC_FOR_ADDR_CMD false
ENABLE_LDC_MEM_CK_ADJUSTMENT false
MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0
LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true
LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0
FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false
NON_LDC_ADDR_CMD_MEM_CK_INVERT false
REGISTER_C2P false
EARLY_ADDR_CMD_CLK_TRANSFER true
MAX10_RTL_SEQ false
PHY_ONLY false
SEQ_MODE 0
ADVANCED_CK_PHASES false
COMMAND_PHASE 0.0
MEM_CK_PHASE 0.0
P2C_READ_CLOCK_ADD_PHASE 0.0
C2P_WRITE_CLOCK_ADD_PHASE 0.0
ACV_PHY_CLK_ADD_FR_PHASE 0.0
MEM_VOLTAGE 1.5V DDR3
PLL_LOCATION Top_Bottom
SKIP_MEM_INIT true
READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS
DQ_INPUT_REG_USE_CLKN false
DQS_DQSN_MODE DIFFERENTIAL
AFI_DEBUG_INFO_WIDTH 32
CALIBRATION_MODE Full
NIOS_ROM_DATA_WIDTH 32
NIOS_ROM_ADDRESS_WIDTH 13
READ_FIFO_SIZE 8
PHY_CSR_ENABLED false
PHY_CSR_CONNECTION INTERNAL_JTAG
USER_DEBUG_LEVEL 1
TIMING_BOARD_DERATE_METHOD AUTO
TIMING_BOARD_CK_CKN_SLEW_RATE 2.0
TIMING_BOARD_AC_SLEW_RATE 1.0
TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0
TIMING_BOARD_DQ_SLEW_RATE 1.0
TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 1.28
TIMING_BOARD_AC_SLEW_RATE_APPLIED 3.51
TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 3.87
TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.56
TIMING_BOARD_TIS 0.0
TIMING_BOARD_TIH 0.0
TIMING_BOARD_TDS 0.0
TIMING_BOARD_TDH 0.0
TIMING_BOARD_TIS_APPLIED 0.292
TIMING_BOARD_TIH_APPLIED 0.308
TIMING_BOARD_TDS_APPLIED 0.2
TIMING_BOARD_TDH_APPLIED 0.2
TIMING_BOARD_ISI_METHOD AUTO
TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H 0.0
TIMING_BOARD_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0
TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0
TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0
TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0
TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0
TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0
PACKAGE_DESKEW false
AC_PACKAGE_DESKEW false
TIMING_BOARD_MAX_CK_DELAY 1.2
TIMING_BOARD_MAX_DQS_DELAY 0.56
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN 0.33
TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED 0.33
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.7
TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.7
TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05
TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0
TIMING_BOARD_SKEW_WITHIN_DQS 0.0085
TIMING_BOARD_SKEW_BETWEEN_DQS 0.05
TIMING_BOARD_DQ_TO_DQS_SKEW 0.004
TIMING_BOARD_AC_SKEW 0.043
TIMING_BOARD_AC_TO_CK_SKEW 0.0
ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false
CORE_DEBUG_CONNECTION EXPORT
ADD_EXTERNAL_SEQ_DEBUG_NIOS false
ED_EXPORT_SEQ_DEBUG false
ADD_EFFICIENCY_MONITOR false
ENABLE_ABS_RAM_MEM_INIT false
ENABLE_ABS_RAM_INTERNAL false
ENABLE_ABSTRACT_RAM false
ABS_RAM_MEM_INIT_FILENAME meminit
DLL_DELAY_CTRL_WIDTH 6
DLL_OFFSET_CTRL_WIDTH 6
DELAY_BUFFER_MODE HIGH
DELAY_CHAIN_LENGTH 8
DLL_SHARING_MODE None
NUM_DLL_SHARING_INTERFACES 1
OCT_TERM_CONTROL_WIDTH 14
OCT_SHARING_MODE None
NUM_OCT_SHARING_INTERFACES 1
AUTO_DEVICE EP4SGX230KF40C2
AUTO_DEVICE_SPEEDGRADE 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

mm_clock_crossing_bridge_0

altera_avalon_mm_clock_crossing_bridge v17.0
dma_read_master_0 Data_Read_Master   mm_clock_crossing_bridge_0
  s0
dma_write_master_0 Data_Write_Master  
  s0
mem_if_ddr3_emif_0 afi_clk  
  m0_clk
afi_reset  
  m0_reset
pcie_hard_ip_0 pcie_core_clk  
  s0_clk
clkin_100 clk_reset  
  s0_reset
m0   mem_if_ddr3_emif_0
  avl


Parameters

DATA_WIDTH 256
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
SYSINFO_ADDR_WIDTH 30
USE_AUTO_ADDRESS_WIDTH 1
AUTO_ADDRESS_WIDTH 30
HDL_ADDR_WIDTH 30
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
COMMAND_FIFO_DEPTH 4
RESPONSE_FIFO_DEPTH 4
MASTER_SYNC_DEPTH 2
SLAVE_SYNC_DEPTH 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

modular_sgdma_dispatcher_0

modular_sgdma_dispatcher v17.0
pcie_hard_ip_0 bar3_2   modular_sgdma_dispatcher_0
  CSR
bar3_2  
  Descriptor_Slave
pcie_core_clk  
  clock
rxm_irq  
  csr_irq
dma_read_master_0 Response_Source  
  Read_Response_Sink
dma_write_master_0 Response_Source  
  Write_Response_Sink
clkin_100 clk_reset  
  clock_reset
Read_Command_Source   dma_read_master_0
  Command_Sink
Write_Command_Source   dma_write_master_0
  Command_Sink


Parameters

PREFETCHER_USE_CASE 0
MODE 0
GUI_RESPONSE_PORT 2
RESPONSE_PORT 2
DESCRIPTOR_INTERFACE 0
DESCRIPTOR_FIFO_DEPTH 64
ENHANCED_FEATURES 0
DESCRIPTOR_WIDTH 128
DESCRIPTOR_BYTEENABLE_WIDTH 16
CSR_ADDRESS_WIDTH 3
DATA_WIDTH 32
DATA_FIFO_DEPTH 32
MAX_BYTE 1024
TRANSFER_TYPE Aligned Accesses
BURST_ENABLE 0
MAX_BURST_COUNT 2
BURST_WRAPPING_SUPPORT 0
STRIDE_ENABLE 0
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BURST_ENABLE 0
BURST_WRAPPING_SUPPORT 0
DATA_FIFO_DEPTH 32
DATA_WIDTH 32
DESCRIPTOR_FIFO_DEPTH 64
ENHANCED_FEATURES 0
MAX_BURST_COUNT 2
MAX_BYTE 1024
MAX_STRIDE 1
PROGRAMMABLE_BURST_ENABLE 0
RESPONSE_FIFO_DEPTH 128
RESPONSE_PORT 2
STRIDE_ENABLE 0
TRANSFER_TYPE Aligned Accesses

onchip_memory2_0

altera_avalon_onchip_memory2 v17.0
dma_read_master_0 Data_Read_Master   onchip_memory2_0
  s1
dma_write_master_0 Data_Write_Master  
  s1
pcie_hard_ip_0 bar1_0  
  s1
pcie_core_clk  
  clk1
clkin_100 clk_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
blockType M9K
dataWidth 256
dataWidth2 32
dualPort false
enableDiffWidth false
derived_enableDiffWidth false
initMemContent false
initializationFileName onchip_memory2_0
enPRInitMode false
instanceID Chek
memorySize 524288
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
derived_singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
copyInitFile false
useShallowMemBlocks false
writable true
ecc_enabled false
resetrequest_enabled true
autoInitializationFileName q_sys_onchip_memory2_0
deviceFamily STRATIXIV
deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width 14
derived_set_addr_width2 14
derived_set_data_width 256
derived_set_data_width2 256
derived_gui_ram_block_type M9K
derived_is_hardcopy false
derived_init_file_name q_sys_onchip_memory2_0.hex
generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE M9K
INIT_CONTENTS_FILE q_sys_onchip_memory2_0
INIT_MEM_CONTENT 0
INSTANCE_ID Chek
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE M9K
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

pcie_hard_ip_0

altera_pcie_hard_ip v17.0
dma_read_master_0 Data_Read_Master   pcie_hard_ip_0
  txs
dma_write_master_0 Data_Write_Master  
  txs
clkin_100 clk  
  cal_blk_clk
clk  
  reconfig_gxbclk
bar1_0   onchip_memory2_0
  s1
pcie_core_clk  
  clk1
bar3_2   modular_sgdma_dispatcher_0
  CSR
bar3_2  
  Descriptor_Slave
pcie_core_clk  
  clock
rxm_irq  
  csr_irq
bar5_4   pio_key
  s1
pcie_core_clk  
  clk
bar5_4   pio_led
  s1
pcie_core_clk  
  clk
bar5_4   ddr3_status
  s1
pcie_core_clk  
  clk
pcie_core_clk   dma_read_master_0
  Clock
pcie_core_clk   dma_write_master_0
  Clock
pcie_core_clk   mm_clock_crossing_bridge_0
  s0_clk


Parameters

under_test 0
INTENDED_DEVICE_FAMILY STRATIXIV
pcie_qsys 1
p_pcie_hip_type 0
lane_mask 240
my_gen2_lane_rate_mode true
max_link_width 4
p_pcie_txrx_clock 100 MHz
p_pcie_app_clk 0
millisecond_cycle_count 250000
core_clk_freq 2500
p_pcie_test_out_width 64bits
enable_gen2_core true
gen2_lane_rate_mode true
no_soft_reset false
p_pcie_version 2.0
core_clk_divider 2
enable_ch0_pclk_out false
core_clk_source PLL_FIXED_CLK
NUM_PREFETCH_MASTERS 1
CB_P2A_AVALON_ADDR_B0 0x00000000
bar0_size_mask 27
bar0_io_space false
bar0_64bit_mem_space true
bar0_prefetchable true
CB_P2A_AVALON_ADDR_B1 0x00000000
bar1_size_mask 0
bar1_io_space false
bar1_64bit_mem_space true
bar1_prefetchable false
CB_P2A_AVALON_ADDR_B2 0x00000000
bar2_size_mask 27
bar2_io_space false
bar2_64bit_mem_space true
bar2_prefetchable true
CB_P2A_AVALON_ADDR_B3 0x00000000
bar3_size_mask 0
bar3_io_space false
bar3_64bit_mem_space false
bar3_prefetchable false
CB_P2A_AVALON_ADDR_B4 0x00000000
bar4_size_mask 27
bar4_io_space false
bar4_64bit_mem_space true
bar4_prefetchable true
CB_P2A_AVALON_ADDR_B5 0x00000000
bar5_size_mask 0
bar5_io_space false
bar5_64bit_mem_space false
bar5_prefetchable false
fixed_address_mode 0
CB_P2A_FIXED_AVALON_ADDR_B0 0
CB_P2A_FIXED_AVALON_ADDR_B1 0
CB_P2A_FIXED_AVALON_ADDR_B2 0
CB_P2A_FIXED_AVALON_ADDR_B3 0
CB_P2A_FIXED_AVALON_ADDR_B4 0
CB_P2A_FIXED_AVALON_ADDR_B5 0
BAR 0,1 - Occupied,2,3 - Occupied,4,5 - Occupied
BAR Type 64 bit Prefetchable,Not used,64 bit Prefetchable,Not used,64 bit Prefetchable,Not used
BAR Size 27,0,27,0,27,0
Avalon Base Address 0,0,0,0,0,0
vendor_id 4466
device_id 57345
revision_id 9
class_code 16711680
subsystem_vendor_id 41222
subsystem_device_id 9220
port_link_number 1
msi_function_count 0
enable_msi_64bit_addressing true
enable_function_msix_support false
eie_before_nfts_count 4
enable_completion_timeout_disable false
completion_timeout NONE
enable_adapter_half_rate_mode false
msix_pba_bir 0
msix_pba_offset 0
msix_table_bir 0
msix_table_offset 0
msix_table_size 0
use_crc_forwarding false
surprise_down_error_support false
dll_active_report_support false
bar_io_window_size 32BIT
bar_prefetchable 32
hot_plug_support 0
no_command_completed true
slot_power_limit 0
slot_power_scale 0
slot_number 0
enable_slot_register false
link_common_clock 1
advanced_errors false
enable_ecrc_check false
enable_ecrc_gen false
my_advanced_errors false
my_enable_ecrc_check false
my_enable_ecrc_gen false
max_payload_size 1
p_pcie_target_performance_preset Maximum
retry_buffer_last_active_address 2047
credit_buffer_allocation_aux ABSOLUTE
vc0_rx_flow_ctrl_posted_header 55
vc0_rx_flow_ctrl_posted_data 403
vc0_rx_flow_ctrl_nonposted_header 54
vc0_rx_flow_ctrl_nonposted_data 0
vc0_rx_flow_ctrl_compl_header 48
vc0_rx_flow_ctrl_compl_data 256
RX_BUF 9
RH_NUM 7
G_TAG_NUM0 32
endpoint_l0_latency 0
endpoint_l1_latency 0
enable_l1_aspm false
l01_entry_latency 31
diffclock_nfts_count 255
sameclock_nfts_count 255
l1_exit_latency_sameclock 7
l1_exit_latency_diffclock 7
l0_exit_latency_sameclock 7
l0_exit_latency_diffclock 7
gen2_diffclock_nfts_count 255
gen2_sameclock_nfts_count 255
CG_COMMON_CLOCK_MODE 1
CB_PCIE_MODE 0
AST_LITE 0
CB_PCIE_RX_LITE 0
CG_RXM_IRQ_NUM 16
CG_AVALON_S_ADDR_WIDTH 20
bypass_tl true
CG_IMPL_CRA_AV_SLAVE_PORT 1
CG_NO_CPL_REORDERING 0
CG_ENABLE_A2P_INTERRUPT 0
p_user_msi_enable 0
CG_IRQ_BIT_ENA 65535
CB_A2P_ADDR_MAP_IS_FIXED 0
CB_A2P_ADDR_MAP_NUM_ENTRIES 2
CB_A2P_ADDR_MAP_PASS_THRU_BITS 24
CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW 0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH 0
CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW 0
Address Page 0,1,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
PCIe Address 63:32 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000
PCIe Address 31:0 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000
RXM_DATA_WIDTH 64
RXM_BEN_WIDTH 8
CB_TXS_ADDRESS_WIDTH 7
TL_SELECTION 1
pcie_mode SHARED_MODE
single_rx_detect 4
enable_coreclk_out_half_rate false
low_priority_vc 0
SLAVE_ADDRESS_MAP_0 0
SLAVE_ADDRESS_MAP_1 0
SLAVE_ADDRESS_MAP_2 0
SLAVE_ADDRESS_MAP_3 0
SLAVE_ADDRESS_MAP_4 0
SLAVE_ADDRESS_MAP_5 0
SLAVE_ADDRESS_MAP_1_0 27
SLAVE_ADDRESS_MAP_3_2 27
SLAVE_ADDRESS_MAP_5_4 27
deviceFamily STRATIXIV
wiz_subprotocol Gen 2-x4
link_width 4
cyclone4 0
AUTO_DEVICE EP4SGX230KF40C2
AUTO_DEVICE_SPEEDGRADE 2
AUTO_CAL_BLK_CLK_CLOCK_RATE 100000000
AUTO_CAL_BLK_CLK_CLOCK_DOMAIN 1
AUTO_CAL_BLK_CLK_RESET_DOMAIN 1
generateLegacySim false
  

Software Assignments

(none)

pio_key

altera_avalon_pio v17.0
pcie_hard_ip_0 bar5_4   pio_key
  s1
pcie_core_clk  
  clk
clkin_100 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
clockRate 250000000
derived_has_tri false
derived_has_out false
derived_has_in true
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 250000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led

altera_avalon_pio v17.0
pcie_hard_ip_0 bar5_4   pio_led
  s1
pcie_core_clk  
  clk
clkin_100 clk_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
clockRate 250000000
derived_has_tri false
derived_has_out true
derived_has_in false
derived_do_test_bench_wiring false
derived_capture false
derived_edge_type NONE
derived_irq_type NONE
derived_has_irq false
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 250000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0
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