ddr4_clock_crossing_bridge

2020.04.22.15:05:45 Datasheet
Overview

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   ddr4_clock_crossing_bridge altera_avalon_mm_clock_crossing_bridge 19.1
Memory Map

ddr4_clock_crossing_bridge

altera_avalon_mm_clock_crossing_bridge v19.1


Parameters

DATA_WIDTH 512
SYMBOL_WIDTH 8
ADDRESS_WIDTH 10
USE_AUTO_ADDRESS_WIDTH 1
AUTO_ADDRESS_WIDTH 35
ADDRESS_UNITS SYMBOLS
MAX_BURST_SIZE 16
COMMAND_FIFO_DEPTH 32
RESPONSE_FIFO_DEPTH 512
MASTER_SYNC_DEPTH 2
SLAVE_SYNC_DEPTH 2
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_clock_crossing_bridge_my_altera_avalon_dc_fifo_cmd_fifo

altera_avalon_mm_clock_crossing_bridge_altera_avalon_dc_fifo v19.1


Parameters

SYMBOLS_PER_BEAT 1
BITS_PER_SYMBOL 619
FIFO_DEPTH 32
CHANNEL_WIDTH 0
ERROR_WIDTH 0
USE_PACKETS 0
USE_IN_FILL_LEVEL 0
USE_OUT_FILL_LEVEL 0
WR_SYNC_DEPTH 2
RD_SYNC_DEPTH 2
ENABLE_EXPLICIT_MAXCHANNEL false
EXPLICIT_MAXCHANNEL 0
BACKPRESSURE_DURING_RESET true
USE_SPACE_AVAIL_IF 0
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_clock_crossing_bridge_my_altera_avalon_dc_fifo_cmd_fifo_my_altera_avalon_dc_fifo_cmd_fifo

altera_avalon_dc_fifo v19.1


Parameters

SYMBOLS_PER_BEAT 1
BITS_PER_SYMBOL 619
FIFO_DEPTH 32
CHANNEL_WIDTH 0
ERROR_WIDTH 0
USE_PACKETS 0
USE_IN_FILL_LEVEL 0
USE_OUT_FILL_LEVEL 0
WR_SYNC_DEPTH 2
RD_SYNC_DEPTH 2
ENABLE_EXPLICIT_MAXCHANNEL false
EXPLICIT_MAXCHANNEL 0
BACKPRESSURE_DURING_RESET true
USE_SPACE_AVAIL_IF 0
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_clock_crossing_bridge_my_altera_avalon_dc_fifo_rsp_fifo

altera_avalon_mm_clock_crossing_bridge_altera_avalon_dc_fifo v19.1


Parameters

SYMBOLS_PER_BEAT 1
BITS_PER_SYMBOL 512
FIFO_DEPTH 512
CHANNEL_WIDTH 0
ERROR_WIDTH 0
USE_PACKETS 0
USE_IN_FILL_LEVEL 0
USE_OUT_FILL_LEVEL 0
WR_SYNC_DEPTH 3
RD_SYNC_DEPTH 3
ENABLE_EXPLICIT_MAXCHANNEL false
EXPLICIT_MAXCHANNEL 0
BACKPRESSURE_DURING_RESET false
USE_SPACE_AVAIL_IF 1
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

ddr4_clock_crossing_bridge_my_altera_avalon_dc_fifo_rsp_fifo_my_altera_avalon_dc_fifo_rsp_fifo

altera_avalon_dc_fifo v19.1


Parameters

SYMBOLS_PER_BEAT 1
BITS_PER_SYMBOL 512
FIFO_DEPTH 512
CHANNEL_WIDTH 0
ERROR_WIDTH 0
USE_PACKETS 0
USE_IN_FILL_LEVEL 0
USE_OUT_FILL_LEVEL 0
WR_SYNC_DEPTH 3
RD_SYNC_DEPTH 3
ENABLE_EXPLICIT_MAXCHANNEL false
EXPLICIT_MAXCHANNEL 0
BACKPRESSURE_DURING_RESET false
USE_SPACE_AVAIL_IF 1
SYNC_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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