rcfg_enable |
1 |
rcfg_jtag_enable |
0 |
rcfg_separate_avmm_busy |
0 |
set_capability_reg_enable |
0 |
set_user_identifier |
0 |
set_csr_soft_logic_enable |
0 |
rcfg_file_prefix |
altera_xcvr_rcfg_10 |
rcfg_sv_file_enable |
0 |
rcfg_h_file_enable |
0 |
rcfg_mif_file_enable |
0 |
rcfg_multi_enable |
0 |
set_rcfg_emb_strm_enable |
0 |
rcfg_reduced_files_enable |
0 |
rcfg_profile_cnt |
2 |
rcfg_profile_select |
1 |
rcfg_profile_data0 |
|
rcfg_profile_data1 |
|
rcfg_profile_data2 |
|
rcfg_profile_data3 |
|
rcfg_profile_data4 |
|
rcfg_profile_data5 |
|
rcfg_profile_data6 |
|
rcfg_profile_data7 |
|
message_level |
error |
reduced_reset_sim_time |
0 |
channel_type |
GX |
protocol_mode |
basic_std |
pma_mode |
basic |
duplex_mode |
tx |
channels |
4 |
set_data_rate |
6000 |
rcfg_iface_enable |
0 |
enable_simple_interface |
1 |
enable_split_interface |
0 |
enable_double_rate_transfer |
0 |
bonded_mode |
pma_pcs |
set_pcs_bonding_master |
Auto |
pcs_bonding_master |
2 |
pcs_reset_sequencing_mode |
bonded |
tx_pma_clk_div |
1 |
plls |
1 |
pll_select |
0 |
enable_port_tx_pma_iqtxrx_clkout |
0 |
enable_port_tx_pma_elecidle |
0 |
std_pcs_pma_width |
20 |
display_std_tx_pld_adapt_width |
20 |
std_low_latency_bypass_enable |
0 |
std_tx_byte_ser_mode |
Disabled |
std_tx_8b10b_enable |
0 |
std_tx_8b10b_disp_ctrl_enable |
0 |
std_tx_bitslip_enable |
0 |
enable_port_tx_std_bitslipboundarysel |
0 |
std_tx_bitrev_enable |
0 |
std_tx_byterev_enable |
0 |
std_tx_polinv_enable |
1 |
enable_port_tx_polinv |
1 |
enable_ports_pipe_sw |
0 |
enable_ports_pipe_hclk |
0 |
enable_debug_ports |
0 |
tx_fifo_mode |
Phase compensation |
tx_fifo_pfull |
5 |
tx_fifo_pempty |
2 |
enable_port_tx_fifo_full |
0 |
enable_port_tx_fifo_empty |
0 |
enable_port_tx_fifo_pfull |
0 |
enable_port_tx_fifo_pempty |
0 |
enable_port_tx_dll_lock |
0 |
tx_clkout_sel |
pcs_clkout |
enable_port_tx_clkout2 |
1 |
tx_clkout2_sel |
pcs_x2_clkout |
tx_pma_div_clkout_divider |
0 |
tx_coreclkin_clock_network |
dedicated |
tx_pcs_bonding_clock_network |
dedicated |
enable_port_latency_measurement |
0 |
generate_docs |
1 |
enable_tx_coreclkin2 |
0 |
rcfg_shared |
0 |
rcfg_use_clk_reset_only |
0 |
set_prbs_soft_logic_enable |
0 |
enable_rcfg_tx_digitalreset_release_ctrl |
0 |
tx_pll_type |
ATX |
tx_pll_refclk |
125.0 |
use_tx_clkout2 |
0 |
use_rx_clkout2 |
0 |
enable_fast_sim |
0 |
design_example_filename |
top |
anlg_voltage |
1_0V |
anlg_link |
lr |
qsf_assignments_enable |
0 |
qsf_assignments_list |
|
tx_pma_analog_mode |
user_custom |
tx_pma_optimal_settings |
1 |
tx_pma_output_swing_ctrl |
12 |
tx_pma_pre_emp_sign_pre_tap_1t |
negative |
tx_pma_pre_emp_switching_ctrl_pre_tap_1t |
0 |
tx_pma_pre_emp_sign_1st_post_tap |
negative |
tx_pma_pre_emp_switching_ctrl_1st_post_tap |
0 |
tx_pma_slew_rate_ctrl |
0 |
tx_pma_term_sel |
r_r1 |
tx_pma_compensation_en |
enable |
rx_pma_optimal_settings |
1 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |