TR4_QSYS TR4_QSYS
1.0
2012.03.07.15:21:40 Generation Report
Output Directory D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/
Files D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/TR4_QSYS.v (452072 bytes VERILOG)

D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.ocp (848 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.sdc (3743 bytes SDC)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu.v (422584 bytes VERILOG_ENCRYPT)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_bht_ram.mif (2392 bytes MIF)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_dc_tag_ram.mif (984 bytes MIF)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_ic_tag_ram.mif (2009 bytes MIF)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_sysclk.v (7033 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_tck.v (8319 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_jtag_debug_module_wrapper.v (10163 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_ociram_default_contents.mif (5714 bytes MIF)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_oci_test_bench.v (1468 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_rf_ram_a.mif (600 bytes MIF)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_rf_ram_b.mif (600 bytes MIF)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cpu_test_bench.v (31415 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_sysid.v (1447 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart.v (23819 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_input_mutex.dat (3 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_input_stream.dat (10 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_jtag_uart_output_stream.dat (0 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_onchip_mem.hex (688141 bytes HEX)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_onchip_mem.v (3981 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_mm_clock_crossing_bridge.v (10052 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_dc_fifo.v (23570 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_dcfifo_synchronizer_bundle.v (1458 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_timer.v (6907 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_ddr3_i2c_scl.v (2293 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_ddr3_i2c_sda.v (2811 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3.v (38060 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_pll0.sv (17333 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_clock_pair_generator.v (3523 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_valid_selector.v (2379 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_datapath.v (6482 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset.v (4153 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_acv_ldc.v (2768 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_pads.v (13566 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_ldc_pads.v (12360 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_addr_cmd_ldc_pad.v (4485 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/addr_cmd_non_ldc_pad.v (3149 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_memphy.v (33210 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_reset_sync.v (1978 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_new_io_pads.v (13397 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_fr_cycle_shifter.v (3943 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_read_datapath.v (28437 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_write_datapath.v (9217 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_hr_to_fr.v (1348 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_simple_ddio_out.v (9122 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_mux_bridge.sv (18324 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_phy_csr.sv (6103 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_iss_probe.v (1784 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_flop_mem.v (2755 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sv (17391 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_altdqdqs.v (6089 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altdq_dqs2_ddio_3reg_stratixiv.sv (57835 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.ppf (98232 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0.sdc (29970 bytes SDC)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_timing.tcl (5747 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing.tcl (17667 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_report_timing_core.tcl (80849 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_map.tcl (81320 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_pin_assignments.tcl (18670 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_parameters.tcl (3117 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_p0_sequencer_cpu.sdc (796 bytes SDC)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/afi_mux_ddr3_ddrx.v (10652 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_software/sequencer.c (214113 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_software/sequencer.h (13839 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_make_qsys_seq.tcl (5147 bytes OTHER)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0.v (267539 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v (32228 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v (85632 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v (33763 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_mem_if_sequencer_mem_no_ifdef_params.sv (2845 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv (9460 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10373 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv (8686 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv (16802 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv (19132 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv (16043 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_reset_controller.v (3595 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_no_ifdef_params.v (3053 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_ac_ROM_reg.v (1456 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_bitcheck.v (3398 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_core.sv (17999 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_datamux.v (1733 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_data_broadcast.v (2357 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_data_decoder.v (2899 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_ddr3.v (8069 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer.v (4084 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_di_buffer_wrap.v (2373 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_dm_decoder.v (1770 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_generic.sv (7568 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_no_ifdef_params.v (3065 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_inst_ROM_reg.v (1480 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_jumplogic.v (3333 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_lfsr12.v (1448 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_lfsr36.v (2107 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_lfsr72.v (1391 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_pattern_fifo.v (2851 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_ram.v (1322 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_ram_csr.v (2522 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_read_datapath.v (3618 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/rw_manager_write_decoder.v (2858 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_data_mgr.sv (3828 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_phy_mgr.sv (17495 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_reg_file.sv (5845 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_acv_phase_decode.v (1890 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_acv_wrapper.sv (5253 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_mgr.sv (23952 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_reg_file.v (2631 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_siii_phase_decode.v (11919 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_siii_wrapper.sv (4872 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_sv_phase_decode.v (3905 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/sequencer_scc_sv_wrapper.sv (6215 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_addr_router.sv (7564 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_addr_router_001.sv (6079 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux.sv (6664 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_demux_001.sv (3512 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_cmd_xbar_mux_003.sv (11876 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_id_router.sv (6000 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_id_router_003.sv (6093 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_irq_mapper.sv (1700 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_rsp_xbar_demux_003.sv (4144 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_rsp_xbar_mux.sv (14489 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_sequencer_mem.hex (59166 bytes HEX)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_AC_ROM.hex (853 bytes HEX)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_s0_inst_ROM.hex (2445 bytes HEX)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_uniphy_ddr3_c0.v (19874 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd.v (25980 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_addr_cmd_wrap.v (51739 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ddr2_odt_gen.v (19238 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ddr3_odt_gen.v (18029 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v (16552 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_odt_gen.v (15324 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rdwr_data_tmg.v (131911 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_arbiter.v (50108 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_burst_gen.v (63619 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_cmd_gen.v (129075 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_csr.v (53869 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_buffer.v (4779 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_buffer_manager.v (8991 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_burst_tracking.v (4707 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_dataid_manager.v (38461 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_fifo.v (8340 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_list.v (8613 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rdata_path.v (52236 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_wdata_path.v (51006 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_define.iv (2237 bytes VERILOG_INCLUDE)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder.v (14578 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v (33133 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v (59416 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder.v (10820 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v (14064 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v (22231 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v (50041 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v (58946 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_input_if.v (10915 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_rank_timer.v (116066 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_sideband.v (58617 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_tbp.v (176124 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_timing_param.v (67437 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_controller.v (172825 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_controller_st_top.v (93779 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv (28323 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/alt_mem_ddrx_mm_st_converter.v (7006 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_mem_if_oct_stratixiv.sv (3483 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_mem_if_dll_stratixiv.sv (2816 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_button.v (1915 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router.sv (6484 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_001.sv (7035 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router.sv (6036 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_002.sv (5967 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_003.sv (5980 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_addr_router_002.sv (7435 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_id_router_004.sv (5967 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_traffic_limiter.sv (12802 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux.sv (4112 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_001.sv (5390 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_mux.sv (10422 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux.sv (4106 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux_002.sv (3482 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux.sv (11235 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux_001.sv (12855 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_cmd_xbar_demux_002.sv (6660 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_demux_004.sv (3482 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_rsp_xbar_mux_002.sv (14467 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_width_adapter.sv (35859 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v (7493 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_st_clock_crosser.v (4900 bytes VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/TR4_QSYS_irq_mapper.sv (1825 bytes SYSTEM_VERILOG)
D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_irq_clock_crosser.sv (1651 bytes SYSTEM_VERILOG)
Instantiations
TR4_QSYS
TR4_QSYS v1.0		 TR4_QSYS_cpu as cpu
TR4_QSYS_sysid as sysid
TR4_QSYS_jtag_uart as jtag_uart
TR4_QSYS_onchip_mem as onchip_mem
altera_avalon_mm_clock_crossing_bridge as clock_crossing_bridge
TR4_QSYS_timer as timer
TR4_QSYS_ddr3_i2c_scl as ddr3_i2c_scl
TR4_QSYS_ddr3_i2c_sda as ddr3_i2c_sda
TR4_QSYS_uniphy_ddr3 as uniphy_ddr3
TR4_QSYS_button as button
altera_merlin_master_translator as cpu_instruction_master_translator, cpu_data_master_translator, clock_crossing_bridge_m0_translator
altera_merlin_slave_translator as cpu_jtag_debug_module_translator, onchip_mem_s1_translator, clock_crossing_bridge_s0_translator, uniphy_ddr3_avl_translator, timer_s1_translator, ddr3_i2c_scl_s1_translator, ddr3_i2c_sda_s1_translator, sysid_control_slave_translator, jtag_uart_avalon_jtag_slave_translator, button_s1_translator
altera_merlin_slave_agent as clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent, onchip_mem_s1_translator_avalon_universal_slave_0_agent, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent, ddr3_i2c_sda_s1_translator_avalon_universal_slave_0_agent, sysid_control_slave_translator_avalon_universal_slave_0_agent, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent, ddr3_i2c_scl_s1_translator_avalon_universal_slave_0_agent, timer_s1_translator_avalon_universal_slave_0_agent, button_s1_translator_avalon_universal_slave_0_agent
altera_avalon_sc_fifo as clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rsp_fifo, uniphy_ddr3_avl_translator_avalon_universal_slave_0_agent_rdata_fifo, onchip_mem_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo, ddr3_i2c_sda_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, ddr3_i2c_scl_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, button_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
altera_merlin_master_agent as cpu_data_master_translator_avalon_universal_master_0_agent, cpu_instruction_master_translator_avalon_universal_master_0_agent, clock_crossing_bridge_m0_translator_avalon_universal_master_0_agent
TR4_QSYS_addr_router as addr_router
TR4_QSYS_addr_router_001 as addr_router_001
TR4_QSYS_id_router as id_router, id_router_001
TR4_QSYS_id_router_002 as id_router_002
TR4_QSYS_id_router_003 as id_router_003
TR4_QSYS_addr_router_002 as addr_router_002
TR4_QSYS_id_router_004 as id_router_004, id_router_005, id_router_006, id_router_007, id_router_008, id_router_009
altera_merlin_traffic_limiter as limiter, limiter_001, limiter_002
altera_reset_controller as rst_controller, rst_controller_001, rst_controller_002
TR4_QSYS_cmd_xbar_demux as cmd_xbar_demux
TR4_QSYS_cmd_xbar_demux_001 as cmd_xbar_demux_001
TR4_QSYS_cmd_xbar_mux as cmd_xbar_mux, cmd_xbar_mux_001
TR4_QSYS_rsp_xbar_demux as rsp_xbar_demux, rsp_xbar_demux_001
TR4_QSYS_rsp_xbar_demux_002 as rsp_xbar_demux_002, rsp_xbar_demux_003
TR4_QSYS_rsp_xbar_mux as rsp_xbar_mux
TR4_QSYS_rsp_xbar_mux_001 as rsp_xbar_mux_001
TR4_QSYS_cmd_xbar_demux_002 as cmd_xbar_demux_002
TR4_QSYS_rsp_xbar_demux_004 as rsp_xbar_demux_004, rsp_xbar_demux_005, rsp_xbar_demux_006, rsp_xbar_demux_007, rsp_xbar_demux_008, rsp_xbar_demux_009
TR4_QSYS_rsp_xbar_mux_002 as rsp_xbar_mux_002
altera_merlin_width_adapter as width_adapter, width_adapter_001
altera_avalon_st_handshake_clock_crosser as crosser, crosser_001
TR4_QSYS_irq_mapper as irq_mapper
altera_irq_clock_crosser as irq_synchronizer, irq_synchronizer_001
TR4_QSYS_cpu
altera_nios2_qsys v11.1
TR4_QSYS_sysid
altera_avalon_sysid_qsys v11.1
TR4_QSYS_jtag_uart
altera_avalon_jtag_uart v11.1
TR4_QSYS_onchip_mem
altera_avalon_onchip_memory2 v11.1
altera_avalon_mm_clock_crossing_bridge
altera_avalon_mm_clock_crossing_bridge v11.1
TR4_QSYS_timer
altera_avalon_timer v11.1
TR4_QSYS_ddr3_i2c_scl
altera_avalon_pio v11.1
TR4_QSYS_ddr3_i2c_sda
altera_avalon_pio v11.1
TR4_QSYS_uniphy_ddr3
altera_mem_if_ddr3_emif v11.1		 TR4_QSYS_uniphy_ddr3_pll0 as pll0
TR4_QSYS_uniphy_ddr3_p0 as p0
afi_mux_ddr3_ddrx as m0
TR4_QSYS_uniphy_ddr3_s0 as s0
TR4_QSYS_uniphy_ddr3_c0 as c0
altera_mem_if_oct_stratixiv as oct0
altera_mem_if_dll_stratixiv as dll0
TR4_QSYS_button
altera_avalon_pio v11.1
altera_merlin_master_translator
altera_merlin_master_translator v11.1
altera_merlin_slave_translator
altera_merlin_slave_translator v11.1
altera_merlin_slave_agent
altera_merlin_slave_agent v11.1
altera_avalon_sc_fifo
altera_avalon_sc_fifo v11.1
altera_merlin_master_agent
altera_merlin_master_agent v11.1
TR4_QSYS_addr_router
altera_merlin_router v11.1
TR4_QSYS_addr_router_001
altera_merlin_router v11.1
TR4_QSYS_id_router
altera_merlin_router v11.1
TR4_QSYS_id_router_002
altera_merlin_router v11.1
TR4_QSYS_id_router_003
altera_merlin_router v11.1
TR4_QSYS_addr_router_002
altera_merlin_router v11.1
TR4_QSYS_id_router_004
altera_merlin_router v11.1
altera_merlin_traffic_limiter
altera_merlin_traffic_limiter v11.1
altera_reset_controller
altera_reset_controller v11.1
TR4_QSYS_cmd_xbar_demux
altera_merlin_demultiplexer v11.1
TR4_QSYS_cmd_xbar_demux_001
altera_merlin_demultiplexer v11.1
TR4_QSYS_cmd_xbar_mux
altera_merlin_multiplexer v11.1
TR4_QSYS_rsp_xbar_demux
altera_merlin_demultiplexer v11.1
TR4_QSYS_rsp_xbar_demux_002
altera_merlin_demultiplexer v11.1
TR4_QSYS_rsp_xbar_mux
altera_merlin_multiplexer v11.1
TR4_QSYS_rsp_xbar_mux_001
altera_merlin_multiplexer v11.1
TR4_QSYS_cmd_xbar_demux_002
altera_merlin_demultiplexer v11.1
TR4_QSYS_rsp_xbar_demux_004
altera_merlin_demultiplexer v11.1
TR4_QSYS_rsp_xbar_mux_002
altera_merlin_multiplexer v11.1
altera_merlin_width_adapter
altera_merlin_width_adapter v11.1
altera_avalon_st_handshake_clock_crosser
altera_avalon_st_handshake_clock_crosser v11.1
TR4_QSYS_irq_mapper
altera_irq_mapper v11.1
altera_irq_clock_crosser
altera_irq_clock_crosser v11.1
TR4_QSYS_uniphy_ddr3_pll0
altera_mem_if_ddr3_pll_dll_oct v11.1
TR4_QSYS_uniphy_ddr3_p0
altera_mem_if_ddr3_phy_core v11.1
afi_mux_ddr3_ddrx
altera_mem_if_ddr3_afi_mux v11.1
TR4_QSYS_uniphy_ddr3_s0
altera_mem_if_ddr3_qsys_sequencer v11.1
TR4_QSYS_uniphy_ddr3_c0
altera_mem_if_nextgen_ddr3_controller v11.1		 alt_mem_if_nextgen_ddr3_controller_core as ng0
alt_mem_ddrx_mm_st_converter as a0
altera_mem_if_oct_stratixiv
altera_mem_if_oct v11.1
altera_mem_if_dll_stratixiv
altera_mem_if_dll v11.1
alt_mem_if_nextgen_ddr3_controller_core
altera_mem_if_nextgen_ddr3_controller_core v11.1
alt_mem_ddrx_mm_st_converter
alt_mem_ddrx_mm_st_converter v11.1
Generation Messages
2012.03.07.15:09:21 [Debug] TR4_QSYS.altera_nios2_qsys: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:11 [Info] TR4_QSYS.cpu: CPUID control register value is 0. Please manually assign CPUID if creating multiple Nios II system 2012.03.07.15:17:21 [Debug] TR4_QSYS.cpu: Timing: VAL:1/0.062s ELA:1/0.016s 2012.03.07.15:17:16 [Info] TR4_QSYS.sysid: System ID will no longer be automatically assigned. 2012.03.07.15:17:16 [Info] TR4_QSYS.sysid: Time stamp will be automatically updated when this component is generated. 2012.03.07.15:17:21 [Debug] TR4_QSYS.sysid: Timing: VAL:2/0.000s/0.000s 2012.03.07.15:17:21 [Info] TR4_QSYS.onchip_mem: Memory will be initialized from onchip_mem.hex 2012.03.07.15:17:21 [Debug] TR4_QSYS.clock_crossing_bridge: Timing: ELA:1/0.000s 2012.03.07.15:17:21 [Info] TR4_QSYS.ddr3_i2c_sda: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2012.03.07.15:17:19 [Info] TR4_QSYS.uniphy_ddr3: Auto interface leveling mode set to 'Leveling' 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.pll_ref_clk: Timing: ELA:1/0.000s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.global_reset: Timing: ELA:4/0.000s/0.000s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.soft_reset: Timing: ELA:4/0.000s/0.000s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.afi_clk: Timing: ELA:8/0.000s/0.000s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.afi_half_clk: Timing: ELA:8/0.002s/0.016s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.afi_reset: Timing: ELA:4/0.000s/0.000s 2012.03.07.15:09:31 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_pll_dll_oct: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.pll0: Timing: VAL:4/0.262s/0.313s ELA:4/0.000s/0.000s 2012.03.07.15:09:32 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_phy_core: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.p0: Timing: VAL:4/0.281s/0.297s ELA:4/0.011s/0.016s 2012.03.07.15:09:33 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_afi_mux: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.m0: Timing: VAL:4/0.031s/0.032s ELA:4/0.007s/0.016s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.as0: Timing: VAL:4/0.027s/0.032s ELA:4/0.003s/0.015s 2012.03.07.15:09:34 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_ddr3_qsys_sequencer: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.s0: Timing: VAL:4/0.246s/0.281s ELA:4/0.016s/0.016s 2012.03.07.15:09:37 [Debug] TR4_QSYS.uniphy_ddr3.c0.altera_mem_if_nextgen_ddr3_controller_core: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.c0.ng0: Timing: VAL:4/0.078s/0.094s ELA:4/0.015s/0.016s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_reset: Timing: ELA:4/0.000s/0.000s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_clk: Timing: ELA:1/0.000s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.c0.afi_half_clk: Timing: ELA:1/0.000s 2012.03.07.15:09:37 [Debug] TR4_QSYS.uniphy_ddr3.c0.alt_mem_ddrx_mm_st_converter: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.c0.a0: Timing: VAL:4/0.000s/0.000s ELA:4/0.007s/0.016s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.c0: Timing: VAL:4/0.070s/0.078s COM:4/0.183s/0.203s 2012.03.07.15:09:37 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_oct: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.oct0: Timing: VAL:4/0.000s/0.000s ELA:4/0.000s/0.000s 2012.03.07.15:09:37 [Debug] TR4_QSYS.uniphy_ddr3.altera_mem_if_dll: When a generate simulation callback is defined a synthesis generation callback should also be defined 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3.dll0: Timing: VAL:4/0.000s/0.000s ELA:4/0.000s/0.000s 2012.03.07.15:17:21 [Debug] TR4_QSYS.uniphy_ddr3: Timing: VAL:4/0.371s/0.406s COM:4/1.929s/2.000s 2012.03.07.15:17:21 [Info] TR4_QSYS.button: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2012.03.07.15:17:21 [Info] TR4_QSYS: Generating TR4_QSYS "TR4_QSYS" for QUARTUS_SYNTH 2012.03.07.15:17:21 [Debug] TR4_QSYS: queue size: 0 starting:TR4_QSYS "TR4_QSYS" 2012.03.07.15:17:24 [Debug] Transform: PipelineBridgeSwap 2012.03.07.15:17:24 [Info] pipeline_bridge_swap_transform: After transform: 11 modules, 37 connections 2012.03.07.15:17:24 [Debug] Transform: ClockCrossingBridgeSwap 2012.03.07.15:17:24 [Debug] Transform: QsysBetaIPSwap 2012.03.07.15:17:24 [Debug] Transform: CustomInstructionTransform 2012.03.07.15:17:24 [Info] No custom instruction connections, skipping transform 2012.03.07.15:17:24 [Debug] Transform: TristateConduitUpgradeTransform 2012.03.07.15:17:27 [Debug] Transform: TranslatorTransform 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Info] merlin_translator_transform: After transform: 24 modules, 76 connections 2012.03.07.15:17:27 [Debug] Transform: DomainTransform 2012.03.07.15:17:27 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 2012.03.07.15:17:27 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:27 [Progress] min: 0 2012.03.07.15:17:27 [Progress] max: 1 2012.03.07.15:17:27 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_jtag_debug_module_translator.avalon_anti_slave_0 and cpu.jtag_debug_module 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces onchip_mem_s1_translator.avalon_anti_slave_0 and onchip_mem.s1 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_bridge_s0_translator.avalon_anti_slave_0 and clock_crossing_bridge.s0 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces uniphy_ddr3_avl_translator.avalon_anti_slave_0 and uniphy_ddr3.avl 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces clock_crossing_bridge.m0 and clock_crossing_bridge_m0_translator.avalon_anti_master_0 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces timer_s1_translator.avalon_anti_slave_0 and timer.s1 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces ddr3_i2c_scl_s1_translator.avalon_anti_slave_0 and ddr3_i2c_scl.s1 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces ddr3_i2c_sda_s1_translator.avalon_anti_slave_0 and ddr3_i2c_sda.s1 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave 2012.03.07.15:17:28 [Debug] Transform merlin_domain_transform not run on matched interfaces button_s1_translator.avalon_anti_slave_0 and button.s1 2012.03.07.15:17:28 [Info] merlin_domain_transform: After transform: 50 modules, 208 connections 2012.03.07.15:17:28 [Debug] Transform: RouterTransform 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Info] merlin_router_transform: After transform: 63 modules, 247 connections 2012.03.07.15:17:28 [Debug] Transform: TrafficLimiterTransform 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Info] merlin_traffic_limiter_transform: After transform: 66 modules, 259 connections 2012.03.07.15:17:28 [Debug] Transform: BurstTransform 2012.03.07.15:17:28 [Debug] Transform: ResetAdaptation 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Info] reset_adaptation_transform: After transform: 69 modules, 265 connections 2012.03.07.15:17:28 [Debug] Transform: NetworkToSwitchTransform 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:28 [Progress] min: 0 2012.03.07.15:17:28 [Progress] max: 1 2012.03.07.15:17:28 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Info] merlin_network_to_switch_transform: After transform: 93 modules, 315 connections 2012.03.07.15:17:29 [Debug] Transform: WidthTransform 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Info] merlin_width_transform: After transform: 95 modules, 321 connections 2012.03.07.15:17:29 [Debug] Transform: RouterTableTransform 2012.03.07.15:17:29 [Debug] Transform: ClockCrossingTransform 2012.03.07.15:17:29 [Info] Inserting clock-crossing logic between cmd_xbar_demux_001.src3 and cmd_xbar_mux_003.sink0 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Info] Inserting clock-crossing logic between rsp_xbar_demux_003.src0 and rsp_xbar_mux_001.sink3 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Info] com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform: After transform: 97 modules, 331 connections 2012.03.07.15:17:29 [Debug] Transform: PipelineTransform 2012.03.07.15:17:29 [Debug] Transform: TrafficLimiterUpdateTransform 2012.03.07.15:17:29 [Info] limiter_update_transform: After transform: 97 modules, 334 connections 2012.03.07.15:17:29 [Debug] Transform: InterruptMapperTransform 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Info] merlin_interrupt_mapper_transform: After transform: 98 modules, 337 connections 2012.03.07.15:17:29 [Debug] Transform: InterruptSyncTransform 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Progress] min: 0 2012.03.07.15:17:29 [Progress] max: 1 2012.03.07.15:17:29 [Progress] current: 1 2012.03.07.15:17:29 [Info] merlin_interrupt_sync_transform: After transform: 100 modules, 347 connections 2012.03.07.15:17:29 [Debug] Transform: InterruptFanoutTransform 2012.03.07.15:17:32 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:dataavailable (dataavailable)" 2012.03.07.15:17:32 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:readyfordata (readyfordata)" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_nios2_qsys "submodules/TR4_QSYS_cpu" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sysid_qsys "submodules/TR4_QSYS_sysid" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_jtag_uart "submodules/TR4_QSYS_jtag_uart" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_onchip_memory2 "submodules/TR4_QSYS_onchip_mem" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_timer "submodules/TR4_QSYS_timer" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_scl" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_sda" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_pio "submodules/TR4_QSYS_button" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_001" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_addr_router_002" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_router "submodules/TR4_QSYS_id_router_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_reset_controller "submodules/altera_reset_controller" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_001" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_002" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_002" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_001" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_004" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_002" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_irq_mapper "submodules/TR4_QSYS_irq_mapper" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2012.03.07.15:17:33 [Debug] TR4_QSYS: "TR4_QSYS" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2012.03.07.15:17:33 [Debug] TR4_QSYS: queue size: 90 starting:altera_nios2_qsys "submodules/TR4_QSYS_cpu" 2012.03.07.15:17:34 [Info] cpu: Starting RTL generation for module 'TR4_QSYS_cpu' 2012.03.07.15:17:34 [Info] cpu: Generation command is [exec C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/11.1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/11.1/quartus/sopc_builder/bin/europa -I C:/altera/11.1/quartus/sopc_builder/bin/perl_lib -I C:/altera/11.1/quartus/sopc_builder/bin -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=TR4_QSYS_cpu --dir=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0001_cpu_gen/ --quartus_dir=C:/altera/11.1/quartus --verilog --config=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0001_cpu_gen//TR4_QSYS_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:35 (*) Starting Nios II generation 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:35 (*) Checking for encrypted license (non-evaluation). 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:42 (*) Encrypted license found. SOF will not be time-limited. 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:42 (*) Elaborating CPU configuration settings 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:42 (*) Creating all objects for CPU 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:42 (*) Testbench 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:43 (*) Instruction decoding 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:43 (*) Instruction fields 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:43 (*) Instruction decodes 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:44 (*) Signals for RTL simulation waveforms 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:44 (*) Instruction controls 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:44 (*) Pipeline frontend 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:44 (*) Pipeline backend 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:49 (*) Generating RTL from CPU objects 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:53 (*) Creating encrypted RTL 2012.03.07.15:17:55 [Info] cpu: # 2012.03.07 15:17:55 (*) Done Nios II generation 2012.03.07.15:17:55 [Info] cpu: Done RTL generation for module 'TR4_QSYS_cpu' 2012.03.07.15:17:55 [Info] cpu: "TR4_QSYS" instantiated altera_nios2_qsys "cpu" 2012.03.07.15:17:55 [Debug] TR4_QSYS: queue size: 89 starting:altera_avalon_sysid_qsys "submodules/TR4_QSYS_sysid" 2012.03.07.15:17:55 [Info] sysid: "TR4_QSYS" instantiated altera_avalon_sysid_qsys "sysid" 2012.03.07.15:17:55 [Debug] TR4_QSYS: queue size: 88 starting:altera_avalon_jtag_uart "submodules/TR4_QSYS_jtag_uart" 2012.03.07.15:17:55 [Info] Starting classic module elaboration. 2012.03.07.15:18:04 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0003_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:07 [Info] Finished elaborating classic module. 2012.03.07.15:18:07 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0003_sopclgen/yysystem.ptf 2012.03.07.15:18:07 [Info] Running sopc_builder... 2012.03.07.15:18:09 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0003_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:11 [Progress] No .sopc_builder configuration file(!) 2012.03.07.15:18:11 [Progress] . 2012.03.07.15:18:13 [Progress] # 2012.03.07 15:18:13 (*) Success: sopc_builder finished. 2012.03.07.15:18:13 [Info] jtag_uart: "TR4_QSYS" instantiated altera_avalon_jtag_uart "jtag_uart" 2012.03.07.15:18:13 [Debug] TR4_QSYS: queue size: 87 starting:altera_avalon_onchip_memory2 "submodules/TR4_QSYS_onchip_mem" 2012.03.07.15:18:13 [Info] Starting classic module elaboration. 2012.03.07.15:18:15 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0004_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:17 [Info] Finished elaborating classic module. 2012.03.07.15:18:17 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0004_sopclgen/yysystem.ptf 2012.03.07.15:18:17 [Info] Running sopc_builder... 2012.03.07.15:18:20 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0004_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:22 [Progress] No .sopc_builder configuration file(!) 2012.03.07.15:18:22 [Progress] . 2012.03.07.15:18:25 [Progress] # 2012.03.07 15:18:25 (*) Success: sopc_builder finished. 2012.03.07.15:18:25 [Info] onchip_mem: "TR4_QSYS" instantiated altera_avalon_onchip_memory2 "onchip_mem" 2012.03.07.15:18:25 [Debug] TR4_QSYS: queue size: 86 starting:altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" 2012.03.07.15:18:25 [Info] clock_crossing_bridge: "TR4_QSYS" instantiated altera_avalon_mm_clock_crossing_bridge "clock_crossing_bridge" 2012.03.07.15:18:25 [Debug] TR4_QSYS: queue size: 85 starting:altera_avalon_timer "submodules/TR4_QSYS_timer" 2012.03.07.15:18:25 [Info] Starting classic module elaboration. 2012.03.07.15:18:28 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0005_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:30 [Info] Finished elaborating classic module. 2012.03.07.15:18:30 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0005_sopclgen/yysystem.ptf 2012.03.07.15:18:30 [Info] Running sopc_builder... 2012.03.07.15:18:31 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0005_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:33 [Progress] No .sopc_builder configuration file(!) 2012.03.07.15:18:33 [Progress] . 2012.03.07.15:18:35 [Progress] # 2012.03.07 15:18:35 (*) Success: sopc_builder finished. 2012.03.07.15:18:36 [Info] timer: "TR4_QSYS" instantiated altera_avalon_timer "timer" 2012.03.07.15:18:36 [Debug] TR4_QSYS: queue size: 84 starting:altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_scl" 2012.03.07.15:18:36 [Info] Starting classic module elaboration. 2012.03.07.15:18:37 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0006_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:39 [Info] Finished elaborating classic module. 2012.03.07.15:18:39 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0006_sopclgen/yysystem.ptf 2012.03.07.15:18:39 [Info] Running sopc_builder... 2012.03.07.15:18:41 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0006_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:43 [Progress] No .sopc_builder configuration file(!) 2012.03.07.15:18:43 [Progress] . 2012.03.07.15:18:45 [Progress] # 2012.03.07 15:18:44 (*) Success: sopc_builder finished. 2012.03.07.15:18:45 [Info] ddr3_i2c_scl: "TR4_QSYS" instantiated altera_avalon_pio "ddr3_i2c_scl" 2012.03.07.15:18:45 [Debug] TR4_QSYS: queue size: 83 starting:altera_avalon_pio "submodules/TR4_QSYS_ddr3_i2c_sda" 2012.03.07.15:18:45 [Info] Starting classic module elaboration. 2012.03.07.15:18:47 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0007_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:49 [Info] Finished elaborating classic module. 2012.03.07.15:18:49 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0007_sopclgen/yysystem.ptf 2012.03.07.15:18:49 [Info] Running sopc_builder... 2012.03.07.15:18:51 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0007_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:18:53 [Progress] No .sopc_builder configuration file(!) 2012.03.07.15:18:53 [Progress] . 2012.03.07.15:18:54 [Progress] # 2012.03.07 15:18:54 (*) Success: sopc_builder finished. 2012.03.07.15:18:55 [Info] ddr3_i2c_sda: "TR4_QSYS" instantiated altera_avalon_pio "ddr3_i2c_sda" 2012.03.07.15:18:55 [Debug] TR4_QSYS: queue size: 82 starting:altera_mem_if_ddr3_emif "submodules/TR4_QSYS_uniphy_ddr3" 2012.03.07.15:18:55 [Info] uniphy_ddr3: Running transform AvalonTransform 2012.03.07.15:18:56 [Debug] Transform: PipelineBridgeSwap 2012.03.07.15:18:56 [Info] pipeline_bridge_swap_transform: After transform: 14 modules, 33 connections 2012.03.07.15:18:56 [Debug] Transform: ClockCrossingBridgeSwap 2012.03.07.15:18:56 [Debug] Transform: QsysBetaIPSwap 2012.03.07.15:18:56 [Debug] Transform: CustomInstructionTransform 2012.03.07.15:18:56 [Info] No custom instruction connections, skipping transform 2012.03.07.15:18:56 [Debug] Transform: TristateConduitUpgradeTransform 2012.03.07.15:18:58 [Debug] Transform: TranslatorTransform 2012.03.07.15:18:58 [Info] No Avalon connections, skipping transform 2012.03.07.15:18:58 [Debug] Transform: DomainTransform 2012.03.07.15:18:58 [Debug] Transform: RouterTransform 2012.03.07.15:18:58 [Debug] Transform: TrafficLimiterTransform 2012.03.07.15:18:58 [Debug] Transform: BurstTransform 2012.03.07.15:18:58 [Debug] Transform: ResetAdaptation 2012.03.07.15:18:58 [Debug] Transform: NetworkToSwitchTransform 2012.03.07.15:18:58 [Debug] Transform: WidthTransform 2012.03.07.15:18:58 [Debug] Transform: RouterTableTransform 2012.03.07.15:18:58 [Debug] Transform: ClockCrossingTransform 2012.03.07.15:18:58 [Debug] Transform: TrafficLimiterUpdateTransform 2012.03.07.15:18:58 [Debug] Transform: InterruptMapperTransform 2012.03.07.15:18:58 [Debug] Transform: InterruptSyncTransform 2012.03.07.15:18:58 [Debug] Transform: InterruptFanoutTransform 2012.03.07.15:18:58 [Info] uniphy_ddr3: Running transform AvalonTransform took 2.922s 2012.03.07.15:18:58 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_pll_dll_oct "submodules/TR4_QSYS_uniphy_ddr3_pll0" 2012.03.07.15:18:58 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_phy_core "submodules/TR4_QSYS_uniphy_ddr3_p0" 2012.03.07.15:18:58 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx" 2012.03.07.15:18:58 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_ddr3_qsys_sequencer "submodules/TR4_QSYS_uniphy_ddr3_s0" 2012.03.07.15:18:58 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2012.03.07.15:18:58 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_oct "submodules/altera_mem_if_oct_stratixiv" 2012.03.07.15:18:58 [Debug] uniphy_ddr3: "uniphy_ddr3" reuses altera_mem_if_dll "submodules/altera_mem_if_dll_stratixiv" 2012.03.07.15:18:58 [Info] uniphy_ddr3: "TR4_QSYS" instantiated altera_mem_if_ddr3_emif "uniphy_ddr3" 2012.03.07.15:18:58 [Debug] TR4_QSYS: queue size: 88 starting:altera_avalon_pio "submodules/TR4_QSYS_button" 2012.03.07.15:18:58 [Info] Starting classic module elaboration. 2012.03.07.15:19:00 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0008_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:19:02 [Info] Finished elaborating classic module. 2012.03.07.15:19:02 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0008_sopclgen/yysystem.ptf 2012.03.07.15:19:02 [Info] Running sopc_builder... 2012.03.07.15:19:04 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0008_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5406_3923719583446690837.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2012.03.07.15:19:06 [Progress] No .sopc_builder configuration file(!) 2012.03.07.15:19:06 [Progress] . 2012.03.07.15:19:07 [Progress] # 2012.03.07 15:19:07 (*) Success: sopc_builder finished. 2012.03.07.15:19:07 [Info] button: "TR4_QSYS" instantiated altera_avalon_pio "button" 2012.03.07.15:19:07 [Debug] TR4_QSYS: queue size: 87 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2012.03.07.15:19:07 [Info] cpu_instruction_master_translator: "TR4_QSYS" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" 2012.03.07.15:19:07 [Debug] TR4_QSYS: queue size: 85 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2012.03.07.15:19:07 [Info] cpu_jtag_debug_module_translator: "TR4_QSYS" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" 2012.03.07.15:19:07 [Debug] TR4_QSYS: queue size: 74 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2012.03.07.15:19:07 [Info] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent: "TR4_QSYS" instantiated altera_merlin_slave_agent "clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent" 2012.03.07.15:19:07 [Debug] TR4_QSYS: queue size: 73 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2012.03.07.15:19:07 [Info] clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo: "TR4_QSYS" instantiated altera_avalon_sc_fifo "clock_crossing_bridge_s0_translator_avalon_universal_slave_0_agent_rsp_fifo" 2012.03.07.15:19:07 [Debug] TR4_QSYS: queue size: 72 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2012.03.07.15:19:07 [Info] cpu_data_master_translator_avalon_universal_master_0_agent: "TR4_QSYS" instantiated altera_merlin_master_agent "cpu_data_master_translator_avalon_universal_master_0_agent" 2012.03.07.15:19:07 [Debug] TR4_QSYS: queue size: 50 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router" 2012.03.07.15:19:08 [Info] addr_router: "TR4_QSYS" instantiated altera_merlin_router "addr_router" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 49 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_001" 2012.03.07.15:19:08 [Info] addr_router_001: "TR4_QSYS" instantiated altera_merlin_router "addr_router_001" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 48 starting:altera_merlin_router "submodules/TR4_QSYS_id_router" 2012.03.07.15:19:08 [Info] id_router: "TR4_QSYS" instantiated altera_merlin_router "id_router" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 46 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_002" 2012.03.07.15:19:08 [Info] id_router_002: "TR4_QSYS" instantiated altera_merlin_router "id_router_002" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 45 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_003" 2012.03.07.15:19:08 [Info] id_router_003: "TR4_QSYS" instantiated altera_merlin_router "id_router_003" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 44 starting:altera_merlin_router "submodules/TR4_QSYS_addr_router_002" 2012.03.07.15:19:08 [Info] addr_router_002: "TR4_QSYS" instantiated altera_merlin_router "addr_router_002" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 43 starting:altera_merlin_router "submodules/TR4_QSYS_id_router_004" 2012.03.07.15:19:08 [Info] id_router_004: "TR4_QSYS" instantiated altera_merlin_router "id_router_004" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 37 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2012.03.07.15:19:08 [Info] limiter: "TR4_QSYS" instantiated altera_merlin_traffic_limiter "limiter" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 34 starting:altera_reset_controller "submodules/altera_reset_controller" 2012.03.07.15:19:08 [Info] rst_controller: "TR4_QSYS" instantiated altera_reset_controller "rst_controller" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 31 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux" 2012.03.07.15:19:08 [Info] cmd_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 30 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_001" 2012.03.07.15:19:08 [Info] cmd_xbar_demux_001: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 29 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_cmd_xbar_mux" 2012.03.07.15:19:08 [Info] cmd_xbar_mux: "TR4_QSYS" instantiated altera_merlin_multiplexer "cmd_xbar_mux" 2012.03.07.15:19:08 [Debug] TR4_QSYS: queue size: 27 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux" 2012.03.07.15:19:09 [Info] rsp_xbar_demux: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 25 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_002" 2012.03.07.15:19:09 [Info] rsp_xbar_demux_002: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 23 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux" 2012.03.07.15:19:09 [Info] rsp_xbar_mux: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux" 2012.03.07.15:19:09 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 22 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_001" 2012.03.07.15:19:09 [Info] rsp_xbar_mux_001: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" 2012.03.07.15:19:09 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 21 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_cmd_xbar_demux_002" 2012.03.07.15:19:09 [Info] cmd_xbar_demux_002: "TR4_QSYS" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_002" 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 20 starting:altera_merlin_demultiplexer "submodules/TR4_QSYS_rsp_xbar_demux_004" 2012.03.07.15:19:09 [Info] rsp_xbar_demux_004: "TR4_QSYS" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_004" 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 14 starting:altera_merlin_multiplexer "submodules/TR4_QSYS_rsp_xbar_mux_002" 2012.03.07.15:19:09 [Info] rsp_xbar_mux_002: "TR4_QSYS" instantiated altera_merlin_multiplexer "rsp_xbar_mux_002" 2012.03.07.15:19:09 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 13 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2012.03.07.15:19:09 [Info] width_adapter: "TR4_QSYS" instantiated altera_merlin_width_adapter "width_adapter" 2012.03.07.15:19:09 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 11 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2012.03.07.15:19:09 [Info] crosser: "TR4_QSYS" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2012.03.07.15:19:09 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_st_pipeline_base.v 2012.03.07.15:19:09 [Debug] TR4_QSYS: queue size: 9 starting:altera_irq_mapper "submodules/TR4_QSYS_irq_mapper" 2012.03.07.15:19:09 [Info] irq_mapper: "TR4_QSYS" instantiated altera_irq_mapper "irq_mapper" 2012.03.07.15:19:10 [Debug] TR4_QSYS: queue size: 8 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2012.03.07.15:19:10 [Info] irq_synchronizer: "TR4_QSYS" instantiated altera_irq_clock_crosser "irq_synchronizer" 2012.03.07.15:19:10 [Debug] TR4_QSYS: queue size: 6 starting:altera_mem_if_ddr3_pll_dll_oct "submodules/TR4_QSYS_uniphy_ddr3_pll0" 2012.03.07.15:19:11 [Info] pll0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_pll_dll_oct "pll0" 2012.03.07.15:19:11 [Debug] TR4_QSYS: queue size: 5 starting:altera_mem_if_ddr3_phy_core "submodules/TR4_QSYS_uniphy_ddr3_p0" 2012.03.07.15:19:11 [Info] p0: Generating clock pair generator 2012.03.07.15:19:24 [Info] p0: Generating TR4_QSYS_uniphy_ddr3_p0_altdqdqs 2012.03.07.15:19:34 [Info] p0: 2012.03.07.15:19:34 [Info] p0: ***************************** 2012.03.07.15:19:34 [Info] p0: 2012.03.07.15:19:34 [Info] p0: Remember to run the TR4_QSYS_uniphy_ddr3_p0_pin_assignments.tcl 2012.03.07.15:19:34 [Info] p0: script after running Synthesis and before Fitting. 2012.03.07.15:19:34 [Info] p0: 2012.03.07.15:19:34 [Info] p0: ***************************** 2012.03.07.15:19:34 [Info] p0: 2012.03.07.15:19:35 [Info] p0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_phy_core "p0" 2012.03.07.15:19:35 [Debug] TR4_QSYS: queue size: 4 starting:altera_mem_if_ddr3_afi_mux "submodules/afi_mux_ddr3_ddrx" 2012.03.07.15:19:35 [Info] m0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_afi_mux "m0" 2012.03.07.15:19:35 [Debug] TR4_QSYS: queue size: 3 starting:altera_mem_if_ddr3_qsys_sequencer "submodules/TR4_QSYS_uniphy_ddr3_s0" 2012.03.07.15:19:35 [Info] s0: Determining sequencer memory size 2012.03.07.15:21:07 [Info] s0: Generating Qsys sequencer system 2012.03.07.15:21:17 [Info] s0: QSYS sequencer system generated successfully 2012.03.07.15:21:19 [Info] s0: Building sequencer software 2012.03.07.15:21:39 [Info] s0: "uniphy_ddr3" instantiated altera_mem_if_ddr3_qsys_sequencer "s0" 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_avalon_sc_fifo.v 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_arbitrator.sv 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_master_agent.sv 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_master_translator.sv 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_slave_agent.sv 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_merlin_slave_translator.sv 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_reset_controller.sdc 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_reset_controller.v 2012.03.07.15:21:39 [Info] Reusing file D:/MYSVN/tr4/cd/demonstrations/tr4_230/TR4_DDR3_UniPHY_1G_QSYS/TR4_QSYS/synthesis/submodules/altera_reset_synchronizer.v 2012.03.07.15:21:39 [Debug] TR4_QSYS: queue size: 2 starting:altera_mem_if_nextgen_ddr3_controller "submodules/TR4_QSYS_uniphy_ddr3_c0" 2012.03.07.15:21:39 [Info] c0: Running transform AvalonTransform 2012.03.07.15:21:39 [Debug] Transform: PipelineBridgeSwap 2012.03.07.15:21:39 [Info] pipeline_bridge_swap_transform: After transform: 5 modules, 8 connections 2012.03.07.15:21:39 [Debug] Transform: ClockCrossingBridgeSwap 2012.03.07.15:21:39 [Debug] Transform: QsysBetaIPSwap 2012.03.07.15:21:39 [Debug] Transform: CustomInstructionTransform 2012.03.07.15:21:39 [Info] No custom instruction connections, skipping transform 2012.03.07.15:21:39 [Debug] Transform: TristateConduitUpgradeTransform 2012.03.07.15:21:39 [Debug] Transform: TranslatorTransform 2012.03.07.15:21:39 [Info] No Avalon connections, skipping transform 2012.03.07.15:21:39 [Debug] Transform: DomainTransform 2012.03.07.15:21:39 [Debug] Transform: RouterTransform 2012.03.07.15:21:39 [Debug] Transform: TrafficLimiterTransform 2012.03.07.15:21:39 [Debug] Transform: BurstTransform 2012.03.07.15:21:39 [Debug] Transform: ResetAdaptation 2012.03.07.15:21:39 [Debug] Transform: NetworkToSwitchTransform 2012.03.07.15:21:39 [Debug] Transform: WidthTransform 2012.03.07.15:21:39 [Debug] Transform: RouterTableTransform 2012.03.07.15:21:39 [Debug] Transform: ClockCrossingTransform 2012.03.07.15:21:39 [Debug] Transform: TrafficLimiterUpdateTransform 2012.03.07.15:21:39 [Debug] Transform: InterruptMapperTransform 2012.03.07.15:21:39 [Debug] Transform: InterruptSyncTransform 2012.03.07.15:21:39 [Debug] Transform: InterruptFanoutTransform 2012.03.07.15:21:39 [Info] c0: Running transform AvalonTransform took 0.282s 2012.03.07.15:21:39 [Debug] c0: "c0" reuses altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2012.03.07.15:21:39 [Debug] c0: "c0" reuses alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2012.03.07.15:21:39 [Info] c0: "uniphy_ddr3" instantiated altera_mem_if_nextgen_ddr3_controller "c0" 2012.03.07.15:21:39 [Debug] TR4_QSYS: queue size: 3 starting:altera_mem_if_oct "submodules/altera_mem_if_oct_stratixiv" 2012.03.07.15:21:39 [Info] oct0: "uniphy_ddr3" instantiated altera_mem_if_oct "oct0" 2012.03.07.15:21:39 [Debug] TR4_QSYS: queue size: 2 starting:altera_mem_if_dll "submodules/altera_mem_if_dll_stratixiv" 2012.03.07.15:21:39 [Info] dll0: "uniphy_ddr3" instantiated altera_mem_if_dll "dll0" 2012.03.07.15:21:39 [Debug] TR4_QSYS: queue size: 1 starting:altera_mem_if_nextgen_ddr3_controller_core "submodules/alt_mem_if_nextgen_ddr3_controller_core" 2012.03.07.15:21:39 [Info] ng0: "c0" instantiated altera_mem_if_nextgen_ddr3_controller_core "ng0" 2012.03.07.15:21:39 [Debug] TR4_QSYS: queue size: 0 starting:alt_mem_ddrx_mm_st_converter "submodules/alt_mem_ddrx_mm_st_converter" 2012.03.07.15:21:39 [Info] a0: "c0" instantiated alt_mem_ddrx_mm_st_converter "a0" 2012.03.07.15:21:39 [Info] TR4_QSYS: Done TR4_QSYS" with 48 modules, 265 files, 6373958 bytes