TR4_SOPC TR4_SOPC
1.0
2011.12.30.15:41:34 Generation Report
Output Directory D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/
Files D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/TR4_SOPC.v (331779 bytes VERILOG)

D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_onchip_memory2.hex (5505088 bytes HEX)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_onchip_memory2.v (4043 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_jtag_uart.v (23819 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_jtag_uart_input_mutex.dat (3 bytes OTHER)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_jtag_uart_input_stream.dat (10 bytes OTHER)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_jtag_uart_output_stream.dat (0 bytes OTHER)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_altpll_0.v (11061 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu.ocp (848 bytes OTHER)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu.sdc (4109 bytes SDC)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu.v (448904 bytes VERILOG_ENCRYPT)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_bht_ram.mif (2392 bytes MIF)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_dc_tag_ram.mif (920 bytes MIF)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_ic_tag_ram.mif (1881 bytes MIF)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_jtag_debug_module_sysclk.v (7033 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_jtag_debug_module_tck.v (8319 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_jtag_debug_module_wrapper.v (10163 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_mult_cell.v (3607 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_ociram_default_contents.mif (5714 bytes MIF)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_oci_test_bench.v (1468 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_rf_ram_a.mif (600 bytes MIF)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_rf_ram_b.mif (600 bytes MIF)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cpu_test_bench.v (31415 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_sysid.v (1447 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_tri_state_bridge_bridge_0.sv (5436 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_tri_state_bridge_pinSharer_0.v (4568 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_tri_state_bridge_pinSharer_0_pin_sharer.sv (4062 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_std_arbitrator_core.sv (8937 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_tri_state_bridge_pinSharer_0_arbiter.sv (2869 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cfi_flash.v (28098 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_tristate_controller_translator.sv (7099 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_slave_translator.sv (16040 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_tristate_controller_aggregator.sv (9382 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_master_translator.sv (16799 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_slave_agent.sv (19129 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_burst_uncompressor.sv (10370 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_avalon_sc_fifo.v (32228 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_master_agent.sv (8683 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_addr_router.sv (6726 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_addr_router_001.sv (7527 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_id_router.sv (6033 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_id_router_002.sv (6045 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_id_router_003.sv (5964 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_traffic_limiter.sv (12799 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_avalon_st_pipeline_base.v (4716 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_burst_adapter.sv (37061 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_reset_synchronizer.v (3561 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cmd_xbar_demux.sv (4744 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cmd_xbar_demux_001.sv (6657 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv (9460 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_cmd_xbar_mux.sv (11835 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_rsp_xbar_demux.sv (4103 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_rsp_xbar_demux_003.sv (3479 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_rsp_xbar_mux.sv (12038 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_rsp_xbar_mux_001.sv (14464 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_width_adapter.sv (35858 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v (7493 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_avalon_st_clock_crosser.v (4900 bytes VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/TR4_SOPC_irq_mapper.sv (1737 bytes SYSTEM_VERILOG)
D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_irq_clock_crosser.sv (1648 bytes SYSTEM_VERILOG)
Instantiations
TR4_SOPC
TR4_SOPC v1.0
TR4_SOPC_onchip_memory2 as onchip_memory2
TR4_SOPC_jtag_uart as jtag_uart
TR4_SOPC_altpll_0 as altpll_0
TR4_SOPC_cpu as cpu
TR4_SOPC_sysid as sysid
TR4_SOPC_tri_state_bridge_bridge_0 as tri_state_bridge_bridge_0
TR4_SOPC_tri_state_bridge_pinSharer_0 as tri_state_bridge_pinSharer_0
TR4_SOPC_cfi_flash as cfi_flash
altera_merlin_master_translator as cpu_instruction_master_translator, cpu_data_master_translator
altera_merlin_slave_translator as cpu_jtag_debug_module_translator, onchip_memory2_s1_translator, cfi_flash_uas_translator, jtag_uart_avalon_jtag_slave_translator, sysid_control_slave_translator, altpll_0_pll_slave_translator
altera_merlin_slave_agent as altpll_0_pll_slave_translator_avalon_universal_slave_0_agent, sysid_control_slave_translator_avalon_universal_slave_0_agent, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent, cfi_flash_uas_translator_avalon_universal_slave_0_agent, onchip_memory2_s1_translator_avalon_universal_slave_0_agent, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent
altera_avalon_sc_fifo as altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo, cfi_flash_uas_translator_avalon_universal_slave_0_agent_rsp_fifo, onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo, jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
altera_merlin_master_agent as cpu_data_master_translator_avalon_universal_master_0_agent, cpu_instruction_master_translator_avalon_universal_master_0_agent
TR4_SOPC_addr_router as addr_router
TR4_SOPC_addr_router_001 as addr_router_001
TR4_SOPC_id_router as id_router, id_router_001
TR4_SOPC_id_router_002 as id_router_002
TR4_SOPC_id_router_003 as id_router_003, id_router_004, id_router_005
altera_merlin_traffic_limiter as limiter, limiter_001
altera_merlin_burst_adapter as burst_adapter
altera_reset_controller as rst_controller, rst_controller_001, rst_controller_002
TR4_SOPC_cmd_xbar_demux as cmd_xbar_demux
TR4_SOPC_cmd_xbar_demux_001 as cmd_xbar_demux_001
TR4_SOPC_cmd_xbar_mux as cmd_xbar_mux, cmd_xbar_mux_001, cmd_xbar_mux_002
TR4_SOPC_rsp_xbar_demux as rsp_xbar_demux, rsp_xbar_demux_001, rsp_xbar_demux_002
TR4_SOPC_rsp_xbar_demux_003 as rsp_xbar_demux_003, rsp_xbar_demux_004, rsp_xbar_demux_005
TR4_SOPC_rsp_xbar_mux as rsp_xbar_mux
TR4_SOPC_rsp_xbar_mux_001 as rsp_xbar_mux_001
altera_merlin_width_adapter as width_adapter, width_adapter_001
altera_avalon_st_handshake_clock_crosser as crosser, crosser_001, crosser_002, crosser_003, crosser_004, crosser_005
TR4_SOPC_irq_mapper as irq_mapper
altera_irq_clock_crosser as irq_synchronizer
TR4_SOPC_onchip_memory2
altera_avalon_onchip_memory2 v11.1
TR4_SOPC_jtag_uart
altera_avalon_jtag_uart v11.1
TR4_SOPC_altpll_0
altpll v11.1
TR4_SOPC_cpu
altera_nios2_qsys v11.1
TR4_SOPC_sysid
altera_avalon_sysid_qsys v11.1
TR4_SOPC_tri_state_bridge_bridge_0
altera_tristate_conduit_bridge v11.1
TR4_SOPC_tri_state_bridge_pinSharer_0
altera_tristate_conduit_pin_sharer v11.1
TR4_SOPC_tri_state_bridge_pinSharer_0_pin_sharer as pin_sharer
TR4_SOPC_tri_state_bridge_pinSharer_0_arbiter as arbiter
TR4_SOPC_cfi_flash
altera_generic_tristate_controller v11.1
altera_tristate_controller_translator as tdt
altera_merlin_slave_translator as slave_translator
altera_tristate_controller_aggregator as tda
altera_merlin_master_translator
altera_merlin_master_translator v11.1
altera_merlin_slave_translator
altera_merlin_slave_translator v11.1
altera_merlin_slave_agent
altera_merlin_slave_agent v11.1
altera_avalon_sc_fifo
altera_avalon_sc_fifo v11.1
altera_merlin_master_agent
altera_merlin_master_agent v11.1
TR4_SOPC_addr_router
altera_merlin_router v11.1
TR4_SOPC_addr_router_001
altera_merlin_router v11.1
TR4_SOPC_id_router
altera_merlin_router v11.1
TR4_SOPC_id_router_002
altera_merlin_router v11.1
TR4_SOPC_id_router_003
altera_merlin_router v11.1
altera_merlin_traffic_limiter
altera_merlin_traffic_limiter v11.1
altera_merlin_burst_adapter
altera_merlin_burst_adapter v11.1
altera_reset_controller
altera_reset_controller v11.1
TR4_SOPC_cmd_xbar_demux
altera_merlin_demultiplexer v11.1
TR4_SOPC_cmd_xbar_demux_001
altera_merlin_demultiplexer v11.1
TR4_SOPC_cmd_xbar_mux
altera_merlin_multiplexer v11.1
TR4_SOPC_rsp_xbar_demux
altera_merlin_demultiplexer v11.1
TR4_SOPC_rsp_xbar_demux_003
altera_merlin_demultiplexer v11.1
TR4_SOPC_rsp_xbar_mux
altera_merlin_multiplexer v11.1
TR4_SOPC_rsp_xbar_mux_001
altera_merlin_multiplexer v11.1
altera_merlin_width_adapter
altera_merlin_width_adapter v11.1
altera_avalon_st_handshake_clock_crosser
altera_avalon_st_handshake_clock_crosser v11.1
TR4_SOPC_irq_mapper
altera_irq_mapper v11.1
altera_irq_clock_crosser
altera_irq_clock_crosser v11.1
TR4_SOPC_tri_state_bridge_pinSharer_0_pin_sharer
altera_tristate_conduit_pin_sharer_core v11.1
TR4_SOPC_tri_state_bridge_pinSharer_0_arbiter
altera_merlin_std_arbitrator v11.1
altera_tristate_controller_translator
altera_tristate_controller_translator v11.1
altera_tristate_controller_aggregator
altera_tristate_controller_aggregator v11.1
Generation Messages
2011.12.30.15:40:45 [Info] TR4_SOPC.onchip_memory2: Memory will be initialized from onchip_memory2.hex 2011.12.30.15:40:45 [Debug] TR4_SOPC.altpll_0: Timing: VAL:1/0.032s ELA:1/0.000s 2011.12.30.15:40:36 [Debug] TR4_SOPC.altera_nios2_qsys: When a generate simulation callback is defined a synthesis generation callback should also be defined 2011.12.30.15:40:45 [Info] TR4_SOPC.cpu: CPUID control register value is 0. Please manually assign CPUID if creating multiple Nios II system 2011.12.30.15:40:45 [Debug] TR4_SOPC.cpu: Timing: VAL:1/0.031s ELA:1/0.015s 2011.12.30.15:40:45 [Info] TR4_SOPC.sysid: System ID will no longer be automatically assigned. 2011.12.30.15:40:45 [Info] TR4_SOPC.sysid: Time stamp will be automatically updated when this component is generated. 2011.12.30.15:40:45 [Debug] TR4_SOPC.sysid: Timing: VAL:2/0.000s/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.tri_state_bridge_bridge_0: Timing: ELA:1/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.tri_state_bridge_pinSharer_0.clock: Timing: ELA:2/0.000s/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.tri_state_bridge_pinSharer_0.reset: Timing: ELA:2/0.000s/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.tri_state_bridge_pinSharer_0.pin_sharer: Timing: ELA:10/0.006s/0.016s 2011.12.30.15:40:45 [Debug] TR4_SOPC.tri_state_bridge_pinSharer_0.arbiter: Timing: ELA:2/0.000s/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.tri_state_bridge_pinSharer_0: Timing: COM:1/0.093s 2011.12.30.15:40:45 [Debug] TR4_SOPC.cfi_flash.clk: Timing: ELA:2/0.008s/0.016s 2011.12.30.15:40:45 [Debug] TR4_SOPC.cfi_flash.reset: Timing: ELA:2/0.000s/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.cfi_flash.tdt: Timing: ELA:4/0.004s/0.016s 2011.12.30.15:40:45 [Debug] TR4_SOPC.cfi_flash.slave_translator: Timing: ELA:5/0.000s/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.cfi_flash.tda: Timing: ELA:4/0.004s/0.016s 2011.12.30.15:40:45 [Debug] TR4_SOPC.cfi_flash: Timing: COM:1/0.015s 2011.12.30.15:40:45 [Debug] TR4_SOPC.c0: Timing: ELA:1/0.000s 2011.12.30.15:40:45 [Debug] TR4_SOPC.c1: Timing: ELA:1/0.000s 2011.12.30.15:40:45 [Info] TR4_SOPC: Generating TR4_SOPC "TR4_SOPC" for QUARTUS_SYNTH 2011.12.30.15:40:45 [Debug] TR4_SOPC: queue size: 0 starting:TR4_SOPC "TR4_SOPC" 2011.12.30.15:40:46 [Debug] Transform: PipelineBridgeSwap 2011.12.30.15:40:46 [Info] pipeline_bridge_swap_transform: After transform: 11 modules, 38 connections 2011.12.30.15:40:46 [Debug] Transform: ClockCrossingBridgeSwap 2011.12.30.15:40:46 [Debug] Transform: QsysBetaIPSwap 2011.12.30.15:40:46 [Debug] Transform: CustomInstructionTransform 2011.12.30.15:40:46 [Info] No custom instruction connections, skipping transform 2011.12.30.15:40:46 [Debug] Transform: TristateConduitUpgradeTransform 2011.12.30.15:40:46 [Debug] Transform: TranslatorTransform 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Info] merlin_translator_transform: After transform: 19 modules, 70 connections 2011.12.30.15:40:46 [Debug] Transform: DomainTransform 2011.12.30.15:40:46 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.instruction_master and cpu_instruction_master_translator.avalon_anti_master_0 2011.12.30.15:40:46 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu.data_master and cpu_data_master_translator.avalon_anti_master_0 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:46 [Progress] min: 0 2011.12.30.15:40:46 [Progress] max: 1 2011.12.30.15:40:46 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Debug] Transform merlin_domain_transform not run on matched interfaces cpu_jtag_debug_module_translator.avalon_anti_slave_0 and cpu.jtag_debug_module 2011.12.30.15:40:47 [Debug] Transform merlin_domain_transform not run on matched interfaces onchip_memory2_s1_translator.avalon_anti_slave_0 and onchip_memory2.s1 2011.12.30.15:40:47 [Debug] Transform merlin_domain_transform not run on matched interfaces cfi_flash_uas_translator.avalon_anti_slave_0 and cfi_flash.uas 2011.12.30.15:40:47 [Debug] Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave 2011.12.30.15:40:47 [Debug] Transform merlin_domain_transform not run on matched interfaces sysid_control_slave_translator.avalon_anti_slave_0 and sysid.control_slave 2011.12.30.15:40:47 [Debug] Transform merlin_domain_transform not run on matched interfaces altpll_0_pll_slave_translator.avalon_anti_slave_0 and altpll_0.pll_slave 2011.12.30.15:40:47 [Info] merlin_domain_transform: After transform: 37 modules, 181 connections 2011.12.30.15:40:47 [Debug] Transform: RouterTransform 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] merlin_router_transform: After transform: 45 modules, 213 connections 2011.12.30.15:40:47 [Debug] Transform: TrafficLimiterTransform 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] merlin_traffic_limiter_transform: After transform: 47 modules, 223 connections 2011.12.30.15:40:47 [Debug] Transform: BurstTransform 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] merlin_burst_transform: After transform: 48 modules, 227 connections 2011.12.30.15:40:47 [Debug] Transform: ResetAdaptation 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] reset_adaptation_transform: After transform: 51 modules, 184 connections 2011.12.30.15:40:47 [Debug] Transform: NetworkToSwitchTransform 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] merlin_network_to_switch_transform: After transform: 66 modules, 218 connections 2011.12.30.15:40:47 [Debug] Transform: WidthTransform 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] merlin_width_transform: After transform: 68 modules, 224 connections 2011.12.30.15:40:47 [Debug] Transform: RouterTableTransform 2011.12.30.15:40:47 [Debug] Transform: ClockCrossingTransform 2011.12.30.15:40:47 [Info] Inserting clock-crossing logic between cmd_xbar_demux_001.src3 and cmd_xbar_mux_003.sink0 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] Inserting clock-crossing logic between cmd_xbar_demux_001.src4 and cmd_xbar_mux_004.sink0 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] Inserting clock-crossing logic between cmd_xbar_demux_001.src5 and cmd_xbar_mux_005.sink0 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] Inserting clock-crossing logic between rsp_xbar_demux_003.src0 and rsp_xbar_mux_001.sink3 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] Inserting clock-crossing logic between rsp_xbar_demux_004.src0 and rsp_xbar_mux_001.sink4 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] Inserting clock-crossing logic between rsp_xbar_demux_005.src0 and rsp_xbar_mux_001.sink5 2011.12.30.15:40:47 [Progress] min: 0 2011.12.30.15:40:47 [Progress] max: 1 2011.12.30.15:40:47 [Progress] current: 1 2011.12.30.15:40:47 [Info] com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform: After transform: 74 modules, 254 connections 2011.12.30.15:40:47 [Debug] Transform: TrafficLimiterUpdateTransform 2011.12.30.15:40:48 [Info] limiter_update_transform: After transform: 74 modules, 256 connections 2011.12.30.15:40:48 [Debug] Transform: InterruptMapperTransform 2011.12.30.15:40:48 [Progress] min: 0 2011.12.30.15:40:48 [Progress] max: 1 2011.12.30.15:40:48 [Progress] current: 1 2011.12.30.15:40:48 [Info] merlin_interrupt_mapper_transform: After transform: 75 modules, 259 connections 2011.12.30.15:40:48 [Debug] Transform: InterruptSyncTransform 2011.12.30.15:40:48 [Progress] min: 0 2011.12.30.15:40:48 [Progress] max: 1 2011.12.30.15:40:48 [Progress] current: 1 2011.12.30.15:40:48 [Info] merlin_interrupt_sync_transform: After transform: 76 modules, 264 connections 2011.12.30.15:40:48 [Debug] Transform: InterruptFanoutTransform 2011.12.30.15:40:48 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:dataavailable (dataavailable)" 2011.12.30.15:40:48 [Warning] system: "No matching role found for jtag_uart:avalon_jtag_slave:readyfordata (readyfordata)" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_onchip_memory2 "submodules/TR4_SOPC_onchip_memory2" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_jtag_uart "submodules/TR4_SOPC_jtag_uart" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altpll "submodules/TR4_SOPC_altpll_0" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_nios2_qsys "submodules/TR4_SOPC_cpu" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sysid_qsys "submodules/TR4_SOPC_sysid" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_tristate_conduit_bridge "submodules/TR4_SOPC_tri_state_bridge_bridge_0" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_tristate_conduit_pin_sharer "submodules/TR4_SOPC_tri_state_bridge_pinSharer_0" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_generic_tristate_controller "submodules/TR4_SOPC_cfi_flash" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_addr_router" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_addr_router_001" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_id_router" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_id_router" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_id_router_002" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_id_router_003" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_id_router_003" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_router "submodules/TR4_SOPC_id_router_003" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_reset_controller "submodules/altera_reset_controller" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_cmd_xbar_demux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_cmd_xbar_demux_001" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_multiplexer "submodules/TR4_SOPC_cmd_xbar_mux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_multiplexer "submodules/TR4_SOPC_cmd_xbar_mux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_multiplexer "submodules/TR4_SOPC_cmd_xbar_mux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux_003" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux_003" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux_003" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_multiplexer "submodules/TR4_SOPC_rsp_xbar_mux" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_multiplexer "submodules/TR4_SOPC_rsp_xbar_mux_001" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_irq_mapper "submodules/TR4_SOPC_irq_mapper" 2011.12.30.15:40:48 [Debug] TR4_SOPC: "TR4_SOPC" reuses altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2011.12.30.15:40:48 [Debug] TR4_SOPC: queue size: 69 starting:altera_avalon_onchip_memory2 "submodules/TR4_SOPC_onchip_memory2" 2011.12.30.15:40:49 [Info] Starting classic module elaboration. 2011.12.30.15:40:50 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0001_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0001_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2011.12.30.15:40:52 [Info] Finished elaborating classic module. 2011.12.30.15:40:52 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0001_sopclgen/yysystem.ptf 2011.12.30.15:40:52 [Info] Running sopc_builder... 2011.12.30.15:40:53 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0001_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0001_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2011.12.30.15:40:55 [Progress] No .sopc_builder configuration file(!) 2011.12.30.15:40:55 [Progress] . 2011.12.30.15:41:06 [Progress] # 2011.12.30 15:41:06 (*) Success: sopc_builder finished. 2011.12.30.15:41:06 [Info] onchip_memory2: "TR4_SOPC" instantiated altera_avalon_onchip_memory2 "onchip_memory2" 2011.12.30.15:41:07 [Debug] TR4_SOPC: queue size: 68 starting:altera_avalon_jtag_uart "submodules/TR4_SOPC_jtag_uart" 2011.12.30.15:41:07 [Info] Starting classic module elaboration. 2011.12.30.15:41:08 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0002_sopclgen --no_splash --refresh C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0002_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2011.12.30.15:41:09 [Info] Finished elaborating classic module. 2011.12.30.15:41:09 [Progress] Executing: C:/altera/11.1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0002_sopclgen/yysystem.ptf 2011.12.30.15:41:09 [Info] Running sopc_builder... 2011.12.30.15:41:10 [Progress] "c:/altera/11.1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/11.1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0002_sopclgen --generate C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0002_sopclgen/yysystem.v --quartus_dir="c:/altera/11.1/quartus" --sopc_perl="c:/altera/11.1/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.1/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.1/quartus/../ip/altera/nios2_ip" 2011.12.30.15:41:11 [Progress] No .sopc_builder configuration file(!) 2011.12.30.15:41:11 [Progress] . 2011.12.30.15:41:13 [Progress] # 2011.12.30 15:41:13 (*) Success: sopc_builder finished. 2011.12.30.15:41:13 [Info] jtag_uart: "TR4_SOPC" instantiated altera_avalon_jtag_uart "jtag_uart" 2011.12.30.15:41:13 [Debug] TR4_SOPC: queue size: 67 starting:altpll "submodules/TR4_SOPC_altpll_0" 2011.12.30.15:41:13 [Debug] set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files 2011.12.30.15:41:13 [Debug] Command: C:/altera/11.1/quartus/bin/quartus_map.exe not_a_project --generate_hdl_interface=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0003_sopcgen/TR4_SOPC_altpll_0.v --source=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0003_sopcgen/TR4_SOPC_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0004_sopcqmap/ 2011.12.30.15:41:17 [Debug] Command took 4.062s 2011.12.30.15:41:17 [Info] altpll_0: "TR4_SOPC" instantiated altpll "altpll_0" 2011.12.30.15:41:17 [Debug] TR4_SOPC: queue size: 66 starting:altera_nios2_qsys "submodules/TR4_SOPC_cpu" 2011.12.30.15:41:17 [Info] cpu: Starting RTL generation for module 'TR4_SOPC_cpu' 2011.12.30.15:41:17 [Info] cpu: Generation command is [exec C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/11.1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/11.1/quartus/sopc_builder/bin/europa -I C:/altera/11.1/quartus/sopc_builder/bin/perl_lib -I C:/altera/11.1/quartus/sopc_builder/bin -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/11.1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=TR4_SOPC_cpu --dir=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0005_cpu_gen/ --quartus_dir=C:/altera/11.1/quartus --verilog --config=C:/DOCUME~1/ADMINI~1/LOCALS~1/Temp/alt5338_2942264173810992964.dir/0005_cpu_gen//TR4_SOPC_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:18 (*) Starting Nios II generation 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:18 (*) Checking for encrypted license (non-evaluation). 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:23 (*) Encrypted license found. SOF will not be time-limited. 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:23 (*) Elaborating CPU configuration settings 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:23 (*) Creating all objects for CPU 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:23 (*) Testbench 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:23 (*) Instruction decoding 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:23 (*) Instruction fields 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:23 (*) Instruction decodes 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:24 (*) Signals for RTL simulation waveforms 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:24 (*) Instruction controls 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:24 (*) Pipeline frontend 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:24 (*) Pipeline backend 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:28 (*) Generating RTL from CPU objects 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:31 (*) Creating encrypted RTL 2011.12.30.15:41:32 [Info] cpu: # 2011.12.30 15:41:32 (*) Done Nios II generation 2011.12.30.15:41:32 [Info] cpu: Done RTL generation for module 'TR4_SOPC_cpu' 2011.12.30.15:41:32 [Info] cpu: "TR4_SOPC" instantiated altera_nios2_qsys "cpu" 2011.12.30.15:41:32 [Debug] TR4_SOPC: queue size: 65 starting:altera_avalon_sysid_qsys "submodules/TR4_SOPC_sysid" 2011.12.30.15:41:32 [Info] sysid: "TR4_SOPC" instantiated altera_avalon_sysid_qsys "sysid" 2011.12.30.15:41:32 [Debug] TR4_SOPC: queue size: 64 starting:altera_tristate_conduit_bridge "submodules/TR4_SOPC_tri_state_bridge_bridge_0" 2011.12.30.15:41:32 [Info] tri_state_bridge_bridge_0: "TR4_SOPC" instantiated altera_tristate_conduit_bridge "tri_state_bridge_bridge_0" 2011.12.30.15:41:32 [Debug] TR4_SOPC: queue size: 63 starting:altera_tristate_conduit_pin_sharer "submodules/TR4_SOPC_tri_state_bridge_pinSharer_0" 2011.12.30.15:41:32 [Info] tri_state_bridge_pinSharer_0: Running transform AvalonTransform 2011.12.30.15:41:33 [Debug] Transform: PipelineBridgeSwap 2011.12.30.15:41:33 [Info] pipeline_bridge_swap_transform: After transform: 4 modules, 7 connections 2011.12.30.15:41:33 [Debug] Transform: ClockCrossingBridgeSwap 2011.12.30.15:41:33 [Debug] Transform: QsysBetaIPSwap 2011.12.30.15:41:33 [Debug] Transform: CustomInstructionTransform 2011.12.30.15:41:33 [Info] No custom instruction connections, skipping transform 2011.12.30.15:41:33 [Debug] Transform: TristateConduitUpgradeTransform 2011.12.30.15:41:33 [Debug] Transform: TranslatorTransform 2011.12.30.15:41:33 [Info] No Avalon connections, skipping transform 2011.12.30.15:41:33 [Debug] Transform: DomainTransform 2011.12.30.15:41:33 [Debug] Transform: RouterTransform 2011.12.30.15:41:33 [Debug] Transform: TrafficLimiterTransform 2011.12.30.15:41:33 [Debug] Transform: BurstTransform 2011.12.30.15:41:33 [Debug] Transform: ResetAdaptation 2011.12.30.15:41:33 [Debug] Transform: NetworkToSwitchTransform 2011.12.30.15:41:33 [Debug] Transform: WidthTransform 2011.12.30.15:41:33 [Debug] Transform: RouterTableTransform 2011.12.30.15:41:33 [Debug] Transform: ClockCrossingTransform 2011.12.30.15:41:33 [Debug] Transform: TrafficLimiterUpdateTransform 2011.12.30.15:41:33 [Debug] Transform: InterruptMapperTransform 2011.12.30.15:41:33 [Debug] Transform: InterruptSyncTransform 2011.12.30.15:41:33 [Debug] Transform: InterruptFanoutTransform 2011.12.30.15:41:33 [Info] tri_state_bridge_pinSharer_0: Running transform AvalonTransform took 0.094s 2011.12.30.15:41:33 [Debug] tri_state_bridge_pinSharer_0: "tri_state_bridge_pinSharer_0" reuses altera_tristate_conduit_pin_sharer_core "submodules/TR4_SOPC_tri_state_bridge_pinSharer_0_pin_sharer" 2011.12.30.15:41:33 [Debug] tri_state_bridge_pinSharer_0: "tri_state_bridge_pinSharer_0" reuses altera_merlin_std_arbitrator "submodules/TR4_SOPC_tri_state_bridge_pinSharer_0_arbiter" 2011.12.30.15:41:33 [Info] tri_state_bridge_pinSharer_0: "TR4_SOPC" instantiated altera_tristate_conduit_pin_sharer "tri_state_bridge_pinSharer_0" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 64 starting:altera_generic_tristate_controller "submodules/TR4_SOPC_cfi_flash" 2011.12.30.15:41:33 [Info] cfi_flash: Running transform AvalonTransform 2011.12.30.15:41:33 [Debug] Transform: PipelineBridgeSwap 2011.12.30.15:41:33 [Info] pipeline_bridge_swap_transform: After transform: 5 modules, 10 connections 2011.12.30.15:41:33 [Debug] Transform: ClockCrossingBridgeSwap 2011.12.30.15:41:33 [Debug] Transform: QsysBetaIPSwap 2011.12.30.15:41:33 [Debug] Transform: CustomInstructionTransform 2011.12.30.15:41:33 [Info] No custom instruction connections, skipping transform 2011.12.30.15:41:33 [Debug] Transform: TristateConduitUpgradeTransform 2011.12.30.15:41:33 [Debug] Transform: TranslatorTransform 2011.12.30.15:41:33 [Debug] Transform merlin_translator_transform not run on matched interfaces tdt.avalon_universal_master_0 and slave_translator.avalon_universal_slave_0 2011.12.30.15:41:33 [Debug] Transform merlin_translator_transform not run on matched interfaces slave_translator.avalon_anti_slave_0 and tda.avalon_slave_0 2011.12.30.15:41:33 [Debug] Transform: DomainTransform 2011.12.30.15:41:33 [Debug] Transform merlin_domain_transform not run on matched interfaces tdt.avalon_universal_master_0 and slave_translator.avalon_universal_slave_0 2011.12.30.15:41:33 [Debug] Transform merlin_domain_transform not run on matched interfaces slave_translator.avalon_anti_slave_0 and tda.avalon_slave_0 2011.12.30.15:41:33 [Debug] Transform: RouterTransform 2011.12.30.15:41:33 [Debug] Transform: TrafficLimiterTransform 2011.12.30.15:41:33 [Debug] Transform: BurstTransform 2011.12.30.15:41:33 [Debug] Transform: ResetAdaptation 2011.12.30.15:41:33 [Debug] Transform: NetworkToSwitchTransform 2011.12.30.15:41:33 [Debug] Transform: WidthTransform 2011.12.30.15:41:33 [Debug] Transform: RouterTableTransform 2011.12.30.15:41:33 [Debug] Transform: ClockCrossingTransform 2011.12.30.15:41:33 [Debug] Transform: TrafficLimiterUpdateTransform 2011.12.30.15:41:33 [Debug] Transform: InterruptMapperTransform 2011.12.30.15:41:33 [Debug] Transform: InterruptSyncTransform 2011.12.30.15:41:33 [Debug] Transform: InterruptFanoutTransform 2011.12.30.15:41:33 [Info] cfi_flash: Running transform AvalonTransform took 0.093s 2011.12.30.15:41:33 [Debug] cfi_flash: "cfi_flash" reuses altera_tristate_controller_translator "submodules/altera_tristate_controller_translator" 2011.12.30.15:41:33 [Debug] cfi_flash: "cfi_flash" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:41:33 [Debug] cfi_flash: "cfi_flash" reuses altera_tristate_controller_aggregator "submodules/altera_tristate_controller_aggregator" 2011.12.30.15:41:33 [Info] cfi_flash: "TR4_SOPC" instantiated altera_generic_tristate_controller "cfi_flash" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 66 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" 2011.12.30.15:41:33 [Info] cpu_instruction_master_translator: "TR4_SOPC" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 64 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" 2011.12.30.15:41:33 [Info] cpu_jtag_debug_module_translator: "TR4_SOPC" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 58 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" 2011.12.30.15:41:33 [Info] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent: "TR4_SOPC" instantiated altera_merlin_slave_agent "altpll_0_pll_slave_translator_avalon_universal_slave_0_agent" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 57 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" 2011.12.30.15:41:33 [Info] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo: "TR4_SOPC" instantiated altera_avalon_sc_fifo "altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 50 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" 2011.12.30.15:41:33 [Info] cpu_data_master_translator_avalon_universal_master_0_agent: "TR4_SOPC" instantiated altera_merlin_master_agent "cpu_data_master_translator_avalon_universal_master_0_agent" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 41 starting:altera_merlin_router "submodules/TR4_SOPC_addr_router" 2011.12.30.15:41:33 [Info] addr_router: "TR4_SOPC" instantiated altera_merlin_router "addr_router" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 40 starting:altera_merlin_router "submodules/TR4_SOPC_addr_router_001" 2011.12.30.15:41:33 [Info] addr_router_001: "TR4_SOPC" instantiated altera_merlin_router "addr_router_001" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 39 starting:altera_merlin_router "submodules/TR4_SOPC_id_router" 2011.12.30.15:41:33 [Info] id_router: "TR4_SOPC" instantiated altera_merlin_router "id_router" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 37 starting:altera_merlin_router "submodules/TR4_SOPC_id_router_002" 2011.12.30.15:41:33 [Info] id_router_002: "TR4_SOPC" instantiated altera_merlin_router "id_router_002" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 36 starting:altera_merlin_router "submodules/TR4_SOPC_id_router_003" 2011.12.30.15:41:33 [Info] id_router_003: "TR4_SOPC" instantiated altera_merlin_router "id_router_003" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 33 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" 2011.12.30.15:41:33 [Info] limiter: "TR4_SOPC" instantiated altera_merlin_traffic_limiter "limiter" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 31 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" 2011.12.30.15:41:33 [Info] burst_adapter: "TR4_SOPC" instantiated altera_merlin_burst_adapter "burst_adapter" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 30 starting:altera_reset_controller "submodules/altera_reset_controller" 2011.12.30.15:41:33 [Info] rst_controller: "TR4_SOPC" instantiated altera_reset_controller "rst_controller" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 27 starting:altera_merlin_demultiplexer "submodules/TR4_SOPC_cmd_xbar_demux" 2011.12.30.15:41:33 [Info] cmd_xbar_demux: "TR4_SOPC" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 26 starting:altera_merlin_demultiplexer "submodules/TR4_SOPC_cmd_xbar_demux_001" 2011.12.30.15:41:33 [Info] cmd_xbar_demux_001: "TR4_SOPC" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 25 starting:altera_merlin_multiplexer "submodules/TR4_SOPC_cmd_xbar_mux" 2011.12.30.15:41:33 [Info] cmd_xbar_mux: "TR4_SOPC" instantiated altera_merlin_multiplexer "cmd_xbar_mux" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 22 starting:altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux" 2011.12.30.15:41:33 [Info] rsp_xbar_demux: "TR4_SOPC" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 19 starting:altera_merlin_demultiplexer "submodules/TR4_SOPC_rsp_xbar_demux_003" 2011.12.30.15:41:33 [Info] rsp_xbar_demux_003: "TR4_SOPC" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_003" 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 16 starting:altera_merlin_multiplexer "submodules/TR4_SOPC_rsp_xbar_mux" 2011.12.30.15:41:33 [Info] rsp_xbar_mux: "TR4_SOPC" instantiated altera_merlin_multiplexer "rsp_xbar_mux" 2011.12.30.15:41:33 [Info] Reusing file D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 15 starting:altera_merlin_multiplexer "submodules/TR4_SOPC_rsp_xbar_mux_001" 2011.12.30.15:41:33 [Info] rsp_xbar_mux_001: "TR4_SOPC" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" 2011.12.30.15:41:33 [Info] Reusing file D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_arbitrator.sv 2011.12.30.15:41:33 [Debug] TR4_SOPC: queue size: 14 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" 2011.12.30.15:41:33 [Info] width_adapter: "TR4_SOPC" instantiated altera_merlin_width_adapter "width_adapter" 2011.12.30.15:41:34 [Info] Reusing file D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_merlin_burst_uncompressor.sv 2011.12.30.15:41:34 [Debug] TR4_SOPC: queue size: 12 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" 2011.12.30.15:41:34 [Info] crosser: "TR4_SOPC" instantiated altera_avalon_st_handshake_clock_crosser "crosser" 2011.12.30.15:41:34 [Info] Reusing file D:/SVN/tr4/cd/demonstrations/tr4_530/tr4_default_flash_loader/TR4_SOPC/synthesis/submodules/altera_avalon_st_pipeline_base.v 2011.12.30.15:41:34 [Debug] TR4_SOPC: queue size: 6 starting:altera_irq_mapper "submodules/TR4_SOPC_irq_mapper" 2011.12.30.15:41:34 [Info] irq_mapper: "TR4_SOPC" instantiated altera_irq_mapper "irq_mapper" 2011.12.30.15:41:34 [Debug] TR4_SOPC: queue size: 5 starting:altera_irq_clock_crosser "submodules/altera_irq_clock_crosser" 2011.12.30.15:41:34 [Info] irq_synchronizer: "TR4_SOPC" instantiated altera_irq_clock_crosser "irq_synchronizer" 2011.12.30.15:41:34 [Debug] TR4_SOPC: queue size: 4 starting:altera_tristate_conduit_pin_sharer_core "submodules/TR4_SOPC_tri_state_bridge_pinSharer_0_pin_sharer" 2011.12.30.15:41:34 [Info] pin_sharer: "tri_state_bridge_pinSharer_0" instantiated altera_tristate_conduit_pin_sharer_core "pin_sharer" 2011.12.30.15:41:34 [Debug] TR4_SOPC: queue size: 3 starting:altera_merlin_std_arbitrator "submodules/TR4_SOPC_tri_state_bridge_pinSharer_0_arbiter" 2011.12.30.15:41:34 [Info] arbiter: "tri_state_bridge_pinSharer_0" instantiated altera_merlin_std_arbitrator "arbiter" 2011.12.30.15:41:34 [Debug] TR4_SOPC: queue size: 2 starting:altera_tristate_controller_translator "submodules/altera_tristate_controller_translator" 2011.12.30.15:41:34 [Info] tdt: "cfi_flash" instantiated altera_tristate_controller_translator "tdt" 2011.12.30.15:41:34 [Debug] TR4_SOPC: queue size: 0 starting:altera_tristate_controller_aggregator "submodules/altera_tristate_controller_aggregator" 2011.12.30.15:41:34 [Info] tda: "cfi_flash" instantiated altera_tristate_controller_aggregator "tda" 2011.12.30.15:41:34 [Info] TR4_SOPC: Done TR4_SOPC" with 37 modules, 124 files, 7561250 bytes