HELLO_QSYS

2012.07.05.11:45:32 Datasheet
Overview
  sys_clk  HELLO_QSYS
   led
 out_port  
 in_port  
Processor
   cpu Nios II 12.0
All Components
   timer altera_avalon_timer 12.0
   jtag_uart altera_avalon_jtag_uart 12.0
   led altera_avalon_pio 12.0
   sysid altera_avalon_sysid_qsys 12.0
   ext_flash altera_generic_tristate_controller 12.0
   onchip_memory altera_avalon_onchip_memory2 12.0
   cpu altera_nios2_qsys 12.0
   button altera_avalon_pio 12.0
   pb_cpu_to_io altera_avalon_mm_bridge 12.0
Memory Map
cpu
 data_master  instruction_master
  timer
s1  0x10000000
  jtag_uart
avalon_jtag_slave  0x10000040
  led
s1  0x10000030
  sysid
control_slave  0x10000048
  ext_flash
uas  0x00000000 0x00000000
  onchip_memory
s1  0x11200000 0x11200000
  cpu
jtag_debug_module  0x11400800 0x11400800
  button
s1  0x10000020

sys_clk

clock_source v12.0
cpu jtag_debug_module_reset   sys_clk
  clk_in_reset
merged_resets out_reset  
  clk_in_reset
clk_reset   timer
  reset
clk  
  clk
clk_reset   jtag_uart
  reset
clk  
  clk
clk_reset   led
  reset
clk  
  clk
clk_reset   sysid
  reset
clk  
  clk
clk_reset   cfi_flash_atb_bridge_0
  reset
clk  
  clk
clk_reset   ext_flash
  reset
clk  
  clk
clk   onchip_memory
  clk1
clk_reset  
  reset1
clk   cpu
  clk
clk_reset  
  reset_n
clk   button
  clk
clk_reset  
  reset
clk   pb_cpu_to_io
  clk
clk_reset  
  reset


Parameters

clockFrequency 50000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

timer

altera_avalon_timer v12.0
sys_clk clk_reset   timer
  reset
clk  
  clk
cpu d_irq  
  irq
jtag_debug_module_reset  
  reset
merged_resets out_reset  
  reset
pb_cpu_to_io m0  
  s1


Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 10
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 50000000
timeoutPulseOutput false
timerPreset CUSTOM
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 10
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 50000000u
LOAD_VALUE 499999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 100u

jtag_uart

altera_avalon_jtag_uart v12.0
sys_clk clk_reset   jtag_uart
  reset
clk  
  clk
cpu d_irq  
  irq
jtag_debug_module_reset  
  reset
merged_resets out_reset  
  reset
pb_cpu_to_io m0  
  avalon_jtag_slave


Parameters

allowMultipleConnections false
avalonSpec 2.0
hubInstanceID 0
legacySignalAllow false
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

led

altera_avalon_pio v12.0
sys_clk clk_reset   led
  reset
clk  
  clk
cpu jtag_debug_module_reset  
  reset
merged_resets out_reset  
  reset
pb_cpu_to_io m0  
  s1


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 15
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0xf
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

sysid

altera_avalon_sysid_qsys v12.0
sys_clk clk_reset   sysid
  reset
clk  
  clk
cpu jtag_debug_module_reset  
  reset
merged_resets out_reset  
  reset
pb_cpu_to_io m0  
  control_slave


Parameters

id 0
timestamp 1341459875
AUTO_CLK_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY STRATIXV
deviceFamily Stratix V
generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 1341459875

cfi_flash_atb_bridge_0

altera_tristate_conduit_bridge v12.0
sys_clk clk_reset   cfi_flash_atb_bridge_0
  reset
clk  
  clk
cpu jtag_debug_module_reset  
  reset
merged_resets out_reset  
  reset
ext_flash tcm  
  tcs


Parameters

INTERFACE_INFO <info><slave name="tcs"><master name="ext_flash.tcm"><pin role="" width="1" type="Invalid" output_name="" output_enable_name="" input_name="" /><pin role="address" width="28" type="Output" output_name="tcm_address_out" output_enable_name="" input_name="" /><pin role="write_n" width="1" type="Output" output_name="tcm_write_n_out" output_enable_name="" input_name="" /><pin role="data" width="32" type="Bidirectional" output_name="tcm_data_out" output_enable_name="tcm_data_outen" input_name="tcm_data_in" /><pin role="read_n" width="1" type="Output" output_name="tcm_read_n_out" output_enable_name="" input_name="" /><pin role="chipselect_n" width="1" type="Output" output_name="tcm_chipselect_n_out" output_enable_name="" input_name="" /></master></slave></info>
AUTO_CLK_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY STRATIXV
deviceFamily Stratix V
generateLegacySim false
  

Software Assignments

(none)

ext_flash

altera_generic_tristate_controller v12.0
sys_clk clk_reset   ext_flash
  reset
clk  
  clk
cpu instruction_master  
  uas
data_master  
  uas
jtag_debug_module_reset  
  reset
merged_resets out_reset  
  reset
tcm   cfi_flash_atb_bridge_0
  tcs


Parameters

TCM_ADDRESS_W 28
TCM_DATA_W 32
TCM_BYTEENABLE_W 4
TCM_READ_WAIT 144
TCM_WRITE_WAIT 144
TCM_SETUP_WAIT 33
TCM_DATA_HOLD 33
TCM_MAX_PENDING_READ_TRANSACTIONS 3
TCM_TURNAROUND_TIME 2
TCM_TIMING_UNITS 0
TCM_READLATENCY 2
TCM_SYMBOLS_PER_WORD 4
USE_READDATA 1
USE_WRITEDATA 1
USE_READ 1
USE_WRITE 1
USE_BEGINTRANSFER 0
USE_BYTEENABLE 0
USE_CHIPSELECT 1
USE_LOCK 0
USE_ADDRESS 1
USE_WAITREQUEST 0
USE_WRITEBYTEENABLE 0
USE_OUTPUTENABLE 0
USE_RESETREQUEST 0
USE_IRQ 0
USE_RESET_OUTPUT 0
ACTIVE_LOW_READ 1
ACTIVE_LOW_LOCK 0
ACTIVE_LOW_WRITE 1
ACTIVE_LOW_CHIPSELECT 1
ACTIVE_LOW_BYTEENABLE 0
ACTIVE_LOW_OUTPUTENABLE 0
ACTIVE_LOW_WRITEBYTEENABLE 0
ACTIVE_LOW_WAITREQUEST 0
ACTIVE_LOW_BEGINTRANSFER 0
ACTIVE_LOW_RESETREQUEST 0
ACTIVE_LOW_IRQ 0
ACTIVE_LOW_RESET_OUTPUT 0
CHIPSELECT_THROUGH_READLATENCY 0
IS_MEMORY_DEVICE 1
MODULE_ASSIGNMENT_KEYS embeddedsw.configuration.hwClassnameDriverSupportList,embeddedsw.configuration.hwClassnameDriverSupportDefault,embeddedsw.CMacro.SETUP_VALUE,embeddedsw.CMacro.WAIT_VALUE,embeddedsw.CMacro.HOLD_VALUE,embeddedsw.CMacro.TIMING_UNITS,embeddedsw.CMacro.SIZE,embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH,embeddedsw.memoryInfo.HAS_BYTE_LANE,embeddedsw.memoryInfo.IS_FLASH,embeddedsw.memoryInfo.GENERATE_DAT_SYM,embeddedsw.memoryInfo.GENERATE_FLASH,embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR,embeddedsw.memoryInfo.FLASH_INSTALL_DIR
MODULE_ASSIGNMENT_VALUES altera_avalon_lan91c111:altera_avalon_cfi_flash1616,altera_avalon_cfi_flash1616,33,144,33,ns,268435456u,32,1,1,1,1,SIM_DIR,APP_DIR
INTERFACE_ASSIGNMENT_KEYS embeddedsw.configuration.isFlash,embeddedsw.configuration.isMemoryDevice,embeddedsw.configuration.isNonVolatileStorage
INTERFACE_ASSIGNMENT_VALUES 1,1,1
CLOCK_RATE 50000000
AUTO_CLK_CLOCK_DOMAIN 2
AUTO_CLK_RESET_DOMAIN 2
AUTO_TRISTATECONDUIT_MASTERS
AUTO_DEVICE_FAMILY STRATIXV
deviceFamily Stratix V
generateLegacySim false
  

Software Assignments

HOLD_VALUE 33
SETUP_VALUE 33
SIZE 268435456u
TIMING_UNITS ns
WAIT_VALUE 144

merged_resets

altera_reset_bridge v12.0


Parameters

ACTIVE_LOW_RESET 1
SYNCHRONOUS_EDGES none
NUM_RESET_OUTPUTS 1
AUTO_CLK_CLOCK_RATE -1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

onchip_memory

altera_avalon_onchip_memory2 v12.0
sys_clk clk   onchip_memory
  clk1
clk_reset  
  reset1
cpu data_master  
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset1
merged_resets out_reset  
  reset1


Parameters

allowInSystemMemoryContentEditor false
autoInitializationFileName HELLO_QSYS_onchip_memory
blockType AUTO
dataWidth 32
deviceFamily STRATIXV
dualPort false
initMemContent true
initializationFileName onchip_memory
instanceID NONE
memorySize 1572864
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
simMemInitOnlyFilename 0
singleClockOperation false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SINGLE_CLOCK_OP 0
SIZE_VALUE 1572864u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

cpu

altera_nios2_qsys v12.0
sys_clk clk   cpu
  clk
clk_reset  
  reset_n
merged_resets out_reset  
  reset_n
instruction_master   ext_flash
  uas
data_master  
  uas
jtag_debug_module_reset  
  reset
data_master   onchip_memory
  s1
instruction_master  
  s1
jtag_debug_module_reset  
  reset1
d_irq   jtag_uart
  irq
jtag_debug_module_reset  
  reset
d_irq   timer
  irq
jtag_debug_module_reset  
  reset
jtag_debug_module_reset   cfi_flash_atb_bridge_0
  reset
jtag_debug_module_reset   sys_clk
  clk_in_reset
jtag_debug_module_reset   led
  reset
jtag_debug_module_reset   sysid
  reset
data_master   pb_cpu_to_io
  s0
jtag_debug_module_reset  
  reset
jtag_debug_module_reset   button
  reset


Parameters

setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
muldiv_divider false
mpu_useLimit false
mpu_enabled false
mmu_enabled false
mmu_autoAssignTlbPtrSz true
manuallyAssignCpuID false
debug_triggerArming true
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
dcache_omitDataMaster false
cpuReset false
is_hardcopy_compatible false
setting_shadowRegisterSets 0
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mmu_TLBMissExcOffset 0
debug_jtagInstanceID 0
resetOffset 76808192
exceptionOffset 288
cpuID 0
cpuID_stored 0
breakOffset 32
userDefinedSettings
resetSlave ext_flash.uas
mmu_TLBMissExcSlave
exceptionSlave onchip_memory.s1
breakSlave cpu.jtag_debug_module
setting_perfCounterWidth 32
setting_interruptControllerType Internal
setting_branchPredictionType Automatic
setting_bhtPtrSz 8
muldiv_multiplierType DSPBlock
mpu_minInstRegionSize 12
mpu_minDataRegionSize 12
mmu_uitlbNumEntries 4
mmu_udtlbNumEntries 6
mmu_tlbPtrSz 7
mmu_tlbNumWays 16
mmu_processIDNumBits 8
impl Fast
icache_size 32768
icache_ramBlockType Automatic
icache_numTCIM 0
icache_burstType None
dcache_bursts false
debug_level Level1
debug_OCIOnchipTrace _128
dcache_size 32768
dcache_ramBlockType Automatic
dcache_numTCDM 0
dcache_lineSize 32
resetAbsoluteAddr 76808192
exceptionAbsoluteAddr 287310112
breakAbsoluteAddr 289409056
mmu_TLBMissExcAbsAddr 0
instAddrWidth 29
dataAddrWidth 29
tightlyCoupledDataMaster0AddrWidth 1
tightlyCoupledDataMaster1AddrWidth 1
tightlyCoupledDataMaster2AddrWidth 1
tightlyCoupledDataMaster3AddrWidth 1
tightlyCoupledInstructionMaster0AddrWidth 1
tightlyCoupledInstructionMaster1AddrWidth 1
tightlyCoupledInstructionMaster2AddrWidth 1
tightlyCoupledInstructionMaster3AddrWidth 1
instSlaveMapParam <address-map><slave name='ext_flash.uas' start='0x0' end='0x10000000' /><slave name='onchip_memory.s1' start='0x11200000' end='0x11380000' /><slave name='cpu.jtag_debug_module' start='0x11400800' end='0x11401000' /></address-map>
dataSlaveMapParam <address-map><slave name='ext_flash.uas' start='0x0' end='0x10000000' /><slave name='timer.s1' start='0x10000000' end='0x10000020' /><slave name='button.s1' start='0x10000020' end='0x10000030' /><slave name='led.s1' start='0x10000030' end='0x10000040' /><slave name='jtag_uart.avalon_jtag_slave' start='0x10000040' end='0x10000048' /><slave name='sysid.control_slave' start='0x10000048' end='0x10000050' /><slave name='onchip_memory.s1' start='0x11200000' end='0x11380000' /><slave name='cpu.jtag_debug_module' start='0x11400800' end='0x11401000' /></address-map>
clockFrequency 50000000
deviceFamilyName STRATIXV
internalIrqMaskSystemInfo 3
customInstSlavesSystemInfo <info/>
deviceFeaturesSystemInfo NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 1 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 1 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 1 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

BIG_ENDIAN 0
BREAK_ADDR 0x11400820
CPU_FREQ 50000000u
CPU_ID_SIZE 1
CPU_ID_VALUE 0x00000000
CPU_IMPLEMENTATION "fast"
DATA_ADDR_WIDTH 29
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 32768
EXCEPTION_ADDR 0x11200120
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 1
HAS_DEBUG_CORE 1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 32768
INITDA_SUPPORTED
INST_ADDR_WIDTH 29
NUM_OF_SHADOW_REG_SETS 0
RESET_ADDR 0x04940000

button

altera_avalon_pio v12.0
sys_clk clk   button
  clk
clk_reset  
  reset
merged_resets out_reset  
  reset
pb_cpu_to_io m0  
  s1
cpu jtag_debug_module_reset  
  reset


Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 50000000
direction Input
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 2
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 50000000u

pb_cpu_to_io

altera_avalon_mm_bridge v12.0
cpu data_master   pb_cpu_to_io
  s0
jtag_debug_module_reset  
  reset
sys_clk clk  
  clk
clk_reset  
  reset
merged_resets out_reset  
  reset
m0   timer
  s1
m0   button
  s1
m0   led
  s1
m0   jtag_uart
  avalon_jtag_slave
m0   sysid
  control_slave


Parameters

DATA_WIDTH 32
SYMBOL_WIDTH 8
ADDRESS_WIDTH 11
ADDRESS_UNITS SYMBOLS
BURSTCOUNT_WIDTH 1
MAX_BURST_SIZE 1
MAX_PENDING_RESPONSES 19
LINEWRAPBURSTS 0
PIPELINE_COMMAND 1
PIPELINE_RESPONSE 1
AUTO_CLK_CLOCK_RATE 50000000
AUTO_DEVICE_FAMILY STRATIXV
deviceFamily Stratix V
generateLegacySim false
  

Software Assignments

(none)
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