---

clk_50

clock_source v13.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

nios2_qsys

altera_nios2_qsys v13.1

Parameters setting_showUnpublishedSettings false setting_showInternalSettings false setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_bit31BypassDCache true setting_bigEndian false setting_export_large_RAMs false setting_asic_enabled false setting_asic_synopsys_translate_on_off false setting_oci_export_jtag_signals false setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTrace_user false setting_activateTestEndChecker false setting_ecc_sim_test_ports false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false setting_breakslaveoveride false muldiv_divider false mpu_useLimit false mpu_enabled false mmu_enabled false mmu_autoAssignTlbPtrSz true manuallyAssignCpuID false debug_triggerArming true debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false dcache_omitDataMaster false cpuReset false is_hardcopy_compatible false setting_shadowRegisterSets 0 mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mmu_TLBMissExcOffset 0 debug_jtagInstanceID 0 resetOffset 0 exceptionOffset 32 cpuID 0 cpuID_stored 0 breakOffset 32 userDefinedSettings resetSlave onchip_memory2.s1 mmu_TLBMissExcSlave exceptionSlave onchip_memory2.s1 breakSlave nios2_qsys.jtag_debug_module setting_perfCounterWidth 32 setting_interruptControllerType Internal setting_branchPredictionType Automatic setting_bhtPtrSz 8 muldiv_multiplierType DSPBlock mpu_minInstRegionSize 12 mpu_minDataRegionSize 12 mmu_uitlbNumEntries 4 mmu_udtlbNumEntries 6 mmu_tlbPtrSz 7 mmu_tlbNumWays 16 mmu_processIDNumBits 8 impl Fast icache_size 4096 icache_tagramBlockType Automatic icache_ramBlockType Automatic icache_numTCIM 0 icache_burstType None dcache_bursts false dcache_victim_buf_impl ram debug_level Level1 debug_OCIOnchipTrace _128 dcache_size 2048 dcache_tagramBlockType Automatic dcache_ramBlockType Automatic dcache_numTCDM 0 dcache_lineSize 32 setting_exportvectors false setting_ecc_present false setting_ic_ecc_present true setting_rf_ecc_present true setting_mmu_ecc_present true setting_dc_ecc_present false setting_itcm_ecc_present false setting_dtcm_ecc_present false regfile_ramBlockType Automatic ocimem_ramBlockType Automatic mmu_ramBlockType Automatic bht_ramBlockType Automatic resetAbsoluteAddr 262144 exceptionAbsoluteAddr 262176 breakAbsoluteAddr 526368 mmu_TLBMissExcAbsAddr 0 dcache_bursts_derived false dcache_size_derived 2048 dcache_lineSize_derived 32 translate_on "synthesis translate_on" translate_off "synthesis translate_off" instAddrWidth 20 dataAddrWidth 20 tightlyCoupledDataMaster0AddrWidth 1 tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster3AddrWidth 1 instSlaveMapParam <address-map><slave name='onchip_memory2.s1' start='0x40000' end='0x7E800' /><slave name='nios2_qsys.jtag_debug_module' start='0x80800' end='0x81000' /></address-map> dataSlaveMapParam <address-map><slave name='onchip_memory2.s1' start='0x40000' end='0x7E800' /><slave name='nios2_qsys.jtag_debug_module' start='0x80800' end='0x81000' /><slave name='timer.s1' start='0x81000' end='0x81020' /><slave name='sw.s1' start='0x81020' end='0x81030' /><slave name='button.s1' start='0x81030' end='0x81040' /><slave name='temp_sda.s1' start='0x81040' end='0x81050' /><slave name='temp_int_n.s1' start='0x81050' end='0x81060' /><slave name='temp_overt_n.s1' start='0x81060' end='0x81070' /><slave name='led.s1' start='0x81070' end='0x81080' /><slave name='fan.s1' start='0x81080' end='0x81090' /><slave name='temp_scl.s1' start='0x81100' end='0x81110' /><slave name='cdcm_od.s1' start='0x81110' end='0x81120' /><slave name='cdcm_pr.s1' start='0x81120' end='0x81130' /><slave name='clk_i2c_sda.s1' start='0x81130' end='0x81140' /><slave name='clk_i2c_scl.s1' start='0x81140' end='0x81150' /><slave name='ref_clock_sata_count.Slave' start='0x81150' end='0x81160' /><slave name='ref_clock_10g_count.Slave' start='0x81170' end='0x81180' /><slave name='cdmc_reset_n.s1' start='0x811C0' end='0x811D0' /><slave name='jtag_uart.avalon_jtag_slave' start='0x81210' end='0x81218' /></address-map> clockFrequency 50000000 deviceFamilyName STRATIXV internalIrqMaskSystemInfo 15 customInstSlavesSystemInfo <info/> deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 1 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 1 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster3MapParam tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster3MapParam deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIG_ENDIAN 0 BREAK_ADDR 0x00080820 CPU_FREQ 50000000u CPU_ID_SIZE 1 CPU_ID_VALUE 0x00000000 CPU_IMPLEMENTATION "fast" DATA_ADDR_WIDTH 20 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 2048 EXCEPTION_ADDR 0x00040020 FLUSHDA_SUPPORTED HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 1 HAS_DEBUG_CORE 1 HAS_DEBUG_STUB HAS_JMPI_INSTRUCTION ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 INITDA_SUPPORTED INST_ADDR_WIDTH 20 NUM_OF_SHADOW_REG_SETS 0 RESET_ADDR 0x00040000

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onchip_memory2

altera_avalon_onchip_memory2 v13.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 dualPort false initMemContent true initializationFileName onchip_memory2 instanceID NONE memorySize 256000 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false simMemInitOnlyFilename 0 singleClockOperation false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true ecc_enabled false autoInitializationFileName TR5_LITE_QSYS_onchip_memory2 deviceFamily STRATIXV deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 1 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 1 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_INTERFACE_PLANNER_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LIMITED_TCL_FITTER_SUPPORT 1 HAS_LOGICAL_FLOORPLANNER_SUPPORT 0 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 1 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 derived_set_addr_width 16 derived_set_data_width 32 derived_gui_ram_block_type Automatic derived_is_hardcopy false derived_init_file_name TR5_LITE_QSYS_onchip_memory2.hex generateLegacySim false

  

Software Assignments ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 CONTENTS_INFO "" DUAL_PORT 0 GUI_RAM_BLOCK_TYPE AUTO INIT_CONTENTS_FILE TR5_LITE_QSYS_onchip_memory2 INIT_MEM_CONTENT 1 INSTANCE_ID NONE NON_DEFAULT_INIT_FILE_ENABLED 0 RAM_BLOCK_TYPE AUTO READ_DURING_WRITE_MODE DONT_CARE SINGLE_CLOCK_OP 0 SIZE_MULTIPLE 1 SIZE_VALUE 256000 WRITABLE 1

---

timer

altera_avalon_timer v13.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true timeoutPulseOutput false systemFrequency 50000000 timerPreset FULL_FEATURED periodUnitsString ms valueInSecond 0 loadValue 49999 mult 0 ticksPerSec 1000 slave_address_width 3 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 COUNTER_SIZE 32 FIXED_PERIOD 0 FREQ 50000000 LOAD_VALUE 49999 MULT 0.001 PERIOD 1 PERIOD_UNITS ms RESET_OUTPUT 0 SNAPSHOT 1 TICKS_PER_SEC 1000.0 TIMEOUT_PULSE_OUTPUT 0

---

sw

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true direction Input edgeType ANY generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 2 clockRate 50000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture true derived_edge_type ANY derived_irq_type EDGE derived_has_irq true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 1 DATA_WIDTH 2 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE ANY FREQ 50000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE EDGE RESET_VALUE 0

---

button

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true direction Input edgeType FALLING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 2 clockRate 50000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture true derived_edge_type FALLING derived_irq_type EDGE derived_has_irq true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 1 DATA_WIDTH 2 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE FALLING FREQ 50000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE EDGE RESET_VALUE 0

---

temp_scl

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

temp_sda

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri true derived_has_out false derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 0 HAS_TRI 1 IRQ_TYPE NONE RESET_VALUE 0

---

temp_int_n

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

temp_overt_n

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

led

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 4 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

jtag_uart

altera_avalon_jtag_uart v13.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 avalonSpec 2.0 legacySignalAllow false enableInteractiveInput false enableInteractiveOutput true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments READ_DEPTH 64 READ_THRESHOLD 8 WRITE_DEPTH 64 WRITE_THRESHOLD 8

---

fan

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 1 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 1

---

cdcm_od

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 3 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 3 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

cdcm_pr

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 2 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 2 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

clk_i2c_scl

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

clk_i2c_sda

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Bidir edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri true derived_has_out false derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 0 HAS_TRI 1 IRQ_TYPE NONE RESET_VALUE 0

---

ref_clock_sata_count

TERASIC_CLOCK_COUNT v1.0

Parameters AUTO_CLK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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cdmc_reset_n

altera_avalon_pio v13.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 1 simDoTestBenchWiring false simDrivenValue 0 width 1 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 1 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 1

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ref_clock_10g_count

TERASIC_CLOCK_COUNT v1.0

Parameters AUTO_CLK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)